Wafer processing tape

Abstract

To provide a wafer processing tape capable of suppressing warpage of a wafer, and a wafer processing method using the wafer processing tape.SOLUTION: A wafer processing tape 1 includes a base material layer 10, and a shrinkage work amount W120 of the base material layer at 120 °C is equal to or less than 8mJ / 20mm in at least one direction in a plane of the base material layer, and is used in a wafer processing method including a back grinding step of polishing a non-element forming surface of a wafer bonded to the wafer processing tape, and a dicing step of dicing the wafer bonded to the wafer processing tape after the back grinding step.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a tape for wafer processing. [Background technology]

[0002] When a semiconductor wafer (hereinafter also referred to as "wafer") or the like is diced, a dicing tape is attached to the wafer, the wafer is diced, and the dicing tape is expanded. After expansion, the chips obtained by dicing the wafer are picked up (peeled) from the dicing tape.

[0003] As such a backgrind tape, for example, Patent Document 1 discloses an adhesive film including a base layer, an irregularity-absorbing resin layer, and an adhesive resin layer in this order. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-065168 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent document 1 explains that by providing an adhesive film with an irregularity-absorbing resin layer, the irregularities caused by the bumps can be absorbed even if the size of the bumps formed on the surface of the wafer becomes large, and that by making the irregularity-absorbing resin layer have a specific composition, the cutting ability of the adhesive film can be improved.

[0006] Before singulating a wafer, a back-grinding process is generally performed in which the back side of the wafer, on which no elements or the like are provided, is polished to thin the wafer, and a dicing process is generally performed in which the wafer is diced after the back-grinding process. In both the back-grinding process and the dicing process, the wafer needs to be fixed to a pedestal, and tape is used to fix the wafer to the pedestal in both processes. While the tape used in both processes was typically different, using the same tape in both processes and allowing the back-grinding process and the dicing process to be performed continuously can enable more efficient singulation of the wafer.

[0007] However, it was found that when the same tape is used in both processes, the wafer warps significantly during the dicing process. When a wafer with a large warp is diced, the wafer cannot be divided as designed, and not only does this deteriorate the division ability, but the warpage of the wafer can also make it difficult to transport.

[0008] The present invention has been made in view of the above problems, and has an object to provide a wafer processing tape that can suppress wafer warpage, and a wafer processing method using the wafer processing tape. [Means for solving the problem]

[0009] The present inventors have conducted extensive research to solve the above problems. As a result, it has been discovered that a shrinkage work amount W of a substrate layer at 120°C can be reduced in at least one direction in the plane of the substrate layer. 120 However, they found that a wafer processing tape with a power consumption of 8 mJ / 20 mm or less could solve the above problems, leading to the completion of the present invention.

[0010] That is, the present invention includes the following aspects. [1] A substrate layer is provided, The shrinkage work W of the base material layer at 120 ° C. in at least one direction in the plane of the base material layer 120 However, it is less than 8mJ / 20mm. Tape for wafer processing. [2] The shrinkage load K of the base material layer at 120°C 120 However, it is 0.15N / 20mm or less. [1] The wafer processing tape according to [1]. [3] The shrinkage load K of the base material layer at 60°C 60 However, it is 0.05N / 20mm or less. [1] or [2]. The wafer processing tape according to [1] or [2]. [4] The rate of change in length of the base material layer at 120°C is 40% or less in at least one direction in the plane of the base material layer. The tape for wafer processing according to any one of [1] to [3]. [5] The thickness of the base layer at 23°C is 50 to 250 μm. The tape for wafer processing according to any one of [1] to [4]. [6] The substrate layer comprises an ionomer. The tape for wafer processing according to any one of [1] to [5]. [7] a back-grinding step of grinding a non-element-formed surface of the wafer attached to the wafer processing tape; and a dicing step of dicing the wafer attached to the wafer processing tape after the back-grinding step, The tape for wafer processing according to any one of [1] to [6]. [8] A heat treatment step of heating the base layer for 3 minutes or more at a temperature of 100°C or more is included. A method for producing a tape for wafer processing according to any one of [1] to [7]. [9] a bonding step of bonding the wafer processing tape according to any one of [1] to [7] to the element formation surface of the wafer; a back grinding step of grinding a non-element forming surface of the wafer bonded to the wafer processing tape; a dicing step of dicing the wafer bonded to the wafer processing tape after the back-grinding step; Wafer processing method.

[10] In the dicing step, a modified portion is generated inside the wafer by laser dicing. [9] The wafer processing method according to [9].

[11] a peeling step of heating and peeling off the wafer processing tape after the dicing step; The wafer processing method according to [9] or

[10] . [Brief explanation of the drawings]

[0011] [Figure 1A] 1 is a perspective view of a wafer processing tape according to an embodiment of the present invention; [Figure 1B] 1B shows an example of a cross-sectional view taken along line AA' in FIG. 1A. [Figure 2] An example of a wafer 2 to be attached to a wafer processing tape 1 is shown. [Figure 3A] FIG. 10 shows an example of a perspective view of a back grinding process. [Figure 3B] 3B shows an example of a cross-sectional view taken along line AA' in FIG. 3A. [Figure 4A] 1A and 1B show an example of a perspective view of a dicing process. [Figure 4B] 4B shows an example of a cross-sectional view taken along line AA' in FIG. 4A. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described in detail with reference to the drawings as necessary, but the present invention is not limited to this, and various modifications are possible without departing from the spirit of the present invention. In the drawings, the same elements are given the same reference numerals, and redundant explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0013] 1. Wafer processing tape The wafer processing tape of this embodiment includes a base layer, and the shrinkage work W of the base layer at 120° C. is 120 However, it is less than 8mJ / 20mm.

[0014] FIG. 1A shows an example of a perspective view of the wafer processing tape of this embodiment, and FIG. 1B shows an example of a cross-sectional view taken along line A-A' in FIG. 1A. As shown in FIGS. 1A and 1B, the wafer processing tape 1 of this embodiment may consist of only a base layer 10, or other layers may be provided as necessary from the viewpoint of adhesion and bonding between the wafer processing tape 1 and the wafer. Of the two surfaces of the base layer 10, the surface that contacts the wafer 2 is referred to as the first surface 11, and the surface opposite the first surface 11 is referred to as the second surface 12. The in-plane of the base layer 10 refers to the in-plane of the surface of the base layer 10 that is perpendicular to the stacking direction in which the wafer 2 is stacked on the wafer processing tape 1.

[0015] 2 shows an example of a wafer 2 attached to the wafer processing tape 1. The wafer 2 has an element-forming surface 21 on which elements 23 such as circuits are formed, and a non-element-forming surface 22 on the opposite side of the element-forming surface 21 on which elements 23 are not formed.

[0016] The wafer 2 is not particularly limited, but may be a conventional general-purpose semiconductor wafer such as a silicon wafer, a gallium nitride wafer, a silicon carbide wafer, or a sapphire wafer.

[0017] After the wafer processing tape 1 is bonded to the element-formed surface 21 of the wafer 2, a backgrinding process is performed to grind the non-element-formed surface 22 of the wafer 2, and then a dicing process is performed to dice the wafer 2 without peeling it off the wafer processing tape 1. To improve the divisibility and transportability of the wafer 2, it is necessary to suppress warpage of the wafer during the dicing process.

[0018] When the wafer processing tape 1 is attached to the wafer 2, in order to improve adhesion, the wafer processing tape 1 is heated to a high temperature before being attached to the wafer 2. Therefore, if the wafer processing tape 1 is prone to shrinkage at high temperatures, the wafer 2 is likely to be warped.

[0019] From this viewpoint, in the wafer processing tape 1 of this embodiment, the shrinkage work W of the base layer 10 at 120° C. is 120 The specification stipulates that the radiation intensity must be 8mJ / 20mm or less.

[0020] In this regard, the wafer processing tape 1 of this embodiment has a shrinkage work load W 120 However, since the energy density is 8 mJ / 20 mm or less, the wafer processing tape 1 is less likely to shrink even at high temperatures, and warpage of the wafer 2 after the dicing process can be reduced.

[0021] Contraction work W 120 is preferably 0 to 8 mJ / 20 mm, 0 to 7 mJ / 20 mm, or 0 to 6 mJ / 20 mm. 120 When the thickness is within the above range, warpage of the wafer 2 tends to be further suppressed.

[0022] In this embodiment, the shrinkage work of the base layer 10 is measured at 120°C in at least one direction within the plane of the base layer 10. Here, 120°C is a reference temperature when the wafer processing tape 1 is bonded to the wafer 2. In this regard, it is expected that the wafer processing tape 1 may be bonded to the wafer 2 at a temperature higher or lower than 120°C in some cases. However, even if the actual temperature when the wafer processing tape 1 is bonded to the wafer 2 is not 120°C but is higher or lower than this temperature, it can be said that warpage of the wafer 2 can be suppressed by the shrinkage work of the base layer 10 measured with reference to 120°C satisfying a predetermined range.

[0023] In this embodiment, at least one direction in the plane of the base material layer 10 is used as the measurement direction for the shrinkage work of the base material layer 10 at 120°C. When the shrinkage work satisfies a predetermined range in at least one direction, it can be said that warpage of the wafer 2 can be reduced. The one direction is not particularly limited, but may be, for example, the following direction. That is, in measuring the shrinkage work, a test piece of the base material layer 10 is fixed to a measuring device, and the measurement may be in one direction in the plane of the base material layer 10, where the length does not change due to such fixation.

[0024] From the same viewpoint, the shrinkage work W of the base material layer 10 at 60° C. in at least one direction in the plane of the base material layer 10 is 60 is preferably 0.0 to 1.0 mJ / 20 mm, 0.0 to 0.5 mJ / 20 mm, 0.0 to 0.3 mJ / 20 mm, 0.0 to 0.2 mJ / 20 mm, or 0.0 to 0.1 mJ / 20 mm. 60 When the thickness is within the above range, warpage of the wafer 2 tends to be further suppressed.

[0025] Contraction work W of the base layer 10 at T ° C. T is calculated using the following formula: Contraction work W T (mJ / 20mm) = shrinkage amount at T°C (mm) x shrinkage load at T°C (N / 20mm)

[0026] The shrinkage load at T°C can be measured, for example, by fixing both ends of the wafer processing tape 1 at room temperature (23°C) before heating in a certain direction within the plane of the base layer 10, placing the wafer processing tape 1 in an oil bath heated to T°C with the chuck distance of 20 mm, heating it, and measuring the change in load over time during heating. The test specimen is a rectangular parallelepiped with a width of 20 mm and a length of 25 mm, and both ends in the longitudinal direction are fixed to prevent change in the longitudinal direction. Therefore, the shrinkage load in this embodiment can also be said to be a value per 20 mm of width.

[0027] The amount of shrinkage at T°C can be obtained, for example, by subtracting the length of the base material layer 10 in one direction at room temperature when the shrinkage load was measured from the length of the base material layer 10 in that direction after being heated to T°C.

[0028] Contraction work W T can be adjusted by the type and composition of the base layer 10. In addition, the shrinkage work W T can be reduced.

[0029] The wafer processing tape 1 of this embodiment is preferably used in a wafer processing method including a back-grinding process for polishing the non-element forming surface 22 of the wafer 2 attached to the wafer processing tape 1, and a dicing process for dicing the wafer 2 attached to the wafer processing tape 1 after the back-grinding process.

[0030] Each component of the tape for wafer processing 1 of this embodiment will be described in detail below.

[0031] 1.1. Base material layer The wafer processing tape 1 of this embodiment includes a base layer 10.

[0032] The thickness of the base layer 10 at room temperature (23°C) is preferably 50 to 250 μm, 75 to 225 μm, or 100 to 200 μm. The thinner the base layer 10, the smaller the shrinkage stress of the base layer 10 and the smaller the warpage of the wafer 2, which tends to result in reduced warpage of the wafer 2. On the other hand, if the thickness of the base layer 10 is too thin, the wafer processing tape 1 may not adhere sufficiently to the wafer 2, and the wafer 2 may not be sufficiently fixed in the back-grinding and dicing processes. From this perspective, if the thickness of the base layer 10 is within the above range, warpage of the wafer 2 can be reduced and the wafer 2 tends to be sufficiently fixed.

[0033] In addition, in order to prevent the wafer processing tape 1 from shrinking at high temperatures, the shrinkage load K 120 is preferably 0.15N / 20mm or less, 0.00 to 0.15N / 20mm, 0.00 to 0.13N / 20mm, or 0.00 to 0.10N / 20mm. 120 When the thickness is within the above range, the warpage of the wafer 2 tends to be further reduced.

[0034] In addition, the shrinkage load K of the base material layer 10 at 60 ° C. 60 is preferably 0.05N / 20mm or less, 0.00 to 0.05N / 20mm, 0.00 to 0.03N / 20mm, or 0.00 to 0.01N / 20mm. 60 When the thickness is within the above range, the warpage of the wafer 2 tends to be further reduced.

[0035] It is preferable that the shrinkage load of the base material layer 10 measured in at least one direction in the plane of the base material layer 10 satisfies the above numerical range.

[0036] The shrinkage load of the base material layer 10 can be adjusted by the type and composition of the base material layer 10. Furthermore, the shrinkage load of the base material layer 10 can be reduced by heat treating the base material layer 10.

[0037] Furthermore, from the viewpoint of making the wafer processing tape 1 less likely to shrink at high temperatures, the length change rate of the base layer 10 at 120°C in at least one direction within the plane of the base layer 10 is preferably 40% or less, 0 to 40%, 0 to 37.5%, or 0 to 35%. When the length change rate is within the above range, warpage of the wafer 2 tends to be further reduced.

[0038] In this embodiment, the length change rate S T is the length L in a certain direction in the plane of the base layer 10 at room temperature (23°C). 23 Based on this, the length L in one direction at T°C T Specifically, it shows how much S T (%)=|L 23 -L T | / L 23 It is expressed as ×100.

[0039] In this embodiment, the length change rate of the base layer 10 is measured at 120°C in at least one direction within the plane of the base layer 10. Here, 120°C is a reference temperature value for the temperature when the wafer processing tape 1 is bonded to the wafer 2. In this regard, it is expected that the wafer processing tape 1 may be bonded to the wafer 2 at a temperature higher or lower than 120°C in some cases. However, even if the actual temperature when the wafer processing tape 1 is bonded to the wafer 2 is not 120°C but is higher or lower than this temperature, it can be said that warpage of the wafer 2 can be suppressed if the length change rate of the base layer 10 measured with reference to 120°C falls within a predetermined range.

[0040] In this embodiment, the length change rate of the base layer 10 at 120°C is measured in at least one direction within the plane of the base layer 10. When the length change rate in at least one direction satisfies a predetermined range, it can be said that warpage of the wafer 2 can be reduced. The one direction is not particularly limited, and may be, for example, the same as the direction in which the contraction work is measured.

[0041] From the same viewpoint, the length change rate of the base layer 10 at 90°C in at least one direction in the plane of the base layer 10 is preferably 25.0% or less, 0.0 to 25.0%, 0.0 to 22.5%, or 0.0 to 20.0%. When the length change rate is within the above range, warpage of the wafer 2 tends to be further reduced.

[0042] From a similar perspective, the length change rate of the base layer 10 at 60°C in at least one direction in the plane of the base layer 10 is preferably 2.0% or less, 0.0 to 2.0%, 0.0 to 1.8%, or 0.0 to 1.5%. When the length change rate is within the above range, warpage of the wafer 2 tends to be further reduced.

[0043] The rate of change in length of the base layer 10 can be adjusted by the type and composition of the base layer 10. Furthermore, the rate of change in length of the base layer 10 can be reduced by heat treating the base layer 10.

[0044] The base layer 10 is not particularly limited, and may include, for example, acrylic copolymers such as copolymers of monomers containing ethylene, (meth)acrylic acid, and a (meth)acrylic acid ester, copolymers of monomers containing ethylene and ethyl (meth)acrylate, copolymers of monomers containing ethylene and (meth)acrylic acid, copolymers of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate, copolymers of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate, copolymers of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-hydroxyethyl (meth)acrylate, homopolymers of (meth)acrylic acid esters, urethane copolymers, ionomers obtained by crosslinking with metal ions such as polyvinyl chloride, polyethylene terephthalate, ethylene-vinyl acetate copolymers, polyethylene, polypropylene, propylene copolymers, copolymers of monomers containing ethylene and (meth)acrylic acid, and copolymers of monomers containing ethylene, (meth)acrylic acid, and a (meth)acrylic acid ester. Among these, ionomers are preferred.

[0045] The ionomer is not particularly limited as long as it is a polymer intermolecularly bonded by metal ions, and examples thereof include polyolefin ionomers, (meth)acrylic ionomers, polystyrene ionomers, and polyester ionomers. These ionomers may be used alone or in combination of two or more.

[0046] The polyolefin ionomer is not particularly limited, but examples thereof include ethylene-methacrylate copolymer, ethylene-acrylate copolymer, and ethylene-methacrylate-acrylate copolymer.

[0047] The (meth)acrylic ionomer is not particularly limited, but examples thereof include an acrylic acid ester-acrylate copolymer, an acrylic acid ester-methacrylate copolymer, a methacrylic acid ester-acrylate copolymer, and a methacrylic acid ester-methacrylate copolymer.

[0048] The polystyrene ionomer is not particularly limited, but examples thereof include a styrene-styrene sulfonate copolymer, a styrene-acrylate copolymer, a styrene-methacrylate copolymer, a styrene-styrene carboxylate copolymer, and a styrene-N-methyl 4-vinylpyridinium salt copolymer.

[0049] The polyester ionomer is not particularly limited, but examples thereof include sulfoterephthalic acid salt copolymerized polyethylene terephthalate, sulfoisophthalic acid salt copolymerized polyethylene terephthalate, sulfoterephthalic acid copolymerized polybutylene terephthalate, and sulfoisophthalic acid copolymerized polybutylene terephthalate.

[0050] The metal ions constituting the salt of the ionomer resin are not particularly limited, but examples thereof include monovalent metal ions such as sodium ions and lithium ions; divalent metal ions such as zinc ions, calcium ions, and magnesium ions; and trivalent metal ions such as aluminum ions, with zinc ions being preferred. The polymer and metal ions in the ionomer resin can be used in any combination based on the ionic functional group in the polymer and the valence of the metal ions.

[0051] The base layer 10 has an MFR (melt mass flow rate) measured in accordance with JIS K7210 under conditions of 125°C and a load of 10.0 kg of preferably 1 to 20 g / 10 min, 2 to 15 g / 10 min, or 3 to 10 g / 10 min. When the MFR of the base layer 10 is within the above range, warpage of the wafer 2 tends to be further reduced.

[0052] The softening point of the base layer 10 is preferably 30 to 200° C., 35 to 175° C., or 40 to 150° C. When the softening point of the base layer 10 is within the above range, warpage of the wafer 2 tends to be further reduced.

[0053] The ionomer content in the base layer 10 is preferably 80 to 100 mass %, 85 to 98 mass %, or 90 to 95 mass %, based on the entire base layer 10.

[0054] The substrate layer 10 may contain additives other than the above-mentioned materials as needed. Examples of additives include, but are not limited to, plasticizers, heat stabilizers, colorants, organic lubricants, inorganic lubricants, surfactants, processing aids, and antistatic agents. The additives may be used alone or in combination.

[0055] The content of the additives relative to the entire base layer 10 is preferably 0.1 to 10.0 mass %, 0.5 to 5.0 mass %, or 1.0 to 2.5 mass %.

[0056] The substrate layer 10 may be a single layer or multi-layer structure comprising the materials described above.

[0057] 1.2. Adhesive layer The wafer processing tape 1 of this embodiment may have an adhesive layer. The adhesive layer contributes to adhesion between the wafer 2 and the wafer processing tape 1. The adhesive layer may have an opening with a diameter smaller than the diameter of the wafer 2. When the adhesive layer has such an opening, an area of ​​the element forming surface 21 of the wafer 2 where no elements are present is attached to the adhesive layer so that the area of ​​the element forming surface 21 where elements are present is positioned within the opening. In this case, the area of ​​the element forming surface 21 where elements are present does not come into contact with the adhesive layer, which tends to prevent adhesive residue in that area.

[0058] The thickness of the adhesive layer is preferably 1 to 100 μm, 5 to 75 μm, 10 to 70 μm, 15 to 60 μm, or 20 to 50 μm.

[0059] The adhesive layer may contain a (meth)acrylate polymer, and preferably contains a (meth)acrylate polymer and a crosslinking agent.

[0060] 1.2.1. (Meth)acrylate polymers The (meth)acrylate monomer contained in the (meth)acrylate polymer is not particularly limited, and examples thereof include butyl (meth)acrylate, 2-butyl (meth)acrylate, t-butyl (meth)acrylate, pentyl (meth)acrylate, octyl (meth)acrylate, 2-ethylhexyl (meth)acrylate, nonyl (meth)acrylate, decyl (meth)acrylate, lauryl (meth)acrylate, methyl (meth)acrylate, ethyl (meth)acrylate, isopropyl (meth)acrylate, tridecyl (meth)acrylate, myristyl (meth)acrylate, cetyl (meth)acrylate, stearyl (meth)acrylate, cyclohexane (meth)acrylate, and the like. Examples of (meth)acrylic monomers such as hexyl (meth)acrylate, benzyl (meth)acrylate, dimethylacrylamide, diethylacrylamide, acryloylmorpholine, and isobornyl acrylate, and functional group-containing monomers include 2-hydroxyethyl (meth)acrylate, 2-hydroxypropyl (meth)acrylate, and 2-hydroxybutyl (meth)acrylate, which have a hydroxyl group; (meth)acrylic acid, crotonic acid, maleic acid, itaconic acid, fumaric acid, acrylamido-N-glycolic acid, and cinnamic acid, which have a carboxyl group; and allyl glycidyl ether and (meth)acrylic acid glycidyl ether, which have an epoxy group.

[0061] The content of the (meth)acrylate polymer is preferably 80 to 100 mass %, 85 to 99.5 mass %, or 90 to 99.0 mass %, relative to the total amount of the adhesive layer.

[0062] The glass transition temperature (Tg) of the (meth)acrylate polymer is preferably from -30 to 5°C, and more preferably from -25 to -5°C.

[0063] 1.2.2. Crosslinking Agents Examples of crosslinking agents include polyfunctional isocyanate crosslinking agents, polyfunctional epoxy crosslinking agents, etc. When the crosslinking agent reacts with the functional group, a crosslinked structure is formed with the functional group as the base point, which increases the cohesive strength of the adhesive and tends to reduce the contamination of the wafer processing tape 1.

[0064] The content of the crosslinking agent is preferably 0.1 to 10.0 mass %, 0.5 to 8.0 mass %, or 1.0 to 6.0 mass %, relative to the total amount of the adhesive layer.

[0065] In the adhesive layer, the mass ratio of the crosslinking agent to the (meth)acrylate polymer (mass of crosslinking agent / mass of (meth)acrylate polymer) is preferably 0.1 to 10.0 mass%, 0.5 to 8.0 mass%, or 1.0 to 6.0 mass%.

[0066] 2. Manufacturing method of wafer processing tape The method for producing the wafer processing tape 1 of this embodiment is not particularly limited, but the following method may be mentioned, for example.

[0067] The means for forming the substrate layer 10 is not particularly limited, but the above-mentioned various materials are mixed using a conventional melt kneader or various mixing devices (single-screw or twin-screw extruder, roll, Banbury mixer, various kneaders, etc.) so that the components are uniformly dispersed, and the mixture is formed into the substrate by the T-die method, calendar method, or inflation method. Preferably, the T-die method using an extruder with good thickness accuracy is used.

[0068] The base layer 10 is preferably subjected to a heat treatment step in which it is heated for 3 minutes or more at a temperature of 100°C or more. As a result, the shrinkage work W of the base layer 10 at 120°C is 120 As a result, the warpage of the wafer 2 tends to be suppressed and further reduced.

[0069] The heating time in the heat treatment step is preferably 1 to 30 minutes, 1 to 20 minutes, or 1 to 10 minutes. The heating temperature in the heat treatment step is preferably 50°C to 300°C, 60 to 200°C, or 70 to 150°C. The conditions for the heat treatment step are preferably 1 to 30 minutes and 50 to 300°C.

[0070] The means for forming the adhesive layer is not particularly limited, but the adhesive layer may be formed by dissolving the various materials in a solvent such as an organic solvent to form a varnish, applying this to the base layer 10 by knife coating, roll coating, spray coating, gravure coating, bar coating, curtain coating, or the like, and then removing the solvent.The adhesive layer may be formed on the base layer 10 by applying the varnished various materials to a molding film and removing the solvent to form an adhesive layer, and then laminating this on the base layer 10.

[0071] Alternatively, the various materials may be mixed without using a solvent, and the mixture may be applied onto the base layer 10 by screen printing or the like to form an adhesive layer.

[0072] 3.Wafer processing method The wafer processing method of this embodiment includes a bonding process s101 in which a wafer processing tape 1 is bonded to the element forming surface 21 of a wafer 2, a back-grinding process s102 in which a non-element forming surface 22 of the wafer 2 bonded to the wafer processing tape 1 is polished, and a dicing process s103 in which the wafer 2 bonded to the wafer processing tape 1 is diced after the back-grinding process s102.

[0073] The wafer processing method of this embodiment tends to achieve both improved efficiency in the wafer processing process by using the same tape for the backgrinding step s102 and the dicing step s103, and improved divisibility of the wafer 2, by using the wafer processing tape 1.

[0074] Each step of the wafer processing method of this embodiment will be described in detail below.

[0075] 3.1. Bonding process In the wafer processing method of this embodiment, first, the wafer processing tape 1 is attached to the element-forming surface 21 of the wafer 2. For example, the first surface 11 of the base layer 10 may be attached to the element-forming surface 21 of the wafer 2. If the wafer processing tape 1 has an adhesive layer, the exposed surface of the wafer processing tape 1 on the first surface 11 side may be attached to the element-forming surface 21 of the wafer 2. This exposed surface may be the surface of the adhesive layer opposite the base layer 10. Alternatively, if the adhesive layer has an opening with a diameter smaller than the diameter of the wafer 2, the exposed surface may include the adhesive layer and the area within the opening of the first surface 11. Alternatively, the area of ​​the element-forming surface 21 of the wafer 2 where no elements are present may be attached to the adhesive layer so that the area of ​​the element-forming surface 21 where elements are present comes into contact with the area within the opening of the first surface 11.

[0076] In the bonding step, in order to improve adhesion between the wafer processing tape 1 and the wafer 2, it is preferable to heat the wafer processing tape 1 to a high temperature and then bond it to the wafer 2. In this case, the wafer processing tape 1 is heated to, but not limited to, a temperature of 80 to 200°C, for example, more specifically, 120°C or 150°C.

[0077] 3.2.Back grinding process Fig. 3A shows an example of a perspective view of the back-grinding step s102, and Fig. 3B shows an example of a cross-sectional view taken along line A-A' in Fig. 3A. As shown in Fig. 3A and Fig. 3B, in the back-grinding step s102, the non-element forming surface 22 of the wafer 2 is polished by a polishing machine P to thin the wafer 2.

[0078] 3.3.Dicing process The wafer processing method of this embodiment includes a dicing step s103 in which a wafer 2 bonded to a wafer processing tape 1 is diced. FIG. 4A shows an example of a perspective view of the dicing step s103, and FIG. 4B shows an example of a cross-sectional view taken along line A-A' in FIG. 4A. Note that FIGS. 4A and 4B show an example of a dicing method in which laser dicing is used, in which a laser is irradiated onto the wafer 2. The dashed lines in FIG. 4A indicate the path of the laser irradiated portion, and in a subsequent step of forming die chips, the wafer 2 is divided along the dashed line portions. L in FIG. 4A is a laser source.

[0079] When laser dicing is employed in the dicing step s103, as shown in Figures 4A and 4B, a laser is irradiated onto the wafer 2 to generate a modified region 24 inside the wafer 2. More specifically, in the dicing step s103, it is preferable to focus a pulsed laser on the inside of the wafer 2 to form the modified region 24 inside the wafer 2. At this time, it is preferable that the modified region 24 does not appear on the surface of the wafer 2. Laser dicing that forms the modified region 24 inside the wafer 2 is also called stealth dicing.

[0080] The laser source is not particularly limited, but examples thereof include ultraviolet lasers, visible light lasers, near-infrared lasers, and far-infrared lasers. More specifically, for example, an Nd:YAG laser can be used.

[0081] In this embodiment, since the wafer processing tape 1 is attached to the element forming surface 21 during the dicing step s103, it is preferable that the surface of the wafer 2 that is irradiated with the laser is the non-element forming surface 22.

[0082] The dicing method in the dicing step s103 is not limited to laser dicing, but may be blade dicing using a blade, plasma dicing using plasma, etc. Regardless of which dicing method is selected, the surface area of ​​the wafer 2 after the dicing step s103 tends to be larger than the surface area of ​​the wafer 2 before the dicing step s103.

[0083] 3.4. Peeling process The wafer processing method of this embodiment may include a peeling step s104 after the dicing step s103, in which the wafer processing tape 1 is heated and peeled off. In the peeling step s104, the wafer processing tape 1 is peeled off from the wafer 2 while being heated. The peeling step s104 is performed after the dicing step s103.

[0084] In the peeling step s104, from the viewpoint of improving peelability, the wafer processing tape 1 may be heated when peeling the wafer processing tape 1 from the wafer 2. When the above heating is performed, the wafer processing tape 1 is preferably heated to a temperature of 25°C or higher, more preferably heated to a temperature of 25°C or higher and 70°C or lower, and even more preferably heated to a temperature of 30°C or higher and 60°C or lower.

[0085] Although the wafer processing method has been exemplified above, the wafer processing tape 1 of this embodiment may be used to process an adherend such as a semiconductor package instead of a wafer. [Example]

[0086] The present invention will be described in more detail below using examples and comparative examples. The present invention is not limited to the following examples. Unless otherwise specified, experiments in each example and comparative example were carried out at room temperature (23°C) and 1 atmosphere.

[0087] [Example 1] A polyolefin ionomer (Fanclear HMD (product name) manufactured by Gunze Ltd., containing 15% by mass of methacrylic acid units), which is a metal ion crosslinked ethylene-methacrylic acid copolymer, was molded to a thickness of 80 μm to obtain a molded article. This molded article was subjected to heat treatment at 100°C for 3 minutes to obtain the wafer processing tape of Example 1. The polyolefin ionomer had an MFR (melt mass flow rate) of 5 g / 10 min measured in accordance with JIS K7210 under conditions of 125°C and a load of 10.0 kg. The softening point was also 72°C.

[0088] [Comparative Example 1] A polyolefin ionomer (Fanclear HMD (product name) manufactured by Gunze Ltd.), which is a metal ion crosslinked ethylene-methacrylic acid copolymer, was molded to a thickness of 80 μm to obtain a wafer processing tape of Comparative Example 1.

[0089] Comparative Example 2 A polyolefin ionomer (Fanclea HMD (product name) manufactured by Gunze Ltd.), which is a metal ion crosslinked ethylene-methacrylic acid copolymer, was molded to a thickness of 150 μm to obtain a wafer processing tape of Comparative Example 2.

[0090] [Measurement of contractile work] Each wafer processing tape was cut into a rectangular parallelepiped shape with a width of 20 mm and a length of 25 mm to prepare a test specimen. The obtained test specimen was then set in a TP-501 (product name) manufactured by Tester Sangyo Co., Ltd. in an environment of 23°C, and both ends in the longitudinal direction were fixed with a chuck distance of 20 mm. The test specimen was then placed in an oil bath heated to a temperature of T°C, and the time when the test specimen was placed in the oil bath was set to t=0 s, and the contraction load (N / 20 mm) was measured after a certain time had elapsed. When T=60°C, the contraction load measured at t=10 s was defined as the contraction load K 60 (N / 20mm). When T=120°C, the shrinkage load measured at t=5s was the shrinkage load K 120 (N / 20mm). The shrinkage load K at 23°C 23 is 0 (N / 20mm).

[0091] Furthermore, rectangular parallelepiped test pieces were prepared by cutting each wafer processing tape to a width of 100 mm and a length of 100 mm so that the width and length directions were the same as those in the measurement of the shrinkage load. An 80 mm line was then drawn in the length direction. The tape was then heated for 30 minutes at a temperature T of 60°C or 120°C. After 30 minutes of heating, the wafer processing tape of each example reached the same temperature as the heating temperature. After that, the length B of the line was measured. T The shrinkage amount A at T°C was measured. T The shrinkage amount A (mm) was calculated. T was calculated using the following formula: The length of the line at 23°C, B 23 is 80mm. Shrinkage A T (mm) = (80 - B T )

[0092] The shrinkage work W at T = 60 ° C and 120 ° C is calculated using the following formula: T (mJ / 20mm) was calculated. Contraction work W T = contraction load K T × Shrinkage A T

[0093] [Measurement of length change rate] Each wafer processing tape was cut into a length of 100 mm and a width of 100 mm to prepare a rectangular parallelepiped test piece. An 80 mm line was then drawn in the horizontal direction. The tape was then heated for 30 minutes at a temperature of T = 60°C, 90°C, or 120°C. After 30 minutes of heating, the wafer processing tape of each example reached the same temperature as the heating temperature. Then, the length C of the line was measured. T (mm) was measured. The length change rate R at T°C was T (mm / mm) was calculated. T was calculated using the following formula: The length of the line at 23°C, C 23 is 80mm. Length change rate R T (%)=|(80-C T ) / 80|×100

[0094] Table 1 shows the measurement results of contraction work, contraction load, and rate of length change.

[0095] [Table 1]

[0096] When the wafer processing tape of each example was used, the amount of warpage of the wafer was measured according to the following method. The wafer processing tape for each example was attached to an 8-inch silicon mirror wafer (Nagano Electronics Co., Ltd., product name: 8-inch dummy wafer), and the wafer thickness was thinned to 110 μm using a back grinder (Disco Corporation, product name: DFG850). Then, using a stealth dicing device (Tokyo Seimitsu Co., Ltd., product name: ML300PlusIIIFH), the entire wafer was subjected to stealth dicing so that the chip size was 250 μm square. After stealth dicing, the wafer was left undisturbed on a horizontal table for 24 hours. After leaving the wafer undisturbed, the maximum warpage of the wafer was measured using a scale, and this was taken as the amount of warpage of the wafer.

[0097] The amount of warpage of the wafer was evaluated based on the following evaluation criteria. Table 2 shows the evaluation results for the amount of warpage of the wafer. ◯: Suitable for practical use. [Evaluation criteria] ◯: The amount of warping is less than 5 mm. △: The amount of warpage is 5 mm or more and less than 10 mm. ×: The amount of warpage is 10 mm or more.

[0098] [Table 2] [Explanation of symbols]

[0099] 1...wafer processing tape, 10...base material layer, 11...first surface, 12...second surface, 2...wafer, 21...element-formed surface, 22...non-element-formed surface, 23...element, 24...modified portion

Claims

1. A substrate layer is provided, The shrinkage work W of the base material layer at 120°C in at least one direction in the plane of the base material layer 120 is 8 mJ / 20 mm or less, Tape for wafer processing.

2. The shrinkage load K of the base material layer at 120°C 120 is 0.15N / 20mm or less, The wafer processing tape according to claim 1 .

3. The shrinkage load K of the base material layer at 60°C 60 is 0.05N / 20mm or less, The wafer processing tape according to claim 1 .

4. a length change rate of the base material layer at 120°C of 40% or less in at least one direction in the plane of the base material layer; The wafer processing tape according to claim 1 .

5. The thickness of the substrate layer at 23°C is 50 to 250 μm. The wafer processing tape according to claim 1 .

6. The substrate layer comprises an ionomer. The wafer processing tape according to claim 1 .

7. a back-grinding step of grinding a non-element-formed surface of the wafer attached to the wafer processing tape; and a dicing step of dicing the wafer attached to the wafer processing tape after the back-grinding step, The wafer processing tape according to claim 1 .

8. A heat treatment step of heating the base layer for 3 minutes or more at a temperature of 100°C or more is included. A method for producing the tape for wafer processing according to any one of claims 1 to 7.

9. a bonding step of bonding the wafer processing tape according to any one of claims 1 to 7 to the element-forming surface of the wafer; a back grinding step of grinding a non-element forming surface of the wafer bonded to the wafer processing tape; a dicing step of dicing the wafer bonded to the wafer processing tape after the back-grinding step; Wafer processing method.

10. In the dicing step, a modified portion is generated inside the wafer by laser dicing. The wafer processing method according to claim 9.

11. a peeling step of heating and peeling off the wafer processing tape after the dicing step; The wafer processing method according to claim 9.

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