Nonvolatile semiconductor memory device

Abstract

To provide a nonvolatile semiconductor memory device which can be highly laminated at a low cost.SOLUTION: According to the embodiment, the nonvolatile semiconductor memory device includes the plurality of first wiring layers 14 stacked apart from each other, the memory pillar MP passing through the plurality of first wiring layers, the local bit line LBL connected to the memory pillar, the bit line BL, the plurality of second wiring layers 14 stacked apart from each other, the first pillar WP passing through the plurality of second wiring layers and connected to the local bit line, the second pillar WP passing through the plurality of second wiring layers, connected to the bit line, and connected to the first pillar, the plurality of third wiring layers 14 stacked apart from each other, and the third pillar RP passing through the plurality of third wiring layers and connected to the bit line. At least one of the plurality of third wiring layers is connected to the local bit line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a nonvolatile semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A three-dimensional stacked NAND flash memory in which memory cells are arranged three-dimensionally is known as one type of nonvolatile semiconductor memory device. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] H. Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology, IEEE, 2007, p. 14-15. [Non-patent document 2] Jeehoon Han et al., “Fundamental Issues in VNAND Integration Toward More Than 1K Layers”, 2023 IEEE IEDM, S35-1, Dec. 2023. Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a nonvolatile semiconductor memory device that allows high stacking at low cost. [Means for solving the problem]

[0005] The nonvolatile semiconductor memory device according to the embodiment includes a plurality of first wiring layers extending in a first direction and stacked at a distance from each other in a second direction intersecting the first direction; a memory pillar extending in the second direction and passing through the plurality of first wiring layers; a local bit line provided at one end side of the plurality of first wiring layers in the second direction and spaced from the plurality of first wiring layers, extending in a third direction intersecting the first and second directions, and electrically connected to one end side of the memory pillar in the second direction; a bit line provided at one end side of the local bit line in the second direction and spaced from the local bit line, extending in the third direction; and a plurality of memory pillars extending in the first direction and stacked at a distance from each other in the second direction. The semiconductor memory device includes a plurality of second wiring layers arranged side by side with a plurality of first wiring layers in the third direction, a first pillar extending in the second direction and passing through the plurality of second wiring layers, and having a local bit line electrically connected to one end side in the second direction, a second pillar extending in the second direction and passing through the plurality of second wiring layers, and having a bit line electrically connected to one end side in the second direction and electrically connected to the first pillar, a plurality of third wiring layers extending in the first direction and stacked at a distance from each other in the second direction and arranged side by side with the plurality of first wiring layers in the third direction, and a third pillar extending in the second direction and passing through the plurality of third wiring layers, and having a bit line electrically connected to one end side in the second direction. At least one of the plurality of third wiring layers is electrically connected to the local bit line. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is an equivalent circuit diagram of a gain block according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a memory cell array according to the first embodiment. [Figure 3] FIG. 2 is a cross-sectional view of the gain block according to the first embodiment in the bit line direction. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a write port section according to the first embodiment. [Figure 5A] FIG. 2 is a plan view showing a first example of a planar layout of a read port portion according to the first embodiment. [Figure 5B] FIG. 10 is a plan view showing a second example of the planar layout of the read port portion according to the first embodiment. [Figure 6A] 5 is a cross-sectional view of the write port portion taken along the lines A1-A2 and B1-B2 in FIG. 4. [Figure 6B] 5B is a cross-sectional view of the lead port portion taken along the lines C1-C2 and D1-D2 in FIG. 5A. [Figure 7A] FIG. 2 is a layout diagram showing an example of a chip configuration of the nonvolatile semiconductor memory device according to the first embodiment. [Figure 7B] FIG. 3 is a cross-sectional view of a WL terrace corresponding to a cell block according to the first embodiment. [Figure 7C] 3A and 3B are diagrams showing an example of bonding an array chip and a CMOS chip in the nonvolatile semiconductor memory device according to the first embodiment. [Figure 7D] 2 is a diagram showing an example of a cross-sectional configuration of a memory cell array process layer and a transistor section thereunder in the nonvolatile semiconductor memory device according to the first embodiment. [Figure 8] 10 is a graph showing the relationship between the number of gain blocks (number of bit line divisions) per bit line layer of a memory cell array, the number of stacked word lines, and the proportion of overhead due to the gain blocks relative to the memory cell array. [Figure 9] FIG. 10 is a diagram showing a comparison of chip sizes between a comparative example and an embodiment when the processing speed is increased by four times. [Figure 10] FIG. 10 is a diagram showing a comparison of chip sizes between a comparative example and an embodiment in the case where the memory capacity is increased four times. [Figure 11] FIG. 1 shows the relationship between the number of gain blocks per bit line layer of a memory cell array, (a) read latency (tR), and (b) chip size. [Figure 12] This figure shows the relationship between memory capacity and chip size under constant speed conditions when the memory capacity is increased by stacking word lines in a 3D-NAND flash memory. [Figure 13] This figure shows the relationship between memory capacity and cost per gigabyte (GB) when memory capacity is increased by stacking word lines in 3D-NAND flash memory. [Figure 14A] FIG. 10 is a plan view showing a first example of a planar layout of a read port section according to the second embodiment. [Figure 14B] FIG. 10 is a plan view showing a second example of the planar layout of the read port portion according to the second embodiment. [Figure 14C] FIG. 10 is a cross-sectional view of a read port portion according to the second embodiment in the bit line direction. [Figure 15] FIG. 11 is an equivalent circuit diagram of a gain block according to the third embodiment. [Figure 16] FIG. 11 is a cross-sectional view of a gain block according to a third embodiment in the bit line direction. [Figure 17A] FIG. 11 is a cross-sectional view of a write port section according to the third embodiment in the word line direction. [Figure 17B] FIG. 11 is a cross-sectional view of a read port portion according to the third embodiment in the word line direction. [Figure 18] FIG. 10 is an equivalent circuit diagram of a gain block according to a fourth embodiment. [Figure 19] FIG. 10 is a cross-sectional view of a gain block according to a fourth embodiment in the bit line direction. [Figure 20A] FIG. 10 is a cross-sectional view of a write port section according to the fourth embodiment in the word line direction. [Figure 20B] FIG. 10 is a cross-sectional view of a read port portion according to the fourth embodiment in the word line direction. [Figure 21A] FIG. 11 is a simplified equivalent circuit diagram of a gain block according to a fifth embodiment. [Figure 21B] 13 is a timing chart showing an example of voltages on each wiring in a write operation of the nonvolatile semiconductor memory device according to the fifth embodiment. [Figure 21C] 13 is a timing chart showing an example of voltages on each wiring in a read operation of the nonvolatile semiconductor memory device according to the fifth embodiment. [Figure 22A] 13 is a timing chart showing an example of voltages on each wiring when a read operation is performed with reduced coupling noise between local bit lines in the nonvolatile semiconductor memory device according to the sixth embodiment. [Figure 22B] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure for reducing coupling noise between local bit lines in a nonvolatile semiconductor memory device according to a sixth embodiment. [Figure 23] FIG. 13 is a plan view showing an example of a planar layout of a write port section according to the sixth embodiment. [Figure 24] 13 is a timing chart showing an example of voltages on each wiring when a read operation is performed with reduced coupling noise between local bit lines in the nonvolatile semiconductor memory device according to the seventh embodiment. [Figure 25A] 13 is a timing chart showing an example of a method for measuring the threshold voltage of the amplifying transistor according to the eighth embodiment. [Figure 25B] 13 is a timing chart showing a method for increasing the threshold voltage of the amplification transistor according to the eighth embodiment. [Figure 25C] 13 is a timing chart showing a method for lowering the threshold voltage of the amplification transistor according to the eighth embodiment. [Figure 26A] 13 is a timing chart showing a first example of a method for increasing the threshold voltage of an amplifying transistor according to the ninth embodiment. [Figure 26B] 13 is a timing chart showing a second example of a method for increasing the threshold voltage of the amplification transistor according to the ninth embodiment. [Figure 27A] 20 is a timing chart showing a method for increasing the threshold voltage of an amplifying transistor according to a tenth embodiment. [Figure 27B] 20 is a timing chart showing a method for lowering the threshold voltage of the amplification transistor according to the tenth embodiment. [Figure 28A] FIG. 23 is a plan view showing a first example of a planar layout of a read port section according to the eleventh embodiment. [Figure 28B] FIG. 23 is a plan view showing a second example of the planar layout of the read port portion according to the eleventh embodiment. [Figure 29] FIG. 23 is a cross-sectional view of a gain block according to a twelfth embodiment in the bit line direction. [Figure 30] FIG. 23 is a cross-sectional view of a gain block according to the thirteenth embodiment in the bit line direction. [Figure 31] 23A and 23B are diagrams showing an example of a cross-sectional structure in the bit line direction of a gain block in an array chip included in a nonvolatile semiconductor memory device according to a fourteenth embodiment, and an example of a circuit configuration of a CMOS chip connected to a local bit line. [Figure 32A] FIG. 1 is a cross-sectional view of a memory cell array applicable to an embodiment. [Figure 32B] 32B is a cross-sectional view taken along line E1-E2 in FIG. 32A. [Figure 32C] FIG. 2 is a plan view showing a first example of a planar layout of a memory cell array applicable to the embodiment. [Figure 32D] FIG. 10 is a plan view showing a second example of a planar layout of a memory cell array applicable to the embodiment. [Figure 33A] 10 is a graph comparing the mobility of silicon required when the number of stacked word lines of a 3D-NAND flash memory is increased between a comparative example and an example. [Figure 33B] FIG. 33B is a circuit diagram showing an example of the circuit configuration of a memory cell string used in the calculation of FIG. 33A. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numeral. Furthermore, when multiple components having the same reference numeral are to be distinguished from one another, a subscript will be added to the common reference numeral. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference numeral, without a subscript. Here, subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase letters added to the end of a reference numeral, and indexes indicating an array.

[0008] Before describing the embodiments of the present invention, an example of a memory cell structure assumed to be applied to the embodiments will be described below with reference to FIGS. 32A, 32B, 32C, and 32D. FIG. 32A is a cross-sectional view showing an example of a memory cell array applicable to the embodiments. FIG. 32B is a cross-sectional view taken along line E1-E2 in FIG. 32A. The example shown in FIG. 32B shows a cross-sectional structure of a memory cell cut along a word line. FIG. 32C is a plan view showing a first example of a planar layout of a memory cell array applicable to the embodiments. FIG. 32D is a plan view showing a second example of a planar layout of a memory cell array applicable to the embodiments. In the following description, the extension direction of word lines (described later) that is parallel to the substrate (silicon substrate) will be referred to as the "X direction" or "word line direction." The extension direction of bit lines (described later) that is parallel to the substrate, intersects the X direction, and is referred to as the "Y direction" or "bit line direction." The direction perpendicular to the XY plane parallel to the substrate will be referred to as the "Z direction." Since multiple word lines are stacked in the Z direction, the Z direction is also referred to as the "stacked layer direction." When limiting the direction from the substrate to the stacked layer in the Z direction, it is also referred to as the "upper direction" or "one end side of the Z direction," and when limiting the direction from the stacked layer to the substrate in the Z direction, it is also referred to as the "lower direction" or "the other end side of the Z direction."

[0009] First, the cross-sectional structure of a memory cell will be described with reference to FIGS. 32A and 32B.

[0010] As shown in FIG. 32A, the memory cell array includes insulating layers 11, 13, and 15, a semiconductor layer 12, a wiring layer 14, a memory pillar MP, a contact plug CP1, a member SLT, and a member SHE1.

[0011] A semiconductor layer 12 is provided on the insulating layer 11. The semiconductor layer 12 has a plate shape extending along the XY plane. The semiconductor layer 12 contains, for example, silicon (Si). The semiconductor layer 12 also contains, for example, phosphorus (P) as a semiconductor impurity. The semiconductor layer 12 functions, for example, as a source line SL, which will be described later.

[0012] An insulating layer 13 is provided on the semiconductor layer 12. A plurality of wiring layers 14 and a plurality of insulating layers 15 are alternately stacked on the insulating layer 13. In other words, the plurality of wiring layers 14 are stacked at intervals in the Z direction. The plurality of wiring layers 14 are also simply referred to as "stacking layers."

[0013] 32A, the stacked layers include 2009 wiring layers 14. The multiple wiring layers 14 function, from the side farthest from the semiconductor layer 12 (source line SL) (upper layer), as three layers of string select signal lines SGDT, three layers of string select signal lines SGD, 2000 layers of word lines WL0 to WL1999, and three layers of string select signal lines SGS, respectively.

[0014] The word lines WL are gate lines of the memory cells. Hereinafter, when limiting the wiring layer 14 that functions as the word lines WL, the wiring layer 14 will also be referred to as a "word line layer." The number of word line WL layers is arbitrary. It is sufficient that one or more word line WL layers are provided.

[0015] The string selection signal lines SGS, SGD, and SGDT are gate lines of the string selection transistors. Hereinafter, when limiting the wiring layer 14 that functions as the string selection signal lines SGS, SGD, and SGDT, the wiring layer 14 is also referred to as a "string selection signal layer." Note that the string selection signal lines SGS, SGD, and SGDT are optional. It is sufficient that one or more layers of each of the string selection signal lines SGS, SGD, and SGDT are provided.

[0016] The insulating layers 13 and 15 include, for example, silicon oxide (SiO). The conductive material of the wiring layer 14 is, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). In this case, the titanium nitride is formed so as to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of tungsten when forming a tungsten film by, for example, CVD (Chemical Vapor Deposition), or as an adhesion layer to improve the adhesion of tungsten. The wiring layer 14 may also include a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed so as to cover the conductive material. The high-dielectric-constant material is provided at least between a memory pillar MP (described later) and the conductive material of the wiring layer 14.

[0017] In the example shown in FIG. 32A, a memory hole MH is formed that penetrates (passes through) the 2009 wiring layers 14 (i.e., stacked layers). The bottom surface of the memory hole MH (i.e., memory pillar MP) reaches the semiconductor layer 12. For example, the memory hole MH has a substantially cylindrical shape extending in the Z direction. The memory pillar MP is formed by filling the memory hole MH. That is, the memory pillar MP has a substantially cylindrical shape extending in the Z direction.

[0018] A memory cell is formed by combining a memory pillar MP with a wiring layer 14 (i.e., a word line layer) that functions as a word line WL. In other words, a memory cell having the word line layer as its gate electrode is formed. Similarly, a string selection transistor is formed by combining a memory pillar MP with a wiring layer 14 (i.e., a string selection signal layer) that functions as a string selection signal line SGS, SGD, or SGDT. In other words, a string selection transistor having the string selection signal layer as its gate electrode is formed. Multiple memory cells MC and multiple string selection transistors formed by one memory pillar MP are connected in series to form a memory cell string. Therefore, one memory pillar MP functions as one memory cell string. Note that the memory pillar MP may have a structure in which multiple pillars are connected in the Z direction.

[0019] The memory pillar MP includes a core film 20 , a silicon channel layer 21 , and a stacked film 22 .

[0020] The core film 20 extends in the Z direction. For example, the core film 20 has a generally cylindrical shape extending in the Z direction. For example, the upper end of the core film 20 is located above the uppermost wiring layer 14, and the lower end is located below the lowermost wiring layer 14. The core film 20 includes an insulator such as silicon oxide.

[0021] The silicon channel layer 21 extends in the Z direction and covers the side, top (surface facing one end in the Z direction) and bottom of the core film 20. For example, the bottom surface of the silicon channel layer 21 contacts the semiconductor layer 12. The silicon channel layer 21 is used as a channel (current path) of the memory cell and the string select transistor. The silicon channel layer 21 contains silicon.

[0022] The laminated film 22 extends in the Z direction and covers the side surfaces of the silicon channel layer 21. For example, the laminated film 22 has a substantially cylindrical shape extending in the Z direction. The outer side surface of the laminated film 22 contacts the memory hole MH. The inner side surface of the laminated film 22 contacts the silicon channel layer 21.

[0023] As shown in FIG. 32B, the stacked film 22 includes, for example, a tunnel insulating layer 221, a charge trapping layer 222, and a block insulating layer 223.

[0024] In a cross section including the wiring layer 14 along the XY plane, the core film 20 is provided, for example, in the center of the memory pillar MP. The silicon channel layer 21 surrounds the outer periphery (side surface) of the core film 20. The tunnel insulating layer 221 surrounds the outer periphery (side surface) of the silicon channel layer 21. The charge trapping layer 222 surrounds the outer periphery (side surface) of the tunnel insulating layer 221. The block insulating layer 223 surrounds the outer periphery (side surface) of the charge trapping layer 222. The wiring layer 14 surrounds the outer periphery (side surface) of the block insulating layer 223. The outer periphery (side surface) of the block insulating layer 223 contacts the wiring layer 14.

[0025] The tunnel insulating layer 221 and the block insulating layer 223 contain, for example, silicon oxide. The charge trapping layer 222 has a function of storing charges. The memory cell may be an FG (Floating Gate) type or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type. The FG type uses a conductor for the charge trapping layer 222. The MONOS type uses an insulating layer (e.g., containing silicon nitride (SiN)) for the charge trapping layer 222. Note that, for example, when aluminum oxide is used as a high-dielectric-constant material for the wiring layer 14, the memory cell is also referred to as a MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type. The memory cell stores information based on a threshold voltage by releasing or injecting electrons into the charge trapping layer 222 due to FN (Fowler-Nordheim) tunneling.

[0026] 32A, a contact plug CP1 is provided on the silicon channel layer 21 of the memory pillar MP. The contact plug CP1 has, for example, a substantially cylindrical shape extending in the Z direction. The contact plug CP1 contains, for example, tungsten or copper (Cu) as a conductive material.

[0027] The member SLT separates multiple wiring layers 14 (i.e., stacked layers) in the Y direction. The wiring layers 14 separated by the member SLT extend in the X direction. That is, the word line layers and the string selection signal layers extend in the X direction. The member SLT includes a conductor LI and a spacer SP. The conductor LI has a plate-like shape extending along the XZ plane. For example, the bottom surface of the conductor LI contacts the semiconductor layer 12. That is, the conductor LI is connected to the source line SL. The spacer SP is provided to cover the side surface of the conductor LI. That is, the spacer SP is provided between the conductor LI and the wiring layer 14. The conductor LI and the wiring layer 14 are insulated by the spacer SP. The conductor LI contains, for example, tungsten as a conductive material. The spacer SP contains, for example, an insulator such as silicon oxide. Note that the conductor LI may be omitted. That is, the member SLT may be filled with an insulator.

[0028] The member SHE1 separates the wiring layers 14 that function as the string select signal lines SGD or SGDT in the Y direction and extends in the X direction. The member SHE1 separates at least the wiring layer 14 that is located farthest (the uppermost layer) from the semiconductor layer 12 among the multiple wiring layers 14. The lower end of the member SHE1 is located between the wiring layer 14 that functions as the string select signal line SGD and the wiring layer 14 that functions as the word line WL. The height of the member SHE1 in the Z direction is based on the number of wiring layers 14 that function as the string select signal lines SGDT and SGD. The member SHE1 includes an insulator such as silicon oxide.

[0029] As described above, multiple word line layers and multiple string selection signal layers are stacked above the semiconductor layer 12 (at one end in the Z direction, spaced apart from the semiconductor layer 12). A memory hole MH is opened, extending in the Z direction perpendicular to the substrate and penetrating (passing through) the multiple word line layers and multiple string selection signal layers. By forming a block insulating layer 223, a charge trapping layer 222, a tunnel insulating layer 221, and a silicon channel layer 21 on the sidewalls of each word line layer inside the memory hole MH, individual memory cells can be formed that store threshold voltages by injecting / ejecting electrons. Note that the memory cell's storage principle may utilize ferroelectric polarization in addition to charge injection and ejection. In this case, the block insulating layer 223 includes a ferroelectric material and performs polarization operation. Alternatively, the block insulating layer 223 and the charge trapping layer 222 may be replaced with ferroelectric layers.

[0030] This memory cell forms a memory cell string in which multiple memory cells, each with a gate electrode made of multiple word line layers, and multiple string selection transistors, each with a gate electrode made of multiple string selection signal layers, are connected in series in the stacking layer direction (Z direction). By processing multiple memory holes MH at once, it is possible to realize a series connection of many memory cells in the Z direction at low cost. In other words, a low-cost nonvolatile semiconductor memory device is realized.

[0031] Next, a first example of a planar layout of a memory cell array will be described.

[0032] As shown in FIG. 32C, in the region between two adjacent components SLT in the Y direction, multiple memory pillars MP are arranged side by side in the X direction, for example, with a width of 24 columns. The 24 columns of memory pillars MP are arranged in a staggered pattern so that the positions of memory pillars MP adjacent in the Y direction in the X direction are different from each other. Multiple memory pillars MP (multiple memory cells) provided between two adjacent components SLT are included in one cell block CB. The cell block CB is, for example, a collection of multiple memory cell strings (memory pillars MP) from which data is erased collectively. The number of cell blocks CB is arbitrary.

[0033] Between two elements SLT, multiple elements SHE1 extending in the X direction are arranged side by side in the Y direction. In the example shown in FIG. 32C, four elements SHE1 are provided. The area between two elements SLT or SHE1 adjacent in the Y direction corresponds to one string unit SU. That is, the cell block CB includes multiple string units SU. In the example shown in FIG. 32C, the cell block CB includes five string units SU0 to SU4. The string unit SU includes, for example, a set of multiple memory cell strings (memory pillars MP) that are collectively selected in a write operation or a read operation. The number of string units SU in the cell block CB is arbitrary.

[0034] In the example shown in FIG. 32C , within the string unit SU, multiple memory pillars MP are arranged side by side across four columns in the X direction. The four columns of memory pillars MP are arranged in a staggered pattern so that the X-directional positions of adjacent memory pillars MP in the Y direction are different from each other. A member SHE1 is provided on the fifth, tenth, fifteenth, and twentieth memory pillars MP from the left side of the page in FIG. 32C . The member SHE1 is provided so as to pass through the center of the memory pillars MP in the XY plane and divide the upper portions of the memory pillars MP. Therefore, the fifth, tenth, fifteenth, and twentieth memory pillars MP do not function as memory cell strings.

[0035] Next, a second example of the planar layout of the memory cell array will be described.

[0036] 32D, in the region between two adjacent members SLT in the Y direction, multiple memory pillars MP are arranged side by side in the X direction, for example, with a width of 20 columns. The 20 columns of memory pillars MP are arranged in a staggered pattern so that the X-direction positions of memory pillars MP adjacent to each other in the Y direction are different from each other.

[0037] In the example shown in FIG. 32D , a member SHE1 is provided between the fourth memory pillar MP and the fifth memory pillar MP from the left side of the page of FIG. 32D . Similarly, a member SHE1 is provided between the eighth memory pillar MP and the ninth memory pillar MP. A member SHE1 is provided between the twelfth memory pillar MP and the thirteenth memory pillar MP. A member SHE1 is provided between the sixteenth memory pillar MP and the seventeenth memory pillar MP. In this case, portions of the fourth, fifth, eighth, ninth, twelfth, thirteenth, sixteenth, and seventeenth memory pillar MPs may be cut by the member SHE1. These memory pillar MPs function as memory cell strings.

[0038] Next, with reference to FIGS. 33A and 33B, the relationship between the number of stacked word lines WL in a three-dimensional stacked NAND flash memory (also referred to as a "3D-NAND flash memory") and the silicon mobility required for a memory cell will be described. FIG. 33A is a graph comparing the silicon mobility required when the number of stacked word lines WL in a 3D-NAND flash memory is increased between a comparative example and an example of an embodiment. FIG. 33B is a circuit diagram showing an example of the circuit configuration of a memory cell string used in the calculation of FIG. 33A. In the following description, when the source and drain of a transistor are not specified, either the source or drain of the transistor will be referred to as "one end of the transistor," and the other of the source or drain of the transistor will be referred to as "the other end of the transistor."

[0039] First, an example of the circuit configuration of a memory cell string will be described with reference to FIG. 33B.

[0040] As shown in FIG. 33B, the memory cell string MSR includes a plurality of memory cells MC and string select transistors ST1 and ST2. In the example shown in FIG. 33B, the memory cell string MSR includes 162 memory cells MC0 to MC161. The current paths of the string select transistor ST1, memory cells MC0 to MC161, and string select transistor ST2 in the memory cell string MSR are connected in series. The drain of the string select transistor ST1 is connected to a bit line BL. The source of the string select transistor ST2 is connected to a source line SL. The control gates of the memory cells MC0 to MC161 are connected to word lines WL0 to WL161, respectively. The gate of the string select transistor ST1 is connected to a string select signal line SGD. The gate of the string select transistor ST2 is connected to a string select signal line SGS.

[0041] The word line WL and the string selection signal lines SGD and SGS are connected to different drivers DRV, respectively, which apply voltages used for various operations to the corresponding word line WL, string selection signal line SGD, or string selection signal line SGS.

[0042] One end of the bit line BL is connected to a page buffer PB. The page buffer PB is a read / write circuit. The page buffer PB also temporarily stores data used in write or read operations. The load capacitance of the bit line BL is denoted as CBL.

[0043] Next, with reference to FIG. 33A, the relationship between the number of stacked word line layers and the required mobility of silicon will be described.

[0044] Today, semiconductor memory is used everywhere, including cloud servers, mainframes, personal computers, home appliances, and mobile phones. Types of semiconductor memory available on the market include volatile DRAM (Dynamic Read Only Memory), SRAM (Static Read Only Memory), nonvolatile MROM (Mask Read Only Memory), NAND flash memory, NOR flash memory, and other flash EEPROMs (Electrically Erasable Programmable Read Only Memory). Three-dimensionally stacked NAND flash memory (3D-NAND flash memory) uses multiple word line layers and then multiple memory pillars (MPs) are formed simultaneously, reducing manufacturing costs. As a result, 1-Tb capacity 3D-NAND flash memory is currently being manufactured and is becoming the mainstream in the market, primarily for smartphones.

[0045] However, currently, the number of stacked word line layers is around 150 to 250 layers. Stacking more than this increases the number of series cells (the number of series-connected memory cells MC in a memory cell string MSR), resulting in a decrease in the cell current (Icell) flowing through the memory cell string MSR. For a given memory cell array size, the total number of memory cell strings connected to a bit line BL during a read operation remains constant. Since the load capacitance CBL is constant, increasing the number of series-connected cells reduces the current driving this load capacitance, resulting in a serious problem of significantly slowing down the read operation.

[0046] FIG. 33A is a diagram showing an overview of the effects of the embodiment. FIG. 33A shows the trend of silicon mobility (required Si mobility) required to maintain constant read performance while maintaining a constant bit line load capacitance CBL, assuming the number of word line layers (WL layer count) continues to increase for cost reduction, relative to the generation (year) on the horizontal axis. As shown in FIG. 33A, the required Si mobility increases in proportion to the number of word line layers. However, there are limitations to high-temperature silicon crystallization and Mic / Milc (Metal-induced Crystallization / Metal-induced Lateral Crystallization) technologies that reduce mobility degradation at polysilicon grain boundaries. It is estimated that silicon mobility is limited to approximately five times the current level. For this reason, the comparative example of the conventional method reaches a limit in the number of word line layers, i.e., cost reduction. In contrast, the embodiment incorporating the present invention allows the number of word line layers to exceed 2000 layers, even with current levels of silicon mobility. Therefore, the time required to drive the load capacitance during a read operation can be reduced to the conventional level.

[0047] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0048] 1. First embodiment 1.1 Memory cell array configuration First, an example of the configuration of a memory cell array will be described with reference to FIGS. 1 to 3. FIG. 1 shows an example of an equivalent circuit diagram of a gain block gBK according to the first embodiment. FIG. 1 shows an example of a cell block CB including multiple memory cell strings MSR connected to one local bit line LBL, a write port unit WPB that transmits the potential of the bit line BL to the local bit line LBL, and a read port unit RPB that amplifies the potential of the local bit line LBL and transmits it to the bit line BL. While FIG. 1 shows one cell block CB and four string units SU, in reality, multiple cell blocks CB and multiple string units SU are arranged within each cell block CB. FIG. 2 is a block diagram showing an example of the configuration of a memory cell array MA according to the first embodiment. In the example shown in FIG. 2, a bit line BL is connected to a page buffer PB, and multiple gain blocks gBK are connected to the bit line BL. FIG. 3 shows an example of a cross-sectional view of a gain block gBK according to the first embodiment in the bit line direction (Y direction). Figure 3 shows an example of a cross-sectional structure of a portion of a cell block CB including multiple memory cell strings MSR (memory pillars MP) connected to one local bit line LBL, a write port section WPB that transmits the potential of the bit line BL to the local bit line LBL, and a read port section RPB that amplifies the potential of the local bit line LBL and transmits it to the bit line BL.

[0049] As shown in FIG. 1, the gain block gBK includes a cell block CB, a read port unit RPB, and a write port unit WPB.

[0050] First, the configuration of the cell block CB will be described. The cell block CB is, for example, a collection of multiple memory cells from which data is erased collectively. The cell block CB includes multiple string units SU. The string unit SU is a collection of multiple memory cell strings MSR that are selected collectively in a write operation or a read operation. In the example shown in FIG. 1, the cell block CB includes four string units SU0 to SU3.

[0051] The memory cell string MSR includes a plurality of memory cells MC and string select transistors STT1, ST1, and ST2. In the example shown in FIG. 1, the memory cell string MSR includes 2000 memory cells MC0 to MC1999, each of which includes one string select transistor STT1, ST1, and ST2. The current paths of the string select transistors STT1 and ST1, the memory cells MC0 to MC1999, and the string select transistor ST2 in the memory cell string MSR are connected in series in this order. The plurality of memory cells MC connected in series form a memory cell string. The drain of the string select transistor STT1 is connected to a local bit line LBL. The source of the string select transistor ST2 is connected to a source line SL. The number of string select transistors STT1 and string select signal lines SGDT can be changed depending on the process or operation method.

[0052] The gates of memory cells MC0 to MC1999 in cell block CB are connected to word lines WL0 to WL1999, respectively. More specifically, the gates of multiple memory cells MC0 in cell block CB are commonly connected to word line WL0. The same is true for memory cells MC1 to MC1999.

[0053] The string selection transistors ST1, ST2, and STT1 are switching elements. The string selection transistors ST1, ST2, and STT1 are used to select the string unit SU, respectively. The gates of the string selection transistors ST1, ST2, and STT1 are connected to string selection signal lines SGD, SGS, and SGDT, respectively.

[0054] More specifically, the gates of the string select transistors STT1 included in the string unit SU0 are connected to a string select signal line SGDT0. The gates of the string select transistors ST1 included in the string unit SU0 are connected to a string select signal line SGD0. Similarly, the gates of the string select transistors STT1 and ST1 included in the string unit SU1 are connected to string select signal lines SGDT1 and SGD1, respectively. The gates of the string select transistors STT1 and ST1 included in the string unit SU2 are connected to string select signal lines SGDT2 and SGD2, respectively. The gates of the string select transistors STT1 and ST1 included in the string unit SU3 are connected to string select signal lines SGDT3 and SGD3, respectively. Furthermore, the gates of the string select transistors ST2 included in the cell block CB are connected to a string select signal line SGS. In order to reduce power consumption, the string select signal line SGS may be controlled by a separate signal for each string unit SU, for example, as string select signal lines SGS0 to SGS3, similar to the string select signal line SGD.

[0055] A plurality of local bit lines LBL are provided in the gain block gBK. Each local bit line LBL is connected to one memory cell string MSR of each string unit SU in the cell block CB. In the example shown in FIG. 1, the local bit line LBL is connected to one memory cell string MSR in the string unit SU0, one memory cell string MSR in the string unit SU1, one memory cell string MSR in the string unit SU2, and one memory cell string MSR in the string unit SU3. The same applies to the other local bit lines LBL (not shown). One end of the local bit line LBL is connected to the write port unit WPB, and the other end is connected to the read port unit RPB.

[0056] The source line SL can be shared among a plurality of cell blocks CB in one gain block gBK, for example.

[0057] Next, the configuration of the write port unit WPB will be described. The write port unit WPB functions as a circuit that transfers the charge of the bit line BL to the local bit line LBL. For example, in a write operation, a voltage of the bit line BL based on write data is applied to the local bit line LBL via the write port unit WPB. The write port unit WPB includes a plurality of strings WSR. More specifically, two strings WSR1 and WSR2 are provided for one local bit line LBL. The two strings WSR1 and WSR2 are connected in series. The bit line BL is electrically connected to the local bit line LBL via the two strings WSR1 and WSR2 connected in series. Hereinafter, when there is no need to specify either the strings WSR1 or WSR2, they will be simply referred to as "string WSR."

[0058] More specifically, each string WSR in this embodiment includes transistors WST0 and WST1, multiple dummy cells DC, and a dummy transistor DT. The transistor WST0, transistor WST1, multiple dummy cells DC, and dummy transistor DT in string WSR1 are connected in series with the dummy transistor DT, multiple dummy cells DC, transistor WST1, and transistor WST0 in string WSR2 in this order. One end (drain) of the transistor WST0 in string WSR1 is connected to the bit line BL. One end (drain) of the transistor WST0 in string WSR2 is connected to the local bit line LBL. The source of the dummy transistor DT in string WSR1 is connected to the source of the dummy transistor DT in string WSR2.

[0059] The transistors WST0 and WST1 function as switch transistors. The gate of each transistor WST0 is connected to a write control signal line WBS0. Similarly, the gate of each transistor WST1 is connected to a write control signal line WBS1. The gate of the dummy cell DC is connected to a dummy word line dWL. The gate of the dummy transistor DT is connected to a dummy string selection signal line dSGS. The drain and source of each of the dummy cell DC and dummy transistor DT are electrically connected regardless of the gate voltage.

[0060] Next, the configuration of the read port unit RPB will be described. The read port unit RPB functions as a circuit that amplifies the potential of the local bit line LBL and transmits it to the bit line BL. For example, in a read operation, the read port unit RPB amplifies the voltage of the local bit line LBL based on the data stored in the memory cell MC and transmits it to the bit line BL. The read port unit RPB includes multiple strings RSR. One string RSR is provided for one local bit line LBL.

[0061] More specifically, the string RSR of this embodiment includes transistors APT and RST, a plurality of dummy cells DC, and a dummy transistor DT. The transistor APT, transistor RST, a plurality of dummy cells DC, and dummy transistor DT in the string RSR are connected in series in this order. One end (drain) of the transistor APT is connected to the bit line BL. The source of the dummy transistor DT is connected to the read source line RSL. Note that the order of the transistor APT and the transistor RST may be reversed.

[0062] The transistor APT functions as an amplifying transistor that amplifies the voltage of the local bit line LBL. The gate of the transistor APT is connected to the local bit line LBL. The transistor RST functions as a switch transistor. The gate of the transistor RST is connected to the read control signal line RBS. As with the write port unit WPB, the gate of the dummy cell DC is connected to the dummy word line dWL. The gate of the dummy transistor DT is connected to the dummy string selection signal line dSGS. The drains and sources of the dummy cell DC and dummy transistor DT are electrically connected regardless of the gate voltage.

[0063] For example, in a conventional nonvolatile semiconductor memory device, one end of a memory cell string MSR is connected to a read / write bit line BL, and the other end is connected to a source line SL. Therefore, a memory cell array MA is configured in which multiple memory cell strings MSR are connected to one bit line BL. In this case, the capacitance of the bit line BL increases depending on the number of memory cell strings MSR connected. For cost reduction, for example, doubling the number of stacked word lines doubles the number of serially connected cells in the memory cell string MSR. In this case, the cell current (Icell) flowing through the memory cell string MSR is halved, and the drive time of the bit line BL, which is the load capacitance, doubles. This results in a slower processing speed. To maintain a constant speed, for example, it is necessary to halve the size of the memory cell array in order to halve the load capacitance. However, this approach doubles the number of page buffers PB across the entire chip, resulting in an enormous chip size.

[0064] 1, one end of each of the plurality of memory cell strings MSR is connected to one local bit line LBL, and the other end is connected to a source line SL. This forms a group of memory cell strings corresponding to one local bit line LBL. That is, a gain block gBK is formed in which the local bit line LBL is connected to one bit line BL via a read port unit RPB and a write port unit WPB.

[0065] As shown in FIG. 2, the nonvolatile semiconductor memory device 1 includes a memory cell array MA and a page buffer PB.

[0066] The memory cell array MA includes a plurality of gain blocks gBK connected to the same bit line BL. In other words, the memory cell array MA is divided into a plurality of gain blocks gBK. The plurality of gain blocks gBK are connected to a common bit line BL. In the example shown in FIG. 2, the memory cell array MA includes 16 gain blocks gBK0 to gBK15. The bit line BL is connected to the 16 gain blocks gBK0 to gBK15 and a page buffer PB, which is a read / write circuit (i.e., the page buffer PB includes a sense amplifier circuit and a write circuit).

[0067] The number of memory cell strings MSR connected to each local bit line LBL in a gain block gBK decreases as the number of gain blocks gBK increases. For example, if the number of gain blocks gBK increases from 1 to 16, the number of memory cell strings MSR connected to the local bit line LBL decreases by 1 / 16. As a result, the load capacitance of the local bit line LBL driven by the cell current is significantly reduced to 1 / 16. This allows the read operation to the local bit line LBL to be 16 times faster. Therefore, even if the number of stacked memory cells MC (number of stacked word lines) is increased by 16 times, the load on the local bit line LBL is reduced to 1 / 16, allowing the same speed as before to be maintained.

[0068] 1, in the write port unit WPB, when a high-level voltage is applied to the write control signal lines WBS0 and WBS1, the transistors WST0 and WST1 are turned on, causing the write port unit WPB to transmit the potential of the bit line BL to the local bit line LBL via the transistors WST0 and WST1 of the two strings WSR1 and WSR2.

[0069] The bit information from the page buffer PB is transmitted to the memory cell string MSR via transistors WST0 and WST1 and the local bit line LBL. The local bit line LBL is shorter and has a smaller load than the bit line BL, so it can achieve a write speed comparable to that of conventional methods. Furthermore, because the write speed is governed by the FN-tunnel current, it does not deteriorate even if the number of series cells in the memory cell string MSR increases.

[0070] In the read port unit RPB, the local bit line LBL is connected to an amplifier transistor APT, which has the local bit line LBL as its gate input and the bit line BL as its drain. The source of the transistor APT is connected to a read source line RSL via a transistor RST, which has the read control signal line RBS as its gate input.

[0071] For example, in a read operation, a high-level voltage is applied to unselected word lines WL in the selected gain block gBK, turning on unselected memory cells MC. In this state, the selected word line WL is set to a threshold voltage determination potential. In other words, a read voltage is applied to the selected word line WL. If the threshold voltage of the selected memory cell MC is higher than the determination potential, the selected memory cell MC is turned off. Therefore, the voltage of the local bit line LBL remains high. On the other hand, if the threshold voltage of the selected memory cell MC is lower than the determination potential, the selected memory cell MC is turned on. Therefore, the voltage of the local bit line LBL drops to low. At this time, because the capacitance of the local bit line LBL is relatively small, the potential of the local bit line LBL drops relatively quickly. In this state, if a high-level voltage is applied to the read control signal line RBS, the amplifier transistor APT, which uses the local bit line LBL as its gate, drives the bit line BL, which has a large load capacitance, and the determination result is transmitted to the page buffer PB.

[0072] The number of series connections between the amplifier transistor APT and the transistor RST, whose gate input is the read control signal line RBS, will be shown later, but because the resistance of the multiple dummy cells DC and dummy transistors DT in the read port unit RPB is reduced through process (structural) design, it is essentially at the level of just a few transistors. As a result, even when the amplifier transistor APT drives the bit line BL, it can operate at a speed more than 10 times faster than when driven by a conventional memory cell string MSR in which 150 to 250 memory cells MC are connected in series, and high-speed operation is possible regardless of the number of cells connected in series.

[0073] Next, the cross-sectional structure of the gain block gBK will be described. First, the cell block CB will be described.

[0074] As shown in FIG. 3 , multiple word line layers (WL0 to WL1999) and string select signal layers (SGDi, SGDTi, SGS) (i is an integer equal to or greater than 0) are stacked and spaced apart in the Z direction. A memory hole MH is opened, extending in the Z direction and penetrating (passing through) the multiple word line layers and the string select signal layers. The bottom of the memory hole MH reaches the semiconductor layer 12. A stacked film 22 (a block insulating layer 223, a charge trapping layer 222, and a tunnel insulating layer 221) and a silicon channel layer 21 are formed on the sidewalls of each word line layer inside the memory hole MH, thereby forming individual memory cells MC that store a threshold voltage by injecting / ejecting electrons. These memory cells MC form a memory cell string MSR, in which multiple memory cells MC with gate electrodes formed by the multiple word line layers and multiple string select transistors STT1, ST1, and ST2 with gate electrodes formed by the multiple string select signal layers are connected in series in the Z direction. By processing the memory holes MH collectively, a large number of memory cells MC can be connected in series in the Z direction at low cost. That is, a low-cost nonvolatile semiconductor memory device 1 is realized.

[0075] 3, the stacked layer made up of multiple wiring layers 14 is formed by stacking word line layers and string selection signal layers. The read port section RPB and the write port section WPB also utilize the wiring layers 14 stacked by the same film formation process.

[0076] For example, the transistors WST0 and WST1 in the write port unit WPB use the write control signal lines WBS0 and WBS1 as their gate inputs and the string select signal layers (SGDT and SGD) used in the cell block CB as their gate electrodes. The wiring layer 17 functioning as the bit line BL is electrically connected to one end of the semiconductor layer 12 located below (spaced apart from the other end in the Z direction) via the underlying contact plugs CP4 and CP3 and the transistors WST0 and WST1. The semiconductor layer 12 in the write port unit WPB functions as the bottom bit line bBL, which connects the two strings WSR1 and WSR2, i.e., electrically connects the bit line BL to the local bit line LBL. The semiconductor layer 12 functioning as the bottom bit line bBL is in the same layer as the source line layer of the cell block CB. The other end of the semiconductor layer 12 is electrically connected to the wiring layer 16 functioning as the local bit line LBL via the underlying transistors WST1 and WST0 and the contact plug CP1. 3, a conductor 30 is provided inside the silicon channel layer 21, for example. The conductor 30 is preferably made of a metal material such as tungsten, or a low-resistance silicon doped with a high concentration of impurities.

[0077] In the read port unit RPB, the wiring layer 14 functioning as the local bit line LBL is connected as the gate input of the transistor APT, which uses the string select signal layer as its gate electrode. In the example shown in FIG. 3, the wiring layer 16 functioning as the local bit line LBL is electrically connected to the string select signal layer (the wiring layer 14 functioning as the local bit line LBL) in the upper three layers of the stacked layer via a contact plug CP2. The read control signal line RBS is formed using the string select signal layer (the wiring layer 14 functioning as the read control signal line RBS) in the lower three layers. The source of the control transistor RST, which receives the gate input of the read control signal line RBS, is connected to the read source line RSL (semiconductor layer 12) via a dummy word line layer in the read port unit RPB and a conductor 30 (tungsten or low-resistivity silicon doped with a high concentration of impurities) that reduces the resistance of the pillar RP. In this way, by using the stacked layers that make up the cell block CB to build the processes for the read port unit RPB and the write port unit WPB, process costs can be significantly reduced. Furthermore, if the read port unit RPB and write port unit WPB connect tens to hundreds of memory cell strings MSR per unit local bit line LBL, the increase in chip area can be kept small. Therefore, even if the memory capacity is increased by increasing the number of stacked word lines, other costs and increases in chip area can be suppressed by only the cost of increasing the number of stacked word lines, and as a result, the cost per bit can be significantly reduced.

[0078] Hereinafter, the cross-sectional configuration of the memory cell array MA of this embodiment will be described in detail, focusing on differences from the structure of the memory cell array described with reference to FIGS. 32A and 32B.

[0079] As shown in FIG. 3, the gain block gBK includes insulating layers 11, 13, and 15, a semiconductor layer 12, wiring layers 14, 16, and 17, a memory pillar MP, pillars WP1, WP2, and RP, contact plugs CP1 to CP4, a member SLT, and a member SHE1.

[0080] A semiconductor layer 12 is provided on the insulating layer 11. The semiconductor layer 12 provided in the cell block CB functions as a source line SL. A plurality of memory pillars MP are provided on the semiconductor layer 12 functioning as the source line SL. One memory pillar MP functions as one memory cell string MSR.

[0081] A plurality of semiconductor layers 12 provided in the write port unit WPB function as bottom bit lines bBL. Two pillars WP1 and WP2 that electrically connect the bit line BL and the local bit line LBL are provided on the semiconductor layer 12 that functions as the bottom bit line bBL. That is, the two pillars WP are electrically connected via one bottom bit line bBL. The pillars WP1 and WP2 function as strings WSR1 and WSR2, respectively. Hereinafter, when there is no need to specify either the pillars WP1 or WP2, they will be simply referred to as "pillar WP."

[0082] The semiconductor layer 12 provided in the read port unit RPB functions as a read source line RSL. A plurality of pillars RP are provided on the semiconductor layer 12 functioning as the read source line RSL. One pillar RP functions as one string RSR.

[0083] An insulating layer 13 is provided on the semiconductor layer 12. A plurality of wiring layers 14 and a plurality of insulating layers 15 are alternately stacked on the insulating layer 13. In the example shown in FIG. 3, 2009 wiring layers 14 are provided, as in FIG. 32A. Each wiring layer 14 is divided into a cell block CB, a write port unit WPB, and a read port unit RPB by a member SLT extending in the X direction.

[0084] The 2009 wiring layers 14 provided in the cell block CB function, from the side (upper layer) farthest from the semiconductor layer 12 (source line SL), as three layers of string select signal lines SGDT, three layers of string select signal lines SGD, 2000 layers of word lines WL0 to WL1999, and three layers of string select signal lines SGS. The wiring layers 14 functioning as the string select signal lines SGDT or SGD are divided into string units SU by members SHE1 extending in the X direction.

[0085] The 2009-layer wiring layer 14 provided in the write port unit WPB functions, from the side (upper layer) farthest from the semiconductor layer 12 (bottom bit line bBL), as a three-layer write control signal line WBS0, a three-layer write control signal line WBS1, a 2000-layer dummy word line dWL, and a three-layer dummy string select signal line dSGS. The wiring layer 14 functioning as the write control signal line WBS0 or the write control signal line WBS1 can also be divided by a member SHE1 extending in the X direction.

[0086] The 2009-layer wiring layer 14 provided in the read port unit RPB functions, from the side (upper layer) farthest from the semiconductor layer 12 (read source line RSL), as three layers of local bit lines LBL, three layers of read control signal lines RBS, a 2000-layer dummy word line dWL, and three layers of dummy string select signal lines dSGS. The wiring layer 14 functioning as the local bit lines LBL or the read control signal lines RBS can also be divided by a member SHE1 extending in the X direction.

[0087] 3, a wiring layer 14 functioning as a string select signal line SGDT, a wiring layer 14 functioning as a write control signal line WBS0, and a wiring layer 14 functioning as a part of a local bit line LBL are provided in the same layer. A wiring layer 14 functioning as a string select signal line SGD, a wiring layer 14 functioning as a write control signal line WBS1, and a wiring layer 14 functioning as a read control signal line RBS are provided in the same layer. A wiring layer 14 functioning as a word line WL and a wiring layer 14 functioning as a dummy word line dWL are provided in the same layer. A wiring layer 14 functioning as a string select signal line SGS and a wiring layer 14 functioning as a dummy string select signal line dSGS are provided in the same layer.

[0088] A plurality of memory pillars MP are provided in the cell block CB. The structure of the memory pillars MP is the same as that described in Figures 32A and 32B.

[0089] A memory cell MC is formed by combining a memory pillar MP with a wiring layer 14 that functions as a word line WL. A string select transistor STT1 is formed by combining a memory pillar MP with a wiring layer 14 that functions as a string select signal line SGDT. A string select transistor ST1 is formed by combining a memory pillar MP with a wiring layer 14 that functions as a string select signal line SGD. A string select transistor ST2 is formed by combining a memory pillar MP with a wiring layer 14 that functions as a string select signal line SGS. In other words, a memory cell MC is formed using the word line WL as its gate electrode. A string select transistor STT1 is formed using the string select signal line SGDT as its gate electrode. A string select transistor ST1 is formed using the string select signal line SGD as its gate electrode. A string select transistor ST2 is formed using the string select signal line SGS as its gate electrode.

[0090] A plurality of pillars WP are provided within the write port unit WPB. Each pillar WP includes a core film 20, a silicon channel layer 21, a stacked film 22 (a block insulating layer 223, a charge trapping layer 222, and a tunnel insulating layer 221), and a conductor 30. The pillar WP of this embodiment has a structure in which the lower part of the core film 20 of the memory pillar MP is replaced with the conductor 30. The conductor 30 extends in the Z direction. The upper end of the conductor 30 is located between the wiring layer 14 functioning as the dummy word line dWL and the wiring layer 14 functioning as the write control signal line WBS1. The core film 20 is provided on the conductor 30. The upper end of the core film 20 is located above the uppermost wiring layer 14. The silicon channel layer 21 extends in the Z direction and covers the core film 20 and the conductor 30. That is, the bottom and side surfaces of the conductor 30 are in contact with the silicon channel layer 21. The laminated film 22 is formed so as to cover the side surfaces of the silicon channel layer 21. The material of the conductor 30 is preferably a metal material such as tungsten, or low-resistivity silicon doped with a high concentration of impurities.

[0091] The pillar WP is combined with the wiring layer 14 that functions as the write control signal line WBS0 to form the transistor WST0. The pillar WP is combined with the wiring layer 14 that functions as the write control signal line WBS1 to form the transistor WST1. The pillar WP is combined with the wiring layer 14 that functions as the dummy word line dWL to form the dummy cell DC. The pillar WP is combined with the wiring layer 14 that functions as the dummy string select signal line dSGS to form the dummy transistor DT. In other words, the transistor WST0 is formed using the write control signal line WBS0 as its gate electrode. The transistor WST1 is formed using the write control signal line WBS1 as its gate electrode. The dummy cell DC is formed using the dummy word line dWL as its gate electrode. The dummy transistor DT is formed using the dummy string select signal line dSGS as its gate electrode.

[0092] A plurality of pillars RP are provided in the read port portion RPB. The structure of the pillars RP is the same as that of the pillars WP. For example, the memory holes MH and holes corresponding to the pillars WP and RP are processed collectively.

[0093] A transistor APT is formed by combining a pillar RP with a wiring layer 14 that functions as a local bit line LBL. A transistor RST is formed by combining a pillar RP with a wiring layer 14 that functions as a read control signal line RBS. A dummy cell DC is formed by combining a pillar RP with a wiring layer 14 that functions as a dummy word line dWL. A dummy transistor DT is formed by combining a pillar RP with a wiring layer 14 that functions as a dummy string select signal line dSGS. In other words, a transistor APT is formed using the local bit line LBL as its gate electrode. A transistor RST is formed using the read control signal line RBS as its gate electrode. A dummy cell DC is formed using the dummy word line dWL as its gate electrode. A dummy transistor DT is formed using the dummy string select signal line dSGS as its gate electrode.

[0094] The drains and sources of the dummy cells DC and dummy transistors DT of the write port unit WPB and the read port unit RPB are electrically connected by conductors 30. Therefore, the current paths of the dummy cells DC and dummy transistors DT have low resistance and are in a conductive state regardless of the gate voltage.

[0095] In the cell block CB, contact plugs CP1 are provided on the memory pillars MP. Wiring layers 16 extending in the Y direction are provided on the contact plugs CP1. The memory pillars MP are electrically connected to the wiring layers 16 via the contact plugs CP1. The wiring layers 16 function as local bit lines LBL. The wiring layers 16 and the contact plugs CP1 contain, for example, copper or tungsten as a conductive material. The contact plugs CP1 to CP4 are partially made of N + Diffusion layer or P +A diffusion layer may be included.

[0096] In the write port unit WPB, of two pillars WP1 and WP2 provided on the bottom bit line bBL, a contact plug CP1 is provided on the pillar WP2 corresponding to the string WSR2. The pillar WP2 is electrically connected to a wiring layer 16 (local bit line LBL) via the contact plug CP1. A contact plug CP3 is provided on the pillar WP1 corresponding to the string WSR1. Furthermore, a contact plug CP4 is provided on the contact plug CP3. A wiring layer 17 extending in the Y direction is provided on the contact plug CP4. The wiring layer 17 is provided above the wiring layer 16. The pillar WP1 is electrically connected to the wiring layer 17 via the contact plugs CP3 and CP4. The wiring layer 17 functions as the bit line BL. The wiring layer 17 and the contact plugs CP3 and CP4 contain, for example, copper or tungsten as a conductive material.

[0097] In the read port unit RPB, a contact plug CP2 is provided, which is electrically connected to the upper three wiring layers 14 that function as the local bit line LBL. The contact plug CP2 passes through the upper two wiring layers 14, and its bottom surface is in contact with the third wiring layer 14. The upper three wiring layers 14 are electrically connected to the wiring layer 16 (local bit line LBL) via the contact plug CP2. A contact plug CP3 is provided on the pillar RP. Furthermore, a contact plug CP4 is provided on the contact plug CP3. A wiring layer 17 is provided on the contact plug CP4. The pillar RP is electrically connected to the wiring layer 17 via the contact plugs CP3 and CP4. The contact plug CP2 contains, for example, copper or tungsten as a conductive material.

[0098] 1.2 Planar layout of the light port Next, an example of a planar layout of the write port unit WPB will be described with reference to Fig. 4. Fig. 4 is a plan view showing an example of a planar layout of the write port unit WPB.

[0099] As shown in FIG. 4, multiple local bit lines LBL (wiring layer 16) extending in the Y direction are arranged side by side in the X direction. Each local bit line LBL extends from a cell block CB (not shown) located on the left side of the drawing toward a write port unit WPB. The local bit line LBL is electrically connected to a pillar WP2 provided below it via a contact plug CP1. The length of the local bit line LBL varies depending on the position of the pillar WP2 (contact plug CP1) to which it is connected. The local bit line LBL is electrically connected to a bottom bit line bBL (semiconductor layer 12) provided below the pillar WP2 via the pillar WP2. The bottom bit line bBL is connected to, for example, a pillar WP1 located at the same position in the X direction and adjacent to the pillar WP2 in the Y direction. That is, two pillars WP1 and WP2 are connected to one bottom bit line bBL. The pillar WP1 connected to the bottom bit line bBL is electrically connected to a bit line BL (wiring layer 17) provided above the local bit line LBL via contact plugs CP3 and CP4. The right end of the local bit line LBL does not extend above the contact plug CP3, so the contact plug CP3 is formed on the pillar WP1 without being obstructed by the local bit line LBL.

[0100] The pillars WP are arranged in a staggered pattern, for example, similar to the memory pillars MP.

[0101] In the example shown in FIG. 4, the bottom bit line bBL has a shape that is bent upward or downward on the paper surface. Note that the shape of the bottom bit line bBL is not limited to this. In the example shown in FIG. 4, two pillars WP in the first and third columns from the left side of the paper, which are located at the same position in the X direction and adjacent in the Y direction, are connected to one bottom bit line bBL. For example, the local bit line LBL is electrically connected to the bit line BL via a contact plug CP1 provided on the pillar WP2 in the first column, the pillar WP2 in the first column, the bottom bit line bBL, the pillar WP1 in the third column, a contact plug CP3 provided on the pillar WP1 in the third column, and a contact plug CP4 provided on the contact plug CP3. Note that another pillar WP in the second column from the left side of the paper, which is located at a different position in the X direction, is also connected to the bottom bit line bBL, but the pillar WP in the second column is a dummy (floating state) and does not contribute to the electrical connection. Similarly, two pillars WP in the fourth and sixth columns from the left side of the page that are positioned in the same X direction and adjacent in the Y direction, and one pillar WP (dummy) in the fifth column, are connected to one bottom bit line bBL. Two pillars WP in the seventh and ninth columns from the left side of the page that are positioned in the same X direction and adjacent in the Y direction, and one pillar WP (dummy) in the eighth column, are connected to one bottom bit line bBL. Two pillars WP in the tenth and twelfth columns from the left side of the page that are positioned in the same X direction and adjacent in the Y direction, and one pillar WP (dummy) in the eleventh column, are connected to one bottom bit line bBL.

[0102] The bottom bit line bBL requires pitch relaxation due to random processing. As shown in FIG. 4, the local bit lines LBL are connected in four-stage offset in the Y direction. More specifically, for example, four local bit lines LBL aligned in the X direction are connected to the pillars WP2 in the first, seventh, fourth, and tenth columns from the left side of the page, in that order. Furthermore, when viewed in the X direction, the connection positions of the local bit lines LBL are repeated in units of four in the Y direction. More specifically, for example, the four pillars WP2 arranged in the first column from the left side of the page are connected to the first, fifth, ninth, and thirteenth local bit lines LBL from the top of the page. Because the right-side ends of the local bit lines LBL differ for each line, it is preferable to form the local bit lines LBL (wiring layer 16) by using an oblique SAP (sidewall processing process) or NIL (nano imprint lithography) processing.

[0103] 1.3 Planar layout of the read port Next, two examples of the planar layout of the read port unit RPB will be described with reference to Figures 5A and 5B. Figure 5A is a plan view showing a first example of the planar layout of the read port unit RPB. Figure 5B is a plan view showing a second example of the planar layout of the read port unit RPB.

[0104] First, a first example of a planar layout of the read port unit RPB will be described with reference to FIG. 5A.

[0105] 5A, in the read port unit RPB, an amplifier transistor APT is formed for each local bit line LBL (wiring layer 16) using that line as its gate. Furthermore, multiple transistors RST are formed for each read control signal line RBS extending in the X direction to gate that line. To form the gate electrodes (wiring layers 14) of the amplifier transistors APT, which are vertically and horizontally isolated islands separated in the X and Y directions, first, a member SHE1 extending in the X direction is formed to separate the upper six wiring layers 14 that function as the local bit line LBL or the read control signal line RBS in the Y direction.

[0106] 5A, multiple pillars RP provided between three components SLT are included in one read port unit RPB. In the region between two components SLT adjacent in the Y direction, the multiple pillars RP are arranged side by side in the X direction, for example, with a width of 11 columns. The 11 columns of memory pillars MP are arranged in a staggered pattern so that the X-direction positions of memory pillars MP adjacent in the Y direction are different from each other.

[0107] Between two members SLT, multiple members SHE1 extending in the X direction are arranged side by side in the Y direction. In the example shown in FIG. 5A, three members SHE1 are provided between two members SLT. More specifically, members SHE1 are provided on the pillars RP in the third, sixth, ninth, fourteenth, seventeenth, and twentieth columns from the left side of the page in FIG. 5A so as to divide the upper portions of the pillars RP. The area between two members SLT or members SHE1 adjacent in the Y direction corresponds to one read control signal line RBS. In other words, the read port unit RPB includes multiple read control signal lines RBS. In the example shown in FIG. 5A, the six wiring layers 14 above the read port unit RPB are divided into eight in the Y direction by the members SLT and SHE1. In other words, the wiring layers 14 functioning as local bit lines LBL or read control signal lines RBS are divided into eight in the Y direction. The eight read control signal lines RBS0 to RBS7 are arranged, for example, from the left side of the paper in the order of read control signal lines RBS6, RBS0, RBS7, RBS1, RBS2, RBS4, RBS3, and RBS5.

[0108] Next, a member SHE2 extending in the Y direction is formed to separate the top three wiring layers 14, which function as local bit lines LBL, in the X direction. This results in the top three wiring layers 14 becoming floating gates separated in the X and Y directions (separated vertically and horizontally). By electrically connecting the wiring layers 16 (local bit lines LBL) to these layers, the amplifier transistor APT can be formed. The bottom three wiring layers 14 of the top six function as read control signal lines RBS, which are input to the gates of the transistors RST connected in series to the amplifier transistor APT, to enable / disable the operation of the amplifier transistor APT.

[0109] For example, each local bit line LBL (wiring layer 16) is electrically connected to any one of the vertically and horizontally separated wiring layers 14 in the region of any one of the read control signal lines RBS0 to RBS7. For example, a local bit line LBL(8j+k) (j is an integer of 0 or more) is electrically connected to a vertically and horizontally separated wiring layer 14 corresponding to the region of a read control signal line RBSk (k is an integer of 0 to 7). The number of read control signal lines RBS divided in the Y direction and the arrangement order thereof are arbitrary.

[0110] The isolation gate (the gate of the amplification transistor APT) separated vertically and horizontally by the members SHE1 and SHE2, i.e., the wiring layer 14 functioning as the local bit line LBL, has an area of ​​2×2 pillars RP, with 2 RP vertically (two pillars RP in the X direction) and 2 RP horizontally (two pillars RP in the Y direction). The isolation gate is formed for each wiring layer 16 functioning as the local bit line LBL, and is therefore formed in eight stages in the horizontal direction (Y direction) of the paper. The local bit line LBL (wiring layer 16) extending from the cell block CB (not shown) located on the right side of the paper to the left side of the paper is connected to the contact plug C. The bit line BL (wiring layer 17) is electrically connected to the wiring layer 14, which functions as the gate of the amplification transistor APT, via contact plugs CP2. The bit line BL (wiring layer 17) is connected to the pillar RP via contact plugs CP4 and CP3. The pillar RP reaches the read source line RSL (semiconductor layer 12) via the amplification transistor APT and a transistor RST to which a read control signal line RBS is connected. The read source line RSL is electrically connected to an upper wiring layer (not shown) via a conductor LI of a member SLT provided in the center of the read port unit RPB (between the read control signal lines RBS1 and RBS2).

[0111] The signal (voltage) applied to the read source line RSL may be a different signal (different voltage) from the signal (voltage) applied to the source line SL, or may be the same signal (same voltage). In the case of a different signal, the source potential of the amplification transistor APT can be adjusted separately from the potential of the source line SL. Therefore, when the potential of the local bit line LBL varies within the range of 0V ("0" data) to 0.7V ("1" data), it is desirable that the threshold voltage Vt of the amplification transistor APT satisfies 0V < Vt < 0.7V. For example, when the threshold voltage Vt is 0.7V or higher, the potential of the read source line RSL can be adjusted by lowering it. Also, in order to adjust the variation in the threshold voltage Vt of the amplification transistor APT, when adjusting the threshold voltage Vt by the electron injection / extraction operation to the amplification transistor APT, it is desirable that an independent signal is applied to the read source line RSL.

[0112] In FIG. 5A, there is an unused pillar RP near the contact plug CP2, but the contact plug CP2 is not electrically connected to the silicon channel layer 21 within the pillar RP. The contact plug CP2 is electrically connected only to the wiring layer 14 that functions as the local bit line LBL. If it is electrically connected to the silicon channel layer 21 within the pillar RP, the semiconductor layer 12 directly under the bottom of the pillar RP can be removed to make the corresponding pillar RP floating.

[0113] Next, referring to FIG. 5B, a second example of the planar layout of the read port portion RPB will be described. Hereinafter, the description will focus on the differences from the first example.

[0114] As shown in FIG. 5B, in this example, the unused pillar RP located near the contact plug CP2 described using FIG. 5A is removed so that the contact plug CP2 and the wiring layer 14 can be more easily connected. There is a concern about the influence of the deterioration of the uniformity of the hole processing corresponding to the pillar RP. In that case, after forming a plurality of holes corresponding to the planar layout described using FIG. 5A, only the unnecessary holes may be filled with an insulator as shown in FIG. 5B, and then the contact plug CP2 may be formed.

[0115] 1.4 Cross-sectional structure of the write port and read port sections in the word line direction Next, an example of the cross-sectional structure of the write port unit WPB and the read port unit RPB in the word line direction (X direction) will be described with reference to Figures 6A and 6B. Figure 6A shows a cross-sectional view of the write port unit WPB in the word line direction (X direction) taken along lines A1-A2 and B1-B2 in Figure 4. Figure 6B shows a cross-sectional view of the read port unit RPB in the word line direction (X direction) taken along lines C1-C2 and D1-D2 in Figure 5A. Note that the description using Figures 6A and 6B will focus on differences from the cross-sectional structure of the gain block gBK in the bit line direction described using Figure 3.

[0116] First, with reference to FIG. 6A, the cross-sectional structure of the write port part WPB in the word line direction will be described.

[0117] Fig. 6A(a) shows a cross section taken along line A1-A2 in Fig. 4, and Fig. 6A(b) shows a cross section taken along line B1-B2 in Fig. 4. In other words, Fig. 6A(a) shows the connection between the wiring layer 16 (local bit line LBL) and the pillar WP2, and Fig. 6A(b) shows the connection between the wiring layer 17 (bit line BL) and the pillar WP1.

[0118] As shown in FIG. 6A(a), the wiring layer 16 functioning as the local bit line LBL is connected to the semiconductor layer 12 functioning as the bottom bit line bBL via a contact plug CP1 and a pillar WP2.

[0119] The semiconductor layer 12 on the right side of FIG. 6A(a) is the same as the semiconductor layer 12 on the right side of FIG. 6A(b). Similarly, the semiconductor layer 12 on the left side of FIG. 6A(a) is the same as the semiconductor layer 12 on the left side of FIG. 6A(b). Therefore, the pillar WP2 on the right side of FIG. 6A(a) is electrically connected to the pillar WP1 on the right side of FIG. 6A(b) via the semiconductor layer 12. Furthermore, the pillar WP2 on the left side of FIG. 6A(a) is electrically connected to the pillar WP1 on the left side of FIG. 6A(b) via the semiconductor layer 12.

[0120] As shown in (b) of Figure 6A, the pillar WP1 is electrically connected to the wiring layer 17 provided above, which functions as the bit line BL, via contact plugs CP3 and CP4. Therefore, the local bit line LBL is electrically connected to the bit line BL via the contact plug CP1, the pillar WP2 in (a) of Figure 6A, the bottom bit line bBL, the pillar WP1 in (b) of Figure 6A, and the contact plugs CP3 and CP4.

[0121] Next, with reference to FIG. 6B, the cross-sectional structure of the read port unit RPB in the word line direction will be described.

[0122] FIG. 6B(a) shows a cross section taken along line C1-C2 in FIG. 5A, and FIG. 6B(b) shows a cross section taken along line D1-D2 in FIG. 5A.

[0123] 6B(b), the wiring layer 16 functioning as the local bit line LBL is connected to the gate of the amplification transistor APT via a contact plug CP2, and is electrically connected to the upper three wiring layers 14 functioning as the local bit line LBL. The wiring layers 14 functioning as the local bit line LBL are separated in the X direction by members SHE2 extending in the Y direction (bit line direction). The members SHE2 contain, for example, silicon oxide as an insulating material.

[0124] 6B(a), the pillar RP is electrically connected to the wiring layer 17 provided above it, which functions as the bit line BL, via contact plugs CP3 and CP4. The amplification transistor APT, which uses the local bit line LBL as its gate, drives the bit line BL, and the current flows to the read source line RSL.

[0125] The semiconductor layer 12 (bottom bit line bBL) of the write port unit WPB is separated for each electrically connected local bit line LBL. In contrast, the semiconductor layer 12 (read source line RSL) of the read port unit RPB is a common wiring for the entire read port unit RPB. In this way, by sharing many process steps with the manufacturing process of the memory cells MC (memory pillar MP), costs can be reduced.

[0126] 1.5 Chip configuration of nonvolatile semiconductor memory device Next, an example of the chip configuration of the nonvolatile semiconductor memory device 1 will be described with reference to FIGS. 7A, 7B, 7C, and 7D. FIG. 7A is a layout diagram showing an example of the chip layout of the nonvolatile semiconductor memory device 1. (a) of FIG. 7A shows the layout of the memory cell array process layer. (b) of FIG. 7A shows the layout of the transistor section below the memory cell array or the CMOS (Complementary Metal Oxide Semiconductor) chip side in wafer bonding. FIG. 7B shows an example of a cross-sectional view of a WL terrace TR corresponding to a cell block CB. FIG. 7C shows an example of bonding an array chip and a CMOS chip. FIG. 7D shows an example of the cross-sectional configuration of the memory cell array process layer and the transistor section below it.

[0127] First, the configuration of the nonvolatile semiconductor memory device 1 will be described with reference to FIGS. 7C and 7D.

[0128] 7C, a gain block gBK including a cell block CB, a read port unit RPB, and a write port unit WPB is formed on the array chip. A page buffer PB, a WL_SG driver DV, and a peripheral circuit PC are formed on the CMOS chip. The array chip and the CMOS chip may be bonded together to form a bonded structure.

[0129] As shown in FIG. 7D, multiple gain blocks gBK may be formed in the memory cell array process layer, and the page buffer PB, WL_SG driver DV, and peripheral circuit PC may be formed in the lower transistor section (FEOL (Front End of Line) region).

[0130] As shown in (a) of FIG. 7A, for example, in the memory cell array process layer, a memory cell array MA is configured by arranging multiple gain blocks gBKs, each of which has a read port unit RPB and a write port unit WPB on both sides of a cell block CB, in the vertical direction of the page. Multiple gain blocks gBKs are commonly connected to bit lines BL. The bit lines BL are also connected to a page buffer PB provided in the CMOS chip (or the FEOL region below the memory cell array). Local bit lines LBL are arranged in each gain block gBK, and word lines WL, string selection signal lines SGDT, SGD, and SGS, which control multiple memory cell strings MSR, are each connected to a WG_SG driver DV provided in the CMOS chip via contact plugs CC provided in the WL terrace TR. Read control signal lines RBS and write control signal lines WBS0 and WBS1 are connected to the RPB control unit and WPB control unit provided in the CMOS chip via contact plugs CC provided in the RPB terrace and WPB terrace, respectively. As shown in FIG. 7A, the bit line BL is a single line across the entire vertical direction of the page, and the number of page buffers PB can be reduced to suppress an increase in chip area, while high-speed operation can be achieved even if the number of serially connected cells in the memory cell string MSR is 1000 to 2000.

[0131] More specifically, as shown in (a) of Figure 7A, a memory cell array MA and a pad region PD are provided in the memory cell array process layer. In the example shown in (a) of Figure 7A, the memory cell array MA includes four gain blocks gBK. Each gain block gBK includes a cell block CB, a write port unit WPB, a read port unit RPB, a WL terrace TR, a WPB terrace, and an RPB terrace.

[0132] A plurality of gain blocks gBK in the memory cell array MA are commonly connected to a bit line BL. The cell block CB, write port unit WPB, and read port unit RPB in each gain block gBK are commonly connected to a local bit line LBL.

[0133] In each gain block gBK, a read port unit RPB and a write port unit WPB are arranged on both sides of the cell block CB in the vertical direction of the paper. For example, four gain blocks gBK are arranged side by side in the vertical direction of the paper.

[0134] The WL terrace TR is a connection region between the wiring layer 14 of the cell block CB and the corresponding contact plug CC. The WPB terrace is a connection region between the wiring layer 14 of the write port unit WPB and the corresponding contact plug CC. The RPB terrace is a connection region between the wiring layer 14 of the read port unit RPB and the corresponding contact plug CC.

[0135] As shown in FIG. 7B, for example, in the WL terrace TR, the X-direction end of the wiring layer 14 provided in the cell block CB is drawn out in a stepped manner. A contact plug CC extending in the Z direction is connected to the top of each of the wiring layers 14 drawn out in a stepped manner. The contact plug CC is electrically connected to a wiring layer (not shown) provided in an upper layer. The contact plug CC contains, for example, tungsten or copper as a conductive material. The same applies to the WPB terrace and the RPB terrace. The WL terrace TR is also referred to as a "word line stepped portion."

[0136] As shown in (a) and (b) of FIG. 7A, the pad region PD is a region where pads to which, for example, power supply lines or the like are connected are formed.

[0137] As shown in FIG. 7A(b), the CMOS chip side (FEOL side) is provided with a page buffer PB, a peripheral circuit PC, a WL_SG driver DV, a WPB control unit, an RPB control unit, and a pad area PD.

[0138] The peripheral circuit PC includes a sequencer, a voltage generation circuit, an input / output circuit, and the like, all of which are not shown. For example, the sequencer controls the operation of the entire nonvolatile semiconductor memory device 1. For example, the sequencer executes write operations, read operations, and erase operations. The voltage generation circuit generates voltages used for write operations, read operations, erase operations, and the like. The input / output circuit is a circuit that inputs and outputs various signals to and from the outside.

[0139] The WL_SG driver DV includes a driver that supplies voltages to the word lines WL and string selection signal lines SGDT, SGD, and SGS of the cell block CB. The WL_SG driver DV is electrically connected to the WL terrace TR via contact plugs CC. That is, the WL_SG driver DV is electrically connected to the word lines WL and string selection signal lines SGDT, SGD, and SGS. In the example shown in FIG. 7A(b), four WL_SG drivers DV are provided corresponding to four cell blocks CB.

[0140] The WPB control unit is a circuit that controls the write control signal lines WBS0 and WBS1. The WPB control unit is electrically connected to the WPB terrace via contact plugs CC. That is, the WPB control unit is electrically connected to the write control signal lines WBS0 and WBS1. In the example shown in FIG. 7A(b), four WPB control units are provided corresponding to the four write port units WPB.

[0141] The RPB control unit is a circuit that controls the read control signal line RBS. The RPB control unit is electrically connected to the RPB terrace via a contact plug CC. That is, the RPB control unit is electrically connected to the read control signal line RBS. In the example shown in FIG. 7A(b), four RPB control units are provided corresponding to the four read port units RPB.

[0142] 1.6 Effects of this embodiment The effects of this embodiment will be described.

[0143] Figure 8 is a graph showing the effect of the first embodiment, illustrating the relationship between the number of gain blocks per bit line (number of bit line divisions) of the memory cell array MA, the number of stacked word lines, and the proportion of overhead due to the gain block gBK relative to the memory cell array MA.

[0144] The gain block gBK includes a cell block CB and a read port unit RPB and a write port unit WPB provided on both sides of the cell block CB. Therefore, the area of ​​the memory cell array MA includes the areas of the read port unit RPB and the write port unit WPB (hereinafter also referred to as "overhead").

[0145] As shown in Figure 8, increasing the number of gain blocks per bit line increases the number of read port units RPB and write port units WPB (overhead) by the number of gain blocks gBK. However, even if the gain blocks gBK are divided into 16, the overhead ratio relative to the memory cell array MA is kept to approximately 3.3%. In this case, the number of stacked word line layers is 2592, easily exceeding 2000. For example, when the bit line length / local bit line length ratio is 64 (64 divisions), a 13% increase in the area of ​​the memory cell array MA can achieve a word line stack number of 10,000. This solves the problems of low speed caused by insufficient cell current Icell and increased chip area at constant speed. The inventors call this 3D-NAND flash memory gNAND (gain NAND Flash or gain Block NAND Flash Memory). Alternatively, the inventors also call it gBiCS Flash.

[0146] FIG. 9 is a diagram showing the effect of the first embodiment, comparing the chip size between a comparative example in which the processing speed is increased by four times and an example of this embodiment. For example, a high-speed NAND flash memory can be used as a cache in a memory such as CXL (registered trademark) (Compute Express Link). FIG. 9(a) shows an example of the chip size of a 3D-NAND flash memory (e.g., BiCS Flash (registered trademark)) before the four-fold speed increase. FIG. 9(b) shows, as a comparative example, the chip size when the speed is increased by four times using the conventional method. FIG. 9(c) shows, as an example, the chip size when the speed is increased by four times by applying this embodiment.

[0147] For example, to reduce the access time tR to the memory cell array MA by a quarter, each delay must be reduced by a quarter. Dividing the memory cell array MA in half along the word line direction (horizontal direction of the chip) reduces the word line delay by half because the word line length is halved, and the resistance and capacitance are each halved, resulting in a total delay of a quarter. However, the bit line length determines the speed of the cell current Icell, which is determined by the resistance R and bit line capacitance C. Therefore, the bit line BL drive time cannot be increased by four times unless the bit line length is reduced by a quarter. Therefore, as shown in Figure 9(b), even if the bit lines BL are divided into four, the area of ​​the page buffer PB per bit line BL remains unchanged. Therefore, as shown in Figure 9(b), the number of page buffers PB in the vertical direction of the chip increases from two to eight, causing the CMOS chip to extend beyond the array chip, resulting in a chip size increase of 223% compared to Figure 9(a). On the other hand, as shown in FIG. 9(c), in this embodiment, even if the memory cell array MA is divided into two in the word line direction, the area occupied by the WL terrace TR (word line staircase section) on the chip is smaller than that of the page buffer PB, and the increase in area is small. In the bit line direction, the bit lines BL are not divided, and local bit lines LBL having a length of 1 / 4 the length of the bit lines BL can be formed. In this case, as shown in FIG. 8, the overhead due to the read port section RPB and write port section WPB is only 0.4%. Ultimately, by applying this embodiment, the chip size can be reduced to 113% to achieve a 4x speed chip.

[0148] 10 is a diagram showing the effect of the first embodiment, illustrating a comparison of chip size between a comparative example in which memory capacity is increased fourfold and an example of this embodiment. FIG. 10(a) shows an example of the chip size of a 3D-NAND flash memory (e.g., BiCS Flash (registered trademark)) before the capacity is increased fourfold. FIG. 10(b) shows, as a comparative example, the chip size when the capacity is increased fourfold using the conventional method. FIG. 10(c) shows, as an example, the chip size when the capacity is increased fourfold by applying this embodiment.

[0149] The chip size in Figure 10(a) is assumed to be 100%. As shown in Figure 10(b), when the conventional method is used to increase the capacity by four times under constant speed conditions, the number of word line WL divisions is the same as in Figure 10(a), but the number of word line stacks is four times larger. As a result, the area of ​​the WL terrace TR (word line staircase section) is required to be four times larger. Furthermore, because the number of word line stacks is four times larger, the cell current Icell is reduced to one-quarter. Therefore, to reduce the bit line capacitance by one-quarter, the bit line BL must be divided into four. As a result, the page buffer PB extends beyond the size of the array chip, resulting in a chip size increase of 260%. On the other hand, in the example shown in Figure 10(c), when increasing the capacity by four times, the area of ​​the WL terrace TR is four times larger in the word line direction, but in the bit line direction, four gain blocks gBK are connected per bit line BL, resulting in a slight increase in chip size. As a result, a 3D-NAND flash memory with four times the memory capacity can be realized with a chip size of 130%.

[0150] FIG. 11 shows the effect of the first embodiment in more detail, showing the relationship between the number of gain blocks per bit line of the memory cell array MA, (a) the read latency (tR), and (b) the chip size.

[0151] 11(a), when the number of word line divisions is increased to 2 or 4, the word line delay is reduced to 1 / 4 or 1 / 8, and the read latency (tR) becomes the delay limiter of the bit line BL. Also, when the number of bit line divisions or the number of gain blocks is increased to 2, 4, 8, or 16, the bit line BL delay is reduced proportionally to 1 / 2, 1 / 4, 1 / 8, or 1 / 16.

[0152] 11(b), in the comparative example (conventional method), as the bit line division progresses, the area of ​​the page buffer PB becomes huge and the chip size increases rapidly. In contrast, in the embodiment, even if the number of bit line divisions increases, the chip size increases only slightly.

[0153] As shown in Figures 11(a) and 11(b), in the comparative example (conventional method), to achieve a read latency of tR = 10 us, it is necessary to divide the word lines WL into four and the bit lines BL into four. In this case, the chip size becomes 2.6 times larger. In contrast, in the embodiment, by combining the conditions of dividing the bit lines into 16 and the word lines into 2, which does not increase the chip size significantly, it is possible to achieve tR = 10 us with a 1.1 times larger chip area.

[0154] FIG. 12 shows the effect of the first embodiment, illustrating the relationship between memory capacity and chip size under constant speed conditions when the memory capacity is increased by stacking word lines WL of a 3D-NAND flash memory. In the comparative example (conventional method) and the working example, increasing the number of stacked word lines increases the area of ​​the WL terrace TR (word line staircase section) and the WL_SG driver (drive circuit). To reduce the area, a different technology is required, and the only way is to reduce the area of ​​the WL terrace TR (word line staircase section). In the bit line direction, an increase in the number of stacked word lines (N times) increases the area of ​​the page buffer (N times) in the comparative example (conventional method), but there is almost no increase in the working example.

[0155] Figure 13 shows the effect of the first embodiment, showing the relationship between memory capacity and cost per gigabyte (GB) when the memory capacity is increased from 1 Tb by stacking word lines WL in a 3D-NAND flash memory. Here, the conditions are constant silicon mobility and constant speed. (a) of Figure 13 shows the case where the number of stacked word lines per layer (per tier) is constant. Here, one tier is the unit for opening memory holes MH by RIE (Reactive Ion Etching). (b) of Figure 13 shows the case where the number of stacked word lines per layer can be gradually increased by increasing the number of stacked word lines.

[0156] 13(a), in the comparative example (conventional method), increasing the number of stacked word lines increases the area of ​​the page buffer PB to compensate for the decrease in cell current Icell, so the cost saturates at 2 Tb. On the other hand, in the embodiment, if the WL terrace TR (word line staircase portion) can be gradually reduced, the cost / GB can continue to decrease by increasing the number of stacked word lines and increasing the memory capacity to 4 Tb to 16 Tb.

[0157] For example, in a conventional structure, a large number of memory cell strings are connected to a bit line BL, reducing the cell current and resulting in a fatal slowdown in operation. In contrast, the configuration according to this embodiment allows for a reduction in the number of memory cell strings MSR connected to each local bit line LBL, significantly reducing the load capacitance driven by the cell current and speeding up read operations to the local bit line LBL. Therefore, even if the number of series-connected memory cell strings MSR is doubled by increasing the number of word lines WL, the load on the local bit line LBL is reduced, achieving speeds equivalent to or even faster than conventional methods. Furthermore, the potential of the local bit line LBL is amplified by the amplifier transistor APT to drive a large-capacity bit line BL, but the number of series-connected transistors in the amplifier section is small, allowing this section to operate at high speed.

[0158] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a case will be described in which the read source line RSL and the source line SL are shared by one semiconductor layer 12. Note that the read source line RSL and the source line SL may be electrically connected via other wiring. Below, differences from the first embodiment will be mainly described.

[0159] An example of the configuration of the read port unit RPB will be described with reference to Figures 14A, 14B, and 14C. Figure 14A is a plan view showing a first example of a planar layout of the read port unit RPB according to the second embodiment. Figure 14B is a plan view showing a second example of a planar layout of the read port unit RPB according to the second embodiment. Figure 14C shows an example of a cross-sectional view of the read port unit RPB according to the second embodiment in the bit line direction (Y direction).

[0160] First, the cross-sectional structure of the read port portion RPB according to the second embodiment will be described with reference to FIG. 14C.

[0161] As shown in FIG. 14C, the semiconductor layer 12 functioning as the read source line RSL is not divided in the Y direction within the read port portion RPB. The semiconductor layer 12 functioning as the read source line RSL extends in the Y direction and is shared with the semiconductor layer 12 functioning as the source line SL. In other words, the pillar RP is connected to the semiconductor layer 12 functioning as the source line SL. The other configurations are the same as those in FIG. 3 of the first embodiment.

[0162] Next, a first example of a planar layout of the read port unit RPB according to the second embodiment will be described with reference to FIG. 14A.

[0163] 14A, in this example, the component SLT arranged between the read control signal lines RBS1 and RBS2 in FIG. 5A of the first embodiment is replaced with a component SHE1. The rest of the layout is the same as FIG. 5A of the first embodiment.

[0164] Next, a second example of the planar layout of the read port unit RPB according to the second embodiment will be described with reference to FIG. 14B.

[0165] 14B, in this example, the unused pillar RP located near the contact plug CP2 described with reference to Fig. 14A is deleted. That is, in this example, the member SLT located between the read control signal lines RBS1 and RBS2 in Fig. 5B of the first embodiment is replaced with a member SHE1.

[0166] The basic effect of this embodiment is the same as that of the first embodiment, in that an amplifier transistor APT is realized using a stacked layer and pillars RP by using the process structure of the cell block CB. The difference from the first embodiment is that the current flowing through the current path of the amplifier transistor APT is shared with the source line SL of the cell block CB via a transistor RST connected to a read control signal line RBS. The read source line RSL is shared with the source line SL connected to the member SLT at the end of the read port unit RPB.

[0167] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, the connection positions of the two pillars WP1 and WP2 and the connection position between the pillar RP and the read source line RSL are different from those in the first embodiment. The following description will focus on the differences from the first and second embodiments.

[0168] An example of the configuration of a gain block gBK according to the third embodiment will be described with reference to FIGS. 15, 16, 17A, and 17B. FIG. 15 shows an example of an equivalent circuit diagram of a gain block gBK according to the third embodiment. FIG. 15 shows an example of a cell block CB including multiple memory cell strings MSR connected to local bit lines LBL, a write port unit WPB that transmits the potential of the bit lines BL to the local bit lines LBL, and a read port unit RPB that amplifies the potential of the local bit lines LBL and transmits it to the bit lines BL. FIG. 16 shows an example of a cross-sectional view of a gain block gBK according to the third embodiment in the bit line direction (Y direction). FIG. 16 shows an example of a cross-sectional structure of a portion of a cell block CB including multiple memory cell strings MSR connected to local bit lines LBL, a write port unit WPB that transmits the potential of the bit lines BL to the local bit lines LBL, and a read port unit RPB that amplifies the potential of the local bit lines LBL and transmits it to the bit lines BL. (a) and (b) of FIG. 17A show cross-sectional views of the write port unit WPB in the word line direction (X direction). (a) and (b) of FIG. 17B show cross-sectional views of the read port unit RPB in the word line direction (X direction).

[0169] As shown in FIG. 15, the circuit configuration of the cell block CB is the same as that of the first embodiment.

[0170] In the write port unit WPB, the source of the transistor WST1 of the string WSR1 connected to the bit line BL is connected to the source of the transistor WST1 of the string WSR2 connected to the local bit line LBL. In this embodiment, the source of the dummy transistor DT of the string WSR1 and the source of the dummy transistor DT of the string WSR2 are not connected to each other.

[0171] In the read port unit RPB, the source of the transistor RST is connected to the read source line RSL. The source of the dummy transistor DT is not connected to the read source line RSL. In this embodiment, the dummy cells DC and dummy transistors DT of the write port unit WPB and the read port unit RPB are not used as current paths.

[0172] As shown in FIG. 16 , the memory pillar MP of this embodiment includes a lower memory pillar LMP and an upper memory pillar UMP provided above the lower memory pillar LMP. The structures of the lower memory pillar LMP and the upper memory pillar UMP are the same as those of the memory pillar MP described with reference to FIG. 3 in the first embodiment. The lower memory pillar LMP penetrates multiple wiring layers 14 functioning as word lines WL or string select signal lines SGS, and its bottom surface contacts the semiconductor layer 12. The upper memory pillar UMP penetrates multiple wiring layers 14 functioning as string select signal lines SGDT or SGD. A contact plug CP1 is provided on the upper memory pillar UMP. In the Z direction, a wiring layer 40 is provided between the wiring layer 14 functioning as the word line WL0 and the wiring layer 14 functioning as the string select signal line SGD. The upper surface of the lower memory pillar LMP and the lower surface (the surface facing the other end in the Z direction) of the upper memory pillar UMP contact the wiring layer 40. The wiring layer 40 in the cell block CB functions as a junction JCT that connects the lower memory pillar LMP and the upper memory pillar UMP included in one memory pillar MP. Therefore, a wiring layer 40 is provided for each memory pillar MP. The wiring layer 40 provided in the cell block CB does not contact the conductor LI of the member SLT. Note that the wiring layer 40 in the cell block CB may be omitted. In this case, the upper memory pillar MP is provided above the lower memory pillar MP.

[0173] 16 and 17A, in the write port unit WPB, the pillar WP has a structure similar to that of the memory pillar MP. In the Z direction, a wiring layer 40 is provided between the wiring layer 14 functioning as the dummy word line dWL and the wiring layer 14 functioning as the write control signal line WBS1.

[0174] The pillar WP1 includes a lower pillar LWP1 and an upper pillar UWP1. Similarly, the pillar WP2 includes a lower pillar LWP2 and an upper pillar UWP2. Hereinafter, when either the lower pillar LWP1 or LWP2 is not specified, it is simply referred to as the "lower pillar LWP." When either the upper pillar UWP1 or UWP2 is not specified, it is simply referred to as the "upper pillar UWP." The semiconductor layer 12 is not provided below the lower pillars LWP1 and LWP2. That is, the semiconductor layer 12 is not provided in the write port section WPB. The upper surfaces of the lower pillars LWP1 and LWP2 and the lower surfaces of the upper pillars UWP1 and UWP2 are in contact with the wiring layer 40. A contact plug CP3 is provided on the upper pillar UWP1, which is connected to the bit line BL (wiring layer 17). A contact plug CP1 is provided on the upper pillar UWP2, which is connected to the local bit line LBL (wiring layer 16). An upper pillar UWP1 connected to the bit line BL via contact plugs CP3 and CP4, and an upper pillar UWP2 connected to the local bit line LBL via contact plug CP1 are provided on one wiring layer 40. The wiring layer 40 provided in the write port unit WPB functions as a middle bit line mBL that electrically connects the two upper pillars UWP1 and UWP2, i.e., the bit line BL and the local bit line LBL.

[0175] 16 and 17B, in the read port unit RPB, the pillar RP has a structure similar to that of the memory pillar MP. In the Z direction, a wiring layer 40 is provided between the wiring layer 14 functioning as the dummy word line dWL and the wiring layer 14 functioning as the read control signal line RBS.

[0176] Each pillar RP includes a lower pillar LRP and an upper pillar URP. As with the write port portion WPB, no semiconductor layer 12 is provided below the lower pillar LRP. That is, no semiconductor layer 12 is provided in the read port portion RPB. The upper surface of the lower pillar LRP and the lower surface of the upper pillar URP are in contact with the wiring layer 40. A contact plug CP3 is provided on the upper pillar URP. The wiring layer 40 provided in the read port portion RPB functions as a read source line RSL that electrically connects the upper pillar URP and the conductor LI of the member SLT. Multiple upper pillars URP are provided on one wiring layer 40.

[0177] The third embodiment achieves the same effects as the first embodiment. Because the capacitance of the local bit line LBL is reduced, the drive time of the local bit line LBL can be shortened even if the number of stacked word lines increases and the cell current Icell decreases. Furthermore, the signal on the local bit line LBL can be used as the input to the amplifier transistor APT in the read port unit RPB to drive the bit line BL at high speed. A write operation is performed by setting the voltages of the write control signal lines WBS0 and WBS1 in the write port unit WPB to a high level to electrically connect the local bit line LBL and the bit line BL. The difference from the first embodiment is that the semiconductor layer 12 is not provided in the read port unit RPB and the write port unit WPB. In the write port unit WPB, a wiring layer 40 functioning as the middle bit line mBL is provided between the wiring layer 14 functioning as the dummy word line dWL and the wiring layer 14 located above it functioning as the write control signal line WBS1. Similarly, in the read port section RPB, a wiring layer 40 functioning as a read source line RSL is provided between a wiring layer 14 functioning as a dummy word line dWL and a wiring layer 14 located above and functioning as a read control signal line RBS.

[0178] In the write port unit WPB, the bit line BL is electrically connected to the local bit line LBL via the transistors WST0 and WST1 of the string WSR1, the wiring layer 40 (middle bit line mBL), and the transistors WST1 and WST0 of the string WSR2.

[0179] In the read port unit RPB, the bit line BL is electrically connected to the wiring layer 40 (read source line RSL) via the amplification transistor APT and the transistor RST.

[0180] In this embodiment, unlike the first embodiment, the dummy cells DC and dummy transistors DT of the strings WSR and RSR are not used as current paths. In this embodiment, the provision of a wiring layer 40 between stacked layers can suppress degradation of parasitic resistance during write and read operations. In the read port section RPB and the write port section WPB, the dummy cells DC corresponding to the dummy word lines dWL and the dummy transistors DT corresponding to the dummy string selection signal lines dSGS located below the wiring layer 40 are in a floating state by removing the semiconductor layer 12, so there are no operational problems. If uniformity in the processing of the memory holes MH and the holes corresponding to the pillars WP and RP is important, the dummy holes below the wiring layer 40 may be left.

[0181] 4. Fourth embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a structure in which the lower memory pillar LMP and the lower pillars LWP and LRP described in the third embodiment are deleted will be described. The following mainly describes the differences from the first to third embodiments.

[0182] An example of the configuration of a gain block gBK according to the fourth embodiment will be described with reference to FIGS. 18, 19, 20A, and 20B. FIG. 18 shows an example of an equivalent circuit diagram of a gain block gBK according to the fourth embodiment. FIG. 18 shows an example of a cell block CB including multiple memory cell strings MSR connected to local bit lines LBL, a write port unit WPB that transmits the potential of the bit lines BL to the local bit lines LBL, and a read port unit RPB that amplifies the potential of the local bit lines LBL and transmits it to the bit lines BL. FIG. 19 shows an example of a cross-sectional view of a gain block gBK according to the fourth embodiment in the bit line direction (Y direction). FIG. 19 shows an example of a cross-sectional structure of a portion of a cell block CB including multiple memory cell strings MSR connected to local bit lines LBL, a write port unit WPB that transmits the potential of the bit lines BL to the local bit lines LBL, and a read port unit RPB that amplifies the potential of the local bit lines LBL and transmits it to the bit lines BL. 20A (a) and (b) show cross-sectional views of the write port unit WPB according to the fourth embodiment in the word line direction (X direction), and FIG. 20B (a) and (b) show cross-sectional views of the read port unit RPB according to the fourth embodiment in the word line direction.

[0183] As shown in FIG. 18, the circuit configuration of the cell block CB is the same as that of the first embodiment.

[0184] The difference from FIG. 15 of the third embodiment is that the dummy cells DC and dummy transistors DT are eliminated from the write port unit WPB and the read port unit RPB.

[0185] As shown in FIGS. 19 and 20A, in this embodiment, the lower pillars LWP1 and LWP2 described with reference to FIGS. 16 and 17A in the third embodiment are eliminated in the write port portion WPB.

[0186] As shown in FIGS. 19 and 20B, in this embodiment, the lower pillar LRP of the pillar RP is eliminated in the read port portion RPB using FIGS. 16 and 17B of the third embodiment.

[0187] The other configurations are the same as those in the third embodiment.

[0188] The fourth embodiment achieves the same effects as the first embodiment, and like the third embodiment, the wiring layer 40 can be used as the connection wiring of the write port unit WPB and as a sink power supply for the current flowing through the amplification transistor APT. The difference from the third embodiment is that the floating and unnecessary pillars formed in the dummy holes below the wiring layer 40 are eliminated.

[0189] 5. Fifth embodiment Next, a fifth embodiment will be described. In the fifth embodiment, an example of a write operation and a read operation will be described. The following mainly describes the differences from the first to fourth embodiments.

[0190] A fifth embodiment will be described with reference to Figures 21A, 21B, and 21C. Figure 21A is a simplified equivalent circuit diagram of a gain block gBK according to the fifth embodiment. Figure 21B is a timing chart showing an example of voltages on each line during a write operation of the nonvolatile semiconductor memory device 1 according to the fifth embodiment. Figure 21C is a timing chart showing an example of voltages on each line during a read operation of the nonvolatile semiconductor memory device 1 according to the fifth embodiment.

[0191] 21A, in the write port unit WPB, the bit line BL is connected to the local bit line LBL via four transistors WST0, WST1, WST1, and WST0 connected in series. A write control signal line WBS0 is connected to the gates of two transistors WST0. A write control signal line WBS1 is connected to the gates of two transistors WST1.

[0192] In the cell block CB, a memory cell string MSR (memory pillar MP) is connected to the local bit line LBL. The memory cell string MSR includes string select transistors STT1, ST1, and ST2, and 2000 memory cells MC0 to MC1999. The current paths of the string select transistors STT1 and ST1, memory cells MC0 to MC1999, and string select transistor ST2 in the memory cell string MSR are connected in series in this order. A string select signal line SGDT0 is connected to the gate of the string select transistor STT1. A string select signal line SGD0 is connected to the gate of the string select transistor ST1. Word lines WL0 to WL1999 are connected to the control gates of the memory cells MC0 to MC1999, respectively. A string select signal line SGS is connected to the gate of the string select transistor ST2.

[0193] In the read port unit RPB, transistors APT and RST are connected in series. The drain of transistor APT is connected to bit line BL, the source is connected to the drain of transistor RST, and the gate is connected to local bit line LBL. The source of transistor RST is connected to read source line RSL, and the gate is connected to read control signal line RBS.

[0194] The write operation will be described with reference to FIG. 21B.

[0195] 21B, first, at time t0, the page buffer PB applies a voltage VBLPG to the bit line BL. The voltage VBLPG is a positive voltage higher than the ground voltage VSS.

[0196] Next, at time t1, in the write port unit WPB, a voltage VWBSon is applied to the write control signal lines WBS0 and WBS1. The voltage VWBSon is a high-level voltage that turns on the transistors WST0 and WST1. By applying a high-level voltage VWBSon to the write control signal lines WBS0 and WBS1, the transistors WST0 and WST1 are turned on. The potential of the bit line BL is transmitted to the local bit line LBL via the transistors WST0 and WST1. Bit information from the page buffer PB (including the sense amplifier circuit and write circuit) is transmitted to the local bit line LBL and memory cell string MSR via the transistors WST0 and WST1. Because the local bit line LBL is shorter and has a smaller load than the bit line BL, the nonvolatile semiconductor memory device 1 can achieve a write speed comparable to that of conventional devices.

[0197] During the period from time t1 to time t2, in the cell block CB, a write operation is executed on memory cells MC selected as write targets (hereinafter also referred to as "selected memory cells MC").

[0198] For example, during the period from time t1 to time t2, the word line WL corresponding to the selected memory cell MC (hereinafter also referred to as the "selected word line WL") is boosted. At this time, if the potential (voltage VBLPG) of the local bit line LBL is low, the string select transistors STT1 and ST1 are turned on. In this case, the potential of the local bit line LBL is transmitted to the silicon channel layer 21 of the selected memory cell MC to be written, and electrons are injected into the charge trap layer 222. Hereinafter, this write operation will be referred to as the "program operation." On the other hand, if the potential (voltage VBLPG) of the local bit line LBL is high, the source potential is high, so the string select transistors STT1 and ST1 are turned off. The silicon channel layer 21 is brought into a floating state, and the silicon channel layer 21 is also boosted as the word line WL is boosted. As a result, almost no electrons are injected into the charge trap layer 222. Hereinafter, this operation will be referred to as the "program inhibit." The write speed is governed by the FN-tunnel current, so it does not deteriorate even if the number of serially connected cells in the memory cell string MSR increases.

[0199] Next, at time t2, after the write operation in the cell block CB is completed, the voltage VSS is applied to the write control signal lines WBS0 and WBS1.

[0200] The read operation will be described with reference to FIG. 21C.

[0201] As shown in FIG. 21C, in a read operation, first, at time t0, a voltage VREAD is applied to an unselected word line. The voltage VREAD is a voltage that turns on the memory cell MC regardless of the threshold voltage. In addition, a voltage VRBSo is applied to the read control signal line RBS. The voltage VRBSo is a voltage that turns on the transistor RST. The voltages VREAD and VRBSo are positive voltages higher than the ground voltage VSS. The voltages VREAD and VRBSo may be the same voltage value or may be different voltage values.

[0202] Next, at time t1, a voltage VBLRD is applied to the bit line BL. The voltage VBLRD is a positive voltage higher than the ground voltage VSS.

[0203] Next, at time t2, a voltage VWBSon is applied to the write control signal lines WBS0 and WBS1. By turning on the transistors WST0 and WST1, the potential of the bit line BL is transferred to the local bit line LBL. For example, a voltage VBLRD is applied to the local bit line LBL.

[0204] Next, at time t3, when the voltage VSS is applied as a low-level voltage to the write control signal lines WBS0 and WBS1, the transistors WST0 and WST1 are turned off, and the local bit line LBL is precharged to the voltage VBLRD and placed in a floating state.

[0205] At this time, the potential of the selected word line WL is gradually increased or set to a fixed potential. In other words, a read voltage is applied to the selected word line WL. If the potential of the selected word line WL is lower than the threshold voltage Vt of the selected memory cell MC, the selected memory cell MC is turned off, and no current flows from the local bit line LBL to the memory cell string MSR. Therefore, the potential of the local bit line LBL is maintained (LBL “1” in FIG. 21C). On the other hand, if the potential of the selected word line WL is higher than the threshold voltage Vt of the selected memory cell, the selected memory cell MC is turned on, and a cell current Icell flows through the memory cell string MSR. Therefore, the potential of the local bit line LBL drops to the ground voltage VSS (LBL “0” in FIG. 21C). In this way, the write information (hereinafter also referred to as the “cell signal”) to the memory cell MC is read (sensed) to the local bit line LBL. At this time, because the capacitance of the local bit line LBL is relatively small, the potential of the local bit line LBL is determined relatively quickly. This result is transmitted to the amplifier transistor APT in the read port unit RPB. The gate of the amplifier transistor APT is connected to the local bit line LBL, and the drain is connected to the bit line BL. The source of the amplifier transistor APT is connected to the transistor RST, whose gate is connected to the read control signal line RBS. The source of the transistor RST is connected to the read source line RSL. When a high-level voltage VRBSo is applied to the read control signal line RBS, the amplifier transistor APT drives the bit line BL, which has a relatively large load capacitance, and the potential of the bit line BL is transmitted to the page buffer PB.

[0206] Next, at time t4, the precharging of the bit line BL by the page buffer PB is released (ended). For example, when the potential of the local bit line LBL is maintained (LBL "1" in FIG. 21C), the amplifier transistor APT is turned on, and the potential of the bit line BL drops (BL "1" in FIG. 21C). On the other hand, when the potential of the local bit line LBL drops (LBL "0" in FIG. 21C), the amplifier transistor APT is turned off, and the potential of the bit line BL is maintained (BL "0" in FIG. 21C).

[0207] The actual potential of the bit line BL is read out as a signal corresponding to the cell signal when the precharge to the bit line BL is released (ended) (the precharge signal is turned off). The number of series connections of this amplifier transistor APT and transistor RST, whose gate input is the read control signal line RBS, is at the level of several transistors, and even when driving the bit line BL, it can be driven more than 10 times faster than driving using the conventional 150 to 250 memory cell strings MSR in series, and the high-speed operation is independent of the number of cells in series.

[0208] 6. Sixth embodiment Next, a sixth embodiment will be described. In the sixth embodiment, an example of a read operation different from that of the fifth embodiment will be described. The following description will focus on the differences from the first to fifth embodiments.

[0209] A sixth embodiment will be described with reference to Figures 22A and 22B. Figure 22A is a timing chart showing an example of voltages of each wiring when a read operation is performed in which coupling noise between local bit lines LBL is reduced in a nonvolatile semiconductor memory device 1 according to the sixth embodiment. Figure 22B is a cross-sectional view showing an example of a cross-sectional structure in which coupling noise between local bit lines LBL is reduced in a nonvolatile semiconductor memory device 1 according to the sixth embodiment.

[0210] 32C and 32D, when one of the string selection signal lines SGD separated by the member SHE1 is selected, information of the memory cells MC is read from all of the memory pillars MP (memory cell strings MSR) connected to the string selection signal line SGD. Therefore, when multiple local bit lines LBL connected to these multiple memory pillars MP are simultaneously operated, a problem occurs in that the local bit lines LBL are subjected to noise derived from the signals of the adjacent memory cell strings MSR due to capacitive coupling with the adjacent local bit lines LBL.

[0211] As shown in FIG. 22B , one way to address the above problem is to form a thin shield metal layer 36 over the side and top surfaces of the wiring layer 16, which functions as the local bit line LBL, via an insulating layer 35. More specifically, a thin insulating layer 35 is formed to cover the multiple wiring layers 16. The insulating layer 35 is thick enough not to fill the spaces between the wiring layers 16. The insulating layer 35 includes, for example, silicon oxide. A shield metal layer 36 is then formed on the insulating layer 35. In this case, it is preferable to form the shield metal layer 36 also on the side surfaces of the local bit line LBL (wiring layer 16). Covering the wiring layer 16 with the shield metal layer 36 increases the inter-wiring capacitance of the local bit line LBL. However, in this embodiment, the length of the local bit line LBL is sufficiently short compared to the length of the bit line BL. Therefore, by providing a large number of gain blocks gBK, the inter-wiring capacitance of the local bit line LBL can be reduced, resulting in no problems in terms of power consumption or speed.

[0212] Another possible method is to read out the potential of the selected local bit line LBL without using the adjacent local bit lines LBL.

[0213] As shown in FIG. 22A, odd-numbered bit lines BLo and even-numbered bit lines BLe are alternately selected.

[0214] More specifically, first, at time t0, a voltage VREAD is applied to the unselected word lines WL, and a voltage VRBSo is applied to the read control signal line RBS.

[0215] Next, at time t1, the voltage VBLRD is applied to the bit lines BLo and BLe.

[0216] Next, at time t2, a voltage VWBSon is applied to both the even and odd write control signal lines WBS0e, WBS1e, WBS0o, and WBS1o. The odd-numbered transistors WST0o and WST1o corresponding to the bit line BLo are turned on, transmitting the potential of the bit line BLo to the odd-numbered local bit line LBLo. Similarly, the even-numbered transistors WST0e and WST1e corresponding to the bit line BLe are turned on, transmitting the potential of the bit line BLe to the even-numbered local bit line LBLe. This causes the voltage VLBLRD to be applied (precharged) to the local bit lines LBLo and LBLe.

[0217] Next, at time t3, the potentials of the write control signal lines WBS0o and WBS1o are maintained at a high level (voltage VWBSon) and the potential of the local bit line LBLo is fixed at a high level (voltage VBLRD), and the ground voltage VSS (low-level voltage) is applied to the write control signal lines WBS0e and WBS1e. This turns off the transistors WST0e and WST1e. At this time, the cell signal is read out to the local bit line LBLe. Since the potential of the adjacent local bit line LBLo is fixed at a high level, coupling noise of the cell signal read out to the local bit line LBLe is suppressed.

[0218] Next, at time t4, the page buffer PB cancels the precharge of the bit line BLe. The potential of the bit line BLe is maintained or decreased based on the potential of the local bit line LBLe. The page buffer PB determines the voltage of the bit line BLe and reads the data on the bit line BLe.

[0219] Next, at time t5, the bit line BLe is precharged again. The ground voltage VSS (low-level voltage) is applied to the write control signal lines WBS0o and WBS1o. This turns off the transistors WST0o and WST1o. At this time, the cell signal is read out to the local bit line LBLo.

[0220] Next, at time t6, the precharge of the bit line BLo by the page buffer PB is released. The potential of the bit line BLo is maintained or decreased based on the potential of the local bit line LBLo. The page buffer PB determines the voltage of the bit line BLo and reads the data of the bit line BLo.

[0221] The signals on the local bit lines LBLo and LBLe can be obtained by applying a high-level voltage (voltage VRBSon) to the read control signal line RBS, amplifying them with the amplifier transistor APT, and then reading them out onto the bit line BL after the precharge of the bit line BL is released. Coupling between the signals on the bit lines BL can be suppressed by current readout while maintaining a constant potential on the bit line BL, such as with a charge transfer method. Note that a high-level voltage may be applied to the read control signal line RBS from the beginning, or a high-level voltage may be applied when the potential on the local bit line LBL is determined, amplified by the amplifier transistor APT, and transmitted to the bit line BL. Furthermore, if the local bit lines LBLe and LBLo are operated separately and at different timings, the signals on the even-numbered read control signal line RBSe and the odd-numbered read control signal line RBSo may be operated separately and at different timings accordingly.

[0222] Next, an example of a planar layout of the write port unit WPB will be described with reference to Fig. 23. Fig. 23 is a plan view showing an example of a planar layout of the write port unit WPB according to the sixth embodiment. Corresponding to the description using Fig. 22A, Fig. 23 shows a plan view of the write port unit WPB for shielding adjacent local bit lines LBL by alternately inputting write control signal lines WBS0o and WBS1o and write control signal lines WBS0e and WBS1e.

[0223] As shown in FIG. 23, in this embodiment, in the write port section WPB, a plurality of wiring layers 14 functioning as write control signal lines WBS0e or WBS1e and a plurality of wiring layers 14 functioning as write control signal lines WBS0o or WBS1o are separated in the Y direction (bit line direction) by a member SHE1.

[0224] The connection positions of the local bit lines LBL (wiring layer 16) and the bit lines BL (wiring layer 17) are divided into even and odd positions for adjacent local bit lines LBL, with write control signal lines WBS0e and WBS1e and write control signal lines WBS0o and WBS1o. This makes it easy to set adjacent local bit lines LBL to a fixed potential or float them, thereby calling the cell current Icell to the local bit lines LBL.

[0225] 7. Seventh embodiment Next, a seventh embodiment will be described. In the seventh embodiment, an example of a read operation different from the fifth and sixth embodiments will be described. The following description will focus on the differences from the first to sixth embodiments.

[0226] The seventh embodiment will be described with reference to Fig. 24. Fig. 24 is a timing chart showing an example of voltages of each wiring when a read operation is performed with reduced coupling noise between local bit lines LBL in the nonvolatile semiconductor memory device 1 according to the seventh embodiment.

[0227] 22A of the sixth embodiment, the cell current Icell of the local bit line LBLe is read first, and then the cell current Icell of the local bit line LBLo is read after the voltage of the bit line BLe is determined. For example, if the local bit line LBLe remains in a floating state after the voltage of the bit line BLe is determined, the signal of the local bit line LBLo may be subject to coupling noise from the nearby local bit line LBLo via the floating local bit line LBLe.

[0228] As shown in Figure 24, the operation from times t1 to t4 is the same as the operation from times t1 to t4 in Figure 22A. At time t3, a low-level voltage (voltage VSS) is applied to the write control signal lines WBS0e and WBS1e to turn off the transistors WST0e and WST1e, and the cell signal is read out to the local bit line LBLe. Next, between times t4 and t5, the amplifying transistor APT transmits the cell signal to the bit line BLe, and the result is input to the page buffer PB.

[0229] Next, at time t5, a high-level voltage (voltage VWBSon) is applied to the write control signal lines WBS0e and WBS1e, thereby turning on the transistors WST0e and WST1e and fixing the local bit line LBLe to the voltage VBLRD.

[0230] Next, at time t6, a low-level voltage (voltage VSS) is applied to the write control signal lines WBS0o and WBS1o to turn off the transistors WST0o and WST1o, and a cell signal is read out to the local bit line LBLo.

[0231] Next, during the period from time t7 to time t8, the amplifying transistor APT transmits the cell signal to the bit line BLo, and the result is fed to the page buffer PB.

[0232] Next, at time t8, a low-level voltage (voltage VSS) is applied to the write control signal lines WBS0e and WBS1e.

[0233] The above flow can eliminate coupling noise on the local bit line LBL. Even if the word lines WL operate simultaneously, the operation slows down when the bit line BL system is read twice. However, according to this embodiment, the operating speed of the local bit lines LBL and bit lines BL can be dramatically increased by increasing the number of gain blocks gBK, so this is not a problem. The potential range of the bit lines BL and local bit lines LBL may be 0 to 0.7V, 0.3V to 1.0V, or −0.2V to 1.2V. To detect memory cells MC with low threshold voltages, the potential range of the bit lines BL and local bit lines LBL may be increased to 0.7V to 1.4V while the potential of the source line SL is set to 0V. In this case, the potential of the read source line RSL may be set to approximately 0.7V. Alternatively, the threshold voltage of the amplifier transistor APT may be increased to set the potential of the read source line RSL to approximately 0V. The range of the potential of the bit line BL and the local bit line LBL can be freely changed by the threshold voltage and margin of the amplification transistor APT.

[0234] 8. Eighth embodiment Next, an eighth embodiment will be described. In the eighth embodiment, two examples of a method for controlling the threshold voltage Vt of the amplification transistor APT will be described. Below, the differences from the first to seventh embodiments will be mainly described.

[0235] An eighth embodiment will be described with reference to Figures 25A, 25B, and 25C. Figure 25A is a timing chart showing an example of a method for measuring the threshold voltage Vt of the amplifier transistor APT according to the eighth embodiment. Figure 25B is a timing chart showing a method for increasing and trimming the threshold voltage Vt of the amplifier transistor APT according to the eighth embodiment. Figure 25C is a timing chart showing a method for decreasing and trimming the threshold voltage Vt of the amplifier transistor APT according to the eighth embodiment.

[0236] For example, when the potential of the read source line RSL is 0V, the amplification transistor APT is turned on (Vgs - Vt = 0.7V - Vt > 0V) when the potential of the local bit line LBL corresponding to "1" data is 0.7V, and the amplification transistor APT is turned off (Vgs - Vt = 0V - Vt < 0V) when the potential of the local bit line LBL corresponding to "0" data is 0V. Therefore, in order for the amplification transistor APT with the local bit line LBL as the gate to operate correctly, 0V < Vt < 0.7V is the operating condition. When the potential (voltage VRSL) of the read source line RSL is varied, the gate-source voltage Vgs of the amplification transistor APT can be adjusted. In this case, 0V < Vt + VRSL < 0.7V is the operating condition. That is, if the threshold voltage Vt is high, the voltage VRSL should be made negative, and if it is low, the voltage VRSL should be made positive. The threshold voltage Vt can be adjusted by an annealing process or the like after ion implantation of impurities into the silicon channel layer 21, and can also be adjusted corresponding to the potential of the read source line RSL. On the other hand, in this embodiment, since the string selection signal layer of the 3D-NAND flash memory can be used as the gate electrode of the amplification transistor APT, the threshold voltage Vt can be adjusted by charge trapping layer 222 or injection / extraction of electrons into / from the floating gate film. Since the amplification transistor APT formed by the pillar RP has a relatively small size, the variation in the threshold voltage Vt is relatively large. Therefore, it is most desirable to measure the threshold voltage Vt of each amplification transistor APT and perform injection / extraction of electrons for each amplification transistor APT to adjust the deviation from the desired threshold voltage Vt individually by program operation / verify operation / erase operation (such adjustment is also referred to as "trimming"). Note that the effective channel area can be increased and the variation can be suppressed by using a plurality of multi-layer string selection signal layers (wiring layer 14 functioning as the local bit line LBL).

[0237] 25A is a timing chart showing a method for measuring variations in the threshold voltage Vt of the amplifier transistor APT. The condition for the amplifier transistor APT to switch from an off state to an on state is (potential of the local bit line LBL) - (potential of the read source line RSL) - threshold voltage Vt = 0 V. Therefore, the threshold voltage Vt can be measured by measuring the relationship between the potential of the local bit line LBL and the potential of the read source line RSL and the on / off operation of the amplifier transistor APT.

[0238] As shown in FIG. 25A, at time t0, a voltage VBLh is applied to the bit line BL. The voltage VBLh is a positive voltage. In this state, if the potential of the local bit line LBL and the potential of the read source line RSL are set in advance, the amplifier transistor APT is turned off when the potential of the local bit line LBL is less than the threshold voltage Vt of the amplifier transistor APT, and is turned on when the potential is equal to or greater than the threshold voltage Vt. At time t1, the precharge of the bit line BL is released. If (potential of the local bit line LBL - read source potential - threshold voltage Vt) is positive (0V or greater), the amplifier transistor APT is turned on, and the potential of the bit line BL decreases. On the other hand, if it is negative (0V or less), the amplifier transistor APT is turned off, and the potential of the bit line BL is maintained. The threshold voltage Vt of the amplifier transistor APT can be measured by changing the potential of the local bit line LBL and the potential of the read source line RSL. For example, if the potential of the local bit line LBL is kept at 0V and the RSL potential is swept from 0V to negative, and the threshold voltage Vt is 0.3V, when the RSL potential drops below -0.3V, the potential of the bit line BL will discharge and drop, and it will be seen that the threshold voltage Vt of the amplification transistor is currently 0.3V.

[0239] If the desired threshold voltage Vt is higher than the measured threshold voltage Vt, electrons can be injected into the charge trapping layer 222 of the amplifier transistor APT. If the desired threshold voltage Vt is lower, electrons can be emitted from the charge trapping layer 222 of the amplifier transistor APT. Specific methods for adjusting the threshold voltage Vt include the FN tunneling method, which involves increasing the source and drain voltages of the amplifier transistor APT by, for example, 15 V or more to lower the threshold voltage Vt, the FN tunneling method, which involves increasing the gate voltage by, for example, 15 V or more to higher than the source and drain voltages to inject electrons into the charge trapping layer 222 and raise the threshold voltage Vt, and the hot carrier effect, which involves increasing the gate voltage higher than the source voltage and the drain voltage higher than the gate voltage to inject electrons into the charge trapping layer 222 and raise the threshold voltage Vt. Using these methods, the threshold voltage Vt can be adjusted before product shipment.

[0240] A method of trimming by increasing the threshold voltage Vt of the amplifier transistor APT will be described with reference to Figure 25B. Figure 25B is a timing chart showing a method of trimming by increasing the threshold voltage Vt of the amplifier transistor APT by injecting electrons due to the hot carrier effect. In the description of Figure 25B, the bit line BL and local bit line LBL corresponding to the amplifier transistor APT that injects electrons to increase the threshold voltage Vt are marked as "Program," and the bit line BL and local bit line LBL corresponding to the amplifier transistor APT that does not inject electrons and does not increase the threshold voltage Vt are marked as "Non-prog."

[0241] As shown in FIG. 25B, at time t0, a voltage VBLPG1 (e.g., 15 V) is applied to the bit line BL (“Program”), and a voltage VWBSon (e.g., 10 V) is applied to the write control signal lines WBS0 and WBS1. The transistors WST0 and WST1 are turned on, and a voltage VBLPG2 (e.g., 7 V) that is a threshold voltage drop of the transistors WST0 and WST1 is applied to the local bit line LBL (“Program”). As a result, for example, a drain-source voltage Vds of 15 V and a gate-source voltage Vgs of 7 V are applied to the amplifier transistor APT corresponding to “Program,” enabling electron injection into the charge trap layer 222 due to the hot carrier effect. In other words, a voltage higher than that applied to the source is applied to the gate of the amplifier transistor APT corresponding to “Program,” and a voltage higher than that applied to the drain is applied to the gate, enabling electron injection into the charge trap layer 222 due to the hot carrier effect. A voltage VSS (e.g., 0V) is applied to the unselected bit lines BL ("Non-prog"), and in the unselected gain blocks gBK, the read control signal line RBS is set to a low-level voltage (e.g., 0V) to stop the hot carriers.

[0242] A method for trimming by lowering the threshold voltage Vt of the amplifier transistors APT will be described with reference to Fig. 25C. Fig. 25C is a timing chart showing a method for trimming by lowering the threshold voltage Vt of all amplifier transistors APT by emitting electrons using the FN tunneling method through an erase operation.

[0243] As shown in FIG. 25C, at time t0, a voltage VERASE is applied to the word line WL and the string select signal lines SGDT, SGD, and SGS. The voltage VERASE turns on the memory cells MC and the string select transistors STT1, ST1, and ST2. This causes electrons in the local bit line LBL to be released to the source line SL. At this time, the potential of the local bit line LBL is, for example, 0 V.

[0244] Next, at time t1, a voltage VH (e.g., 20 V) is applied to the read source line RSL to inject holes from the read source line RSL to the bit line BL by band-to-band tunneling, or the potential of the bit line BL is increased to voltage VH (e.g., 20 V) to increase the source and drain potentials of the amplifier transistor APT to voltage VH (e.g., 20 V) higher than the gate potential (e.g., 0 V). This allows an erase operation to be performed, which releases electrons from the charge trap layer 222 of the amplifier transistor APT, thereby lowering the threshold voltage Vt. For example, when the potential of the local bit line LBL is 0 V and the potential of the bit line BL is 20 V, the high electric field difference between the bit line BL and the local bit line LBL can be gradually alleviated by applying a voltage VWBS of, for example, 10 V to the write control signal line WBS0 and a voltage VSS (e.g., 0 V) ​​to the write control signal line WBS1.

[0245] 9. Ninth embodiment Next, a ninth embodiment will be described. In the ninth embodiment, which is different from the eighth embodiment, two examples of a method for increasing the threshold voltage Vt of the amplifier transistor APT and performing trimming will be described. Below, the differences from the first to eighth embodiments will be mainly described.

[0246] The ninth embodiment will be described with reference to Fig. 26A and Fig. 26B. In the description of Fig. 26A and Fig. 26B, the bit line BL and local bit line LBL corresponding to the amplification transistor APT that injects electrons to increase the threshold voltage Vt are denoted as "Program," and the bit line BL and local bit line LBL corresponding to the amplification transistor APT that does not inject electrons and does not increase the threshold voltage Vt are denoted as "Non-prog."

[0247] First, a first example of a method for trimming the threshold voltage Vt will be described with reference to Fig. 26A, which is a timing chart showing a first example of a method for increasing and trimming the threshold voltage Vt of the amplification transistor APT according to the ninth embodiment.

[0248] As shown in FIG. 26A, at time t0, a voltage VBL1 (e.g., 10V) is applied to the bit line BL ("Program") . A voltage VWBS1 (e.g., 10V) is applied to the write control signal lines WBS0 and WBS1. This turns on the transistors WST0 and WST1. Furthermore, a voltage VWL1a (e.g., 10V) is applied to the word lines WL and string select signal lines SGDT and SGD of the cell block CB. This turns on the memory cells MC and string select transistors STT1 and ST1. A voltage VLBL1a (e.g., an intermediate potential of about 10V) is applied to the local bit line LBL ("Program") (and the silicon channel layer 21 connected thereto). The voltage VLBL1a is a positive voltage lower than the voltage VWBS1.

[0249] Next, at time t1, voltage VSS is applied to bit line BL ("Program"), and voltage VSS is applied to write control signal line WBS1. This turns off transistor WST1, preventing backflow of precharged charges from bit line BL to local bit line LBL ("Program").

[0250] Next, at time t2, a voltage VWL1b (e.g., 20V) is applied to the word lines WL and string select signal lines SGDT and SGD of the cell block CB to boost them. The voltage VWL1b is higher than the voltage VWL1a. Using the gate-channel capacitance of the memory cell string MSR, the voltage of the local bit line LBL ("Program") is boosted to a voltage VLBL1b (e.g., approximately 19V) by self-boosting. At this time, the voltage of the local bit line LBL ("Non-prog") is boosted to a voltage VLBL1c (e.g., approximately 9V). The voltage VLBL1c is lower than the voltage VLBL1b. A voltage VSS (e.g., 0V) is applied to the write control signal line WBS1. The voltage VSS is applied to the bit line BL and the read source line RSL. In this state, a voltage VLBL1b (e.g., 19 V) is applied to the gate of the amplifier transistor APT corresponding to the local bit line LBL ("Program"), and a voltage VSS (e.g., 0 V) ​​is applied to the source and drain. This allows the threshold voltage Vt of the amplifier transistor APT to be increased and trimmed by electron injection due to FN tunneling.

[0251] Next, at time t3, after trimming is completed, the voltage VSS is applied to the word line WL and the string selection signal lines SGDT and SGD, which causes the voltage of the local bit line LBL, which has been boosted by self-boost, to drop.

[0252] Next, at time t4, a voltage VWBS1 is applied to the write control signal line WBS1, which turns on the transistor WST0, causing electrons in the local bit line LBL to be released to the bit line BL.

[0253] Next, at time t5, the voltage VSS is applied to the write control signal lines WBS0 and WBS1.

[0254] Next, a second example of a method for trimming the threshold voltage Vt will be described with reference to Fig. 26B, which is a timing chart showing a second example of a method for increasing and trimming the threshold voltage Vt of the amplification transistor APT according to the ninth embodiment.

[0255] As shown in FIG. 26B, at time t0, a voltage VBL2 (e.g., 2V) is applied to the bit line BL ("Program"), and a voltage VSS (e.g., 0V) is applied to the bit line BL ("Non-prog"). A voltage VWBS2a (e.g., 2V) and a voltage VWBS2b (e.g., 10V) are applied to the write control signal lines WBS1 and WBS0, respectively. The voltage VWBS2a is, for example, the same voltage as the voltage VBL2. The voltage VWBS2b is a voltage higher than the voltage VWBS2a. As a result, a voltage VLBL2a is applied to the local bit line LBL ("Program"). The voltage VLBL2a is a voltage lower than the voltage VWBS2a.

[0256] Next, at time t1, as in the description of FIG. 26A , a voltage VWL2 (e.g., 20 V) is applied to the word lines WL and the string select signal lines SGDT and SGD of the cell block CB to boost them. In the case of the bit line BL (“Non-prog”), the potential of the local bit line LBL (“Non-prog”) is passed to the bit line BL (“Non-prog”), so the potential of the local bit line LBL (“Non-prog”) remains at voltage VSS (e.g., 0 V). In contrast, in the case of the bit line BL (“Program”), for example, the voltage VBL2 and the voltage VWBS2a are the same value, so the gate-source voltage Vgs of the transistor WST1 becomes 0 V. Therefore, in the transistor WST1, the backflow of charge from the local bit line LBL (“Program”) to the bit line BL (“Program”) is stopped. Due to the self-boosting of the memory cell string MSR, the local bit line LBL (“Program”) is boosted to voltage VBL2b (e.g., 18 V). In this state, a voltage VBL2b (e.g., 18 V) is applied to the gate of the amplifier transistor APT corresponding to the local bit line LBL ("Program"), a voltage VSS (e.g., 0 V) ​​is applied to the source, and a voltage VBL2 (e.g., 2 V) is applied to the drain. This allows the threshold voltage Vt of the amplifier transistor APT to be increased and trimmed by electron injection due to FN tunneling. If it is desired to also apply voltage VBL2 (e.g., 2 V) to the drain of the amplifier transistor APT corresponding to the local bit line LBL ("Non-prog"), a low-level voltage that turns off the transistor RST can be applied to the read control signal line RBS. This turns off the transistor RST, and electrons on the bit line BL ("Non-prog") become a dead end, so that the source of the amplifier transistor APT has the same potential as the gate.

[0257] Next, at time t2, after trimming is completed, the voltage VSS is applied to the word line WL and the string selection signal lines SGDT and SGD, which causes the voltage of the local bit line LBL ("Program"), which had been boosted by self-boost, to drop.

[0258] Next, at time t3, the voltage VSS is applied to the bit line BL (“Program”), which causes the local bit line LBL (“Program”) to also drop to the voltage VSS.

[0259] Next, at time t4, the voltage VSS is applied to the write control signal line WBS1.

[0260] Next, at time t5, the voltage VSS is applied to the write control signal line WBS0.

[0261] 10. Tenth embodiment Next, a tenth embodiment will be described. In the tenth embodiment, two examples of a method for trimming the threshold voltage Vt of the amplification transistor APT that differ from the eighth and ninth embodiments will be described. The following description will focus on the differences from the first to ninth embodiments.

[0262] The tenth embodiment will be described with reference to Figures 27A and 27B. In the description of Figures 27A and 27B, the bit line BL and local bit line LBL corresponding to the amplification transistor APT that injects electrons to increase the threshold voltage Vt are denoted as "Program," and the bit line BL and local bit line LBL corresponding to the amplification transistor APT that does not inject electrons and does not increase the threshold voltage Vt are denoted as "Non-prog."

[0263] First, a method of trimming by increasing the threshold voltage Vt will be described with reference to Fig. 27A, which is a timing chart showing a method of trimming by increasing the threshold voltage Vt of the amplification transistor APT according to the tenth embodiment.

[0264] As shown in FIG. 27A, first, at time t0, a voltage VBL3a (e.g., 10V) is applied to the bit lines BL ("Program") and BL ("Non-prog"). A voltage VWBS3a (e.g., 20V) is applied to the write control signal lines WBS0 and WBS1. For example, the voltage VWBS3a is higher than the voltage VBL3a. The transistors WST0 and WST1 are turned on. As a result, a voltage VLBL3a is applied to the local bit lines LBL ("Program") and LBL ("Non-prog"). For example, the voltage VLBL3a has the same voltage value as the voltage VBL3a.

[0265] Next, at time t1, a voltage VBL3b (e.g., 20V) is applied to the bit line BL ("Program"). The voltage VBL3b is higher than the voltage VBL3a. As a result, a voltage VLBL3b (e.g., 19V) is applied to the local bit line LBL ("Program"). The voltage VLBL3b is higher than the voltage VLBL3a. That is, a boosted potential is written from the bit line BL ("Program") to the local bit line LBL ("Program"). Furthermore, to maintain the bit line BL at 20V, the RST transistor must be turned off. However, to maintain the transistor's withstand voltage, two RST transistors controlled by read control signal lines RBS0 and RBS1 in series may be connected below the APT transistor as shown in FIG. 27A. This allows the two series transistors RST to be turned off while gradually reducing the 20V potential difference.

[0266] Next, at time t2, a voltage VBL3a is applied to the bit line BL ("Program"). A voltage VWBS3b (e.g., 10V) is applied to the write control signal lines WBS0 and WBS1. The voltage VWBS3b is lower than the voltage VWBS3a. Since the transistors WST0 and WST1 corresponding to the local bit line LBL ("Program") are cut off, the local bit line LBL ("Program") maintains the voltage VLBL3b.

[0267] Next, at time t3, a voltage VSS (e.g., 0V) is applied to the bit lines BL (“Program”) and BL (“Non-prog”), the write control signal line WBS1, and the read control signal lines RBS0 and RBS1. In this state, a voltage VLBL3b (e.g., 19V) is applied to the gate of the amplifier transistor APT corresponding to the local bit line LBL (“Program”), a voltage VSS (e.g., 0V) is applied to its source, and a voltage VSS (e.g., 0V) is applied to its drain. This allows electron injection by FN tunneling to increase the threshold voltage Vt of the amplifier transistor APT, thereby enabling trimming. The write control signal lines WBS0 and WBS1 are moved stepwise at times t2 and t3 to alleviate the electric field, for example, to prevent stress of 10V or more from being applied.

[0268] Next, at time t4, a voltage VWBS3b is applied to the write control signal line WBS1, causing electrons in the local bit line LBL to be released to the bit line BL.

[0269] Next, a method of trimming by lowering the threshold voltage Vt will be described with reference to Fig. 27B, which is a timing chart showing a method of trimming by lowering the threshold voltage Vt of the amplification transistor APT according to the tenth embodiment.

[0270] As shown in FIG. 27B, first, at time t0, a voltage VBL4 (e.g., 10V) is applied to the bit line BL ("Non-prog"). A voltage VWBS4 (e.g., 10V) is applied to the write control signal lines WBS0 and WBS1. The transistors WST0 and WST1 are turned on. This causes a voltage VLBL4 (e.g., 10V) to be applied to the local bit line LBL ("Non-prog"). Note that the voltage VLBL4 may be the same voltage value as the voltage VBL4, or may be a voltage lower than the voltage VBL4.

[0271] Next, at time t1, a voltage VSS (e.g., 0V) is applied to the bit line BL ("Non-prog") and the write control signal line WBS1. The transistor WST1 is turned off. The local bit line LBL ("Program") holds the voltage VSS (e.g., 0V), and the local bit line LBL ("Non-prog") holds the voltage VLBL4 (near 10V).

[0272] Next, at time t2, a voltage VRSL (e.g., about 20V) is applied to the read source line RSL and the bit line BL. Electron emission by FN tunneling allows selectively lowering and trimming the threshold voltage Vt of the amplification transistor APT corresponding to the local bit line LBL ("Program") For example, since the potential of the local bit line LBL moves in the range of 0V to 10V, a boost trap is not required. In other words, using the method shown in FIG. 26B, 0V, for example, is applied to the bit line BL ("Program"), and 2V, for example, is applied to the bit line BL ("Non-prog"). Then, by boosting the word line WL and the string selection signal lines SGDT and SGD, the voltage of the local bit line LBL ("Program") is set to, for example, 0V, and the voltage of the local bit line LBL ("Non-prog") is set to, for example, 10V. In this state, the threshold voltage Vt of the amplification transistor APT may be lowered by boosting the read source line RSL and the bit line BL to 20 V and selectively releasing electrons from the charge trap layer 222. For example, a voltage of 2 V instead of 10 V may be applied to the bit line BL, and as shown in FIG. 26B, the voltage of the local bit line LBL ("Non-prog") may be set to, for example, 10 V and the voltage of the local bit line LBL ("Program") may be set to, for example, 0 V by self-boosting.

[0273] 11. Eleventh embodiment Next, an eleventh embodiment will be described. In the eleventh embodiment, two examples of the planar layout of the read port unit RPB will be described. The following mainly describes the differences from the planar layout of the read port unit RPB described using FIGS. 5A and 5B in the first embodiment.

[0274] An eleventh embodiment will be described with reference to FIGS. 28A and 28B.

[0275] First, a first example of a planar layout of the read port unit RPB will be described with reference to Fig. 28A, which is a plan view showing a first example of a planar layout of the read port unit RPB according to the eleventh embodiment.

[0276] As shown in FIG. 28A, in this embodiment, in the region between two members SLT adjacent to each other in the Y direction, multiple pillars RP are arranged in a row across a width of, for example, nine columns in the X direction. The nine columns of memory pillars MP are arranged in a staggered pattern so that the X-direction positions of adjacent memory pillars MP in the Y direction are different from each other. Three members SHE1 are provided between two members SLT. That is, six members SHE1 are provided in the read port unit RPB. As in FIG. 5A of the first embodiment, the upper six wiring layers 14 functioning as the local bit lines LBL or read control signal lines RBS of the read port unit RPB are divided into eight parts in the Y direction by the members SLT and SHE1. That is, the wiring layers 14 functioning as the local bit lines LBL or read control signal lines RBS are divided into eight parts in the Y direction. In this embodiment, the eight read control signal lines RBS0 to RBS7 are arranged in this order, for example, from the left side of the drawing.

[0277] In the example shown in FIG. 28A , the first, third, fourth, and sixth members SHE1 from the left side of the page are provided between two pillars RP adjacent in the Y direction. More specifically, the first member SHE1 from the left side of the page is provided between the pillars RP in the second row and the pillars RP in the third row from the left side of the page. The third member SHE1 from the left side of the page is provided between the pillars RP in the seventh row and the pillars RP in the eighth row from the left side of the page. The fourth member SHE1 from the left side of the page is provided between the pillars RP in the eleventh row and the pillars RP in the twelfth row from the left side of the page. The sixth member SHE1 from the left side of the page is provided between the pillars RP in the sixteenth row and the pillars RP in the seventeenth row from the left side of the page. The second and fifth members SHE1 from the left side of the page are provided so as to divide the upper portions of the pillars RP in the fifth and fourteenth rows from the left side of the page, respectively.

[0278] The plurality of wiring layers 17 functioning as bit lines BL are electrically connected to any of the pillars RP in the first, third, sixth, eighth, tenth, twelfth, fifteenth, and seventeenth columns from the left side of the paper.

[0279] The other configurations are the same as those in the first embodiment.

[0280] Next, a second example of the planar layout of the read port unit RPB will be described with reference to Fig. 28B. Fig. 28B is a plan view showing a second example of the planar layout of the read port unit RPB according to the eleventh embodiment. The following description will focus on differences from the first example described with reference to Fig. 28A.

[0281] As shown in Figure 28B, in this example, similar to Figure 5B of the first embodiment, the pillar RP located near the contact plug CP2 in Figure 28A has been removed to make it easier to connect the contact plug CP2 and the wiring layer 14 that functions as the local bit line LBL.

[0282] This embodiment is similar to the first embodiment shown in FIGS. 5A and 5B, and also has the same main effects. The difference is that in FIGS. 5A and 5B, the separation of the string selection signal layer (the wiring layer 14 functioning as the local bit line LBL or the read control signal line RBS) using the member SHE1 is performed at the center of the pillars RP arranged side by side in the X direction. In contrast, in FIGS. 28A and 28B, some of the members SHE1 are provided between pillars RP adjacent to each other in the Y direction. This has the effect of reducing the gate area of ​​the amplification transistor APT and downsizing the read port unit RPB.

[0283] 12. Twelfth embodiment Next, a twelfth embodiment will be described. In the twelfth embodiment, a cross-sectional structure of a gain block gBK that is different from those of the first to eleventh embodiments will be described. The following description will focus on the differences from the first to eleventh embodiments.

[0284] The twelfth embodiment will be described with reference to Fig. 29. Fig. 29 shows an example of a cross-sectional view in the bit line direction (Y direction) of a gain block gBK according to the twelfth embodiment. Fig. 29 shows an example of a cross-sectional structure of a part of a cell block CB including a plurality of memory cell strings MSR connected to one local bit line LBL, a write port unit WPB that transmits the potential of the bit line BL to the local bit line LBL, and a read port unit RPB that amplifies the potential of the local bit line LBL and transmits it to the bit line BL.

[0285] 29, in this example, three additional wiring layers 14 (dummy string selection signal layers) are provided above the stacked layers (2009 wiring layers 14) of the cell block CB, read port unit RPB, and write port unit WPB described with reference to FIG. 19 of the fourth embodiment. More specifically, in the description with reference to FIG. 19, six wiring layers 14 are provided above the wiring layer 40, but in this example, as shown in FIG. 29, nine wiring layers 14 are provided above the wiring layer 40. In other words, nine wiring layers 14 (string selection signal layers) are provided above the wiring layers 14 (word line layers) that function as word lines WL or dummy word lines dWL.

[0286] In the cell block CB, nine wiring layers 14 provided above the wiring layer 40 (JCT) function, from the top, as six string select signal lines SGDT and three string select signal lines SGD. The upper nine wiring layers 14 functioning as the string select signal lines SGDT or SGD are divided into string units SU by members SHE1 extending in the X direction. Upper memory pillars UMP are provided that penetrate the upper nine wiring layers 14 and have their lower surfaces in contact with the wiring layer 40. Lower memory pillars LMP are provided below the wiring layer 40, as in FIG. 19. The lower memory pillars LMP penetrate 2000 wiring layers 14 functioning as word lines WL0 to WL1999 and three wiring layers 14 functioning as string select signal lines SGS. In this embodiment, in the upper memory pillars UMP, N + A diffusion layer 50 (diffusion layer region) is formed. For example, N + In the diffusion layer 50, phosphorus (P) or arsenic (As) is implanted as an impurity into the silicon channel layer 21. For example, N + Diffusion layers 50 are formed in the same layer as the upper three wiring layers 14 (string selection signal lines SGDT). + A diffusion layer 50 is formed. + The position of the lower side of the diffusion layer 50 may be higher than the wiring layer 14 (string selection signal line SGDT), which is the third layer from the top.

[0287] In the write port unit WPB, the nine wiring layers 14 provided above the wiring layer 40 (mBL) function, from the top layer side, as a six-layer write control signal line WBS0 and a three-layer write control signal line WBS1. The upper nine wiring layers 14 functioning as the write control signal line WBS0 or the write control signal line WBS1 are divided by a member SHE1 extending in the X direction. Upper pillars UWP1 and UWP2 are provided which penetrate the upper nine wiring layers 14 and whose lower surfaces contact the wiring layer 40. As with the upper memory pillar UMP, in the upper pillars UWP1 and UWP2, N + A diffusion layer 50 is formed.

[0288] In the read port section RPB, nine wiring layers 14 provided above the wiring layer 40 (RSL) function, from the upper layer side, as six local bit lines LBL and three read control signal lines RBS. The upper nine wiring layers 14 functioning as local bit lines LBL or read control signal lines RBS are divided by a member SHE1 extending in the X direction. The upper six wiring layers 14 functioning as local bit lines LBL are electrically connected to the wiring layer 16 functioning as local bit lines LBL via contact plugs CP2. As with the upper memory pillar UMP and upper pillar UWP, in the upper pillar URP, N + A diffusion layer 50 is formed.

[0289] By adding three wiring layers 14 (dummy string selection signal layers) to the upper layer, N is formed at the contact portion with the local bit line LBL or the bit line BL. + When the diffusion layer 50 is formed, N + The diffusion layer length of the diffusion layer 50 varies, and N + Even if the bottom end of the diffusion layer 50 is present, there is no problem. + The memory pillar MP and the pillars WP and RP provided with the diffusion layer 50 are N +The string selection transistor STT1, the transistor WST0, and the amplification transistor APT, which correspond to the wiring layer 14 in the same layer as the diffusion layer 50, have a low threshold voltage Vt and are always in an on state. + This is because the control threshold voltage Vt is determined by the string select transistor STT1, transistor WST0, and amplifier transistor APT, which correspond to the wiring layer 14, which is in the same layer as the non-doped silicon channel layer 21 without the diffusion layer 50. This dummy additional string select signal layer (wiring layer 14) is applicable to all other embodiments. In this embodiment, an example has been shown in which the read control signal line RBS and the write control signal lines WBS0 and WBS1 are all configured with three string select signal layers (wiring layers 14), but each signal line may be configured with one or two layers, or with more than three layers.

[0290] 13. Thirteenth embodiment Next, a thirteenth embodiment will be described. In the thirteenth embodiment, a cross-sectional structure of a gain block gBK that is different from those of the first to twelfth embodiments will be described. The following description will focus on the differences from the first to twelfth embodiments.

[0291] A thirteenth embodiment will be described with reference to Fig. 30. Fig. 30 shows an example of a cross-sectional view of a gain block gBK according to the thirteenth embodiment in the bit line direction (Y direction). Fig. 30 shows an example of the cross-sectional structure of a part of a cell block CB including a plurality of memory cell strings MSR connected to one local bit line LBL, a write port unit WPB that transmits the potential of the bit line BL to the local bit line LBL, and a read port unit RPB that amplifies the potential of the local bit line LBL and transmits it to the bit line BL.

[0292] 30, in this embodiment, a plurality of additional wiring layers 14 functioning as dummy string select signal lines dSGD or dSGDT are provided above the wiring layer 14 functioning as the string select signal line SGDT or SGD of the cell block CB. In the example shown in Fig. 30, the six additional wiring layers 14 are used for the dummy string select signal line dSGDT or dSGD in the cell block CB, but are used for the write control signal line WBS0 or WBS1 in the read port unit RPB, and for the local bit line LBL or the read control signal line RBS in the write port unit WPB.

[0293] More specifically, for example, in a cell block CB, a wiring layer 40 is provided as a junction JCT above a wiring layer 14 that functions as a string select signal line SGDT. Six wiring layers 14 are provided above the wiring layer 40, spaced apart in the Z direction. Of the six wiring layers 14, the upper three function as dummy string select signal lines dSGDT, and the lower three function as dummy string select signal lines dSGDT. The memory pillars MP include upper memory pillars UMP and lower memory pillars LMP. The upper memory pillars UMP penetrate the six wiring layers 14 that function as the dummy string select signal lines dSGDT or dSGD, and their lower surfaces contact the wiring layer 40. The lower memory pillars LMP penetrate the six wiring layers 14 that function as the string select signal lines SGDT or SGD, the 2000th wiring layer 14 that function as word lines WL0 to WL1999, and the three wiring layers 14 that function as the string select signal lines SGS. The lower surface of the lower memory pillar LMP is in contact with the semiconductor layer 12, and the upper surface is in contact with the wiring layer 40.

[0294] The member SHE1 divides, in the Y direction, the six wiring layers 14 that function as the dummy string selection signal lines dSGDT or dSGD and the six wiring layers 14 that function as the string selection signal lines SGDT or SGD.

[0295] In the write port unit WPB, six wiring layers 14 are provided above the wiring layer 40 functioning as the middle bit line mBL, spaced apart in the Z direction. Of the six wiring layers 14, the top three function as the write control signal line WBS0, and the bottom three function as the write control signal line WBS1. The pillars WP1 and WP2 include upper pillars UWP1 and UWP2, respectively. The upper pillars UWP1 and UWP2 penetrate the six wiring layers 14 functioning as the write control signal line WBS0 or WBS1, and their lower surfaces contact the wiring layer 40 (mBL). The lower pillars LWP1 and LWP2 are not provided. The six wiring layers 14 functioning as the string select signal line SGDT or SGD in the cell block CB function as the dummy string select signal line dSGDT or dSGD in the write port unit WPB. That is, the 2009th wiring layer 14 located below the wiring layer 40 (mBL) is treated as a dummy layer.

[0296] In the read port unit RPB, six wiring layers 14 are provided above the wiring layer 40 functioning as the read source line RSL, spaced apart in the Z direction. Of the six wiring layers 14, the top three function as the local bit line LBL, and the bottom three function as the read control signal line RBS. The pillars RP include upper pillars URP. The upper pillars URP penetrate the six wiring layers 14 functioning as the local bit line LBL or the read control signal line RBS, and their lower surfaces contact the wiring layer 40 (RSL). No lower pillars LRP are provided. As in the write port unit WPB, the six wiring layers 14 functioning as the string select signal line SGDT or SGD in the cell block CB function as the dummy string select signal line dSGDT or dSGD in the read port unit RPB. That is, the 2009 wiring layers 14 located below the wiring layer 40 (RSL) are treated as dummy layers.

[0297] In the write port unit WPB, the wiring layer 14 used as the write control signal line WBS0 or WBS1 can be selected arbitrarily. Any layer of the stacked layers formed by the multiple wiring layers 14 may be used as the write control signal line WBS0 or WBS1. In the read port unit RPB, the wiring layer 14 used as the local bit line LBL or the read control signal line RBS can be selected arbitrarily. Any layer of the stacked layers formed by the multiple wiring layers 14 may be used as the gate electrode of the amplification transistor APT. Because the stacked layers are collectively separated by members SLT and SHE1, etc., increasing the number of stacked layers does not significantly increase the process cost. With this device configuration, even if the number of stacked word lines is doubled, the read speed and write speed do not decrease. Furthermore, since additional transistors dedicated to the read port unit RPB and the write port unit WPB are not required, increasing the number of stacked word lines significantly reduces the bit cost, thereby realizing a faster 3D-NAND flash memory.

[0298] 14. Fourteenth embodiment Next, a fourteenth embodiment will be described. In the fourteenth embodiment, a configuration of the nonvolatile semiconductor memory device 1 that is different from the first to thirteenth embodiments will be described. The following description will focus on the differences from the first to thirteenth embodiments.

[0299] The fourteenth embodiment will be described with reference to Fig. 31. Fig. 31 shows an example of the cross-sectional structure of a gain block gBK in an array chip in the bit line direction (Y direction) and an example of the circuit configuration of a CMOS chip connected to a local bit line LBL.

[0300] As shown in FIG. 31 , the array chip includes a memory cell array MA. The memory cell array MA includes multiple cell blocks CB. Each cell block CB includes multiple wiring layers 16 functioning as local bit lines LBL and multiple memory pillars MP connected to each wiring layer 16. In other words, the memory cell array MA includes multiple cell blocks CB, each including multiple memory cell strings MSR connected to the local bit lines LBL. The configuration of each cell block CB is the same as that described with reference to FIG. 3 in the first embodiment. In the example shown in FIG. 31 , the memory cell array MA includes N (N is a natural number) cell blocks CB0 to CB(N-1). For example, the cell block CB0 includes multiple wiring layers 16 functioning as the local bit line LBL0. Similarly, the cell block CB(N-1) includes multiple wiring layers 16 functioning as the local bit line LBL(N-1).

[0301] The CMOS chip includes a write port unit WPB that transmits the potential of the bit line BL to the local bit line LBL, and a read port unit RPB that amplifies the potential of the local bit line LBL and transmits it to the bit line BL. In the example shown in Figure 31, the CMOS chip includes N write port units WPB0 to WPB(N-1) and N read port units RPB0 to RPB(N-1) corresponding to cell blocks CB0 to CB(N-1).

[0302] The write port unit WPB0 includes a transistor WST0. The drain of the transistor WST0 is connected to the bit line BL. The source of the transistor WST0 is electrically connected to the gate of the amplifier transistor APT0 and the local bit line LBL0 of the cell block CB0. The gate of the transistor WST0 is connected to a write control signal line WBS0. Similarly, the write port unit WPB(N-1) includes a transistor WST(N-1). The drain of the transistor WST(N-1) is connected to the bit line BL. The source of the transistor WST(N-1) is electrically connected to the gate of the amplifier transistor APT(N-1) and the local bit line LBL(N-1) of the cell block CB(N-1). The gate of the transistor WST(N-1) is connected to a write control signal line WBS(N-1).

[0303] The read port unit RPB0 includes an amplifier transistor APT0 and a transistor RST0. The amplifier transistor APT0 and the transistor RST0 are connected in series. The drain of the amplifier transistor APT0 is connected to the bit line BL. The source of the transistor RST0 is connected to a specific power supply such as a read source line RSL, or is grounded. Similarly, the read port unit RPB(N-1) includes an amplifier transistor APT(N-1) and a transistor RST(N-1). The amplifier transistor APT(N-1) and the transistor RST(N-1) are connected in series. The drain of the amplifier transistor APT(N-1) is connected to the bit line BL. The source of the transistor RST(N-1) is connected to a specific power supply such as a read source line RSL, or is grounded.

[0304] In the example shown in FIG. 31 , the nonvolatile semiconductor memory device 1 has a laminated structure in which an array chip and a CMOS chip are bonded together. More specifically, the array chip includes a plurality of electrode pads 60 provided on a surface facing the CMOS chip. The CMOS chip includes a plurality of electrode pads 61 provided on a surface facing the array chip. In the laminated structure, the electrode pads 60 and 61 are bonded together to form a single laminated pad. In other words, the conductor included in the electrode pad 60 is bonded to the conductor included in the electrode pad 61. The laminated pad functions as a current path between the array chip and the CMOS chip. The surface where the array chip and the CMOS chip are bonded together is also referred to as the “lamination surface.” Note that the nonvolatile semiconductor memory device 1 does not necessarily have a laminated structure. The above-mentioned CMOS chip side circuit (including the write port unit WPB and the read port unit RPB) may be provided on the FEOL side (transistor section) of the same silicon substrate as the array chip. In this case, the local bit lines LBL may be pulled down from the memory cell array MA to the FEOL side, and the read port unit RPB and write port unit WPB may be configured using bulk transistors formed on a silicon substrate.

[0305] The configuration of this embodiment eliminates the need for a read port unit RPB and a write port unit WPB within the memory cell array MA, thereby suppressing an increase in the size of the memory cell array MA. In this case, the CMOS chip (FEOL side) requires bit lines BL with a fine wiring pitch similar to that of the memory cell array MA. High-voltage transistors are required for the amplifier transistors APT. A triple-well configuration is required because the transistors in the write port unit WPB and the read port unit RPB are boosted during erase operations. Furthermore, a relatively large amplifier transistor APT or trimming of the threshold voltage Vt of the amplifier transistor APT is required to suppress variations in the threshold voltage Vt. Since the amplifier transistor APT does not have a charge trap layer 222, adjusting the threshold voltage Vt takes time.

[0306] 15.Other The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0307] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0308] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0309] 1...Nonvolatile semiconductor memory device 11, 13, 15, 35...insulating layers 12...Semiconductor layer 14, 16, 17, 40...wiring layer 20...Core membrane 21...Silicon channel layer 22...Laminated film 30, LI...Conductor 36...Shield metal layer 50...N+ diffusion layer 60, 61...Electrode pads 221...Tunnel insulating layer 222...Charge trap layer 223...Block insulation layer APT, APT0, APT(N-1)...Amplifying transistors BL, BLe, BLo...bit lines CB, CB0 to CB(N-1)...Cell Block CC, CP1 to CP4...contact plugs DC: Dummy cell DRV...Driver DT...dummy transistor DV…WL_SG driver JCT: Junction LBL, LBL0 to LBL(N-1)...Local bit lines LMP: Lower memory pillar LRP, LWP, LWP1, LWP2...Lower pillar MA: Memory cell array MC, MC0 to MC1999...Memory cells MH...Memory Hole MP…Memory Pillar MSR...Memory cell string PB...Page buffer PC...peripheral circuits PD: Pad area RBS, RBS0 to RBS7...Read control signal lines RP, WP, WP1, WP2... Pillar RPB, RPB0 to RPB(N-1)...Read port section RSL: Lead source line RSR, WSR1, WSR2...Strings RST, RST0, RST(N-1), WST, WST0, WST0e, WST0o, WST1, WST1e, WST1o, WST(N-1)...transistors SGD, SGD0 to SGD3, SGDT, SGDT0 to SGDT3, SGS...String selection signal lines SHE1, SHE2, SLT...components SP...Spacer ST1, STT1, ST2... String select transistors SL...Source line SU, SU0-SU4...String unit TR…WL Terrace WBS0, WBS0e, WBS0o, WBS1, WBS1e, WBS1o, ... Write control signal lines UMP: Upper memory pillar URP, UWP, UWP1, UWP2... upper pillars WL, WL0~1999...word lines WPB, WPB0 to WPB(N-1)...Write port section bBL...Bottom bit line dWL...dummy word line dSGDT, dSGD, dSGS, ... dummy string selection signal lines gBK, gBK0 to gBK15...Gain block mBL...middle bit line

Claims

1. a plurality of first wiring layers extending in a first direction and stacked at intervals in a second direction intersecting the first direction; a memory pillar extending in the second direction and passing through the plurality of first wiring layers; a local bit line provided at one end side of the plurality of first wiring layers in the second direction and spaced apart from the plurality of first wiring layers, extending in a third direction intersecting the first direction and the second direction, and electrically connected to the one end side of the memory pillar in the second direction; a bit line provided at one end of the local bit line in the second direction and spaced apart from the local bit line, the bit line extending in the third direction; a plurality of second wiring layers extending in the first direction, stacked at a distance from each other in the second direction, and arranged side by side with the plurality of first wiring layers in the third direction; a first pillar extending in the second direction, passing through the plurality of second wiring layers, and having the local bit line electrically connected to one end side of the first pillar in the second direction; a second pillar extending in the second direction, passing through the plurality of second wiring layers, electrically connected to the bit line at one end side in the second direction, and electrically connected to the first pillar; a plurality of third wiring layers extending in the first direction, stacked at a distance from each other in the second direction, and arranged side by side with the plurality of first wiring layers in the third direction; a third pillar extending in the second direction, passing through the plurality of third wiring layers, and having the bit line electrically connected to the one end side in the second direction; Equipped with At least one of the plurality of third wiring layers is electrically connected to the local bit line. Nonvolatile semiconductor memory device.

2. The memory pillar is an insulator extending in the second direction; a silicon channel layer extending in the second direction and surrounding the insulator; a tunnel insulating layer extending in the second direction and surrounding a side surface of the silicon channel layer; a charge trapping layer extending in the second direction and surrounding a side surface of the tunnel insulating layer; a block insulating layer extending in the second direction and surrounding a side surface of the charge trapping layer; Including, Each of the first to third pillars is a conductor extending in the second direction; the insulator extending in the second direction and provided so as to contact the one end side of the conductor in the second direction; the silicon channel layer extending in the second direction and surrounding the conductor and the insulator; the tunnel insulating layer extending in the second direction and surrounding a side surface of the silicon channel layer; the charge trapping layer extending in the second direction and surrounding a side surface of the tunnel insulating layer; the block insulating layer extending in the second direction and surrounding a side surface of the charge trapping layer; Including, 2. The nonvolatile semiconductor memory device according to claim 1.

3. a first semiconductor layer provided on the other end side of the plurality of first wiring layers in the second direction and spaced apart from the plurality of first wiring layers, the first semiconductor layer being in contact with the other end side of the memory pillar in the second direction; a second semiconductor layer provided on the other end side of the second wiring layers in the second direction and spaced apart from the second wiring layers, located in the same layer as the first semiconductor layer, and in contact with the other end side of the first pillar in the second direction and the other end side of the second pillar in the second direction; a third semiconductor layer that is provided on the other end side of the third wiring layers in the second direction and is spaced apart from the third wiring layers, that is located in the same layer as the first semiconductor layer and the second semiconductor layer, and that contacts the other end side of the third pillar in the second direction; Further comprising:

2. The nonvolatile semiconductor memory device according to claim 1.

4. a fourth semiconductor layer provided at the other end side of the plurality of first wiring layers and the plurality of third wiring layers in the second direction and spaced apart from the plurality of first wiring layers and the plurality of third wiring layers, and in contact with the other end side of the memory pillar in the second direction and the other end side of the third pillar in the second direction; a fifth semiconductor layer that is provided on the other end side of the plurality of second wiring layers in the second direction and is spaced from the plurality of second wiring layers, that is located in the same layer as the fourth semiconductor layer, and that is in contact with the other end side of the first pillar in the second direction and the other end side of the second pillar in the second direction; Further comprising:

2. The nonvolatile semiconductor memory device according to claim 1.

5. a fourth wiring layer provided between any of the plurality of second wiring layers in the second direction; a fifth wiring layer provided between any of the plurality of third wiring layers in the second direction and positioned in the same layer as the fourth wiring layer; Further provided with the memory pillars include a lower memory pillar extending in the second direction, and an upper memory pillar extending in the second direction, provided on the one end side of the lower memory pillar in the second direction, and electrically connected to the lower memory pillar; the first pillar includes a fourth pillar that extends in the second direction, has one end side in the second direction to which the local bit line is electrically connected, and has the other end side in the second direction to which the fourth wiring layer is in contact; the second pillar includes a fifth pillar that extends in the second direction, has one end side in the second direction to which the bit line is electrically connected, and has the other end side in the second direction in contact with the fourth wiring layer; the third pillar includes a sixth pillar that extends in the second direction, has one end side in the second direction to which the bit line is electrically connected, and has the other end side in the second direction in contact with the fifth wiring layer; 2. The nonvolatile semiconductor memory device according to claim 1.

6. the silicon channel layer includes a diffusion layer region provided on the one end side in the second direction.

3. The nonvolatile semiconductor memory device according to claim 2.

7. the blocking insulating layer includes a ferroelectric material and operates by polarization; 3. The nonvolatile semiconductor memory device according to claim 2.

8. the blocking insulating layer and the charge trapping layer are ferroelectric layers; 3. The nonvolatile semiconductor memory device according to claim 2.

9. A page buffer; a bit line connected to the page buffer; a plurality of gain blocks connected to the bit lines; Equipped with The gain block comprises: Local bit lines and a cell block including a memory cell string including a first string select transistor, a second string select transistor, a plurality of memory cells, and a third string select transistor connected in series, one end of a current path being connected to the local bit line and the other end of the current path being connected to a source line; a write port unit configured to transmit the potential of the bit line to the local bit line; a read port unit configured to amplify the potential of the local bit line and transmit the amplified potential to the bit line; Including, Nonvolatile semiconductor memory device.

10. The light port portion a first transistor connected to the bit line; a second transistor connected to the local bit line; a third transistor having one end connected to the first transistor, the other end connected to the second transistor, and a gate connected to a first control signal line; Including, 10. The nonvolatile semiconductor memory device according to claim 9.

11. The read port portion is a fourth transistor having one end connected to the bit line and a gate connected to the local bit line; a fifth transistor having one end connected to the other end of the fourth transistor, the other end connected to the read source line, and a gate connected to the second control signal line; Including, 10. The nonvolatile semiconductor memory device according to claim 9.

12. the threshold voltage of the fourth transistor is greater than 0V and less than 0.7V; 12. The nonvolatile semiconductor memory device according to claim 11.

13. the fourth transistor includes a charge trapping layer; When lowering the threshold voltage of the fourth transistor, a first voltage is applied to the gate, and a second voltage higher than the first voltage is applied to the source and drain, thereby releasing electrons from the charge trapping layer.

12. The nonvolatile semiconductor memory device according to claim 11.

14. the fourth transistor includes a charge trapping layer; When increasing the threshold voltage of the fourth transistor, a third voltage is applied to the source and the drain, and a fourth voltage higher than the third voltage is applied to the gate, thereby injecting electrons into the charge trapping layer.

12. The nonvolatile semiconductor memory device according to claim 11.

15. the fourth transistor includes a charge trapping layer; when the threshold voltage of the fourth transistor is increased, a fifth voltage is applied to the source, a sixth voltage higher than the fifth voltage is applied to the gate, and a seventh voltage higher than the sixth voltage is applied to the drain, thereby injecting electrons into the charge trap layer by a hot carrier effect; 12. The nonvolatile semiconductor memory device according to claim 11.

16. In a read operation of a selected memory cell among the plurality of memory cells, When the threshold voltage of the selected memory cell is higher than the determination potential, the selected memory cell is turned off, the voltage of the local bit line becomes higher than the threshold voltage of the fourth transistor, the fourth transistor is turned on, and when the precharge of the bit line is released, the voltage of the bit line drops; When the threshold voltage of the selected memory cell is lower than the determination potential, the selected memory cell is turned on, the voltage of the local bit line becomes lower than the threshold voltage of the fourth transistor, the fourth transistor is turned off, and the voltage of the bit line does not decrease even when the precharge of the bit line is released.

12. The nonvolatile semiconductor memory device according to claim 11.

17. a plurality of first wiring layers extending in a first direction and stacked at intervals in a second direction intersecting the first direction; a memory pillar extending in the second direction and passing through the plurality of first wiring layers; a local bit line provided at one end side of the plurality of first wiring layers in the second direction and spaced apart from the plurality of first wiring layers, extending in a third direction intersecting the first direction and the second direction, and electrically connected to the one end side of the memory pillar in the second direction; a cell block including A page buffer; a bit line connected to the page buffer; a write port unit configured to transmit the potential of the bit line to the local bit line; a read port unit configured to amplify the potential of the local bit line and transmit the amplified potential to the bit line; Equipped with The memory pillar is an insulator extending in the second direction; a silicon channel layer extending in the second direction and surrounding the insulator; a tunnel insulating layer extending in the second direction and surrounding a side surface of the silicon channel layer; a charge trapping layer extending in the second direction and surrounding a side surface of the tunnel insulating layer; a block insulating layer extending in the second direction and surrounding a side surface of the charge trapping layer; Including, Nonvolatile semiconductor memory device.

18. The light port portion a first transistor having one end connected to the bit line, the other end connected to the local bit line, and a gate connected to a first control signal line; Including, 18. The nonvolatile semiconductor memory device according to claim 17.

19. The read port portion is a second transistor having one end connected to the bit line and a gate connected to the other end of the first transistor and the local bit line; a third transistor having one end connected to the other end of the second transistor, the other end connected to a specific power supply, and a gate connected to the second control signal line; Including, 19. The nonvolatile semiconductor memory device according to claim 18.

20. a first chip including the page buffer, the bit lines, the write port unit, and the read port unit; a second chip including the cell block; Further provided with The first chip and the second chip are bonded together.

18. The nonvolatile semiconductor memory device according to claim 17.

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