Circuit device and switching regulator

Abstract

To provide a circuit device or the like capable of switching to a suitable feedback control system according to a load current of a switching regulator.SOLUTION: The circuit device 100 includes the control circuit 120 that performs the voltage mode control or the hysteresis control and performs the switching control on the switching element 111 based on the result of the voltage mode control or the hysteresis control, and the mode determination circuit 150 that determines, based on the inductor current IL flowing through the inductor 10, the first mode in which the voltage mode control is performed and the second mode in which the hysteresis control is performed. When the mode determination circuit 150 determines that the operation mode is the first mode, the control circuit 120 performs switching control of the switching element 111 based on the result of the voltage mode control. When the mode determination circuit 150 determines that the operation mode is the second mode, the control circuit 120 performs switching control of the switching element 111 based on the result of the hysteresis control.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, a switching regulator, and the like. [Background technology]

[0002] Patent Document 1 discloses a DC-DC converter that includes an error amplifier that compares the output voltage with a reference voltage, a peak current comparator that compares the coil current with the output of the error amplifier to generate a peak detection voltage, an off-time timer circuit that generates an off-time signal that sets the off time, control logic that generates a signal that drives the power stage based on the peak detection voltage and the off-time signal, and a power stage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0083583 Summary of the Invention [Problem to be solved by the invention]

[0004] Various control methods for switching regulators are known, such as voltage mode control and hysteresis control, and it is desirable to use an appropriate method depending on the load current of the switching regulator. For example, in Patent Document 1, feedback control is performed using one method, and the method is not changed in response to changes in the load current. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device used in a switching regulator that outputs an output voltage by regulating a power supply voltage using an inductor and a switching element that drives the inductor, the circuit device including: a control circuit that performs voltage mode control or hysteresis control to control the output voltage to a given constant voltage, and that controls the switching of the switching element based on a result of the voltage mode control or the hysteresis control; and a mode determination circuit that determines, based on an inductor current flowing through the inductor, a first mode in which the voltage mode control is performed and a second mode in which the hysteresis control is performed; and when the mode determination circuit determines the first mode, the control circuit controls the switching of the switching element based on the result of the voltage mode control, and when the mode determination circuit determines the second mode, the control circuit controls the switching of the switching element based on the result of the hysteresis control.

[0006] Another aspect of the present disclosure relates to a switching regulator including the above circuit device, the switching element, and the inductor. [Brief explanation of the drawings]

[0007] [Figure 1] An example of a switching regulator configuration. [Figure 2] An explanatory diagram of the operation of a switching regulator. [Figure 3] 10 shows an example of a detailed configuration of a control circuit. [Figure 4] Truth table describing the operation of the pre-driver. [Figure 5] FIG. 2 is a diagram illustrating a first operation example of the switching regulator. [Figure 6] FIG. 10 is a diagram illustrating a second operation example of the switching regulator. [Figure 7] FIG. 10 is a diagram illustrating a third operation example of the switching regulator. [Figure 8] 10 shows a detailed configuration example of a mode determination circuit. [Figure 9]FIG. 4 is a diagram illustrating the operation of a mode determination circuit. [Figure 10] A detailed example of the current detection circuit configuration. [Figure 11] 10 is a signal waveform example illustrating the operation of the current detection circuit when the load current is relatively large and no reverse current is detected. [Figure 12] 6 is a signal waveform example illustrating the operation of the current detection circuit when the load current is relatively small and a reverse current is detected. [Figure 13] 1 shows a first detailed configuration example of a voltage mode control circuit and a hysteresis control circuit. [Figure 14] 10 is a first detailed configuration example of a pulse signal output circuit. [Figure 15] 10 shows a detailed configuration example of an off timer when the length of the off time is variable. [Figure 16] An example of detailed configuration of the on timer. [Figure 17] Example waveforms illustrating continuous operation in first mode or voltage mode control. [Figure 18] Example waveforms illustrating discontinuous operation in first mode or voltage mode control. [Figure 19] Example waveforms illustrating the second mode, or hysteresis control. [Figure 20] An example of the operating waveforms of a switching regulator when the load current fluctuates. [Figure 21] An example of the operating waveforms of a switching regulator when the load current fluctuates. [Figure 22] 2 shows a second detailed configuration example of a voltage mode control circuit and a hysteresis control circuit. [Figure 23] 10 shows a second detailed configuration example of a pulse signal output circuit. [Figure 24] 10 shows an example of the operating waveform of a switching regulator to which the second detailed configuration example is applied. [Figure 25] 10 shows an example of the operating waveform of a switching regulator to which the second detailed configuration example is applied. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0009] 1.Configuration example 1 shows an example of the configuration of a switching regulator 200. The switching regulator 200 includes a circuit device 100, an inductor 10, and a capacitor 20. The switching regulator 200 is also called a DC-DC converter. The inductor 10 is also called a coil.

[0010] The switching regulator 200 regulates a power supply voltage VIN to an output voltage VOUT and supplies the output voltage VOUT to a load 30. A power supply circuit (not shown) is provided outside or inside the circuit device 100, and the power supply voltage VIN is supplied from the power supply circuit to the circuit device 100. The load 30 is, for example, a microcomputer that controls an electronic device including the switching regulator 200, but is not limited to this and may be various circuits.

[0011] The circuit device 100 includes a switching element 111, an N-type MOS transistor 112, a control circuit 120, and a mode determination circuit 150. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. While FIG. 1 shows an example in which the switching element 111 and the N-type MOS transistor 112 are built into the circuit device 100, they may also be provided outside the circuit device 100. Furthermore, while FIG. 1 shows an example in which the inductor 10 and the capacitor 20 are provided outside the circuit device 100, one or both of them may also be built into the circuit device 100.

[0012] The switching element 111 is a P-type MOS transistor. The source of the switching element 111 is connected to a node of a power supply voltage VIN, and the drain is connected to a node NSW. A drive signal DRP from the control circuit 120 is input to the gate of the switching element 111. When the switching element 111 is on, the inductor 10 is driven by the power supply voltage VIN. Note that the switching element 111 may be any element that can be switched under the control of the control circuit 120, and may be, for example, an N-type MOS transistor or a bipolar transistor.

[0013] The source of the N-type MOS transistor 112 is connected to the ground node, and the drain is connected to the node NSW. A drive signal DRN from the control circuit 120 is input to the gate of the N-type MOS transistor. Although an example in which the switching regulator 200 is a synchronous type has been described here, in the case of an asynchronous type, a diode may be provided instead of the N-type MOS transistor. The anode of the diode may be connected to the ground node, and the cathode may be connected to the node NSW.

[0014] One end of the inductor 10 is connected to the node NSW, and the other end is connected to an output node NVOUT at which the output voltage VOUT is output. One end of the capacitor 20 is connected to the output node NVOUT, and the other end is connected to the ground node.

[0015] The mode determination circuit 150 determines the feedback control mode of the switching regulator based on the inductor current IL flowing through the inductor 10, and outputs the result as a mode signal SMODE. The modes include a first mode in which voltage mode control is performed, and a second mode in which hysteresis control is performed. The mode determination circuit 150 determines the mode based on the current flowing through the switching element 111, i.e., the drain current of the P-type MOS transistor that is the switching element 111.

[0016] The output voltage VOUT is input to the control circuit 120. The control circuit 120 pulse-modulates the drive signals DRP and DRN so that the output voltage VOUT becomes a given constant voltage. Hereinafter, the given constant voltage may be referred to as a target voltage. The control circuit 120 includes a voltage-mode control circuit 310 that performs pulse modulation control using voltage-mode control, and a hysteresis control circuit 330 that performs pulse modulation control using hysteresis control. When the mode signal SMODE indicates the first mode, the control circuit 120 outputs the drive signals DRP and DRN based on the output signal of the voltage-mode control circuit 310. When the mode signal SMODE indicates the second mode, the control circuit 120 outputs the drive signals DRP and DRN based on the output signal of the hysteresis control circuit 330.

[0017] Voltage mode control is a method of controlling the on-time of the switching element 111 by comparing an error voltage indicating the error between the output voltage VOUT and a given constant voltage with the slope voltage without using the inductor current IL to generate the slope voltage. Hysteresis control is a method of using a comparator to compare the output voltage VOUT with a given constant voltage and using the result to control the switching element 111. The on-time may be constant or controlled by the hysteresis of the comparator.

[0018] FIG. 2 is a diagram illustrating the operation of the switching regulator 200 of FIG. 1. The mode determination circuit 150 compares the inductor current IL with a first threshold ITa. The mode determination circuit 150 determines the first mode when the inductor current IL is equal to or greater than the first threshold ITa, and determines the second mode when the inductor current IL is less than the first threshold ITa. The mode determination circuit 150 may switch the mode immediately after the inductor current IL falls below or exceeds the first threshold ITa, or may switch the mode at a predetermined timing after the inductor current IL falls below or exceeds the first threshold ITa, as described later with reference to FIG. 20 and other figures.

[0019] In this embodiment, the circuit device 100 is used in a switching regulator 200. The switching regulator 200 outputs an output voltage VOUT by regulating a power supply voltage VIN using an inductor 10 and a switching element 111 that drives the inductor 10. The circuit device 100 includes a control circuit 120 and a mode determination circuit 150. The control circuit 120 performs voltage-mode control or hysteresis control to maintain the output voltage VOUT at a given constant voltage, and controls the switching of the switching element 111 based on the results of the voltage-mode control or hysteresis control. The mode determination circuit 150 determines whether the mode is a first mode in which voltage-mode control is performed or a second mode in which hysteresis control is performed, based on an inductor current IL flowing through the inductor 10. When the mode determination circuit 150 determines that the first mode is selected, the control circuit 120 controls the switching of the switching element 111 based on the results of the voltage-mode control. When the mode determination circuit 150 determines that the second mode is selected, the control circuit 120 controls the switching of the switching element 111 based on the result of the hysteresis control.

[0020] According to this embodiment, the switching regulator 200 has a feedback path based on voltage-mode control and a feedback path based on hysteresis control. The control mode is switched between voltage-mode control and hysteresis control based on the mode determination result based on the inductor current IL. This makes it possible to switch to an appropriate feedback method depending on the load current Id of the switching regulator 200.

[0021] In this embodiment, the mode determination circuit 150 may compare the inductor current IL with a first threshold ITa. The mode determination circuit 150 may determine the first mode when the inductor current IL is equal to or greater than the first threshold ITa, and may determine the second mode when the inductor current IL is smaller than the first threshold ITa.

[0022] According to this embodiment, voltage-mode control is selected when the inductor current IL is equal to or greater than the first threshold ITa, and hysteresis control is selected when the inductor current IL is less than the first threshold ITa. In this way, an appropriate feedback control is selected depending on the load current Id. Furthermore, as described below, switching the control mode allows unused circuits to be shut down, thereby enabling lower power consumption. For example, the hysteresis control circuit 330 has fewer components than the voltage-mode control circuit 310, reducing power consumption. Therefore, by setting the voltage-mode control circuit 310 to a low power setting during hysteresis control, power consumption during low loads can be reduced. Under low loads, the power consumption of the switching regulator 200 reduces power efficiency, but reducing power consumption improves power efficiency.

[0023] 2. Detailed configuration example 3 shows a detailed configuration example of the control circuit 120. The control circuit 120 includes a first voltage dividing circuit 131, a second voltage dividing circuit 132, a mode determination circuit 150, a pre-driver 170, a backflow detection circuit 180, a voltage mode control circuit 310, a hysteresis control circuit 330, and a pulse signal output circuit 380.

[0024] The first voltage divider circuit 131 divides the output voltage VOUT and outputs the resulting first feedback voltage FBA to a node NFBA. The first voltage divider circuit 131 includes a resistor RA1 and a resistor RA2. One end of the resistor RA1 is connected to the output node NVOUT and the other end is connected to a node NFBA. One end of the resistor RA2 is connected to the node NFBA and the other end is connected to a ground node. The voltage division ratio is RA2 / (RA1+RA2), and FBA=VOUT×(RA2 / (RA1+RA2)).

[0025] The voltage mode control circuit 310 performs voltage mode control to make the first feedback voltage FBA equal to the first reference voltage VR1, thereby controlling the output voltage VOUT to a target voltage, which is the output voltage VOUT that satisfies the equation VR1=VOUT×(RA2 / (RA1+RA2)).

[0026] The second voltage divider circuit 132 divides the output voltage VOUT and outputs the resulting second feedback voltage FBB to a node NFBB. The second voltage divider circuit 132 includes resistors RB1 and RB2. One end of the resistor RB1 is connected to the output node NVOUT and the other end is connected to a node NFBB. One end of the resistor RB2 is connected to the node NFBB and the other end is connected to a ground node. The voltage division ratio is RB2 / (RB1+RB2), where FBB=VOUT×(RB2 / (RB1+RB2)).

[0027] The hysteresis control circuit 330 performs hysteresis control to make the second feedback voltage FBB equal to the second reference voltage VR2, thereby controlling the output voltage VOUT to a target voltage, which is the output voltage VOUT that satisfies the equation VR2=VOUT×(RB2 / (RB1+RB2)).

[0028] The first reference voltage VR1, the second reference voltage VR2, the voltage division ratio of the first voltage divider circuit 131, and the voltage division ratio of the second voltage divider circuit 132 are set so that the target voltage for voltage-mode control and the target voltage for hysteresis control are the same. For example, VR1 = VR2 may be set. In this case, the voltage division ratio of the first voltage divider circuit 131 may be the same as the voltage division ratio of the second voltage divider circuit 132. The voltage division ratio of the first voltage divider circuit 131 and the voltage division ratio of the second voltage divider circuit 132 may be variable. For example, the resistors RA2 and RB2 may each be a variable resistor. In this case, the circuit device 100 may include a register (not shown) that sets the resistance value of the variable resistor, and the resistance values ​​of the resistors RA2 and RB2 may be set based on the set value. The first reference voltage VR1 and the second reference voltage VR2 may be supplied, for example, from a voltage generation circuit (not shown) included in the circuit device 100 or from outside the circuit device 100.

[0029] When the mode signal SMODE indicates the first mode, the pulse signal output circuit 380 outputs a pulse signal QOUT based on the output signal of the voltage-mode control circuit 310. The pulse signal QOUT is a signal that indicates whether the switching element 111 is on or off, and in the first mode, is a signal that is pulse-modulated by voltage-mode control. When the mode signal SMODE indicates the second mode, the pulse signal output circuit 380 outputs a pulse signal QOUT based on the output signal of the hysteresis control circuit 330. In the second mode, the pulse signal QOUT is a signal that is pulse-modulated by hysteresis control.

[0030] The reverse current detection circuit 180 detects the reverse current of the inductor current IL flowing through the inductor 10. Specifically, a sense resistor RSN is provided between the source of the N-type MOS transistor 112 and the ground node. The reverse current detection circuit 180 is a comparator that compares the voltage VRSN at one end of the sense resistor RSN with the ground voltage and outputs the result as the reverse current detection signal ZCMPO. FIG. 3 shows an example in which the voltage VRSN is input to the negative input terminal of the comparator serving as the reverse current detection circuit, and the ground voltage is input to the positive input terminal. When VRSN<0V, a high-level reverse current detection signal ZCMPO is output. When the inductor current IL reverses, VRSN≧0V, and a low-level reverse current detection signal ZCMPO is output. Note that the reverse current detection circuit 180 may disable reverse current detection and output a high-level reverse current detection signal ZCMPO when the pulse signal QOUT is high.

[0031] The pre-driver 170 controls the switching of the switching element 111 and the N-type MOS transistor 112 based on the pulse signal QOUT and the reverse current detection signal ZCMPO. FIG. 4 is a truth table explaining the operation of the pre-driver 170. In FIG. 4, "L" indicates a low level, and "H" indicates a high level. Furthermore, for the drive signal DRP related to the on / off of the switching element 111 and the drive signal DRN related to the on / off of the N-type MOS transistor 112, both on or off and the logical level are indicated, such as "OFF(H)."

[0032] When the backflow detection signal ZCMPO is at a high level, i.e., when no backflow is detected, the pre-driver 170 exclusively turns on or off the switching element 111 and the N-type MOS transistor 112 in response to the pulse signal QOUT. That is, when the pulse signal QOUT is at a low level, the pre-driver 170 turns off the switching element 111 and turns on the N-type MOS transistor 112. When the pulse signal QOUT is at a high level, the pre-driver 170 turns on the switching element 111 and turns off the N-type MOS transistor 112. When the backflow detection signal ZCMPO is at a low level, i.e., when a backflow is detected, the pre-driver 170 turns on or off the switching element 111 in response to the logic level of the pulse signal QOUT, and turns off the N-type MOS transistor 112 regardless of the logic level of the pulse signal QOUT. When the pulse signal QOUT is at a low level, the pre-driver 170 turns off the switching element 111, and when the pulse signal QOUT is at a high level, the pre-driver 170 turns on the switching element 111.

[0033] FIG. 5 is a diagram illustrating a first operation example of the switching regulator 200 using the control circuit 120 of FIG. 3. In this operation example, the voltage mode control circuit 310 is set to a low power setting during part of the second mode period. The low power setting means that some or all of the circuits are stopped or in a low power consumption state. The stopped state means that operation is stopped by stopping the supply of power or bias current, etc. The low power consumption state is a state in which power consumption is reduced by reducing or partially stopping the bias current, etc.

[0034] The second mode, in which hysteresis control is performed, is divided into a third mode and a fourth mode depending on the inductor current IL. Specifically, the mode determination circuit 150 compares the inductor current IL with a second threshold ITb, which is smaller than the first threshold ITa. The mode determination circuit 150 determines the third mode when the inductor current IL is smaller than the first threshold ITa and equal to or greater than the second threshold ITb, and determines the fourth mode when the inductor current IL is smaller than the second threshold ITb. The voltage-mode control circuit 310 performs normal operation in the first and third modes and switches to a low-power setting in the fourth mode. The hysteresis control circuit 330 performs normal operation in all of the first, third, and fourth modes.

[0035] 6 is a diagram illustrating a second operation example of the switching regulator 200 using the control circuit 120 of FIG. 3. In this operation example, the voltage mode control circuit 310 is set to low power throughout the entire period of the second mode. In this operation example, the third and fourth modes do not necessarily have to be provided.

[0036] FIG. 7 illustrates a third example of operation of the switching regulator 200 using the control circuit 120 of FIG. 3. In this example, the hysteresis control circuit 330 is set to a low power setting in the first mode. The voltage-mode control circuit 310 is set to a low power setting in, for example, the fourth mode. Alternatively, the voltage-mode control circuit 310 may be set to a low power setting throughout the entire second mode period, as shown in FIG. 6, or may perform normal operation in any mode.

[0037] As described above, by setting the voltage mode control circuit 310 and the hysteresis control circuit 330 that are not selected by the mode to a low power setting, it is possible to reduce power loss in the switching regulator 200. Reducing power loss can improve the power efficiency of the switching regulator 200. In particular, when the load current Id is small, the power supplied to the load is small, so the power loss in the switching regulator 200 may significantly reduce power efficiency. In this embodiment, when the load current Id is small, hysteresis control is selected, and the voltage mode control circuit 310 that is not used at that time is set to a low power setting. This improves power efficiency under low load conditions.

[0038] 8 shows a detailed configuration example of the mode determination circuit 150. The mode determination circuit 150 includes a current detection circuit 190 and a comparison circuit 155. Here, an example is shown in which the mode determination circuit 150 outputs a 2-bit mode signal SMODE[1:0]. Note that the current detection circuit 190 may be provided outside the circuit device 100, in which case the mode determination circuit 150 may include only the comparison circuit 155.

[0039] The current detection circuit 190 detects the inductor current IL and outputs the result as a voltage VIL. The voltage VIL increases as the inductor current IL increases. Because the inductor current IL changes according to the load current Id, the voltage VIL can also be considered a voltage corresponding to the load current Id. The current detection circuit 190 converts the drain current of the switching element 111 into a voltage, peak-holds the voltage based on the pulse signal QOUT, and outputs the voltage VIL based on the peak-held voltage. The current detection circuit 190 reduces the peak-held voltage based on the reverse current detection signal ZCMPO, allowing the load current Id to be more accurately reflected in the voltage VIL. Details of the current detection circuit 190 will be described later with reference to FIG. 10.

[0040] The comparison circuit 155 includes resistors RD1 to RD3 and comparators 151 and 152. The resistors RD1 to RD3 are connected in series between the node of the voltage VIL and the ground node, and output voltages VM1 and VM2 obtained by dividing the voltage VIL. The voltage VM1 is lower than the voltage VM2. The comparator 151 compares the voltage VM1 with the reference voltage VREF, and outputs the result as the bit SMODE[0] of the mode signal. FIG. 8 shows an example in which the reference voltage VREF is input to the positive input terminal of the comparator 151 and the voltage VM1 is input to the negative input terminal. In this case, the comparator 151 outputs a low-level bit SMODE[0] when VM1≧VREF, and outputs a high-level bit SMODE[0] when VM1<VREF. The comparator 152 compares the voltage VM2 with the reference voltage VREF, and outputs the result as the bit SMODE[1] of the mode signal. FIG. 8 shows an example in which the reference voltage VREF is input to the positive input terminal of the comparator 151 and the voltage VM2 is input to the negative input terminal. In this case, the comparator 152 outputs a low-level bit SMODE[1] when VM2≧VREF, and outputs a high-level bit SMODE[1] when VM2<VREF.

[0041] FIG. 9 is a diagram for explaining the operation of the mode determination circuit 150 in FIG. 8. The first threshold voltage VTa and the second threshold voltage VTb with respect to the voltage VIL respectively correspond to the first threshold current ITa and the second threshold current ITb with respect to the inductor current IL. In the correspondence with FIG. 8, VIL = VTa is equivalent to VM1 = VREF, and VIL = VTb is equivalent to VM2 = VREF. The comparison circuit 155 outputs a mode signal SMODE[1:0]=00b indicating the first mode when IL≧ITa, that is, when VIL≧VTa. The b at the end of 00b indicates that 00 is a binary number. The comparison circuit 155 outputs a mode signal SMODE[1:0]=01b indicating the third mode when ITa>IL≧ITb, that is, when VTa>VIL≧VTb. The comparison circuit 155 outputs a mode signal SMODE[1:0]=11b indicating the fourth mode when ITb>IL, that is, when VTb>VIL.

[0042] 10 shows a detailed configuration example of the current detection circuit 190. The current detection circuit 190 includes a mirror transistor 191, a P-type MOS transistor 192, an error amplifier 193, a current mirror circuit 194, a sample-and-hold circuit 195, a logic circuit 196, switches SWE1 and SWE2, resistors RE1 and RE2, and a capacitor CE.

[0043] The mirror transistor 191 is a transistor of the same conductivity type as the switching element 111, and in this case is a P-type MOS transistor. The source of the mirror transistor 191 is connected to the node of the power supply voltage VIN, and the drain is connected to the negative input terminal of the error amplifier 193. A drive signal DRP is input to the gate of the mirror transistor 191. The positive input terminal of the error amplifier 193 is connected to the node NSW, and the output terminal is connected to the gate of the P-type MOS transistor 192. The source of the P-type MOS transistor 192 is connected to the negative input terminal of the error amplifier 193.

[0044] The error amplifier 193 controls the gate voltage of the P-type MOS transistor 192 so that the drain voltage VEA of the mirror transistor 191 matches the voltage SW of the node NSW. This causes the mirror transistor 191 to mirror the current flowing through the switching element 111. The mirrored current IMA is a mirror of the inductor current IL when the switching element 111 is on, and is output from the drain of the P-type MOS transistor 192.

[0045] The current mirror circuit 194 mirrors the current IMA and outputs it as a current IMB. The resistor RE1 is provided between the output node of the current mirror circuit 194 and the ground node, and converts the current IMB into a voltage VDET1. The switch SWE1 is connected between the output node of the current mirror circuit 194 and the input node of the sample and hold circuit 195. The capacitor CE is connected between the input node of the sample and hold circuit 195 and the ground node. The resistor RE2 and the switch SWE2 are connected in series between the input node of the sample and hold circuit 195 and the ground node.

[0046] The logic circuit 196 outputs signals SH1 and SH2 corresponding to edges of the pulse signal QOUT. The signal SH1 corresponds to the edge of the pulse signal QOUT when the switching element 111 changes from on to off. The signal SH2 corresponds to the edge of the pulse signal QOUT when the switching element 111 changes from off to on. The switch SWE1 is controlled to be turned on or off by the signal SH1. The sample-and-hold circuit 195 samples and holds the voltage VDET2 of the input node based on the signal SH2, and outputs the result as the voltage VIL. The switch SWE2 is controlled to be turned on or off based on the reverse current detection signal ZCMPO. The logic circuit 196 may be provided in the pulse signal output circuit 380 or the pre-driver 170.

[0047] FIG. 11 shows an example of signal waveforms that explain the operation of the current detection circuit 190 when the load current Id is relatively large and no backflow is detected.

[0048] When the switching element 111 is on, a current IMA flows according to the inductor current IL. The current IMA is converted to a voltage VDET1 by the resistor RE1. When the switching element 111 changes from on to off, the signal SH1 goes high, turning on the switch SWE1. The signal SH1 immediately goes low, turning off the switch SWE1. At this time, the peak voltage of the voltage VDET1 is held in the capacitor CE as the voltage VDET2. The reverse current detection signal ZCMPO is high, and the switch SWE2 is off. Therefore, the voltage VDET2 is maintained until the next time the signal SH1 goes high. When the switching element 111 changes from off to on, the signal SH2 goes high, causing the sample-and-hold circuit 195 to sample the voltage VDET2 and output it as the voltage VIL. The signal SH2 immediately goes low, causing the sample-and-hold circuit 195 to hold the voltage VIL.

[0049] FIG. 12 shows an example of signal waveforms illustrating the operation of the current detection circuit 190 when the load current Id is relatively small and a reverse current is detected.

[0050] The process is the same as in FIG. 11 up to the point where voltage VDET1 is held as voltage VDET2 in capacitor CE by signal SH1. After that, when reverse current is detected and reverse current detection signal ZCMPO goes low, switch SWE2 turns on. The charge held in capacitor CE is discharged to ground via resistor RE2 and switch SWE2, causing voltage VDET2 to gradually decrease. When switching element 111 goes from off to on, signal SH2 goes high, causing sample-and-hold circuit 195 to sample voltage VDET2 and output it as voltage VIL. Signal SH2 immediately goes low, causing sample-and-hold circuit 195 to hold voltage VIL.

[0051] The smaller the load current Id, the longer the on-time interval of the switching element 111, that is, the longer the period during which the reverse current detection signal ZCMPO is at a low level. For this reason, the smaller the load current Id, the lower the voltage VDET2, and the voltage VDET2 is sample-held by the sample-hold circuit 195. Thereby, in the case of a low load, a voltage VIL that more accurately reflects the current value of the load current Id can be obtained, that is, more accurate current detection becomes possible.

[0052] FIG. 13 is a first detailed configuration example of the voltage mode control circuit 310 and the hysteresis control circuit 330.

[0053] The voltage mode control circuit 310 includes an error amplifier 161, a first comparator 162, a slope voltage generation circuit 168, and an off timer 140.

[0054] The error amplifier 161 amplifies the error between the first feedback voltage FBA and the first reference voltage VR1, and outputs the result as an error voltage COMP. FIG. 13 shows an example in which the first feedback voltage FBA is input to the negative input terminal of the error amplifier 161 and the first reference voltage VR1 is input to the positive input terminal. In this case, the error amplifier 161 decreases the error voltage COMP when FBA>VR1, and increases the error voltage COMP when FBA<VR1. The error amplifier 161 is an integrating circuit that integrates the difference between the first feedback voltage FBA and the first reference voltage VR1, and includes, for example, an operational amplifier and an integrating capacitor. The first reference voltage VR1 is input to the positive input terminal of the operational amplifier, the first feedback voltage FBA is input to the negative input terminal of the operational amplifier, and the output terminal of the operational amplifier and the negative input terminal are feedback-connected by the integrating capacitor.

[0055] The first feedback voltage FBA output by the first voltage divider circuit 131 is controlled to be close to the first reference voltage VR1 by the virtual short of the operational amplifier, and fluctuations in the output voltage VOUT are not directly reflected therein. However, by providing the second voltage divider circuit 132 as shown in FIG. 3, fluctuations in the output voltage VOUT are directly reflected in the second feedback voltage FBB. This allows fluctuations in the output voltage VOUT to be properly transmitted to the hysteresis control circuit 330.

[0056] The slope voltage generation circuit 168 generates a slope voltage RAMP that increases over time when the pulse signal QOUT is at a high level, and resets the slope voltage RAMP when the pulse signal QOUT is at a low level. The slope voltage is also called a triangular wave. Resetting the slope voltage RAMP means initializing it to the initial voltage of the slope voltage RAMP, i.e., the voltage at which the slope starts.

[0057] The first comparator 162 compares the error voltage COMP with the slope voltage RAMP and outputs the result as a first reset signal RST1. Fig. 13 shows an example in which the error voltage COMP is input to the negative input terminal of the first comparator 162 and the slope voltage RAMP is input to the positive input terminal.

[0058] The off timer 140 starts when the pulse signal QOUT changes from high level to low level, that is, when the switching element 111 changes from on to off. When the off timer 140 measures the lapse of the off time, it changes the first set signal SET1 from low level to high level. As a result, the pulse signal QOUT changes from low level to high level, as described below, and in response, the off timer 140 resets the timer and changes the first set signal SET1 from high level to low level. The off time measured by the off timer 140 is a period for setting the length of time the switching element 111 is off. The length of the off time may be fixed, or may be variably controlled according to the inductor current IL, as described below with reference to FIG. 15.

[0059] The hysteresis control circuit 330 includes a second comparator 332 and an on-timer 340 .

[0060] The second comparator 332 compares the second feedback voltage FBB with the second reference voltage VR2 and outputs the result as a second set signal SET2. Fig. 13 shows an example in which the second feedback voltage FBB is input to the negative input terminal of the second comparator 332 and the second reference voltage VR2 is input to the positive input terminal.

[0061] The on-timer 340 starts the timer when the pulse signal QOUT changes from low level to high level, that is, when the switching element 111 changes from off to on. When the on-timer 340 measures the passage of the on-time, it changes the second reset signal RST2 from low level to high level. As a result, as will be described later, the pulse signal QOUT changes from high level to low level, and in response, the on-timer 340 resets the timer and changes the second reset signal RST2 from high level to low level. The on-time measured by the on-timer 340 is a period for setting the length of time that the switching element 111 is on.

[0062] 14 shows a first detailed configuration example of the pulse signal output circuit 380. The pulse signal output circuit 380 includes a selector 385 and an RS latch circuit 163.

[0063] The selector 385 selects either a first set signal SET1 and a first reset signal RST1, or a second set signal SET2 and a second reset signal RST2, as the set signal SETIN and the reset signal RSTIN of the RS latch circuit 163 based on the mode signal SMODE. Specifically, the selector 385 includes a first selector 381 and a second selector 382. In the first mode, the first selector 381 selects the first set signal SET1 as the set signal SETIN, and the second selector 382 selects the first reset signal RST1 as the reset signal RSTIN. In the second mode, the first selector 381 selects the second set signal SET2 as the set signal SETIN, and the second selector 382 selects the second reset signal RST2 as the reset signal RSTIN.

[0064] The RS latch circuit 163 outputs a pulse signal QOUT based on the set signal SETIN and reset signal RSTIN selected by the selector 385 .

[0065] FIG. 15 shows a detailed configuration example of the off timer 140 when the length of the off time is variable.

[0066] Off timer 140 includes current source 141, variable current source 142, capacitor 143, switch 144, and comparator 145. If the length of the off time is fixed, variable current source 142 may be omitted.

[0067] When the pulse signal QOUT is at a high level, that is, when the switching element 111 is on, the switch 144 is on. At this time, both ends of the capacitor 143 are shorted to ground, so the voltage DET1 becomes 0 V. Since VIN-VOUT>0 V in the step-down DC-DC converter, the comparator 145 outputs a first set signal SET1 at a low level.

[0068] When the pulse signal QOUT is at a low level, that is, when the switching element 111 is off, the switch 144 is off. Let the capacitance value of the capacitor 143 be Coff. Denote the output current IB1 of the current source 141 as VIN / Roff. The output current IB2 of the variable current source 142 is 0 A when VIL≧VBS, and is g2×(VBS - VIL) when VIL<VBS. VBS is a bias voltage supplied from a voltage generation circuit (not shown). g2 is the voltage-current conversion coefficient in the variable current source 142. At this time, the voltage DET1 is charged by the current (IB1 - IB2) and rises. When DET1>VIN - VOUT, the comparator 145 changes the first set signal SET1 from a low level to a high level. As a result, the pulse signal QOUT changes from a low level to a high level.

[0069] The time when the pulse signal QOUT is at a low level is the off time. Denoting the off time as Toff, then Toff = Coff×(VIN - VOUT) / (IB1 - IB2). When the load current Id is large, the inductor current IL becomes large and the voltage VIL becomes high. When VIL≧VBS, IB2 = 0 A, and at this time Toff=(1 - VOUT / VIN)×Roff×Coff. The length of the off time Toff is constant regardless of the inductor current IL. In the sense that only the on time is controlled, it corresponds to PWM control. When the load current Id is small, the inductor current IL becomes small and the voltage VIL becomes low. When VIL<VBS, IB2 = g2×(VBS - VIL). As the inductor current IL becomes smaller, the voltage VIL drops and the current IB2 increases, so the length of the off time Toff becomes longer. In the sense that the off time is controlled according to the inductor current IL, it corresponds to PFM control.

[0070] Figure 16 shows a detailed configuration example of the on-timer 340. The on-timer 340 includes a current source 341, a capacitor 343, a switch 344, a comparator 345, and an inverter 349.

[0071] The inverter 349 inverts the logic level of the pulse signal QOUT and outputs the result as the signal XQOUT. The switch 344 is controlled to be turned on or off based on the signal XQOUT.

[0072] When the pulse signal QOUT is at a low level, that is, when the switching element 111 is off, the switch 344 is off. At this time, both ends of the capacitor 343 are shorted to ground, so the voltage DET2 becomes 0 V. Since VOUT > 0 V, the comparator 345 outputs a second reset signal RST2 at a low level.

[0073] When the pulse signal QOUT is at a high level, that is, when the switching element 111 is on, the switch 344 is off. The capacitance value of the capacitor 343 is Con. The output current IB3 of the current source 341 is expressed as VIN / Ron. At this time, the voltage DET2 is charged by the current IB3 and rises. When DET2 > VOUT, the comparator 345 changes the second reset signal RST2 from a low level to a high level. This changes the pulse signal QOUT from a high level to a low level. The time during which the pulse signal QOUT is at a high level is the on time. If the on time is Ton, then Ton = Con × VOUT / IB3.

[0074] Figure 17 shows example waveforms illustrating continuous operation in the first mode, i.e., voltage mode control. Here, it is assumed that the load current Id does not fluctuate. Continuous operation is the operation when the load current Id is relatively large and no reverse flow of the inductor current IL occurs. Since no reverse flow occurs, the reverse current detection signal ZCMPO is at a high level.

[0075] Period PA is the period during which the switching element 111 is on and the N-type MOS transistor 112 is off. During period PA, the voltage SW of node NSW becomes the power supply voltage VIN, the inductor current IL increases, and the output voltage VOUT rises. Period PB is the period during which the switching element 111 is off and the N-type MOS transistor 112 is on. During period PB, the voltage SW of node NSW becomes 0V, the inductor current IL decreases, and the output voltage VOUT drops. In continuous operation, one cycle of switching consists of period PA and period PB. The variations in the output voltage VOUT and the inductor current IL due to switching are what is called so-called ripple.

[0076] In continuous operation, the off-time Toff corresponds to period PB. When the off-time Toff ends, the off-timer 140 changes the first set signal SET1 from the low level to the high level. In response to this, the RS latch circuit 163 changes the pulse signal QOUT from the low level to the high level. In response to this, the off-timer 140 changes the first set signal SET1 from the high level to the low level, and the slope voltage generation circuit 168 starts generating the slope voltage RAMP. When the slope voltage RAMP reaches the error voltage COMP, the first comparator 162 changes the first reset signal RST1 from the low level to the high level. In response to this, the RS latch circuit 163 changes the pulse signal QOUT from the high level to the low level. In response to this, the slope voltage generation circuit 168 resets the slope voltage RAMP, and the off-timer 140 starts measuring the off-time Toff. In response to the slope voltage RAMP being reset and becoming RAMP < COMP, the first comparator 162 changes the first reset signal RST1 from the high level to the low level. The off-timer 140 changes the first set signal SET1 from the low level to the high level when the off-time Toff has elapsed. Subsequently, the same operation is repeated.

[0077] Figure 18 shows example waveforms that explain discontinuous operation in the first mode, i.e., voltage mode control. Here, it is assumed that the load current Id does not fluctuate. Discontinuous operation occurs when the load current Id is relatively small and a reverse flow of the inductor current IL occurs. Below, we will mainly explain the differences from Figure 17.

[0078] The period PC is a period during which the switching element 111 is off and the N-type MOS transistor 112 is off. During the period PC, the node NSW is in a high impedance state and the inductor current IL is 0 A. In discontinuous operation, the periods PA, PB, and PC make up one switching cycle.

[0079] In discontinuous operation, the off-time Toff corresponds to periods PB and PC. During period PB, when the inductor current IL decreases and reaches 0 A, the reverse current detection signal ZCMPO changes from high to low. In response, the pre-driver 170 changes the N-type MOS transistor 112 from on to off. This initiates period PC, and the N-type MOS transistor 112 is off, preventing the inductor current IL from flowing backward. When the off-time Toff ends, the off-timer 140 changes the first set signal SET1 from low to high. This initiates period PA, and operation is similar to the normal operation shown in FIG. 17 until period PB ends.

[0080] Figure 19 shows example waveforms illustrating the second mode, i.e., hysteresis control. Here, it is assumed that the load current Id does not fluctuate. Hysteresis control is selected when the load current Id is relatively small, so that the inductor current IL flows backward.

[0081] When the voltage DET2 reaches the output voltage VOUT, the on-timer 340 determines that the on-time Ton has ended and changes the second reset signal RST2 from low to high. In response, the RS latch circuit 163 changes the pulse signal QOUT from high to low. In response, the on-timer 340 resets the voltage DET2 and changes the second reset signal RST2 from high to low. When the switching element 111 turns off, the output voltage VOUT decreases, causing the second feedback voltage FBB to decrease. When the second feedback voltage FBB reaches the second reference voltage VR2, the second comparator 332 changes the second set signal SET2 from low to high. In response, the RS latch circuit 163 changes the pulse signal QOUT from low to high. In response, the on-timer 340 begins measuring the on-time Ton. When the switching element 111 turns on, the output voltage VOUT increases, causing the second feedback voltage FBB to increase. This causes the second comparator 332 to change the second set signal SET2 from high to low. The same operation is repeated thereafter. The operation of the backflow detection circuit 180 is the same as that shown in FIG.

[0082] 20 and 21 show examples of the operating waveforms of the switching regulator 200 when the load current Id fluctuates. Here, an example is shown in which the voltage mode control circuit 310 is set to low power in the fourth mode as shown in Fig. 5. Although the waveforms are divided into Fig. 20 and Fig. 21, it is assumed that time flows continuously from Fig. 20 to Fig. 21.

[0083] When the load current Id decreases and the inductor current IL decreases, the voltage VIL decreases. The mode determination circuit 150 changes the mode signal SMODE[1:0] from 00b, indicating the first mode, to 01b, indicating the third mode, at the timing when the reverse current detection signal ZCMPO first changes from high to low after the voltage VIL becomes smaller than the first threshold voltage VTa. The mode determination circuit 150 changes the mode signal SMODE[1:0] from 01b, indicating the third mode, to 11b, indicating the fourth mode, at the timing when the reverse current detection signal ZCMPO first changes from high to low after the voltage VIL becomes smaller than the second threshold voltage VTb.

[0084] As the load current Id increases and the inductor current IL increases, the voltage VIL rises. The mode determination circuit 150 changes the mode signal SMODE[1:0] from 11b, indicating the fourth mode, to 01b, indicating the third mode, at the timing when the pulse signal QOUT first changes from high to low after the voltage VIL becomes equal to or greater than the second threshold voltage VTb. The mode determination circuit 150 changes the mode signal SMODE[1:0] from 01b, indicating the third mode, to 00b, indicating the first mode, at the timing when the pulse signal QOUT first changes from high to low after the voltage VIL becomes equal to or greater than the first threshold voltage VTa.

[0085] When the load current Id is decreasing, the mode is switched on the condition that the inductor current IL is actually small and a reverse current is detected, that is, when the reverse current detection signal ZCMPO changes from high to low. On the other hand, when the load current Id is increasing, the inductor current IL does not actually need to be small, that is, there is no need for a reverse current to be detected, so the mode can be switched when the pulse signal QOUT changes from high to low.

[0086] In the first mode, the switching regulator 200 operates using voltage-mode control as shown in FIG. 17 or 18. In the third and fourth modes, the switching regulator 200 operates using hysteresis control as shown in FIG. 19. During the period TLOW in the fourth mode, the voltage-mode control circuit 310 is set to low power. Specifically, the bias currents of some or all of the error amplifier 161, first comparator 162, slope voltage generation circuit 168, and off-timer 140 are stopped. FIGS. 20 and 21 show an example in which all of these are stopped. The error amplifier 161 stops generating the error voltage COMP, the slope voltage generation circuit 168 stops generating the slope voltage, the first comparator 162 does not perform comparison operations, and the off-timer 140 stops the current source 141 and variable current source 142, preventing the voltage DET1 from changing. In the third mode, the voltage-mode control circuit 310 operates normally. For example, when transitioning from the fourth mode to the first mode, the presence of the third mode in between provides time for the voltage-mode control circuit 310 to return to normal operation from the low power setting.

[0087] 22 shows a second detailed configuration example of the voltage mode control circuit 310 and the hysteresis control circuit 330. In this configuration example, the off timer 140 is included in the control circuit 120 as a common element of the voltage mode control circuit 310 and the hysteresis control circuit 330.

[0088] The voltage mode control circuit 310 includes an error amplifier 161, a first comparator 162, and a slope voltage generating circuit 168. The operation of each circuit is the same as in FIG.

[0089] The hysteresis control circuit 330 includes a second comparator 332. The second comparator 332 compares the second feedback voltage FBB with the second reference voltage VR2 and outputs the result as a second reset signal RST2. Figure 22 shows an example in which the second feedback voltage FBB is input to the positive input terminal of the second comparator 332 and the second reference voltage VR2 is input to the negative input terminal.

[0090] The off timer 140 starts when the pulse signal QOUT changes from high to low, that is, when the switching element 111 changes from on to off. When the off timer 140 measures the lapse of the off time, it changes the set signal SETIN from low to high. As a result, as will be described later, the pulse signal QOUT changes from low to high, and in response, the off timer 140 resets the timer and changes the set signal SETIN from high to low. The length of the off time may be fixed, or may be variably controlled in accordance with the inductor current IL, as described with reference to FIG. 15.

[0091] 23 shows a second detailed configuration example of the pulse signal output circuit 380. The pulse signal output circuit 380 includes a selector 385 and an RS latch circuit 163.

[0092] The RS latch circuit 163 receives a set signal SETIN from the off timer 140. The selector 385 selects the first reset signal RST1 or the second reset signal RST2 as the reset signal RSTIN of the RS latch circuit 163 based on the mode signal SMODE. Specifically, the selector 385 includes a second selector 382. The second selector 382 selects the first reset signal RST1 as the reset signal RSTIN in the first mode, and selects the second reset signal RST2 as the reset signal RSTIN in the second mode.

[0093] 24 and 25 show example operating waveforms of the switching regulator 200 to which the second detailed configuration example is applied. Here, an example is shown in which the voltage mode control circuit 310 is set to low power in the fourth mode as in FIG. 5. Although the waveforms are divided into FIGS. 24 and 25, it is assumed that time flows continuously from FIG. 24 to FIG. 25. Below, differences from FIGS. 20 and 21 will be mainly explained.

[0094] When the second feedback voltage FBB rises and reaches the second reference voltage VR2, the second comparator 332 changes the second reset signal RST2 from low to high. When the pulse signal QOUT changes from high to low, the switching element 111 turns on, the output voltage VOUT drops, and the second feedback voltage FBB drops. As a result, the second comparator 332 changes the second reset signal RST2 from high to low.

[0095] Because the off timer 140 is shared by both voltage mode control and hysteresis control, normal operation is performed without being set to low power even in the fourth mode. In the fourth mode, bias currents of the error amplifier 161, the first comparator 162, and part or all of the slope voltage generation circuit 168 are stopped.

[0096] In this embodiment, the control circuit 120 includes a voltage-mode control circuit 310 that performs voltage-mode control, a hysteresis control circuit 330 that performs hysteresis control, a pulse signal output circuit 380, and a pre-driver 170. The pulse signal output circuit 380 outputs a pulse signal QOUT based on the output signal of the voltage-mode control circuit 310 in the first mode, and outputs a pulse signal QOUT based on the output signal of the hysteresis control circuit 330 in the second mode. The pre-driver 170 controls the switching of the switching element 111 based on the pulse signal QOUT. At least some circuits of the voltage-mode control circuit 310 are stopped or set to a low power setting that is a low power consumption state during at least a portion of the second mode.

[0097] For example, the voltage mode control circuit 310 is in the low power setting for part of the second mode period in the examples of FIGS. 5 and 7, and for the entire second mode period in the example of FIG.

[0098] According to this embodiment, hysteresis control is selected during low load conditions, and at least some circuits of the voltage mode control circuit 310 that are not used are set to low power consumption, thereby reducing the power consumption of the switching regulator 200 during low load conditions. Under low load conditions, the power consumption of the switching regulator 200 reduces power efficiency, but reducing power consumption can improve power efficiency.

[0099] As described with reference to FIG. 5 and other figures, the second mode may include a third mode in which the low-power setting is not performed and a fourth mode in which the low-power setting is performed. The mode determination circuit 150 may compare the inductor current IL with a first threshold ITa and a second threshold ITb that is smaller than the first threshold ITa. The mode determination circuit 150 may determine the first mode when the inductor current IL is equal to or greater than the first threshold ITa, the third mode when the inductor current IL is smaller than the first threshold ITa and equal to or greater than the second threshold ITb, and the fourth mode when the inductor current IL is smaller than the second threshold ITb. At least some of the circuits of the voltage-mode control circuit 310 may not be set to the low-power setting when the mode determination circuit 150 determines the third mode, but may be set to the low-power setting when the mode determination circuit 150 determines the fourth mode.

[0100] According to this embodiment, when the load current Id increases and transitions from the fourth mode to the first mode, the voltage-mode control circuit 310 does not switch to the low-power setting in the third mode during that time. Hysteresis control is performed in the third mode, and the voltage-mode control circuit 310 is not used. As a result, when the voltage-mode control circuit 310 transitions from the low-power setting of the fourth mode to the normal operation of the first mode, time is provided until the operating point is determined in the third mode, and the transition to the first mode is possible after returning to an operating point at which proper operation is possible.

[0101] 6, the mode determination circuit 150 may compare the inductor current IL with a first threshold ITa. The mode determination circuit 150 may determine the first mode when the inductor current IL is equal to or greater than the first threshold ITa, and may determine the second mode when the inductor current IL is less than the first threshold ITa. At least some of the circuits in the voltage-mode control circuit 310 may be set to a low power setting when the mode determination circuit 150 determines the second mode.

[0102] According to this embodiment, the voltage mode control circuit 310 can be set to low power in the second mode in which hysteresis control is performed, and the power consumption of the switching regulator 200 during low load operation can be reduced.

[0103] In this embodiment, the voltage-mode control circuit 310 may include an error amplifier 161, a slope voltage generation circuit 168, and a first comparator 162. The error amplifier 161 may receive a first feedback voltage FBA corresponding to the output voltage VOUT, amplify the error between the first feedback voltage FBA and a first reference voltage VR1, and output an error voltage COMP. The slope voltage generation circuit 168 may generate a slope voltage RAMP. The first comparator 162 may compare the error voltage COMP with the slope voltage RAMP. The hysteresis control circuit 330 may include a second comparator 332. The second comparator 332 may receive a second feedback voltage FBB corresponding to the output voltage VOUT, and compare the second feedback voltage FBB with a second reference voltage VR2. The pulse signal output circuit 380 may output the pulse signal QOUT based on the output signal of the first comparator 162 in the first mode, and may output the pulse signal QOUT based on the output signal of the second comparator 332 in the second mode.

[0104] According to this embodiment, in the first mode, the output voltage VOUT can be controlled to a given constant voltage by voltage mode control based on the first feedback voltage FBA corresponding to the output voltage VOUT, and in the second mode, the output voltage VOUT can be controlled to a given constant voltage by hysteresis control based on the second feedback voltage FBB corresponding to the output voltage VOUT.

[0105] As described with reference to FIGS. 13 and 14 , the voltage-mode control circuit 310 may also include an off-timer 140 that sets the length of the off-time during which the switching element 111 is off. The hysteresis control circuit 330 may also include an on-timer 340 that sets the length of the on-time during which the switching element 111 is on. The pulse signal output circuit 380 may also include an RS latch circuit 163 that outputs a pulse signal QOUT and a selector 385 that selects the set signal SETIN and the reset signal RSTIN of the RS latch circuit 163. In the first mode, the selector 385 may output the output signal of the off-timer 140 as the set signal SETIN and the output signal of the first comparator 162 as the reset signal RSTIN. In the second mode, the selector 385 may output the output signal of the second comparator 332 as the set signal SETIN and the output signal of the on-timer 340 as the reset signal RSTIN.

[0106] In this way, the switching of the switching element 111 can be controlled based on the result of the voltage mode control in the first mode, and the switching of the switching element 111 can be controlled based on the result of the hysteresis control in the second mode.

[0107] 22 and 23, the control circuit 120 may also include an off timer 140 that sets the length of the off time during which the switching element 111 is off. The pulse signal output circuit 380 may also include an RS latch circuit 163 that outputs a pulse signal QOUT and a selector 385 that selects a reset signal RSTIN of the RS latch circuit 163. The output signal of the off timer 140 may be input to the RS latch circuit 163 as the set signal SETIN. The selector 385 may output the output signal of the first comparator 162 as the reset signal RSTIN in the first mode, and may output the output signal of the second comparator 332 as the reset signal RSTIN in the second mode.

[0108] Even with this configuration, the switching of the switching element 111 can be controlled based on the result of the voltage mode control in the first mode, and the switching of the switching element 111 can be controlled based on the result of the hysteresis control in the second mode.

[0109] As described with reference to FIG. 7, at least some of the circuits in the hysteresis control circuit 330 may be stopped or set to a low power consumption state in the first mode.

[0110] According to this embodiment, in the first mode in which voltage mode control is performed, the power consumption of the switching regulator 200 can be reduced.

[0111] In this embodiment, the circuit device 100 may also include a backflow detection circuit 180 that detects a backflow of the inductor current IL. When the mode determination circuit 150 determines that the inductor current IL is smaller than a first threshold value ITa, the mode determination circuit 150 may switch from the first mode to the second mode at the timing when the backflow is detected by the backflow detection circuit 180.

[0112] In this embodiment, when the mode determination circuit 150 determines that the inductor current IL is equal to or greater than the first threshold, the mode determination circuit 150 may switch from the second mode to the first mode at the timing when the switching element 111 changes from on to off.

[0113] According to this embodiment, when the load current Id is decreasing, the mode can be switched on the condition that the inductor current IL is actually small and a reverse flow is detected. On the other hand, when the load current Id is increasing, the inductor current IL does not actually need to be small, i.e., a reverse flow does not need to be detected, so the mode can be switched when the pulse signal QOUT changes from high level to low level.

[0114] Furthermore, in this embodiment, the mode determination circuit 150 may receive a current detection voltage VIL from the current detection circuit 190. The current detection circuit 190 may convert the inductor current IL into a current detection voltage VIL corresponding to the inductor current IL. The mode determination circuit 150 may compare the inductor current IL with the first threshold voltage VTa by comparing the current detection voltage VIL with a first threshold voltage VTa corresponding to the first threshold voltage ITa of the inductor current IL, and determine whether the mode is the first mode or the second mode based on the comparison result.

[0115] According to this embodiment, the mode determination circuit 150 can compare the inductor current IL with the first threshold value ITa by comparing the current detection voltage VIL with the first threshold voltage VTa corresponding to the first threshold value ITa of the inductor current IL.

[0116] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different, broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also within the scope of the present disclosure. Furthermore, the configurations and operations of the mode determination circuit, voltage-mode control circuit, hysteresis control circuit, pulse signal output circuit, pre-driver, first voltage divider circuit, second voltage divider circuit, control circuit, circuit device, load, and switching regulator are not limited to those described in the present embodiment and may be modified in various ways. [Explanation of symbols]

[0117] 10...inductor, 20...capacitor, 30...load, 100...circuit device, 111...switching element, 112...N-type MOS transistor, 120...control circuit, 131...first voltage divider circuit, 132...second voltage divider circuit, 140...off timer, 141...current source, 142...variable current source, 143...capacitor, 144...switch, 145...comparator, 150...mode determination circuit, 151...comparator, 152...comparator , 155... comparison circuit, 161... error amplifier, 162... first comparator, 163... RS latch circuit, 168... slope voltage generation circuit, 170... pre-driver, 180... reverse current detection circuit, 190... current detection circuit, 191... mirror transistor, 192... P-type MOS transistor, 193... error amplifier, 194... current mirror circuit, 195... sample and hold circuit, 196... logic circuit, 200... switching regulator modulator, 310...voltage mode control circuit, 330...hysteresis control circuit, 332...second comparator, 340...on timer, 341...current source, 343...capacitor, 344...switch, 345...comparator, 349...inverter, 380...pulse signal output circuit, 381...first selector, 382...second selector, 385...selector, COMP...error voltage, FBA...first feedback voltage, FBB...second feedback voltage, IL...inductor current, ITa...first threshold, ITb...second threshold, Id...load current, QOUT...pulse signal, RAMP...slope voltage, RSTIN...reset signal, SETIN...set signal, SMODE...mode signal, VIL...current detection voltage, VIN...power supply voltage, VOUT...output voltage, VR1...first reference voltage, VR2...second reference voltage, VTa...first threshold voltage, VTb...second threshold voltage, ZCMPO...reverse current detection signal

Claims

1. A circuit device used in a switching regulator that outputs an output voltage by regulating a power supply voltage using an inductor and a switching element that drives the inductor, a control circuit that performs voltage mode control or hysteresis control to control the output voltage to a given constant voltage, and controls the switching of the switching element based on a result of the voltage mode control or the hysteresis control; a mode determination circuit that determines, based on an inductor current flowing through the inductor, whether the mode is a first mode in which the voltage mode control is performed or a second mode in which the hysteresis control is performed; Including, The control circuit When the mode determination circuit determines that the first mode is selected, the switching element is controlled based on a result of the voltage mode control. When the mode determination circuit determines that the second mode is selected, the circuit device controls the switching of the switching element based on the result of the hysteresis control.

2. 2. The circuit device according to claim 1, The mode determination circuit comparing the inductor current with a first threshold; determining that the inductor current is equal to or greater than the first threshold value as the first mode; A circuit device characterized in that it determines that the second mode is in operation when the inductor current is smaller than the first threshold value.

3. 2. The circuit device according to claim 1, The control circuit a voltage mode control circuit that performs the voltage mode control; a hysteresis control circuit that performs the hysteresis control; a pulse signal output circuit that outputs a pulse signal based on an output signal of the voltage mode control circuit in the first mode, and outputs the pulse signal based on an output signal of the hysteresis control circuit in the second mode; a pre-driver that controls the switching of the switching element based on the pulse signal; Including, At least a part of the circuit of the voltage mode control circuit is A circuit device characterized in that, during at least a part of the period of the second mode, the circuit device is in a low power setting that is a stopped or low power consumption state.

4. 4. The circuit device according to claim 3, the second mode includes a third mode in which the low power setting is not performed and a fourth mode in which the low power setting is performed; The mode determination circuit comparing the inductor current with a first threshold and a second threshold that is less than the first threshold; determining that the inductor current is equal to or greater than the first threshold value as the first mode; When the inductor current is smaller than the first threshold value and equal to or larger than the second threshold value, the third mode is determined; When the inductor current is smaller than the second threshold, the fourth mode is determined; The at least some circuits of the voltage mode control circuit include: A circuit device characterized in that when the mode determination circuit determines that the third mode is selected, the low power setting is not performed, and when the mode determination circuit determines that the fourth mode is selected, the low power setting is performed.

5. 4. The circuit device according to claim 3, The mode determination circuit comparing the inductor current with a first threshold; determining that the inductor current is equal to or greater than the first threshold value as the first mode; determining the second mode when the inductor current is smaller than the first threshold; The at least some circuits of the voltage mode control circuit include: When the mode determination circuit determines that the second mode is selected, the circuit device is set to the low power setting.

6. 4. The circuit device according to claim 3, The voltage mode control circuit an error amplifier that receives a first feedback voltage corresponding to the output voltage, amplifies an error between the first feedback voltage and a first reference voltage, and outputs an error voltage; a slope voltage generating circuit that generates a slope voltage; a first comparator that compares the error voltage with the slope voltage; Including, The hysteresis control circuit includes: a second comparator that receives a second feedback voltage corresponding to the output voltage and compares the second feedback voltage with a second reference voltage; The pulse signal output circuit In the first mode, the pulse signal is output based on an output signal of the first comparator; In the second mode, the circuit device outputs the pulse signal based on the output signal of the second comparator.

7. 7. The circuit device according to claim 6, The voltage mode control circuit an off timer that sets the length of an off time during which the switching element is off; The hysteresis control circuit includes: an on-timer that sets the length of an on-time period during which the switching element is on; The pulse signal output circuit an RS latch circuit that outputs the pulse signal; a selector for selecting a set signal and a reset signal of the RS latch circuit; Including, The selector In the first mode, an output signal of the off timer is output as the set signal, and an output signal of the first comparator is output as the reset signal; In the second mode, the circuit device outputs an output signal of the second comparator as the set signal, and outputs an output signal of the on-timer as the reset signal.

8. 7. The circuit device according to claim 6, The control circuit an off timer that sets the length of an off time during which the switching element is off; The pulse signal output circuit an RS latch circuit that receives the output signal of the off timer as a set signal and outputs the pulse signal; a selector for selecting a reset signal for the RS latch circuit; Including, The selector In the first mode, an output signal of the first comparator is output as the reset signal; In the second mode, the circuit device outputs an output signal of the second comparator as the reset signal.

9. 2. The circuit device according to claim 1, The control circuit a voltage mode control circuit that performs the voltage mode control; a hysteresis control circuit that performs the hysteresis control; a pulse signal output circuit that outputs a pulse signal based on an output signal of the voltage mode control circuit in the first mode, and outputs the pulse signal based on an output signal of the hysteresis control circuit in the second mode; a pre-driver that controls the switching of the switching element based on the pulse signal; Including, At least a part of the hysteresis control circuit is In the first mode, the circuit device is set to a low power setting that is a stopped or low power consumption state.

10. 2. The circuit device according to claim 1, a reverse current detection circuit for detecting a reverse current of the inductor; The mode determination circuit When the inductor current is determined to be smaller than a first threshold, the circuit device switches from the first mode to the second mode at the timing when the reverse current is detected by the reverse current detection circuit.

11. 2. The circuit device according to claim 1, The mode determination circuit A circuit device characterized in that, when it is determined that the inductor current is equal to or greater than a first threshold, the circuit device switches from the second mode to the first mode at the timing when the switching element changes from on to off.

12. 2. The circuit device according to claim 1, The mode determination circuit a current detection circuit that converts the inductor current into a current detection voltage corresponding to the inductor current receives the current detection voltage; A circuit device characterized in that the inductor current is compared with the first threshold by comparing the current detection voltage with a first threshold voltage corresponding to a first threshold of the inductor current, and the first mode or the second mode is determined based on the comparison result.

13. A circuit arrangement according to any one of claims 1 to 12; the switching element; the inductor; A switching regulator comprising:

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