Semiconductor device

Abstract

To provide a semiconductor device in which a NOR type flash memory and a NAND type flash memory are fused.SOLUTION: A stack type flash memory 20 provided in a memory system 10 includes a NOR flash memory 100, a NAND flash memory 200, a controller 300, and an external bus 30 capable of inputting / outputting data in synchronization with a serial clock signal. When a read command conforming to the specifications of the NOR flash memory is received from the external bus 30, the controller 300 serially outputs a part of the specific data read from the NOR flash memory 100 in response to the read command, and then serially outputs the rest of the specific data read from the NAND flash memory 200. In this manner, data is read out from the extended NAND flash memory as if the NOR flash memory were accessed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a NOR flash memory and a NAND flash memory. [Background technology]

[0002] NOR flash memory allows random access and high-speed readout, while NAND flash memory allows for highly integrated memory cell arrays and can program large amounts of data quickly, but takes longer to read than NOR flash memory.

[0003] In recent years, an increasing number of flash memories have been equipped with serial interfaces that increase the speed of input and output data using fewer terminals. Serial interfaces include the standard serial peripheral interface (SPI), which requires an 8-bit instruction code and a 16-bit address.

[0004] NOR flash memory is equipped with a function for continuously inputting and outputting data, such as burst mode or page mode. For example, in a read operation, as shown in FIG. 1(A), when the chip select signal / CS is set to low active and a read command and address are input from an external terminal in synchronization with a serial clock signal, the column address is automatically incremented, and the read data is sequentially output from the external terminal in synchronization with the serial clock signal. In a program operation, when a program command and address are input from the external terminal, the column address is automatically incremented, and the program data input from the external terminal in synchronization with the serial clock signal is programmed into the memory cells. Such continuous read or write is terminated by setting the chip select signal / CS to high level (Patent Document 1).

[0005] Meanwhile, NAND flash memory equipped with a serial interface has also been put to practical use to ensure compatibility with NOR serial flash. When performing continuous reads with NAND flash memory, when a continuous read command and address are input from an external terminal, data read from a page of the memory cell array is stored in a page buffer / sense circuit, the column address is automatically incremented, and the data stored in the page buffer / sense circuit is output from an external terminal in synchronization with a serial clock signal.

[0006] Figure 1(B) shows a timing chart of a continuous read operation of a NAND flash memory. The chip select signal CS is set to active low, and an 8-bit page data read command (e.g., "13h") and a 16-bit page address PA (a row address for selecting a block and page) are input. After a latency corresponding to the time it takes for the data of the selected page of the memory cell array to be transferred to the page buffer / sensing circuit, an 8-bit read command for continuous read and a 16-bit address (this is an empty dummy address) are input. The NAND flash memory enters continuous read mode upon input of this series of commands and addresses. The input page address PA is automatically incremented, and the sequentially read page data is serially output to the outside in synchronization with the serial clock. While the chip select signal CS is at a low level, i.e., while in continuous read mode, the flash memory does not require the input of a page data read command or page address PA (see Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6232109 Summary of the Invention [Problem to be solved by the invention]

[0008] As the amount of code, operating systems (OS), and data used in systems increases, the capacity of flash memory also tends to increase. NOR flash memory allows high-speed reads through random access, and has excellent durability and retention characteristics, making it suitable for storing boot code and firmware for system startup. However, with NOR flash memory, some capacities above a certain capacity cannot be commercialized due to silicon die size constraints, and even if commercialized, the higher the capacity, the more expensive it becomes.

[0009] In view of the above-mentioned conventional problems, an object of the present invention is to provide a semiconductor device that combines a NOR flash memory and a NAND flash memory. [Means for solving the problem]

[0010] The semiconductor device according to the present invention includes a NOR flash memory and a NAND flash memory, and includes input / output means capable of inputting and outputting data via an input / output bus in synchronization with a serial clock signal, and control means for controlling the operation of the NOR flash memory and the NAND flash memory, wherein the control means causes the input / output means to serially output a portion of specific data read from the NOR flash memory in response to a read command received from the input / output means, and then causes the input / output means to serially output the remainder of the specific data read from the NAND flash memory.

[0011] In one embodiment, the semiconductor device further includes a register that stores information regarding the operating specifications of the input / output means, the register being externally accessible. In one embodiment, the control means outputs a portion of the specific data during an initial latency period during continuous reads from the NAND flash memory. In one embodiment, the control means writes a portion of the specific data to the NOR flash memory in response to a write command received from the input / output means, and writes the remainder of the specific data to the NAND flash memory. In one embodiment, the size of the portion of the specific data depends on the bus width of the input / output means and the frequency of the serial clock signal. In one embodiment, the portion of the specific data is equal to or smaller than the data size that can be serially output during the initial latency period during continuous reads from the NAND flash memory.

[0012] The memory system of the present invention includes the above-mentioned semiconductor device and a host device connected to the semiconductor device via the I / O bus, and the host device obtains information regarding the operating specifications stored in the register and determines the allocation of specific data to be programmed into the NOR flash memory and the NAND flash memory based on the information regarding the operating specifications.

[0013] In the method of operating a semiconductor device including a NOR flash memory and a NAND flash memory according to the present invention, a control means for controlling the operation of the NOR flash memory and the NAND flash memory serially outputs a part of specific data read from the NOR flash memory in response to a read command received from the input / output means, and then serially outputs the rest of the specific data read from the NAND flash memory. [Effects of the Invention]

[0014] According to the present invention, after a part of the specific data read from the NOR flash memory is serially output from the input / output means, the remaining specific data read from the NAND flash memory is serially output from the input / output means, thereby enabling the storage of large-sized specific data and increasing the speed of reading such specific data.Furthermore, by storing specific data corresponding to the latency period of the NAND flash memory in the NOR flash memory and reading the specific data from the NOR flash memory during the initial latency period, the drawback of the latency of the NAND flash memory can be eliminated. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1A is a timing chart illustrating the continuous read operation of a NOR flash memory, and FIG. 1B is a timing chart illustrating the continuous read operation of a NAND flash memory. [Figure 2] 1 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention; [Figure 3] 1 is a diagram showing an internal configuration of a stacked flash memory according to an embodiment of the present invention; [Figure 4] 10 is a flowchart illustrating a program operation of specific data in a memory system according to an embodiment of the present invention. [Figure 5] 10 is a table illustrating the data size that can be serially output during the latency period when reading from a NAND flash memory, in relation to the frequency of the serial clock signal and the IO bus width. [Figure 6] 10 is a flowchart showing a read operation of specific data in a memory system according to an embodiment of the present invention. [Figure 7] 10A to 10C are diagrams illustrating examples of reading specific data of various data sizes in this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] The semiconductor device according to the present invention includes at least one NOR flash memory and at least one NAND flash memory as heterogeneous flash memories, achieving a large memory capacity and high-speed access equivalent to that of a NOR flash memory. For example, the semiconductor device according to the present invention includes a chip on which a NOR flash memory is formed and a chip on which a NAND flash memory is formed housed in a package. For example, a NAND flash memory chip and a NOR flash memory chip are stacked on a circuit board, or the respective chips are mounted side by side on the circuit board. [Example]

[0017] Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a diagram showing the configuration of a storage system according to an embodiment of the present invention. A memory system 10 of this embodiment includes a stacked flash memory 20 and a host device 40. The stacked flash memory 20 includes a NOR flash memory 100, a NAND flash memory 200, a controller 300, and an internal bus 400. The NOR flash memory 100, the NAND flash memory 200, and the controller 300 are interconnected via the internal bus 400, and data can be transferred between them via the internal bus 400.

[0018] The stacked flash memory 20 is connected to a host device 40 via an external bus 30, a chip select signal line CS, a serial clock signal line CLK, and the like. The external bus 30 serially transfers data between the host device 40 and the stacked flash memory 20 using, for example, an SPI communication method. The SPI IO bus width and serial clock signal frequency are not particularly limited. For example, the IO bus width can be 1-bit single SPI, 2-bit dual SPI, 4-bit quad SPI, or 8-bit octal SPI. The serial clock signal frequency can be, for example, 104 MHz, 133 MHz, 166 MHz, or another frequency. If the external bus 30 is SPI-compatible, the internal bus 400 can be an SPI with the same operating specifications as the external bus 30, or an SPI with a faster transfer speed than the external bus 30. In other words, the internal bus 400 has a transfer speed at least equal to or greater than that of the external bus 30. For example, if the external bus 30 is a quad SPI, the internal bus 400 can be a quad SPI or an octal SPI. The external bus 30 may also be compatible with ONFI.

[0019] The stacked flash memory 20 may include, but is not limited to, a chip (die) on which the NOR flash memory 100 is formed, a chip (or die) on which the NAND flash memory 200 is formed, and a chip (or die) on which the controller 300 is formed. Alternatively, the stacked flash memory 20 may include a chip (or die) on which the NOR flash memory 100 and the controller 300 are formed, and a chip (or die) on which the NAND flash memory 200 is formed. The stacked chips are electrically connected to each other; for example, a conductive pad formed on the surface of one chip is connected directly or indirectly via a conductive member to a conductive pad formed on the surface of the other chip. Alternatively, the electrical connection between the stacked chips may be realized by a conductive member penetrating between the stacked chips. However, the chips are not limited to being stacked, and may also be arranged side by side on a circuit board.

[0020] The stacked flash memory 20 includes a package (e.g., resin-sealed or ceramic-sealed) that houses stacked chips. The package includes external terminals (e.g., BGA or LGA formed on the back surface of the package) that provide an electrical interface between the internal chips and the external host device 40.

[0021] The host device 40 is not particularly limited, but is configured by, for example, a computer device including a microprocessor, a CPU, a ROM / RAM, etc. The host device 40 outputs commands (instructions), addresses, and data to the stacked flash memory 20 via the external bus 30, and outputs a serial clock signal and a chip select signal via a CLK signal line and a CS signal line, causing the stacked flash memory 20 to perform a desired operation.

[0022] In one embodiment, the commands used by the host device 40 comply with the specifications of the NOR flash memory 100, i.e., the host device 40 uses the stacked flash memory 20 as if it were a NOR flash memory, issuing program commands, read commands, and erase commands for the NOR flash memory, and using the NAND flash memory 200 as an extended storage area behind the scenes.

[0023] In another embodiment, the host device 40 uses a command for operating the NOR flash memory 100 and a command for operating the NAND flash memory 200, respectively, to operate the NOR flash memory 100 and the NAND flash memory 200 separately. For example, as shown in Figures 1(A) and 1(B), the host device 40 may activate either the NOR flash memory 100 or the NAND flash memory 200 using a CS signal, and program a large amount of data into the NAND flash memory 200 and a small amount of data that requires high-speed readout into the NOR flash memory 100.

[0024] 3 is a diagram showing an example of the internal configuration of the stacked flash memory 20 of this embodiment. The NOR flash memory 100 includes a NOR memory cell array 110 in which multiple memory cells are connected in parallel between bit lines and source lines, an X-DEC 120 that selects and drives word lines based on a row address, an SA / WA 130 that senses data read from the memory cells and writes data to the memory cells, a buffer 140 that holds one page of data during a read operation or a program operation, and a Y-DEC 150 that selects bit lines based on a column address.

[0025] The NOR flash memory 100 is equipped with a function for continuously inputting and outputting data (continuous read and write), and can read and program data in bit units or page units. The unit of one page is not particularly limited and can be set arbitrarily. In one embodiment, the buffer 140 of the NOR flash memory 100 can store one page of data. During a programming operation, the buffer 140 holds data received via the input / output unit 340. The data held in the buffer 140 is selected based on a column address of the Y-DEC 150, and the selected data is transferred to the SA / WA (sense amplifier / write amplifier) ​​130. The SA / WA 130 programs selected memory cells of selected bits based on the transferred data. During a read operation, the buffer 140 holds one page of data read from the NOR memory array, and the held data is selected based on a column address of the Y-DEC 150, and the selected data is transferred to the input / output unit 340.

[0026] The NAND flash memory 200 includes a NAND memory cell array 210 in which a plurality of memory cells arranged in rows and columns are connected in series to form a NAND string, an X-DEC 220 that selects and drives blocks and word lines based on a row address, a page buffer / sense circuit 230 that holds data read from a selected page of the memory cell array 210 and data to be programmed into the selected page, a cache register 240 that transfers data (e.g., in half-page units) between the page buffer / sense circuit 230, and a Y-DEC 250 that selects bit lines based on a column address. Although not shown, the stacked flash memory 20 may also include a voltage generation circuit and an internal clock generation circuit that generate voltages required for data reading, programming, erasing, and the like.

[0027] The controller 300 includes a NOR control unit 310 that controls the operation of the NOR flash memory 100, a NAND control unit 320 that controls the operation of the NAND flash memory 200, a configuration register 330 that stores information related to the operating specifications of the external bus 30, and an input / output unit 340 that provides an interface between the external bus 30 and an internal bus 400. The input / output unit 340 is connected to a host device 40 via the external bus 30, and receives commands, addresses, data, etc. from the host device 40. The input / output unit 340 is also connected to the NOR flash memory 100 and the NAND flash memory 200 via the internal bus 400.

[0028] In SPI, data is serially output or input in synchronization with the rising edge and / or falling edge of a serial clock signal. During a program operation, data serially input from the external bus 30 is programmed into the NOR flash memory 100 and / or the NAND flash memory 200 via the input / output unit 340 and the internal bus 400. During a read operation, data read from the NOR flash memory 100 and / or the NAND flash memory 200 is serially output from the external bus 30 to the host device 40 via the internal bus 400 and the input / output unit 340.

[0029] The controller 300 controls the operations of the NOR flash memory 100 and the NAND flash memory 200 based on commands received from the host device 40 via the external bus 30, and also controls data transfer over the internal bus 400. The NOR control unit 310 mainly controls the operations of the NOR flash memory 100, and the NAND control unit 320 mainly controls the operations of the NAND flash memory 200. In one embodiment, the NOR control unit 310 controls operations such as reading, programming, and erasing of the NOR flash memory 100 based on commands received via the input / output unit 340, or controls the NAND flash memory 200 via the NAND control unit 320 based on specific commands received from the input / output unit 340.

[0030] For example, if the specific command is a command to control a program in the NAND flash memory 200, the NOR control unit 310 generates an internal command and an internal address for controlling the program in the NAND flash memory 200, and causes the NAND control unit 320 to control the NAND flash memory 200 based on the generated internal command and internal address. The NOR control unit 310 references, for example, the LUT and generates an internal address corresponding to the address received from the host device 40. In response to the received internal command, the NAND flash memory 200 programs the data received from the input / output unit 340 into a selected page of the NAND memory array 210.

[0031] Furthermore, if the specific command is a command for controlling reading from the NAND flash memory 200, the NOR control unit 310 generates an internal command and an internal address for controlling reading from the NAND flash memory 200, and causes the NAND control unit 320 to control the NAND flash memory 200 based on the generated internal command and internal address. In response to the received internal command, the NAND flash memory 200 transfers data read from the selected page of the NAND memory array 210 to the page buffer / sense circuit 230.

[0032] In one embodiment, when the stacked flash memory 20 receives a command conforming to the NOR flash memory from the host device 40, the NOR control unit 310 controls the NOR flash memory 100 and / or the NAND flash memory 200 in accordance with the command. For example, when the host device 40 programs specific data such as boot code or firmware into the stacked flash memory 20 or when reading such specific data, the host device 40 outputs specific commands, addresses, etc. to the stacked flash memory 10. In this way, the host device 40 can access the stacked flash memory 20 as if it were a NOR flash memory and read data stored in the expanded NAND flash memory from the stacked flash memory 20.

[0033] The configuration register 330 stores the IO bus width and the operating frequency of the serial clock signal as information relating to the operating specifications of the external bus 30 of the stacked flash memory 20. This operating information is read from the fuse memory during, for example, the power-up sequence of the stacked flash memory 20 and loaded into the configuration register 330. The host device 40 reads the operating specifications of the external bus 30 stored in the configuration register 330 and determines the allocation of specific data to be programmed into the NOR flash memory 100 and the NAND flash memory 200 based on the operating specifications.

[0034] Next, the stacked flash memory of this embodiment will be described in detail. When reading specific data with a fixed read size, such as boot data for starting the system or code used by the system, the data size to be read at one time is divided, and when a certain amount or more is to be read, the data is stored in the NAND flash memory 200.

[0035] To access data during reading in the same way as the NOR flash memory 100, the storage addresses of the NOR flash memory and the NAND flash memory are linked for data stored in the NAND flash memory 200. The linking method is not particularly limited, but may be, for example, a lookup table or a write (flag) to each address.

[0036] When continuously reading from the NAND flash memory 200, an initial latency occurs, which corresponds to the time required to transfer data from the first page of the memory cell array to the page buffer / sense circuit, as shown in Figure 1(B). Therefore, data is read from the NOR flash memory during the time corresponding to the initial latency, and data is read from the NAND flash memory once the initial latency ends and reading becomes possible.

[0037] The initial latency period during continuous reads from NAND flash memory is constant, and the data size that can be read from NOR flash memory during the latency period, i.e., the data size that can be serially output from stacked flash memory, varies depending on the operating frequency of the serial clock signal and the width of the SPI IO bus. The higher the operating frequency and IO bus width, the larger the data size that can be read from NOR flash memory during the latency period (the data size that can be serially output). Conversely, the smaller the operating frequency and bus width, the smaller the data size that can be read from NOR flash memory during the latency period.

[0038] Therefore, when programming specific data, the host device 40 determines the allocation of the specific data to be programmed to each of the NOR flash memory 100 and the NAND flash memory 200 based on the operating frequency of the serial clock signal and the IO bus width.

[0039] 4 shows the operation flow when programming specific data into the stacked flash memory in the memory system of this embodiment. The host device 40 accesses the stacked flash memory 20 and acquires the SPI operating specifications stored in the configuration register 330 (S100). The operating specifications include at least the SPI IO bus width and the maximum operating frequency of the serial clock signal. For example, the operating specifications are read from the fuse memory when the stacked flash memory 20 is powered up and stored in the configuration register 330.

[0040] Next, the host device 40 determines the data size S that can be serially output during the initial latency period when continuously reading the NAND flash memory 200 based on the acquired operating specifications. LATENCY Here, the period of the initial latency is known (S110).

[0041] 5 shows an example of the data size that can be read from the NOR flash memory 100 before the NAND flash memory 200 becomes ready, assuming that the initial latency of the NAND flash memory is 60 μS, as a function of the IO bus width and the operating frequency. For example, when the operating frequency is 52 MHz and the bus width is ×1, the data size that can be read during the latency period is 3121 bits (318 bytes). When the bus width is ×4, the data size that can be read is four times that amount, or 12484 bits (1561 bytes). Also, when the operating frequency is 104 MHz, when the bus width is ×1, 6244 bits (781 bytes) can be read, and when the bus width is ×4, the data size that can be read is 24976 bits (3122 bytes).

[0042] Next, the host device 40 determines the data size S of the specific data to be programmed into the stacked flash memory 20. SPECIFIC and the data size S that can be read during the latency period. LATENCY (S120) The specific data is, for example, boot data or code data for starting the system, and the size of this data is known.

[0043] Size of specific data S SPECIFIC The data size S that can be read during the latency period LATENCY If it is smaller than (S130), the host device 40 programs (S140) all of the specific data into the NOR flash memory 100. In this case, the specific data is read without being affected by the latency of the NAND flash memory.

[0044] On the other hand, the size of the specific data S SPECIFIC The data size S that can be read during the latency period LATENCY If the maximum data size S allocated to the NOR flash memory 100 is larger than the maximum data size S allocated to the NOR flash memory 100 (S130), the host device 40 determines the allocation for programming the specific data based on the operation specifications of the SPI (S150). MAX is S MAX = Frequency x Latency time x Bit width (Number of IOs). For example, if the clock frequency is 52MHz, the latency is 60μS, and the number of IOs is 1 bit, then S MAX = (60 × 1000) / 19.23 ≒ 3121 bits. The specific data to be programmed into the NOR flash memory 100 has a maximum data size S MAX or smaller in size.

[0045] The host device 50 writes a data size S corresponding to the latency as part of the specific data to the NOR flash memory 100 in accordance with the allocation of the specific data. LATENCY Then, the remaining specific data is programmed into the NAND flash memory 200 (S160).

[0046] 5, when the clock frequency is 104 MHz and IO×4, the 2048 bytes of specific data is smaller than the data size (shaded area) that can be read during the latency period, and therefore data reading from the NOR flash memory is completed before the latency of the NAND flash memory. As a result, all of the specific data is programmed into the NOR flash memory 100.

[0047] In operating specifications other than those described above, the 2048 bytes of specific data is larger than the data size that can be read during the latency period, so data reading continues even after the initial latency of the NAND flash memory ends. For this reason, the specific data is allocated and programmed to the NOR flash memory 100 and the NAND flash memory 200. For example, in the above table, for a 52 MHz, IO×4 setting, the host device 40 programs up to 1561 bytes into the NOR flash memory and programs 1562 bytes to 2048 bytes into the NAND flash memory.

[0048] When writing specific data, data input is synchronized with the clock. Since the number of clocks determines the size of the data to be written, the host device 40 counts the number of serial clocks and writes the specific data to each NOR flash memory and NAND flash memory according to the data allocation determined above. In the case of DDR, where data input is synchronized with the rising and falling edges of the clock, data is input twice per cycle.

[0049] More specifically, when the NOR control unit 310 receives a program command, an address, and specific data from the host device 40, it programs a portion of the specific data into the NOR memory array 110 based on the received address. Next, the NAND control unit 320 programs the remainder of the specific data into the NAND memory array 210. At this time, the NOR control unit 310 associates the address of the specific data programmed into the NOR memory array 110 with the address of the specific data programmed into the NAND memory array 210. The linking method is not particularly limited, and may be based on a lookup table that defines the relationship between the address space of the NOR memory array 110 and the address space of the NAND memory array 210, or may define the relationship between the specific data programmed in the NOR memory array 110 and the specific data programmed in the NAND memory array by setting a flag related to the specific data programmed in the NOR memory array 110 and / or the address destination of the NAND memory array, or by setting a flag related to the specific data programmed in the NAND memory array 210 and / or the address source of the NOR memory array 110. In this way, the specific data is written to the NOR memory array 110 and the NAND memory array 210, respectively, in accordance with the data allocation set based on the SPI operation specifications.

[0050] In the above write operation, the data size S corresponding to the latency is LATENCYIn the above example, the specific data is written to the NOR flash memory, and then the remaining specific data is written to the NAND flash memory, but this writing is not necessarily limited to this. For example, the host device 40 may write part of the specific data to the NOR flash memory 100 and, in parallel, write the remaining specific data to the NAND flash memory 200, or the host device 40 may write all of the specific data to both the NOR flash memory 100 and the NAND flash memory 200. In the latter case, a backup of the specific data can be left in the NAND flash memory 200, and data that requires reliability, such as boot data, can be guaranteed.

[0051] 6 shows the operation flow when specific data is continuously read from the stacked flash memory in the memory system of this embodiment. The NOR control unit 310 receives a continuous read command and address as shown in FIG. 1(A) from the host device 40 (S200). This continuous read command is distinguished from a continuous read command for normal data, and the NOR control unit 310 recognizes that it is a continuous read of specific data.

[0052] Based on the received address, the NOR control unit 310 starts continuous reading of specific data from the NOR flash memory 100 (S210). The read data is output from the external bus 30 to the host device 40 in synchronization with the serial clock signal.

[0053] In parallel with the continuous reading of the NOR flash memory, the NOR control unit 310 starts continuous reading of specific data in the NAND flash memory via the NAND control unit 320 (S210). The NAND control unit 320 identifies the address of the NAND memory array 210 based on the address linking method described above (lookup table, flag, etc.), and starts reading the specific data from the NAND memory array 210 using the identified address.

[0054] In sequential reads of a NAND flash memory, an initial latency occurs between the time data is read from the selected page of the memory array to the page buffer / sense circuit, and during this initial latency, specific data stored in the NOR flash memory 100 is sequentially read.

[0055] As soon as the specific data is read from the NOR flash memory 100, the remaining specific data is successively read from the NAND flash memory 200 (S220). That is, the specific data pipelined and stored in the page buffer / sense circuit 230 and the cache register 240 is serially output from the external device 30 to the host device 40 in synchronization with the serial clock signal.

[0056] 7A and 7B are diagrams showing examples of reading specific data of various data sizes. LATENCT In this case, during the read latency period of the NAND flash memory, data of size S is read from the NOR flash memory 100. LATENCT The specific data is successively read out, and then the remaining specific data is successively read out from the NAND flash memory 200. FIG. 7C shows the specific data when the data size S LATENCT In this example, the specific data is continuously read only from the NOR flash memory 100 (the specific data is not stored in the NAND flash memory).

[0057] As described above, according to this embodiment, when specific data is stored in a stacked flash memory including a NOR flash memory and a NAND flash memory and the specific data is read from the stacked flash memory, the array read latency of the NAND flash memory is effectively offset, and high-speed readout can be achieved by overcoming the drawback of the initial latency of the NAND flash memory.

[0058] This embodiment also enables the system to omit commands, address input, and the initial detection of a read busy (tR) state of the NAND flash memory at startup.Furthermore, the address that can be specified can be anywhere in the user area, which increases the degree of freedom in address mapping.

[0059] In the above embodiment, an example of operation in which the NOR flash memory 100 and the NAND flash memory 200 are used together has been shown, but it is also possible to use the NOR flash memory 100 and the NAND flash memory 200 individually.

[0060] Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0061] 10: Memory system 20: Stacked flash memory 30: External bus 40: Host device 100: NOR flash memory 200: NAND flash memory 300: Controller 400: Internal bus

Claims

1. A semiconductor device including a NOR flash memory and a NAND flash memory, an input / output means capable of inputting and outputting data via an input / output bus in synchronization with a serial clock signal; a control means for controlling the operation of the NOR flash memory and the NAND flash memory, The control means causes a part of the specific data read from the NOR type flash memory to be serially output from the input / output means in response to a read command received from the input / output means, and then causes the remainder of the specific data read from the NAND type flash memory to be serially output from the input / output means.

2. 2. The semiconductor device according to claim 1, further comprising a register for storing information relating to operational specifications of said input / output means, said register being externally accessible.

3. 2. The semiconductor device according to claim 1, wherein said control means causes a part of the specific data to be output during an initial latency period during continuous reading of the NAND flash memory.

4. 2. The semiconductor device according to claim 1, wherein said control means writes a part of the specific data to a NOR flash memory and writes the rest of the specific data to a NAND flash memory in response to a write command received from said input / output means.

5. 2. The semiconductor device according to claim 1, wherein the part of the specific data has a size corresponding to a bus width of said input / output means and a frequency of a serial clock signal.

6. 6. The semiconductor device according to claim 5, wherein the part of the specific data has a size equal to or smaller than the data size that can be serially output during an initial latency period during continuous reads from the NAND flash memory.

7. 3. A memory system including the semiconductor device according to claim 2 and a host device connected to the semiconductor device via the input / output bus, The host device acquires information about the operating specifications stored in the register, and determines the allocation of specific data to be programmed into the NOR flash memory and the NAND flash memory based on the information about the operating specifications.

8. A method for operating a semiconductor device including a NOR flash memory and a NAND flash memory, comprising: A control means for controlling the operation of the NOR flash memory and the NAND flash memory serially outputs a part of the specific data read from the NOR flash memory in response to a read command received from the input / output means, and then serially outputs the rest of the specific data read from the NAND flash memory.

9. 9. The operating method according to claim 8, wherein the control means outputs a part of the specific data during an initial latency period when the NAND flash memory is continuously read.

10. 9. The operating method according to claim 8, wherein said control means writes a part of the specific data to the NOR flash memory and writes the rest of the specific data to the NAND flash memory in response to a write command received from the input / output means.

11. 9. The operating method according to claim 8, wherein the part of the specific data has a size corresponding to the bus width of said input / output means and the frequency of the serial clock signal.

12. 12. The operating method according to claim 11, wherein the part of the specific data has a size equal to or smaller than a data size that can be serially output during an initial latency period when continuously reading the NAND pattern flash memory.

Images