Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of reducing surface noise, and to provide a method of manufacturing the semiconductor device.SOLUTION: The semiconductor device includes a semiconductor layer having a first conductivity type, a trench having a bottom surface in the semiconductor layer, and an insulating layer covering a surface of the trench, wherein the semiconductor layer includes a first impurity region in contact with a side surface of the trench and having a second conductivity type different from the first conductivity type, a first contact region in contact with the side surface of the trench and located in a surface portion of the semiconductor layer, and having the first conductivity type, and a second impurity region in contact with the first impurity region and located in the surface portion of the semiconductor layer, and having the first conductivity type. And a second impurity region located on the first impurity region and below the second contact region, being in contact with both the first impurity region and the second contact region, and having the second conductivity type, wherein the first impurity region and the first contact region are separated from each other.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a Zener diode formed on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-312428

[0004] [overview] An object according to one aspect of the present disclosure is to provide a semiconductor device capable of reducing surface noise and a method for manufacturing the semiconductor device.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer located on a substrate and having a first conductivity type, a groove having the semiconductor layer as a bottom surface, and an insulating layer covering a surface of the groove, wherein the semiconductor layer has: a first impurity region spaced apart from the substrate, in contact with a side surface of the groove, and having a second conductivity type different from the first conductivity type; a first contact region located on the first impurity region in a surface portion of the semiconductor layer, in contact with the side surface of the groove, and having the first conductivity type; a second contact region located on the first impurity region in a surface portion of the semiconductor layer, spaced apart from the first contact region, and having the second conductivity type; and a second impurity region located on the first impurity region below the second contact region, in contact with both the first impurity region and the second contact region, and having the second conductivity type, wherein the first impurity region and the first contact region are spaced apart from each other. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 2]FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9A] FIG. 9A is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9B] FIG. 9B is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9C] FIG. 9C is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9D] FIG. 9D is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9E] FIG. 9E is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a reference example.

[0007] [Detailed explanation] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, identical elements or elements having the same functions will be designated by the same reference numerals, and duplicate explanations will be omitted. In this specification, the term "same" and similar words are not limited to "completely identical." Furthermore, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of the components shown may differ from the actual dimensions.

[0008] FIG. 1 is a schematic plan view showing a semiconductor device according to this embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. Wiring is omitted in FIGS. 1 and 2. As shown in FIG. 1, the semiconductor device 100 includes a rectangular parallelepiped silicon chip 101 (semiconductor chip). The chip 101 is one of multiple devices formed on a silicon wafer having a diameter of, for example, 300 mm (approximately 12 inches). The semiconductor device 100 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 100 may be referred to as an SSI (Small Scale IC), MSI (Middle Scale IC), LSI (Large Scale IC), VLSI (Very Large Scale IC), or ULSI (Ultra Large Scale IC) based on the number of circuit elements integrated therein. The semiconductor device 100 is used, for example, as an LSI equipped with a gate clamper.

[0009] The chip 101 has a pair of main surfaces, a first main surface 3 and a second main surface 4, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D connecting the first main surface 3 and the second main surface 4. Hereinafter, the extension direction of the first side surface 5A and the second side surface 5B in a plan view is referred to as a first direction X, the extension direction of the third side surface 5C and the fourth side surface 5D in a plan view is referred to as a second direction Y, and the normal direction of the first main surface 3 and the second main surface 4 is referred to as a third direction Z. The second direction Y is a direction intersecting the first direction X in a plan view, and the third direction Z corresponds to the thickness direction of the chip 101. In this specification, "plan view" corresponds to viewing from the third direction Z.

[0010] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the third direction Z, but are not limited to this. In this embodiment, the first main surface 3 is the top surface, and the second main surface 4 is the bottom surface. Therefore, a configuration located near the first main surface 3 in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 100, and a configuration located near the second main surface 4 in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 100.

[0011] The semiconductor device 100 has a plurality of device regions 10 defined on the first main surface 3 and spaced apart from one another. The number and arrangement of the device regions 10 in the semiconductor device 100 are determined as appropriate. Each of the device regions 10 includes a functional device formed using regions inside and outside the chip 101. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may also include a circuit network that combines at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device.

[0012] The semiconductor switching device may include at least one of a bipolar transistor, a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0013] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used as the MISFET. The MOSFET may be an enhancement type or a depletion type. The MOSFET may have a planar structure or a vertical structure. The element region ER can also be a power transistor. MISFETs with cathode-anode voltages of high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V) are also known. In addition, optical devices such as light-emitting elements and light-receiving elements can be used as the element region ER formed in the device region 10.

[0014] In this embodiment, the semiconductor material constituting the chip 101 is silicon (Si), but is not limited to this. Compound semiconductors can also be used as the semiconductor material constituting the chip 101. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. III-V compound semiconductors are, for example, Ga-containing semiconductors such as GaAs and GaN. IV-IV compound semiconductors are, for example, Si-containing semiconductors such as SiC and SiGe.

[0015] As shown in FIGS. 1 and 2, a device region 10 constituting a semiconductor device includes a semiconductor substrate 1 and a semiconductor layer 2 located on the semiconductor substrate 1. The semiconductor substrate 1 functions as a base substrate for forming the semiconductor layer 2 and is, for example, a single-crystal Si substrate or a single-crystal SiC substrate. The semiconductor layer 2 is an epitaxial layer formed on the semiconductor substrate 1. A main surface 2a (surface portion) of the semiconductor layer 2 corresponds to, but is not limited to, the first main surface 3 of the chip 101. The device region 10 is defined by a buried region BL, an element region ER located on the buried region BL, and a trench structure 50 surrounding the element region ER in a planar view. The buried region BL is formed in at least the semiconductor layer 2. The buried region BL may be formed in the semiconductor substrate 1 in addition to the semiconductor layer 2.

[0016] In this example, each semiconductor region constituting the semiconductor device has a first conductivity type of n-type and a second conductivity type different from the first conductivity type of p-type, but these conductivity types are interchangeable. That is, the first conductivity type may be p-type and the second conductivity type may be n-type. An exemplary p-type impurity (trivalent element) is boron (B). An exemplary n-type impurity (pentavalent element) is phosphorus (P) or arsenic (As). The material of the semiconductor substrate 1 in this example is Si. In this embodiment, the semiconductor substrate 1 exhibits the second conductivity type, the semiconductor layer 2 exhibits the first conductivity type, and the buried region BL exhibits the first conductivity type.

[0017] The impurity concentration of the semiconductor substrate 1 is 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 500 μm or less. The impurity concentration of the buried region BL may be 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The impurity concentration of the semiconductor layer 2 may be 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3The thickness of the semiconductor layer 2 may be 5 μm or more and 50 μm or less.

[0018] The structure of the element region is not particularly limited. The following describes the structure of the element region ER according to this embodiment. In this embodiment, the element region ER includes a first impurity region 11 located in the semiconductor layer 2 and spaced apart from the semiconductor substrate 1, a trench structure 12 formed in the semiconductor layer 2 and adjacent to the first impurity region 11, a first contact region 13 located in the semiconductor layer 2 and above the first impurity region 11, a second contact region 14 located in the semiconductor layer 2, and a second impurity region 15 located in the semiconductor layer 2 and in contact with both the first impurity region 11 and the second contact region 14. Additionally, the element region ER may include a wiring L1 connected to the first contact region 13 and a wiring L2 connected to the second contact region 14. In the element region ER, a Zener diode 6 is provided by a portion of the semiconductor layer 2, the first impurity region 11, and the trench structure 12. In addition, the first contact region 13, the second contact region 14, and the second impurity region 15 provide a current path for the Zener diode 6 in the element region ER.

[0019] The first impurity region 11 is a well region having the second conductivity type and is provided in the center of the element region ER. The first impurity region 11 is spaced apart from the major surface 2a of the semiconductor layer 2. In other words, the first impurity region 11 is located below the major surface 2a of the semiconductor layer 2 in the third direction Z. In addition, the first impurity region 11 is spaced apart from the buried region BL. That is, the first impurity region 11 is located above the buried region BL in the third direction Z. The first impurity region 11 is in contact with the trench structure 12 and is sandwiched between the trench structures 12 in the first direction X and the second direction Y. The first impurity region 11 is located above the bottom of the trench structure 12 in the third direction Z, but is not limited to this. The first impurity region 11 is formed, for example, by introducing (adding, doping) an impurity having the second conductivity type into a part of the semiconductor layer 2. The impurity concentration of the first impurity region 11 is, for example, 1.0×10 15cm -3 Over 1.0 x 10 19 cm -3 The dimension of the first impurity region 11 along the third direction Z is, for example, not less than 2 μm and not more than 4 μm.

[0020] The trench structure 12 is a portion (shallow trench) adjacent to the first impurity region 11 in a plan view, and is spaced apart from the buried region BL. That is, the trench structure 12 is located above the buried region BL in the third direction Z. The trench structure 12 has a groove 21 having the semiconductor layer 2 as its bottom surface, an insulator 22 covering the surface of the groove 21, and a conductor 23 located within the groove 21 and spaced apart from the semiconductor layer 2.

[0021] The groove 21 is a depression (trench) provided in the semiconductor layer 2, extends in the third direction Z from the first main surface 3 toward the second main surface 4, and has a bottom surface in the semiconductor layer 2. The groove 21 has, for example, a ring shape surrounding the first impurity region 11, the first contact region 13, and the second contact region 14 in a plan view, but is not limited to this. The groove 21 may have, for example, a shape surrounding a portion of the first impurity region 11 in a plan view. A bottom surface 21a of the groove 21 (a portion of the surface of the groove 21) is located closer to the semiconductor substrate 1 than the first impurity region 11 in the third direction Z, but is spaced apart from the buried region BL. That is, the bottom surface 21a is located below the first impurity region 11. From the viewpoint of miniaturizing the Zener diode 6, the short side (width W1) of the groove 21 in a plan view is, for example, 0.5 μm or more and 2.4 μm or less. The dimension (depth D1) of the groove 21 along the third direction Z is, for example, 4 μm or more and 8 μm or less. Therefore, the ratio of the width W1 of the groove 21 to the depth D1 of the groove 21 is, for example, 0.062 or more and 0.6 or less. Note that the width W1 is constant, but is not limited to this. For example, the width W1 may become narrower downward in the third direction Z. Therefore, in this embodiment, the width W1 corresponds to the maximum value of the short side of the groove 21 in a plan view.

[0022] A side surface 21b of the trench 21 (another part of the surface of the trench 21) is defined by a third impurity region 16 located in the semiconductor layer 2 and having the first conductivity type. The third impurity region 16 is a region formed along the side surface 21b in the semiconductor layer 2 and adjacent to the first impurity region 11. In this embodiment, the third impurity region 16 is a region provided during the formation of the trench structure 12, as will be described later, and is therefore considered to be a part of the trench structure 12 and the side surface 21b of the trench 21. Therefore, the side surface 21b of the trench 21 in the trench structure 12 (actually, the third impurity region 16) is adjacent to the first impurity region 11. Therefore, a PN junction is formed between the first impurity region 11 and the third impurity region 16. Therefore, the third impurity region 16 can also function as a region functioning as one of the anode and cathode of the Zener diode 6. Similarly, the third impurity region 16 can also function as a region functioning as the other of the anode and cathode of the Zener diode 6. From the viewpoint of the performance of the Zener diode 6, the impurity concentration of the third impurity region 16 is set to, for example, 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The thickness of the third impurity region 16 along the direction perpendicular to the third direction Z is, for example, 30 nm or more and 300 nm or less. The impurity concentration of the third impurity region 16 is significantly higher than the impurity concentration of the semiconductor layer 2. Therefore, the third impurity region 16 is part of the conduction path in the Zener diode 6, and functions as a main part of the conduction path between the first impurity region 11 and the first contact region 13.

[0023] The insulator 22 is an insulating member for preventing contact between the semiconductor layer 2 and the conductor 23, and covers the bottom surface 21a and side surface 21b of the groove 21. The insulator 22 is formed of, for example, an oxide insulating film such as a silicon oxide film or an aluminum oxide film, a nitride insulating film such as a silicon nitride film, or an oxynitride insulating film such as a silicon oxynitride film. From the viewpoint of preventing a short circuit between the semiconductor layer 2 and the conductor 23, the thickness of the insulator 22 is, for example, not less than 3 nm and not more than 200 nm. The thickness of the portion of the insulator 22 that is in contact only with the bottom surface 21a and the thickness of the portion that is in contact only with the side surface 21b may be different from each other or may be the same as each other.

[0024] The conductor 23 is a conductive member located inside the groove 21 relative to the insulator 22. Applying a voltage to the conductor 23 can reduce the parasitic resistance R between the third impurity region 16 and the semiconductor layer 2. In this case, the conductor 23 may have the function of reducing the resistance of the conduction path through the Zener diode 6. However, the conductor 23 may be in a floating state. The bottom surface 23a and the side surface 23b of the conductor 23 are each covered by the insulator 22. The top surface 23c of the conductor 23 is exposed from the insulator 22. When a predetermined voltage is applied to the conductor 23, the top surface 23c may be connected to a wiring (not shown). The bottom surface 23a of the conductor 23 is located closer to the semiconductor substrate 1 than the first impurity region 11 in the third direction Z. That is, the bottom surface 23a of the conductor 23 is located lower than the first impurity region 11. The conductor 23 is, for example, a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), or tungsten (W), or polysilicon having a first or second conductivity type.

[0025] The first contact region 13 is a region that functions as one of the anode and cathode of the Zener diode 6, and is located on the first impurity region 11 and on the major surface 2a of the semiconductor layer 2. In addition, the first contact region 13 is in contact with the side surface 21b of the trench 21 (i.e., the third impurity region 16) and has the first conductivity type. In a plan view, the first contact region 13 is located between the trench 21 and the second contact region 14. On the other hand, the first contact region 13 is spaced apart from the first impurity region 11. In a plan view, the first contact region 13 is located inside the trench structure 12 and surrounds at least a portion of the second contact region 14. In this embodiment, the first contact region 13 and a portion of the third impurity region 16 that is located above the first impurity region 11 in the third direction Z have different structures, but this is not limited to this. A portion of the side surface 21b may be formed by the first contact region 13. The impurity concentration of the first contact region 13 is higher than the impurity concentration of the first impurity region 11 and the impurity concentration of the second impurity region 15, and is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0026] The second contact region 14 is a region that functions as the other of the anode and cathode of the Zener diode 6, and is located on the first impurity region 11 and on the main surface 2a of the semiconductor layer 2. The second contact region 14 is spaced apart from the first contact region 13 and has the second conductivity type. In addition, the second contact region 14 is spaced apart from the trench structure 12. The impurity concentration of the second contact region 14 is higher than the impurity concentration of the first impurity region 11 and the impurity concentration of the second impurity region 15, and is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0027] The second impurity region 15 is a region that connects the first impurity region 11 and the second contact region 14, and is located on the first impurity region 11 and below the second contact region 14. In addition, the second impurity region 15 is in contact with both the first impurity region 11 and the second contact region 14, and has the second conductivity type. The second contact region 14, the second impurity region 15, and the first impurity region 11 each have the second conductivity type. The second impurity region 15 is spaced apart from the first contact region 13 and the trench structure 12. The impurity concentration of the second impurity region 15 is, for example, 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The following is the result.

[0028] One of an anode voltage and a cathode voltage is applied to the first contact region 13 via wiring L1. The other of the anode voltage and the cathode voltage is applied to the second contact region 14 via wiring L2. At this time, a current flows from the second contact region 14 to the first contact region 13 via, for example, the first impurity region 11, the second impurity region 15, the semiconductor layer 2, the third impurity region 16, etc.

[0029] Next, the trench structure 50 will be described in detail. The trench structure 50 is an element isolation structure for electrically isolating the element region ER from other device regions 10, and is a deep trench isolation (DTI) provided in the semiconductor substrate 1. The trench structure 50 has a ring shape in a plan view and surrounds the element region ER. Therefore, the element region ER is surrounded by the trench structure 50 and the buried region BL. The trench structure 50 is spaced apart from the element region ER but is in contact with the buried region BL. The trench structure 50 has a groove 51 (second groove), an insulating layer 52 covering a portion of the surface of the groove 51, and a conductor 53 (second conductor) located in the groove 51 and spaced apart from the semiconductor layer 2.

[0030] The groove 51 is a depression (trench) penetrating the semiconductor layer 2, extending in the third direction Z from the first main surface 3 toward the second main surface 4, and having a bottom surface in the semiconductor substrate 1. The groove 51 has, for example, a ring shape in plan view that surrounds each component of the Zener diode 6 (e.g., the first impurity region 11, the trench structure 12, the first contact region 13, the second contact region 14, the second impurity region 15, etc.). A bottom surface 51a of the groove 51 (a part of the surface of the groove 51) is located below the buried region BL in the third direction Z and is spaced apart from the buried region BL. A short side (width W2) of the groove 51 in plan view is larger than the width W1 of the groove 21, and is, for example, 2.5 μm or more and 4.5 μm or less. The width W2 of the groove 51 is, for example, 104% or more and 900% or less of the width W1 of the groove 21. The dimension (depth D2) of the groove 51 along the third direction Z is larger than the dimension (depth D1) of the groove 21, and is, for example, 20 μm or more and 40 μm or less. The width W2 is constant, but is not limited to this. For example, the width W2 may be narrower downward in the third direction Z. Therefore, in this embodiment, the width W2 corresponds to the maximum value of the short side of the groove 51 in a plan view. The ratio of the width W2 of the groove 51 to the depth D2 of the groove 51 is, for example, 0.062 or more and 0.23 or less. In addition, the ratio of the width W1 of the groove 21 to the depth D1 of the groove 21 is 27% or more and 960% or less of the ratio of the width W2 of the groove 51 to the depth D2 of the groove 51. As will be described later, the groove 51 is formed simultaneously with the groove 21.

[0031] A side surface 51b of the trench 51 (another part of the surface of the trench 51) is defined by a fourth impurity region 17 located in the semiconductor substrate 1 and the semiconductor layer 2 and having the first conductivity type. The fourth impurity region 17 is a region formed along the side surface 51b in the semiconductor substrate 1 and the semiconductor layer 2. In this embodiment, the fourth impurity region 17 is a region provided during the formation of the trench structure 50 as described below, and is therefore considered to be a part of the trench structure 50 and the side surface 51b of the trench 51. As described below, the fourth impurity region 17 is formed simultaneously with the third impurity region 16. Therefore, the impurity concentration and thickness of the fourth impurity region 17 are approximately the same as those of the third impurity region 16, respectively.

[0032] The insulating layer 52 is a member for preventing contact between the semiconductor layer 2 and the conductor 53, and covers at least the side surface 51b of the groove 51. In this embodiment, the insulating layer 52 covers not only the side surface 51b of the groove 51 but also a portion of the bottom surface 51a of the groove 51. In other words, another portion of the bottom surface 51a of the groove 51 is exposed from the insulating layer 52. The insulating layer 52 is formed, for example, from the above-mentioned oxide insulating film, nitride insulating film, or oxynitride insulating film. From the viewpoint of preventing contact with the semiconductor layer 2, the thickness of the insulating layer 52 is, for example, not less than 3 nm and not more than 200 nm. As will be described later, the insulating layer 52 is formed simultaneously with the insulator 22.

[0033] The conductor 53 is a member located inside the insulating layer 52 in the trench 51 and in contact with the semiconductor substrate 1. The conductor 53 is a frame-shaped conductor surrounded by the insulating layer 52 in a plan view, and extends in the third direction Z from the first main surface 3 to the second main surface 4. The conductor 53 fills the trench 51 and contacts a portion of the semiconductor substrate 1 located below the buried region BL. This makes the potential of the conductor 53 the same as the potential of the semiconductor substrate 1. The conductor 53 is, for example, a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), or tungsten (W), or polysilicon having a first conductivity type or a second conductivity type. As will be described later, the conductor 53 is formed simultaneously with the conductor 23.

[0034] From the viewpoint of reducing leakage current, etc., an STI 60 (shallow trench isolation) is formed between the first contact region 13 and the second contact region 14. The STI 60 is a portion in which an insulator 62 is buried in a recess 61 provided in a portion of the semiconductor layer 2 located between the first contact region 13 and the second contact region 14. The STI 60 has, for example, a ring shape surrounding the second contact region 14 in a plan view, but is not limited to this. From the viewpoint of reducing leakage current between the first contact region 13 and the second contact region 14, etc., a bottom surface 60a of the STI 60 is located below the bottom surfaces of the first contact region 13 and the second contact region 14.

[0035] Furthermore, from the viewpoint of reducing leakage current, an STI 63 is formed between the first contact region 13 and the trench structure 50. The STI 63 is a portion in which an insulator 65 is buried in a recess 64 provided in a portion of the semiconductor layer 2 located between the first contact region 13 and the trench structure 50. The STI 63 has, for example, a ring shape surrounding the first contact region 13 in a plan view, but is not limited to this. The STI 63 is located outside the trench structure 12 in a plan view.

[0036] Next, an example of a method for manufacturing the semiconductor device 100 according to this embodiment will be described with reference to Figures 3 to 8. Each of Figures 3 to 8 is a schematic cross-sectional view for explaining an example of a method for manufacturing the semiconductor device 100 according to this embodiment.

[0037] First, as shown in FIGS. 3 and 4, a semiconductor layer 2 (first step) located on a semiconductor substrate 1 and having a first conductivity type is formed. In the first step, as shown in FIG. 3, a first epitaxial layer 102a is formed by epitaxially growing a semiconductor on the semiconductor substrate 1. Here, the first epitaxial layer 102a is formed while forming a buried region BL by controlling the amount of impurity added. Note that the introduction of impurities into the semiconductor substrate 1 and / or the first epitaxial layer 102a is performed by a known method, such as ion implantation. Next, an impurity having a second conductivity type is introduced into the first epitaxial layer 102a, and then a semiconductor is epitaxially grown on the first epitaxial layer 102a. As a result, a semiconductor layer 2 having a first epitaxial layer 102a and a second epitaxial layer 102b and including a first impurity region 11 is formed, as shown in FIG.

[0038] 5, a trench structure 12 located in the semiconductor layer 2 and a trench structure 50 penetrating the semiconductor layer 2 are simultaneously formed (second step). A part of the first impurity region 11 may be removed in accordance with the formation of the trench structure 12, or the first impurity region 11 may not be removed by the formation of the trench structure 12. The trench structure 50 is formed at a position spaced apart from the first impurity region 11.

[0039] The second step will be described in detail below with reference to Figures 9A to 9E, each of which is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure.

[0040] First, as shown in FIG. 9A, a trench 21 having a bottom surface in the semiconductor layer 2 and adjacent to the first impurity region 11, and a trench 51 penetrating the semiconductor layer 2 are simultaneously formed (Step 2A). In Step 2A, a hard mask M having openings O1 and O2 is first formed on the main surface 2a of the semiconductor layer 2. Next, the trenches 21 and 51 are formed by etching the portions of the semiconductor layer 2 exposed through the opening O1 and the opening O2. The hard mask M is made of a material having a low etching rate with respect to the etchant for the semiconductor layer 2, such as a silicon oxide film. The opening width W3 of the opening O1 is equal to the maximum value of the width W1 of the trench 21, and the opening width W4 of the opening O2 is equal to the maximum value of the width W2 of the trench 51. Note that the hard mask M has a different shape from the mask used in Step 2.

[0041] In step 2A, the trenches 21 and 51 are formed by anisotropic etching, such as a Bosch process using F radicals. This allows the width W1 of the trench 21 to be controlled to be equal to or less than the opening width W3, and the width W2 of the trench 51 to be controlled to be equal to or less than the opening width W4. The difference between the opening widths W3 and W4 is the main factor in differentiating the etching rates of the portions of the semiconductor layer 2 exposed through the opening O1 and the portions of the semiconductor layer 2 exposed through the opening O2. Specifically, by making the opening widths W3 and W4 different from each other, the etching rate of the portions of the semiconductor layer 2 exposed through the opening O1 is made higher than the etching rate of the portions of the semiconductor layer 2 exposed through the opening O2. This allows the depth D1 of the trench 21 to be shallower than the depth D2 of the trench 51, even though the trenches 21 and 51 are formed simultaneously. Therefore, in step 2A, the trench 21, whose bottom surface is the semiconductor layer 2, and the trench 51, whose bottom surface is the semiconductor substrate 1, can be formed.

[0042] Next, as shown in FIG. 9B , impurities having the first conductivity type are introduced into the side surface 21b of the trench 21 and the side surface 51b of the trench 51 (step 2B). This forms a third impurity region 16 along the side surface 21b and a fourth impurity region 17 along the side surface 51b. In step 2B, the impurities are introduced simultaneously into the side surfaces 21b and 51b by, for example, oblique ion implantation using a hard mask M. In step 2B, the impurities are not introduced into the bottom surface 21a of the trench 21 and the bottom surface 51a of the trench 51, but this is not a limitation.

[0043] Next, as shown in FIG. 9C , an insulator 122 filling the groove 21 and an insulating layer 152 covering the groove 51 are simultaneously formed (Step 2C). In Step 2C, the insulator 122 and the insulating layer 152 are simultaneously formed by a known method, such as chemical vapor deposition (CVD). In this embodiment, due to differences in the widths and depths of the grooves 21 and 51, the groove 21 is completely filled with the insulator 122, while the groove 51 is not completely filled with the insulating layer 152. For this reason, a portion 152a of the insulating layer 152 located on the bottom surface 51a of the groove 51 is thinner than the remaining portion. In particular, the thickness of the portion 152a is thinner than the depth dimension of the insulator 122 (i.e., the depth D1 of the groove 21). Note that in Step 2C, the groove 21 does not necessarily have to be completely filled with the insulator 122. Although not shown, a hard mask M may or may not be used in Step 2C. In the latter case, for example, before the 2C step, the hard mask M is removed. The removal of the hard mask M is performed by, for example, chemical mechanical polishing (CMP). Then, an insulator may also be deposited on the main surface 2a of the semiconductor layer 2.

[0044] Next, as shown in FIG. 9D , a portion of the insulator 122 is removed so as not to expose the bottom surface 21a of the groove 21, and a portion 152a of the insulating layer 152 is removed so as to expose the semiconductor substrate 1 in the groove 51 (step 2D). In step 2D, the insulator 122 and the insulating layer 152 are etched, for example, by anisotropic etching. In step 2D, the insulator 122 and the insulating layer 152 are etched to the extent that the portion 152a of the insulating layer 152 is removed. As described above, the thickness of the portion 152a of the insulating layer 152 is thinner than the depth dimension of the insulator 122. This forms the insulator 22 that covers the groove 21 and the insulating layer 52 that covers the side surface 51b of the groove 51. In step 2D, the insulator deposited on the main surface 2a may be partially or entirely etched. In step 2D, a portion of the insulator remains on the main surface 2a, but this is not a limitation. Each of the semiconductor substrate 1 and the semiconductor layer 2 can function as an etching stopper in the 2D step.

[0045] Next, as shown in FIG. 9E, the conductor 23 spaced from the semiconductor layer 2 is embedded in the groove 21, and the conductor 53 in contact with the semiconductor substrate 1 is embedded in the groove 51 (Step 2E). In Step 2E, first, a conductor (not shown) is formed to embed the grooves 21 and 51 using a known method such as sputtering or CVD. The conductor is formed not only in the grooves 21 and 51 but also on the main surface 2a of the semiconductor layer 2. Next, the portion of the conductor located on the main surface 2a of the semiconductor layer 2 is removed using a known method such as CMP. If an insulator, hard mask M, or the like remains on the main surface 2a of the semiconductor layer 2, the insulator may be removed simultaneously with the portion of the conductor located on the main surface 2a of the semiconductor layer 2. By performing Steps 2A to 2E described above, trench structures 12 and 50 are simultaneously formed, as shown in FIG. 9E.

[0046] 6 , an impurity region 115 is formed in the semiconductor layer 2 above the first impurity region 11 and in contact with the first impurity region 11 (third step). In the third step, a mask (not shown) is first formed on the semiconductor layer 2, and then an impurity having the second conductivity type is introduced into a portion of the semiconductor layer 2 exposed from the mask. The introduction of the impurity into the portion is performed by a known method such as ion implantation. The impurity region 115 formed in the third step is a region that will later become the second contact region 14 and the second impurity region 15.

[0047] Next, as shown in FIG. 7 , STIs 60 and 63 are formed (fourth step). In the fourth step, first, recesses 61 and 64 are formed in a part of the semiconductor layer 2. The recess 61 is, for example, inside the trench structure 12 and has a ring shape surrounding the impurity region 115 in a plan view. In one example, the recess 61 is in contact with the impurity region 115 and is spaced apart from the trench structure 12 in a plan view. The recess 64 is located outside the trench structure 12 and inside the trench structure 50 in a plan view. In one example, the recess 64 is in contact with the trench structures 12 and 50, but is not limited to this. Next, insulators 62 and 65 are formed to fill the recesses 61 and 64, respectively. As described above, an STI 60 including the recess 61 and the insulator 62 and an STI 63 including the recess 64 and the insulator 65 are formed.

[0048] Next, as shown in FIG. 8 , the first contact region 13 and the second contact region 14, which are the first impurity region 11 and located on the main surface 2a of the semiconductor layer 2, are formed (fifth step). In the fifth step, first, one of the first contact region 13 and the second contact region 14 is formed. For example, using a mask (not shown), impurities having one of the first conductivity type and the second conductivity type are introduced into the portion of the semiconductor layer 2 exposed from the mask. Next, the other of the first contact region 13 and the second contact region 14 is formed. For example, using a mask (not shown), impurities having the other of the first conductivity type and the second conductivity type are introduced into the portion of the semiconductor layer 2 exposed from the mask. This forms the first contact region 13 that is in contact with the side surface 21b of the trench 21 and has the first conductivity type, and the second contact region 14 that is spaced apart from the first contact region 13 and has the second conductivity type.

[0049] In this embodiment, an impurity having the second conductivity type is introduced into the main surface 2a of the semiconductor layer 2 and its vicinity in the impurity region 115. This forms a second impurity region 15 and a second contact region 14 located on the second impurity region 15 and in contact with the second impurity region 15.

[0050] By carrying out the first to fifth steps described above, a Zener diode 6 (see FIG. 2) having a first impurity region 11 and a trench structure 12, as well as a first contact region 13, a second contact region 14, and a second impurity region 15 that function as a current path for the Zener diode 6 are formed.

[0051] The effects of the semiconductor device 100 manufactured by the manufacturing method according to the present embodiment will be described below with reference to FIG. 10 . FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a reference example. FIG. 10 shows a Zener diode 200. Unlike the Zener diode 6, the Zener diode 200 does not have the first impurity region 11, the trench structure 12, or the second impurity region 15. Instead, the Zener diode 200 has a trench structure 250 that is in contact with the first contact region 13 and is a DTI, and an impurity region 260 that is in contact with the second contact region 14 and has the first conductivity type. The trench structure 250 has a structure similar to the trench structure 50 of the Zener diode 6 and is adjacent to the second contact region 14. The impurity region 260 is located directly below the second contact region 14 and is spaced apart from the buried region BL.

[0052] In the Zener diode 200, a PN junction is formed by the second contact region 14 and the impurity region 260. Here, the second contact region 14 is formed on the main surface 2a of the semiconductor layer 2. For this reason, the performance of the Zener diode 200 is easily affected by the surface quality of the second contact region 14. Furthermore, in the Zener diode 200, the current C flowing from the second contact region 14 to the first contact region 13 mainly passes through the surfaces of the impurity region 260, the semiconductor layer 2, the buried region BL, and the trench structure 250. For this reason, the parasitic resistance of the current path passing through the Zener diode 200 tends to increase as the thickness of the semiconductor layer 2 increases.

[0053] In contrast, the Zener diode 6 included in the semiconductor device 100 according to this embodiment has a first impurity region 11, a trench structure 12, and a second impurity region 15. In the Zener diode 6, a PN junction is formed by the second impurity region 15 and the third impurity region 16 that forms the side surface 21b of the groove 21 of the trench structure 12. This separates the portion of the Zener diode 6 where the PN junction is formed from the principal surface 2a of the semiconductor layer 2. This reduces the influence of the quality of the principal surface 2a of the semiconductor layer 2 on the performance of the Zener diode 6. Therefore, this embodiment provides a semiconductor device 100 capable of reducing surface noise. This reduces the risk of drift in the Zener diode 6 compared to the Zener diode 200.

[0054] Furthermore, in this embodiment, the first impurity region 11, the trench structure 12, and the second impurity region 15 are located above the buried region BL, so that the parasitic resistance R of the current path passing through the Zener diode 6 is less likely to change even if the thickness of the semiconductor layer 2 increases. In addition, the current path in the Zener diode 6 is significantly shorter than that of the Zener diode 200. Therefore, the internal resistance of the Zener diode 6 can be significantly smaller than that of the Zener diode 200.

[0055] Furthermore, in this embodiment, trench structures 12 and 50 having different depths are formed simultaneously. Specifically, by making the width W1 of the groove 21 of the trench structure 12 different from the opening width W3 of the groove 51 of the trench structure 50, the groove 21 having the semiconductor layer 2 as its bottom surface and the groove 51 penetrating the semiconductor layer 2 can be formed simultaneously in the above-mentioned step 2A. In addition, the insulator 22 of the trench structure 12 and the insulating layer 52 of the trench structure 50 can be formed simultaneously in the above-mentioned steps 2C and 2D, and the conductor 23 of the trench structure 12 and the conductor 53 of the trench structure 50 can be formed simultaneously in the above-mentioned step 2E. As described above, according to this embodiment, multiple types of trench structures 12 and 50 can be formed simultaneously while reducing the number of manufacturing steps for the semiconductor device 100. Therefore, by applying the manufacturing method for the semiconductor device 100 according to this embodiment, multiple types of trench structures can be efficiently manufactured.

[0056] Furthermore, in this embodiment, by simultaneously forming multiple types of trench structures (i.e., trench structures 12 and 50), it is possible to simultaneously form the trench structure 50, which is a DTI, and the Zener diode 6 using the trench structure 12. Therefore, in this embodiment, it is possible to omit the process for forming only the trench structure for the Zener diode 6. In other words, it is possible to omit a mask for forming only the trench structure for the Zener diode 6. Therefore, it is possible to effectively reduce the manufacturing cost of the semiconductor device 100 including the Zener diode 6 and the trench structure 50 (DTI).

[0057] In one example, the ratio of the width W1 of the groove 21 to the depth D1 of the groove 21 is 27% or more and 960% or less of the ratio of the width W2 of the groove 51 to the depth D2 of the groove 51. In this case, when the groove 51 penetrating the semiconductor layer 2 is formed, the bottom surface 21a of the groove 21 can be easily defined by the semiconductor layer 2.

[0058] In one example, the impurity concentration of the second contact region 14 is higher than the impurity concentration of the first impurity region 11 and the impurity concentration of the second impurity region 15. In this case, the contact resistance between the Zener diode 6 and the wiring L2 can be effectively reduced.

[0059] In one example, the semiconductor layer 2 has a third impurity region 16 that forms the side surface 21b of the trench 21 and has the first conductivity type, and the first impurity region 11 and the first contact region 13 are each in contact with the third impurity region 16. In this case, the internal resistance of the Zener diode 6 can be effectively reduced.

[0060] In one example, the semiconductor device 100 includes an insulator 62 filling a recess 61 provided in the main surface 2a of the semiconductor layer 2, and the insulator 62 is located between the first contact region 13 and the second contact region 14. In this case, the leakage current between the first contact region 13 and the second contact region 14 can be effectively reduced.

[0061] In one example, the semiconductor device 100 includes a conductor 23 buried in the groove 21, and the conductor 23 is in a floating state. In this case, the parasitic resistance R of the portion of the current path through the Zener diode 6 that is located near the conductor 23 can be reduced.

[0062] In one example, the manufacturing method includes a step 2B of introducing an impurity having the first conductivity type into the side surface 21b of the trench 21 and the side surface 51b of the trench 51 before forming the insulator 22 and the insulating layer 52. In this case, the third impurity region 16, which becomes part of the current path of the Zener diode 6, can be formed simultaneously with the formation of the fourth impurity region 17 included in the trench structure 50, thereby effectively simplifying the manufacturing process.

[0063] In one example, the conductors 23 and 53 are each made of polysilicon, which allows the conductors 23 and 53 to be easily embedded in the trenches 21 and 51, respectively.

[0064] Although the embodiment according to one aspect of the present disclosure has been described above, the present disclosure can also be embodied in other forms.

[0065] In the above embodiment, the Zener diode is located on a semiconductor substrate, but this is not limiting. In one example, the Zener diode may be located on a substrate other than a semiconductor substrate. In this case, the semiconductor layer is formed on the substrate. That is, the semiconductor layer does not need to be formed based on the semiconductor substrate. If a semiconductor substrate is not used, the conductor of the trench structure, which is the DTI, does not need to contact the substrate.

[0066] In the above embodiments, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for a solar cell, a wind power generator, or other power generation device. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0067] Although an embodiment according to one aspect of the present disclosure has been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims. As explained above, various embodiments of the present disclosure can be defined as follows:

[0068] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0069] [A1] a semiconductor layer located on a substrate and having a first conductivity type; a groove having the semiconductor layer as a bottom surface; an insulating layer covering the surface of the groove; Equipped with The semiconductor layer is a first impurity region spaced apart from the substrate, in contact with a side surface of the trench, and having a second conductivity type different from the first conductivity type; a first contact region that is located on the first impurity region and in a surface portion of the semiconductor layer, that contacts the side surface of the trench, and that has the first conductivity type; a second contact region located on the first impurity region and in the surface portion of the semiconductor layer, spaced apart from the first contact region, and having the second conductivity type; a second impurity region located on the first impurity region and below the second contact region, in contact with both the first impurity region and the second contact region, and having the second conductivity type; the first impurity region and the first contact region are spaced apart from each other; Semiconductor device.

[0070] [A2] The semiconductor device according to [A1], wherein the impurity concentration of the second contact region is higher than the impurity concentration of the first impurity region and the impurity concentration of the second impurity region.

[0071] [A3] the semiconductor layer further includes a third impurity region that forms the side surface of the trench and has the first conductivity type; The semiconductor device according to [A1] or [A2], wherein the first impurity region and the first contact region are each in contact with the third impurity region.

[0072] [A4] further comprising an insulator filling a recess provided in the surface portion of the semiconductor layer; The semiconductor device according to any one of [A1] to [A3], wherein the insulator is located between the first contact region and the second contact region.

[0073] [A5] Further, a conductor is provided which is embedded in the groove, The semiconductor device according to any one of [A1] to [A4], wherein the conductor is in a floating state.

[0074] [A6] The semiconductor device according to [A5], wherein the conductor is polysilicon.

[0075] [A7] a second groove penetrating the semiconductor layer and surrounding the groove; The semiconductor device according to any one of [A1] to [A6], wherein the width of the second groove is larger than the width of the groove.

[0076] [A8] The semiconductor device according to [A7], wherein the ratio of the width of the groove to the depth of the groove is 27% or more and 960% or less of the ratio of the width of the second groove to the depth of the second groove.

[0077] [A9] forming a semiconductor layer overlying a semiconductor substrate and having a first conductivity type; forming a trench having a bottom surface in the semiconductor layer, the trench being located within the semiconductor layer and adjacent to a first impurity region having a second conductivity type different from the first conductivity type; forming a second impurity region in the semiconductor layer on and in contact with the first impurity region, the second impurity region having the second conductivity type; forming a first contact region having the first conductivity type, the first contact region being located on the first impurity region and in a surface portion of the semiconductor layer, in contact with a side surface of the trench, and a second contact region having the second conductivity type, the second contact region being located on the first impurity region and in the surface portion of the semiconductor layer, spaced apart from the first contact region; A method for manufacturing a semiconductor device comprising:

[0078] [A10] Before forming the second impurity region, forming an insulator to fill the trench; removing a portion of the insulator so as not to expose the bottom surface of the groove; and filling the trench with a conductor spaced apart from the semiconductor layer, The method for manufacturing a semiconductor device according to [A9], wherein the conductor is in a floating state.

[0079] [A11] In the step of forming the groove, a second groove penetrating the semiconductor layer is formed simultaneously with the groove, In the step of forming the insulator, an insulating layer covering the second groove is simultaneously formed; In the step of removing the portion of the insulator, the portion of the insulating layer is removed so as to expose the substrate in the second groove, In the step of embedding the conductor in the groove, a second conductor in contact with the substrate is embedded in the second groove; The method for manufacturing a semiconductor device according to [A10], wherein the width of the second groove is larger than the width of the groove.

[0080] [A12] The method for manufacturing a semiconductor device according to [A11], wherein the substrate is a semiconductor substrate.

[0081] [A13] The semiconductor device according to [A11] or [A12], wherein the ratio of the width of the groove to the depth of the groove is 27% or more and 960% or less of the ratio of the width of the second groove to the depth of the second groove. [Explanation of symbols]

[0082] 1...Semiconductor substrate 2...Semiconductor layer 2a...Main surface (surface part) 6...Zener diode 10...Device area 11...First impurity region 12...Trench structure 13...First contact area 14...2 contact area 15…Second impurity region 16…Third impurity region 17…Fourth impurity region 21...Groove 21a…Bottom surface 21b...side 22...Insulator 23...Conductor 23a…Bottom surface 23b…side 23c…Top surface 50...Trench structure 51...Groove (2nd groove) 51a…Bottom surface 51b…side 52...insulating layer 53...Conductor 60...STI 60a...bottom 61...Depression 62...Insulator 100...Semiconductor device 102a...first epitaxial layer 102b...second epitaxial layer 115...Impurity region 122...Insulator 152...insulating layer 200...Zener diode BL...Buried region C…Current ER: Element region L1...Wiring L2...Wiring O1…opening O2…opening R…parasitic resistance W1…Width W2…Width W3...Opening width W4…Aperture width.

Claims

1. a semiconductor layer overlying the substrate and having a first conductivity type; a groove having the semiconductor layer as a bottom surface; an insulating layer covering the surface of the groove; Equipped with The semiconductor layer is a first impurity region spaced apart from the substrate, in contact with a side surface of the trench, and having a second conductivity type different from the first conductivity type; a first contact region that is located on the first impurity region and in a surface portion of the semiconductor layer, that contacts the side surface of the trench, and that has the first conductivity type; a second contact region located on the first impurity region and in the surface portion of the semiconductor layer, spaced apart from the first contact region, and having the second conductivity type; a second impurity region located on the first impurity region and below the second contact region, in contact with both the first impurity region and the second contact region, and having the second conductivity type; the first impurity region and the first contact region are spaced apart from each other; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the impurity concentration of said second contact region is higher than the impurity concentration of said first impurity region and the impurity concentration of said second impurity region.

3. the semiconductor layer further includes a third impurity region that forms the side surface of the trench and has the first conductivity type; 3. The semiconductor device according to claim 1, wherein the first impurity region and the first contact region are in contact with the third impurity region.

4. further comprising an insulator filling a recess provided in the surface portion of the semiconductor layer; The semiconductor device according to claim 1 , wherein the insulator is located between the first contact region and the second contact region.

5. Further, a conductor is provided which is embedded in the groove, 3. The semiconductor device according to claim 1, wherein the conductor is in a floating state.

6. 6. The semiconductor device according to claim 5, wherein said conductor is polysilicon.

7. a second groove penetrating the semiconductor layer and surrounding the groove; The semiconductor device according to claim 1 , wherein the width of the second groove is larger than the width of the first groove.

8. 8. The semiconductor device according to claim 7, wherein a ratio of the width of the groove to the depth of the groove is 27% or more and 960% or less of a ratio of the width of the second groove to the depth of the second groove.

9. forming a semiconductor layer overlying a semiconductor substrate and having a first conductivity type; forming a trench having a bottom surface in the semiconductor layer, the trench being located within the semiconductor layer and adjacent to a first impurity region having a second conductivity type different from the first conductivity type; forming a second impurity region in the semiconductor layer on and in contact with the first impurity region, the second impurity region having the second conductivity type; forming a first contact region having the first conductivity type, the first contact region being located on the first impurity region and in a surface portion of the semiconductor layer, in contact with a side surface of the trench, and a second contact region having the second conductivity type, the second contact region being located on the first impurity region and in the surface portion of the semiconductor layer, spaced apart from the first contact region; A method for manufacturing a semiconductor device comprising:

10. Before forming the second impurity region, forming an insulator to fill the trench; removing a portion of the insulator so as not to expose the bottom surface of the groove; and filling the trench with a conductor spaced apart from the semiconductor layer, The method for manufacturing a semiconductor device according to claim 9 , wherein the conductor is in a floating state.

11. In the step of forming the groove, a second groove penetrating the semiconductor layer is formed simultaneously with the groove; In the step of forming the insulator, an insulating layer covering the second groove is simultaneously formed; In the step of removing the portion of the insulator, the portion of the insulating layer is removed so as to expose the substrate in the second groove; In the step of embedding the conductor in the groove, a second conductor in contact with the substrate is embedded in the second groove; The method for manufacturing a semiconductor device according to claim 10 , wherein the width of the second groove is larger than the width of the groove.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the substrate is a semiconductor substrate.

13. 13. The method for manufacturing a semiconductor device according to claim 11, wherein a ratio of the width of the groove to the depth of the groove is 27% or more and 960% or less of a ratio of the width of the second groove to the depth of the second groove.

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