Driver circuit and display device

Abstract

To improve the accuracy of a setting signal (Q signal) for controlling another stage in a driver circuit.SOLUTION: The driver circuit includes a plurality of stages of unit circuits, drives a plurality of signal lines, and includes a clock terminal to which a clock signal is input, a setting terminal that outputs a setting signal to a unit circuit in another stage, a setting transistor connected to the clock terminal and the setting terminal, a control node, a control capacitor, and a control transistor having a gate terminal connected to the control node.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to driver circuits. [Background technology]

[0002] Patent Document 1 discloses a driver circuit used in a display device that performs partial display. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2011-209714 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional driver circuits have a problem in that the accuracy of the setting signals that control other stages is low. [Means for solving the problem]

[0005] A driver circuit according to one aspect of the present disclosure is a driver circuit that includes a plurality of stages of unit circuits and drives a plurality of signal lines, and includes a clock terminal to which a clock signal is input, a setting terminal that outputs a setting signal to a unit circuit of another stage, a setting transistor connected to the clock terminal and the setting terminal, a control node, a control capacitance, and a control transistor whose gate terminal is connected to the control node, and the control node is connected to one conduction terminal of the control transistor via the control capacitance, and the other conduction terminal of the control transistor is connected to the clock terminal. [Effects of the Invention]

[0006] The accuracy of the setting signal (Q signal) in the driver circuit is improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 2] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 3] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 4] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 5] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 6] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. [Figure 7] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 8] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 9] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 10] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 11] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 2 is a timing chart showing the operation of the driver circuit according to this embodiment. FIGS. 3 to 5 are circuit diagrams showing the configuration of a unit circuit of the driver circuit according to this embodiment. As shown in FIGS. 1 to 5, the driver circuit 20 is a driver circuit including multiple stages of unit circuits (Jn, Jn-1, Jn+1, etc.) and driving multiple signal lines (Ga to Gf, etc.). The driver circuit 20 includes a clock terminal IK to which a clock signal K1 is input, a setting terminal Un that outputs a setting signal Qn to another stage of unit circuit (Jn+2, etc.), a setting transistor Tq connected to the clock terminal IK and the setting terminal Un, a control node NZ, a control capacitance Cz, and a control transistor Tz whose gate terminal is connected to the control node NZ. The control node NZ is connected to one conduction terminal of the control transistor Tz via the control capacitance Cz, and the other conduction terminal of the control transistor Tz is connected to the clock terminal IK. n is a natural number.

[0009] The setting terminal Un may be connected to the clock terminal IK via a setting transistor Tq. The setting signal Qn may have a function of setting the unit circuit in the subsequent stage. The setting signal Qn may have a function of resetting the unit circuit in the preceding stage. This reduces the effect on the setting terminal Un of noise generated in the control capacitor Cz by a high-frequency clock signal K1 or the like, making it possible to generate a highly accurate setting signal Qn.

[0010] The n-th stage unit circuit Jn may have a first input terminal I1 to which a first pulse signal P1 is input, a first drive terminal Xn to which a first drive signal Va is output to one of a plurality of signal lines (including Ga to Gc), and a first transistor T1. The first drive terminal Xn may be connected to the first input terminal I1 via the first transistor T1. A gate terminal of the first transistor T1 may be connected to a control node NZ, and a gate terminal of the setting transistor Tq may be connected to the control node NZ.

[0011] As shown in Figure 2, in the nth stage unit circuit Jn, the control node NZ becomes active (High) during the set period LS (active period of Qn-2), turning on the control transistor Tz and charging the control capacitance Cz, and the control node NZ may be boosted by the rising edge of the clock signal K1.

[0012] The control node NZ is boosted by the control capacitance Cz, thereby increasing the drive capability of the setting transistor Tq and stabilizing the setting signal Qn. That is, the pulse of the clock signal K1 is stably output from the setting terminal Un. Furthermore, the control node NZ is boosted by the control capacitance Cz, thereby increasing the drive capability of the first transistor T1 and stabilizing the first drive signal Va. That is, the pulse of the first pulse signal P1 is stably output from the first drive terminal Xn.

[0013] The driver circuit 20 includes a first power supply line D1 (e.g., a high-potential power supply line, VDD line) and a second power supply line D2 (e.g., a low-potential power supply line, VSS line), and the n-th stage unit circuit Jn may have a set transistor Ts to which a set signal (Qn-2) from the previous stage is input, and a reset transistor Tr to which a reset signal (Qn+3) from the subsequent stage is input. A control node NZ may be connected to the first power supply line D1 via the set transistor Ts, and may also be connected to the second power supply line D2 via the reset transistor Tr. As a result, the control node NZ is activated by the rising edge of the set signal Qn-2 (the n-th stage unit circuit Jn is set), and the control node NZ is deactivated by the rising edge of the reset signal Qn+3 (the n-th stage unit circuit Jn is reset).

[0014] In the n-th stage unit circuit Jn, the setting signal Qn may be active (High) during a first period L1, and the first period T1 may overlap with at least a portion of the active period (High period) of the first drive signal Va. The active period of the setting signal Qn may substantially coincide with the active period of the first drive signal Va. The setting signal Qn may be active during a second period L2, and the first drive signal Va may be inactive during the second period L2.

[0015] The setting signal Qn has a function of a set signal, and another stage (Jn+2) may be set in the first period L1 and the second period L2. The setting signal Qn may be active in the second period L2, and pulses of the first pulse signal P1 may be thinned out in the second period L2.

[0016] The first power supply line D1 may be a high-potential power supply line, and the second power supply line D2 may be a low-potential power supply line. The n-th stage unit circuit Jn may have an inversion node NR whose state is inverted with respect to the control node NZ, and multiple pull-down transistors T11, T13, and T14 whose gate terminals are connected to the inversion node NR. The setting terminal Un and the control node NZ may be connected to the second power supply line D2 via different pull-down transistors. That is, the setting terminal Un may be connected to the second power supply line D2 via the pull-down transistor T13, and the control node NZ may be connected to the second power supply line D2 via the pull-down transistor T14. The first drive terminal Xn may be connected to the second power supply line D2 via the pull-down transistor T11.

[0017] In this way, during the period LZ when the control node NZ is active (high), the pull-down transistors T13 and T14 are turned off, while the control node NZ becomes inactive (low) (the inversion node NR becomes active high), turning the setting transistor Tq off and the pull-down transistors T13 and T14 on. As a result, the potentials of the setting terminal Un and the control node NZ are maintained at low level regardless of the level of the clock signal K1, and the setting signal Qn is maintained inactive (low).

[0018] Furthermore, during the period LZ when the control node NZ is active (High), the pull-down transistor T11 is turned OFF, while the control node NZ becomes inactive (Low) (the inversion node NR becomes active High), which turns the first transistor T1 OFF and the pull-down transistor T11 ON. As a result, the potential of the first drive terminal Xn is maintained at a Low level regardless of the level of the first pulse signal P1, and the first drive signal Va is maintained inactive (Low).

[0019] In the n-th stage unit circuit Jn, the inverting node NR may be connected to a first power supply line D1 (high-potential side power supply line) via a diode-connected transistor T9 (power supply line transistor) and to a second power supply line D2 (low-potential side power supply line) via a transistor T10 (inverting transistor), and the gate terminal of the transistor T10 may be connected to a control node NZ. The transistors T9 to T11 and T13 and T14 may form an inverting circuit.

[0020] As shown in FIG. 1, the driver circuit 20 may include a signal generating circuit 30 that generates clock signals K1 to K6 and first to sixth pulse signals P1 to P6, and an input line group 25 that transmits the clock signals K1 to K6 and the first to sixth pulse signals P1 to P6.

[0021] 3 to 5, the setting transistor Tq, the control transistor Tz, the set transistor Ts, the reset transistor Tr, the pull-down transistors T13 and T14, and the transistors T9 and T10 may be, but are not limited to, n-channel transistors. These transistors may also be p-channel transistors, or may be a mixture of n-channel and p-channel transistors.

[0022] Fig. 6 is a block diagram showing the configuration of a display device according to this embodiment. As shown in Fig. 6, a display device 50 according to this embodiment may include a display unit 40, a data driver 2, a scan driver 3, and a controller 4. The display unit 40 may be capable of setting a refresh rate for each region. The driver circuit 20 may include a scan driver 3 (shift register circuit), a controller 4, and an input line group 25. The controller 4 may include a signal generating circuit 30 and a processor 35. The controller 4 may be a timing controller.

[0023] In the display device 50, the display unit 40 may have a plurality of liquid crystal capacitors (including pixel electrodes, counter electrodes, and a liquid crystal layer). In the display device 50, the display unit 40 may have a plurality of light-emitting elements (e.g., organic light-emitting diodes, quantum dot light-emitting diodes), and the driver circuit 20 may include at least one of a scan driver and a light-emission control driver.

[0024] FIG. 7 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIGS. 8 to 10 are circuit diagrams showing the configuration of a unit circuit of the driver circuit according to this embodiment. FIG. 11 is a timing chart showing the operation of the driver circuit according to this embodiment. As shown in FIGS. 8 to 10, the n-th stage unit circuit Jn may have, in addition to a first input terminal I1 and a first drive terminal Xn, a second input terminal I2 to which a second pulse signal P2 is input, a second drive terminal Yn to which a second drive signal Vb is output to another one (Gb) of the multiple signal lines, and a second transistor T2. The second drive terminal Yn may be connected to the second input terminal I1 via the second transistor T2, and the gate terminal of the second transistor T2 may be connected to the control node NZ.

[0025] This reduces the effect on the setting terminal Un of noise generated in the control capacitance Cz by high frequency signals (K1·P1·P2, etc.), making it possible to generate a highly accurate setting signal Qn.

[0026] The n-th stage unit circuit Jn may have a set node NQ that is activated in the set period LS and a bootstrap capacitance Cq. A set terminal Un may be connected to the set node NQ via the bootstrap capacitance Cq.

[0027] The nth-stage unit circuit Jn may have third and fifth transistors T3 and T5 (set transistors) whose gate terminals (set terminals Sn) receive a set signal (e.g., Qn-1) from the previous stage, and fourth and sixth transistors T4 and T6 (reset transistors) whose gate terminals (reset terminals Rn) receive a reset signal (e.g., Qn+2) from the next stage.

[0028] The control node NZ may be connected to the first power supply line D1 via the third transistor T3 and to the second power supply line D2 via the fourth transistor T4. The setting node NQ may be connected to the first power supply line D1 via the fifth transistor T5 and to the second power supply line D2 via the sixth transistor T6. As a result, the control node NZ and the setting node NQ are activated by the rising edge of the set signal Qn-1, and are deactivated by the rising edge of the reset signal Qn+2.

[0029] 7 to 11, the setting signal Qn is active during the first period L1, and the first period L1 includes at least a part of the active period La of the first drive signal Va and at least a part of the active period Lb of the second drive signal Vb. The first period L1 may include the entire active period La of the first drive signal Va and the entire active period Lb of the second drive signal Vb. The first period L1 may include the entire active period La of the first drive signal Va and a part of the active period Lb of the second drive signal Vb.

[0030] In the driver circuit 20, the two signal lines Ga and Gb can be driven by the first and second drive signals Va and Vb generated by the n-th stage unit circuit Jn, thereby reducing the circuit scale of the driver circuit 20.

[0031] Each of the signals Ga to Gf ​​may be a scanning line, and each of the first and second drive signals Va and Vb may be a scan signal. The signal line Ga may be a (2n-1)-stage scanning line formed on the display unit 40, and the signal line Gb may be a (2n)-stage scanning line formed on the display unit 40.

[0032] The period LZ during which the setting node NQ remains active (High) may include the active period of the first drive signal Va and the active period of the second drive signal Vb. The potential of the control node NZ is Vz, and the potential of the setting node NQ is Vq. Let's say.

[0033] In the driver circuit 20, the setting signal Qn may be active during the second period L2, and the first and second drive signals Va and Vb may be inactive during the second period L2. That is, full scanning, which scans all of the signal lines (including Ga to Gf), and partial scanning, which scans only a portion of the signal lines (including Ge and Gf), may be performed. The setting signal Qn functions as a set signal, and another stage (Jn+2) may be set during the first period L1 and the second period L2. This allows the refresh rate (rewriting frequency) to be changed for each region of the display unit 40 (including signal lines Ga to Gf) to be driven, thereby reducing power consumption.

[0034] 7 to 11, the area including the signal lines (scanning lines) Ga to Gd has a low refresh rate, and the area including the signal lines (scanning lines) Ge and Gf has a high refresh rate. A still image may be displayed in the low refresh rate area, and a moving image may be displayed in the high refresh rate area.

[0035] 11, in the driver circuit 20, the first and second drive signals Va and Vb may be sequentially activated (rising from low to high) during a first period L1 (the active period of the setting signal Qn). A portion (e.g., the latter half) of the active period of the first drive signal Va may overlap with a portion (e.g., the first half) of the active period of the second drive signal Vb. During the first period L1, each of the first and second drive signals Va and Vb may return to an inactive state (from active high).

[0036] As shown in Fig. 11, during the first period L1, the first and second pulse signals P1 and P2 may be sequentially activated while the clock signal K1 remains active. In Fig. 11, the first and second pulse signals P1 and P2 have the same pulse width but different phases, and the pulse width of the clock signal K1 is a natural number multiple (e.g., twice) of the pulse widths of the first and second pulse signals P1 and P2, but this is not limited to this. Furthermore, the activation timing (rising edge) of the clock signal K1 and the activation timing (rising edge) of the first pulse signal P1 are synchronized, but this is not limited to this.

[0037] The phase shift between the first and second pulse signals may correspond to one horizontal scanning period. The periods of the clock signal K1 and the first and second pulse signals P1 and P2 may be equal. In FIG. 11, as an example, the clock signal K1 has a period of 6H and is active 4H, and the first and second pulse signals P1 and P2 have a period of 6H and are active 2H. 1H is one horizontal scanning period.

[0038] As shown in FIG. 11, the setting signal Qn may be active during the second period L2, and the pulses of the first and second pulse signals P1 and P2 may be thinned out during the second period L2.

[0039] A group of clock signals (K1 to KK3) with two or more phases including clock signal K1 and a group of pulse signals (P1 to P6) with three or more phases including first and second pulse signals P1 and P2 may be input to driver circuit 20. The number of phases of the group of clock signals (three phases, K1 to K3, in FIG. 2) may be less than the number of phases of the group of pulse signals (six phases, P1 to P6, in FIG. 2).

[0040] The n-th stage unit circuit Jn shown in Figure 11 includes, in addition to the control node NZ, a setting node NQ that is activated during the setting period LS, and the setting terminal Un is connected to the setting node NQ via a bootstrap capacitance Cq. In this case, when the setting node NQ becomes active (High) during the setting period LS, the setting transistor Tq turns ON and the bootstrap capacitance Cq is charged, and the setting node NQ may be boosted by the rising edge of the clock signal K1. This increases the driving capability of the setting transistor Tq and stabilizes the setting signal Qn. In other words, the pulse of the clock signal K1 is stably output from the setting terminal Un.

[0041] By providing the setting node NQ in addition to the control node NZ, the load on the control node NZ can be reduced and the influence of the first and second pulse signals P1 and P2 on the setting node NQ can be substantially eliminated, thereby further stabilizing the setting signal Qn.

[0042] The n-th stage unit circuit Jn may have an inversion node NR whose state is inverted with respect to the setting node NQ, and a plurality of pull-down transistors T11 to T15 whose gate terminals are connected to the inversion node NR. The setting terminal Un, the control node NZ, and the setting node NQ may be connected to the second power supply line D2 via different pull-down transistors. That is, the setting terminal Un may be connected to the second power supply line D2 via pull-down transistor T13, the setting node NQ may be connected to the second power supply line D2 via pull-down transistor T14, and the control node NZ may be connected to the second power supply line D2 via pull-down transistor T15. The first drive terminal Xn may be connected to the second power supply line D2 via pull-down transistor T11, and the second drive terminal Yn may be connected to the second power supply line D2 via pull-down transistor T12.

[0043] In this way, while the setting node NQ is active (high), the pull-down transistors T11 to T15 are turned off, and when the setting node NQ becomes inactive (low) (the inversion node NR becomes active high), the setting transistor Tq is turned off and the pull-down transistors T11 to T15 are turned on. As a result, regardless of the levels of the clock signal K1 and the first and second pulse signals P1 and P2, the potentials of the setting terminal Un, the control node NZ, and the setting node NQ are maintained at low level, and the setting signal Qn and the first and second drive signals Va and Vb are maintained inactive (low).

[0044] In the n-th stage unit circuit Jn, the inverting node NR may be connected to a first power supply line D1 (high potential side power supply line) via a diode-connected transistor T9 (power supply line transistor) and to a second power supply line D2 (low potential side power supply line) via a transistor T10 (inverting transistor), and the gate terminal of the transistor T10 may be connected to a setting node NQ. The transistors T9 to T15 may form an inverting circuit.

[0045] The above-described embodiments are intended to be illustrative and explanatory, and not limiting, and many variations will be apparent to those skilled in the art based on these examples and descriptions.

[0046] The present embodiment will be summarized below. In the following, "the above" includes the technical content disclosed in at least one of FIGS.

[0047] A driver circuit including a plurality of unit circuits and configured to drive a plurality of signal lines, a clock terminal to which a clock signal is input, a setting terminal to which a setting signal is output to a unit circuit of another stage, a setting transistor connected to the clock terminal and the setting terminal, a control node, a control capacitance, and a control transistor having a gate terminal connected to the control node; the control node is connected to one conduction terminal of the control transistor via the control capacitance, and the other conduction terminal of the control transistor is connected to the clock terminal.

[0048] the n-th stage unit circuit has a first input terminal to which a first pulse signal is input, a first drive terminal to which a first drive signal is output to one of the plurality of signal lines, and a first transistor; The driver circuit as described above, wherein the first drive terminal is connected to the first input terminal via the first transistor.

[0049] The driver circuit as described above, wherein the gate terminal of the first transistor is connected to the control node.

[0050] The driver circuit as described above, wherein the gate terminal of the setting transistor is connected to the control node.

[0051] In the driver circuit described above, when the control node becomes active during a set period, the control transistor is turned on and the control capacitance is charged, and when the clock signal rises, the control node is boosted.

[0052] a first power line and a second power line; the n-th stage unit circuit has a set transistor to which a set signal from a previous stage is input and a reset transistor to which a reset signal from a subsequent stage is input, The driver circuit described above, wherein the control node is connected to the first power supply line via the set transistor and is connected to the second power supply line via the reset transistor.

[0053] the setting signal is active during a first time period; The driver circuit as described above, wherein the first period overlaps with at least a portion of an active period of the first drive signal.

[0054] the setting signal is active during a second time period; The driver circuit as described above, wherein during the second period, the first drive signal is inactive.

[0055] The setting signal has a function of a set signal, The driver circuit as described above, wherein the other stage is set during the first period and the second period.

[0056] the setting signal is active during a second time period; The driver circuit as described above, wherein the pulses of the first pulse signal are thinned out during the second period.

[0057] the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the n-th stage unit circuit has an inversion node whose state is inverted with respect to the control node, and a plurality of pull-down transistors whose gate terminals are connected to the inversion node; The driver circuit as described above, wherein the setting terminal and the control node are connected to the second power supply line via different pull-down transistors.

[0058] The driver circuit as described above, wherein the first drive terminal is connected to the second power supply line via a pull-down transistor.

[0059] each of the plurality of signal lines is a scanning line; The driver circuit as described above, wherein the first drive signal is a scan signal.

[0060] The driver circuit as described above, wherein the plurality of signal lines are formed in a display section in which a refresh rate can be set for each area.

[0061] The driver circuit described above performs full scanning, which scans all of the plurality of signal lines, and partial scanning, which scans some of the plurality of signal lines.

[0062] the n-th stage unit circuit has a second input terminal to which a second pulse signal is input, a second drive terminal to which a second drive signal is output to another one of the plurality of signal lines, and a second transistor; the second drive terminal is connected to the second input terminal via the second transistor; The driver circuit as described above, wherein the gate terminal of the second transistor is connected to the control node.

[0063] the n-th stage unit circuit has a set node that is activated during a set period and a bootstrap capacitance; a gate terminal of the set transistor is connected to a set node; The driver circuit as described above, wherein the setting terminal is connected to the setting node via the bootstrap capacitance.

[0064] The driver circuit described above, wherein the active period of the setting signal includes the active period of the first drive signal and the active period of the second drive signal.

[0065] The driver circuit as described above, wherein the first and second drive signals are sequentially activated during an active period of the setting signal.

[0066] The driver circuit described above, wherein a portion of an active period of the first drive signal overlaps with a portion of an active period of the second drive signal.

[0067] The driver circuit as described above, wherein during an active period of the setting signal, the first and second drive signals each return to an inactive state.

[0068] The driver circuit as described above, wherein during an active period of the setting signal, the first and second pulse signals are sequentially activated while the clock signal remains active.

[0069] the first and second pulse signals have the same pulse width but different phases; The driver circuit as described above, wherein the pulse width of the clock signal is a natural number multiple of the pulse widths of the first and second pulse signals.

[0070] The driver circuit as described above, wherein the activation timing of the clock signal and the activation timing of the first pulse signal are synchronized.

[0071] The driver circuit as described above, wherein the phase difference between the first and second pulse signals corresponds to one horizontal scanning period.

[0072] The driver circuit described above receives as input a group of clock signals of two or more phases including the clock signal, and a group of pulse signals of three or more phases including the first and second pulse signals.

[0073] The driver circuit as described above, wherein the number of phases of the clock signal group is smaller than the number of phases of the pulse signal group.

[0074] a first power line and a second power line; the n-th stage unit circuit has third and fifth transistors to which a set signal is input from a previous stage side, and fourth and sixth transistors to which a reset signal is input from a subsequent stage side, the control node is connected to the first power supply line via the third transistor and to the second power supply line via the fourth transistor; The driver circuit described above, wherein the setting node is connected to the first power supply line via the fifth transistor and is connected to the second power supply line via the sixth transistor.

[0075] The driver circuit described above includes a signal generating circuit that generates the clock signal and the first and second pulse signals, and a group of input lines that transmit the clock signal and the first and second pulse signals.

[0076] A display device comprising the driver circuit described above.

[0077] The display device described above includes a display unit capable of setting a refresh rate for each area. [Explanation of symbols]

[0078] 20 Driver circuit 40 Display section Un setting terminal Xn 1st drive terminal Yn Second drive terminal Jn nth stage unit circuit Qn setting signal Va 1st drive signal Vb Second drive signal L1 1st period L2 2nd period

Claims

1. A driver circuit including a plurality of unit circuits and configured to drive a plurality of signal lines, a clock terminal to which a clock signal is input, a setting terminal to which a setting signal is output to a unit circuit of another stage, a setting transistor connected to the clock terminal and the setting terminal, a control node, a control capacitance, and a control transistor having a gate terminal connected to the control node; the control node is connected to one conduction terminal of the control transistor via the control capacitance, and the other conduction terminal of the control transistor is connected to the clock terminal.

2. the n-th stage unit circuit has a first input terminal to which a first pulse signal is input, a first drive terminal to which a first drive signal is output to one of the plurality of signal lines, and a first transistor; 2. The driver circuit of claim 1, wherein the first drive terminal is connected to the first input terminal through the first transistor.

3. 3. The driver circuit of claim 2, wherein a gate terminal of a first transistor is connected to the control node.

4. 2. The driver circuit of claim 1, wherein a gate terminal of the set transistor is connected to the control node.

5. 2. The driver circuit according to claim 1, wherein the control node becomes active during a set period, thereby turning on the control transistor and charging the control capacitance, and the control node is boosted by the rising edge of the clock signal.

6. a first power supply line and a second power supply line; the n-th stage unit circuit has a set transistor to which a set signal from a previous stage is input, and a reset transistor to which a reset signal from a subsequent stage is input, 3. The driver circuit according to claim 2, wherein the control node is connected to the first power supply line via the set transistor and to the second power supply line via the reset transistor.

7. the setting signal is active during a first time period; The driver circuit of claim 2 , wherein the first period overlaps at least a portion of an active period of the first drive signal.

8. the setting signal is active during a second time period; The driver circuit of claim 7 , wherein during the second period, the first drive signal is inactive.

9. The setting signal has a function of a set signal, The driver circuit according to claim 8 , wherein other stages are set during the first period and the second period.

10. the setting signal is active during a second time period; 9. The driver circuit according to claim 8, wherein the pulses of the first pulse signal in the second period are thinned out.

11. the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the n-th stage unit circuit has an inversion node whose state is inverted with respect to the control node, and a plurality of pull-down transistors whose gate terminals are connected to the inversion node; 7. The driver circuit of claim 6, wherein the setting terminal and the control node are connected to the second power supply line through different pull-down transistors.

12. 12. The driver circuit of claim 11, wherein the first drive terminal is connected to the second power supply line through a pull-down transistor.

13. each of the plurality of signal lines is a scanning line; 2. The driver circuit of claim 1, wherein the first drive signal is a scan signal.

14. 14. The driver circuit according to claim 13, wherein the plurality of signal lines are formed in a display section in which a refresh rate can be set for each area.

15. 14. The driver circuit according to claim 13, wherein full scanning is performed to scan all of the plurality of signal lines, and partial scanning is performed to scan some of the plurality of signal lines.

16. the n-th stage unit circuit has a second input terminal to which a second pulse signal is input, a second drive terminal to which a second drive signal is output to another one of the plurality of signal lines, and a second transistor; the second drive terminal is connected to the second input terminal via the second transistor; 3. The driver circuit of claim 2, wherein the gate terminal of the second transistor is connected to the control node.

17. the n-th stage unit circuit has a set node that is activated during a set period and a bootstrap capacitance; a gate terminal of the set transistor is connected to a set node; 17. The driver circuit of claim 16, wherein the set terminal is connected to the set node through the bootstrap capacitance.

18. 17. The driver circuit of claim 16, wherein an active period of the setting signal encompasses an active period of the first drive signal and an active period of the second drive signal.

19. 17. The driver circuit of claim 16, wherein the first and second drive signals are sequentially activated during an active period of the setting signal.

20. 17. The driver circuit of claim 16, wherein a portion of an active period of the first drive signal overlaps with a portion of an active period of the second drive signal.

21. 17. The driver circuit of claim 16, wherein the first and second drive signals each return to inactive during an active period of the set signal.

22. 17. The driver circuit of claim 16, wherein during an active period of the setting signal, the first and second pulse signals are sequentially activated while the clock signal remains active.

23. the first and second pulse signals have the same pulse width but different phases; 17. The driver circuit of claim 16, wherein the pulse width of the clock signal is a natural number multiple of the pulse widths of the first and second pulse signals.

24. 17. The driver circuit of claim 16, wherein the activation timing of the clock signal and the activation timing of the first pulse signal are synchronized.

25. 17. The driver circuit of claim 16, wherein the phase shift between the first and second pulse signals corresponds to one horizontal scanning period.

26. 17. The driver circuit according to claim 16, wherein a group of clock signals having two or more phases including the clock signal and a group of pulse signals having three or more phases including the first and second pulse signals are input.

27. 27. The driver circuit of claim 26, wherein the number of phases of the group of clock signals is less than the number of phases of the group of pulse signals.

28. a first power supply line and a second power supply line; the n-th stage unit circuit has third and fifth transistors to which a set signal is input from a preceding stage side, and fourth and sixth transistors to which a reset signal is input from a subsequent stage side, the control node is connected to the first power supply line via the third transistor and to the second power supply line via the fourth transistor; 17. The driver circuit according to claim 16, wherein the setting node is connected to the first power supply line via the fifth transistor and to the second power supply line via the sixth transistor.

29. 17. The driver circuit of claim 16, comprising: a signal generating circuit that generates the clock signal and the first and second pulse signals; and a group of input lines that transmit the clock signal and the first and second pulse signals.

30. A display device comprising a driver circuit according to any one of claims 1 to 29.

31. The display device according to claim 30, comprising a display section in which a refresh rate can be set for each area.

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