Semiconductor package and method of manufacturing the same

Abstract

To provide a semiconductor package having improved structural stability, and to provide a method of manufacturing the same.SOLUTION: The semiconductor package includes a substrate, a first chip 100 mounted on the substrate and having a photonic integrated circuit (PIC), a second chip 200 disposed on the first chip and having an electronic integrated circuit (EIC), and a third chip 300 disposed on the first chip and horizontally spaced apart from the second chip. The micro-lens module includes a support block (300) bonded to an upper surface of the first chip, a molding layer (400) surrounding the second chip and the support block on the first chip and exposing an upper surface of the support block, and a micro-lens layer (500) covering the molding layer, the first chip, and the support block on the molding layer, wherein the micro-lens layer is bonded to an upper surface of the molding layer and an upper surface of the support block using a first transparent adhesive layer (510) provided on a lower surface of the micro-lens layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a semiconductor package including an optical element and a manufacturing method thereof. [Background technology]

[0002] The development of the electronics industry has led to an increasing demand for higher performance, faster speeds, and smaller electronic components. In response to this trend, recent packaging technology has progressed toward mounting multiple semiconductor chips within a single package.

[0003] Recently, the electronics market has seen a rapid increase in demand for portable devices, which has led to a continuous demand for smaller and lighter electronic components mounted in these products. To achieve this demand, not only is technology for reducing the individual size of mounted components required, but also semiconductor packaging technology for integrating multiple individual devices into a single package is required. In particular, semiconductor packages integrating multiple devices require various structural, electrical, and optical characteristics according to the characteristics and functions of the devices. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 1,372,160 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor package with improved structural stability and a method for manufacturing the same. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention provides a semiconductor package comprising: a substrate; a first chip mounted on the substrate and having a photonic integrated circuit (PIC); a second chip disposed on the first chip and having an electronic integrated circuit (EIC); a support block disposed on the first chip and horizontally spaced apart from the second chip and bonded to an upper surface of the first chip; a molding film on the first chip surrounding the second chip and the support block and exposing an upper surface of the support block; and a microlens layer on the molding film covering the molding film, the first chip, and the support block, wherein the microlens layer is bonded to an upper surface of the molding film and an upper surface of the support block using a first transparent adhesive layer provided on a lower surface of the microlens layer.

[0007] To achieve the above object, a method for manufacturing a semiconductor package according to one aspect of the present invention includes the steps of: providing a first chip having a photonic integrated circuit (PIC) and a sensor portion, the first chip pads being arranged on an active surface of the first chip; mounting a second chip having an electronic integrated circuit (EIC) on the first chip so as to be connected to the first chip pads; bonding a support block located on the sensor portion to the first chip; forming a molding film on the first chip to cover the second chip and the support block; performing a thinning process on the molding film to expose an upper surface of the support block; and bonding a microlens layer to the upper surface of the molding film and the upper surface of the support block using a transparent adhesive layer.

[0008] According to another aspect of the present invention, a method for manufacturing a semiconductor package includes: providing a microlens layer; adhering a second chip having an electronic integrated circuit (EIC) and a support block to one surface of the microlens layer using a transparent adhesive layer; forming a molding film on the microlens layer to cover the second chip and the support block; performing a thinning process on the molding film to expose top surfaces of connection terminals of the second chip and the top surface of the support block; and bonding a first chip having a photonic integrated circuit (PIC) and chip pads and a sensor unit disposed on an active surface thereof to the molding film, the second chip, and the support block, wherein the chip pads are connected to the top surfaces of the connection terminals and the sensor unit is disposed on the support block. [Effects of the Invention]

[0009] According to the semiconductor package of the present invention, the insulating film formed by oxidizing or nitriding the lower part of the support block can be combined with the insulating film of the first chip to form an integrated unit, so that the support block can be firmly attached or coupled to the first chip, thereby providing a semiconductor package with improved structural stability.

[0010] In addition, the number of material layers through which light passes on the path of light passing through the transparent layer and incident on the sensor unit of the first chip can be reduced, and the support block can be made of a material with high transmittance for the light to be received by the first chip, thereby reducing light loss, and thus providing a semiconductor package with improved optical properties.

[0011] Furthermore, because the microlens layer is bonded using the first adhesive layer, the manufacturing process of the semiconductor package can be simplified and defects such as voids in the first adhesive layer can be reduced. Therefore, the loss of light passing through the first adhesive layer can be reduced. In other words, a semiconductor package with improved optical properties can be provided.

[0012] According to the method for manufacturing a semiconductor package of the present invention, after mounting a second chip on a first chip and bonding a support block, a thinning process can be performed together with the first molding film, thereby reducing the thickness of the second chip and the support block, thereby providing a miniaturized semiconductor package. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view illustrating a first example of a semiconductor package according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of region A in FIG. [Figure 3] FIG. 4 is a cross-sectional view illustrating a second example of a semiconductor package according to an embodiment of the present invention. [Figure 4] FIG. 10 is a cross-sectional view illustrating a third example of a semiconductor package according to an embodiment of the present invention. [Figure 5] FIG. 10 is a cross-sectional view illustrating a fourth example of a semiconductor package according to an embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view illustrating a fifth example of a semiconductor package according to an embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view illustrating a sixth example of a semiconductor package according to an embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view illustrating a seventh example of a semiconductor package according to an embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view illustrating an eighth example of a semiconductor package according to an embodiment of the present invention. [Figure 10]FIG. 13 is a cross-sectional view illustrating a ninth example of a semiconductor package according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 13] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 21] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 22] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 23] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 24] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 25]10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 26] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of embodiments for carrying out the semiconductor package of the present invention will be described in detail with reference to the drawings.

[0015] Fig. 1 is a cross-sectional view illustrating a first example of a semiconductor package according to an embodiment of the present invention, and Fig. 2 is an enlarged view of region A in Fig. 1.

[0016] 1 and 2, a first chip 100 is provided. The first chip 100 is a wafer-level die made of a semiconductor such as silicon (Si). The top surface of the first chip 100 is an active surface. That is, the first chip 100 is provided in a face-up form.

[0017] The first chip 100 includes a first semiconductor substrate 110 , a first circuit layer 120 , and chip vias 128 .

[0018] A first semiconductor substrate 110 is provided. The first semiconductor substrate 110 includes a semiconductor material. For example, the first semiconductor substrate 110 is a silicon (Si) single crystal substrate. The first semiconductor substrate 110 has an upper surface and a lower surface facing each other. The upper surface of the first semiconductor substrate 110 is the front surface of the first semiconductor substrate 110, and the lower surface of the first semiconductor substrate 110 is the back surface of the first semiconductor substrate 110. Here, the front surface of the first semiconductor substrate 110 is defined as one surface of the first semiconductor substrate 110 on which integrated devices are formed or mounted, or on which wiring, pads, etc. are formed, and the back surface of the first semiconductor substrate 110 is defined as the opposite surface opposite the front surface.

[0019] The first chip 100 has a first integrated device provided on an upper surface of a first semiconductor substrate 110. The first integrated device includes a photonic integrated circuit (PIC).

[0020] The first semiconductor substrate 110 has a first region R1 and a second region R2 that are horizontally spaced apart from each other. The first region R1 is a region where a second chip 200 (described later) is mounted. The second region R2 is a region where a support block 300 (described later) is disposed. In other words, the first region R1 is a region where the first chip 100 receives electrical signals from the second chip 200, and the second region R2 is a region where the first chip 100 receives optical signals from the outside.

[0021] The first semiconductor substrate 110 further includes a sensor unit 112. The sensor unit 112 is disposed on the second region R2. The sensor unit 112 is exposed on the top surface of the first semiconductor substrate 110. The sensor unit 112 receives light and converts it into an electrical signal.

[0022] The first chip 100 has a first circuit layer 120 provided on an upper surface of a first semiconductor substrate 110. The first circuit layer 120 includes a first insulating layer 122 and a first device wiring portion .

[0023] The top surface of the first semiconductor substrate 110 is covered with a first insulating film 122. The first insulating film 122 covers the first integrated element and the sensor unit 112 formed on the first semiconductor substrate 110. That is, the first integrated element and the sensor unit 112 are not exposed by the first insulating film 122. The first insulating film 122 includes an oxide, nitride, or oxynitride of a material that constitutes the first semiconductor substrate 110. The first insulating film 122 includes, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0024] A first element wiring portion 124 connected to the first integrated element is provided within the first insulating layer 122. The first element wiring portion 124 is disposed on the first region R1. The first element wiring portion 124 includes a wiring pattern embedded in the first insulating layer 122. For example, the wiring pattern includes a redistribution pattern for horizontal wiring and a via pattern for vertical connection. The first element wiring portion 124 vertically penetrates the first insulating layer 122 and is connected to the first integrated element. The first element wiring portion 124 is located between the upper and lower surfaces of the first insulating layer 122. The first element wiring portion 124 includes, for example, copper (Cu) or tungsten (W).

[0025] A first chip pad 126 is provided on the top surface of the first insulating layer 122. The first chip pad 126 is disposed on the first region R1. The first chip pad 126 is exposed on the top surface of the first insulating layer 122. The first chip pad 126 protrudes above the top surface of the first insulating layer 122. Alternatively, the top surface of the first chip pad 126 may be coplanar with the top surface of the first insulating layer 122. The first chip pad 126 is connected to the first device wiring portion 124. The first chip pad 126 includes, for example, copper (Cu) or tungsten (W).

[0026] The first chip 100 further includes chip vias 128 that vertically penetrate the first semiconductor substrate 110 and are connected to the first device wiring portion 124 or the first integrated device. The chip vias 128 are disposed on the first region R1. The chip vias 128 are patterns for vertical wiring. The chip vias 128 vertically penetrate the first semiconductor substrate 110 and are connected to a lower surface of a portion of the first device wiring portion 124. The chip vias 128 vertically penetrate the first semiconductor substrate 110 and are exposed on the lower surface of the first semiconductor substrate 110. The first semiconductor substrate 110 includes, for example, tungsten (W).

[0027] The second chip 200 is provided on the first chip 100. The second chip 200 is disposed on the first region R1. The second chip 200 is a wafer-level die made of a semiconductor such as silicon (Si). The bottom surface of the second chip 200 is the active surface. That is, the second chip 200 is provided face-down. The distance from the top surface of the first chip 100 to the top surface of the second chip 200 is 1 μm to 500 μm.

[0028] The second chip 200 includes a second semiconductor substrate 210 and a second circuit layer 220 .

[0029] A second semiconductor substrate 210 is provided. The second semiconductor substrate 210 includes a semiconductor material. For example, the second semiconductor substrate 210 is a silicon (Si) single crystal substrate. The second semiconductor substrate 210 has an upper surface and a lower surface facing each other. The lower surface of the second semiconductor substrate 210 is the front surface of the second semiconductor substrate 210, and the upper surface of the second semiconductor substrate 210 is the back surface of the second semiconductor substrate 210.

[0030] The second chip 200 has a second integrated device provided on the bottom surface of a second semiconductor substrate 210. The second integrated device includes an electronic integrated circuit (EIC).

[0031] The second chip 200 has a second circuit layer 220 provided on the bottom surface of the second semiconductor substrate 210. The second circuit layer 220 includes a second insulating layer 222 and a second device wiring portion 224.

[0032] The bottom surface of the second semiconductor substrate 210 is covered with a second insulating film 222. The second insulating film 222 covers the second integrated devices formed on the second semiconductor substrate 210. That is, the second integrated devices are not exposed by the second insulating film 222. The second insulating film 222 includes, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0033] A second element wiring portion 224 connected to the second integrated element is provided within the second insulating layer 222. The second element wiring portion 224 includes a wiring pattern embedded in the second insulating layer 222. For example, the wiring pattern includes a rewiring pattern for horizontal wiring and a via pattern for vertical connection. The second element wiring portion 224 vertically penetrates the second insulating layer 222 and is connected to the second integrated element. The second element wiring portion 224 is located between the upper and lower surfaces of the second insulating layer 222. The second element wiring portion 224 includes, for example, copper (Cu) or tungsten (W).

[0034] A second chip pad 226 is provided on the lower surface of the second insulating layer 222. The second chip pad 226 is exposed on the lower surface of the second insulating layer 222. The second chip pad 226 protrudes above the lower surface of the second insulating layer 222. Alternatively, the lower surface of the second chip pad 226 may be coplanar with the lower surface of the second insulating layer 222. The second chip pad 226 is connected to the second device wiring portion 224. The second chip pad 226 includes, for example, copper (Cu) or tungsten (W).

[0035] The second chip 200 is mounted on the first chip 100 using a flip-chip method. For example, the second chip 200 is disposed on the first circuit layer 120 of the first chip 100 in the first region R1. The second circuit layer 220 of the second chip 200 faces the top surface of the first chip 100. The second chip pads 226 of the second chip 200 are aligned perpendicular to the first chip pads 126 of the first chip 100. First connecting terminals 230 are provided between the first chip pads 126 and the second chip pads 226. The first connecting terminals 230 are connected to the top surface of the first chip pads 126 and the bottom surface of the second chip pads 226. The second chip 200 is electrically connected to the first chip 100 through the first connecting terminals 230.

[0036] A first underfill layer 240 is provided between the first chip 100 and the second chip 200. The first underfill layer 240 fills the space between the first chip 100 and the second chip 200 and surrounds the first connecting terminals 230.

[0037] A support block 300 is provided on the first chip 100. The support block 300 is disposed on the second region R2. The support block 300 is disposed horizontally spaced apart from the second chip 200. The support block 300 is positioned above the sensor unit 112. The support block 300 covers the entire sensor unit 112. The thickness T1 of the support block 300 is 1 μm to 500 μm. The top surface of the support block 300 is located at the same level as the top surface of the second chip 200. The support block 300 transmits light to be received by the first chip 100. The support block 300 includes silicon (Si), more specifically, bulk silicon (bulk Si). However, the present invention is not limited thereto. The support block 300 may be formed of various materials depending on the light to be received by the first chip 100. For example, the support block 300 transmits light having a wavelength of 700 nm to 1500 nm.

[0038] The support block 300 has a third insulating film (hereinafter referred to as a “second insulating film” in the claims) 310 provided on the lower surface of the support block 300 .

[0039] The third insulating film 310 covers the lower surface of the support block 300. The thickness T2 of the third insulating film 310 is 1 nm to 100 nm. The third insulating film 310 includes an oxide, nitride, or oxynitride of the material forming the support block 300. The third insulating film 310 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). For example, the third insulating film 310 is a layer formed on the lower surface of the support block 300 by performing an oxidation process, a nitridation process, or an oxynitridation process. Alternatively, the third insulating film 310 is a layer formed by naturally oxidizing, nitriding, or oxynitriding the lower surface or lower portion of the support block 300. The third insulating film 310 includes the same material as the first insulating film 122. Alternatively, the third insulating film 310 and the first insulating film 122 include an oxide, nitride, or oxynitride of the same material, and the third insulating film 310 and the first insulating film 122 include different materials.

[0040] In one embodiment, the third insulating film 310 is formed of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), and the remaining portion of the support block 300 is formed of silicon (Si). Although FIG. 2 merely illustrates that the third insulating film 310 contains oxygen or nitrogen, the concentration of oxygen or nitrogen in the third insulating film 310 is not limited. For example, the concentration of oxygen or nitrogen in the third insulating film 310 is uniform.

[0041] According to another embodiment, the concentration of oxygen or nitrogen in the third insulating layer 310 gradually decreases from the bottom surface of the support block 300 toward the inside of the support block 300 .

[0042] 1 and 2, the support block 300 is disposed on the first chip 100 in the second region R2. The bottom surface of the support block 300 contacts the top surface of the first chip 100. More specifically, the bottom surface of the third insulating film 310 of the support block 300 contacts the top surface of the first insulating film 122 of the first chip 100.

[0043] The first insulating film 122 of the first chip 100 and the third insulating film 310 of the support block 300 are bonded at the interface between the first chip 100 and the support block 300. At this time, the first insulating film 122 and the third insulating film 310 form a hybrid bonding of oxide, nitride, or oxynitride. In this specification, hybrid bonding refers to bonding in which two components containing the same material are fused at their interface. For example, the bonded first insulating film 122 and the third insulating film 310 have a continuous structure, and the interface between the first insulating film 122 and the third insulating film 310 is visually invisible. For example, the first insulating film 122 and the third insulating film 310 are made of the same material (e.g., silicon oxide (SiO)), and there is no interface between the first insulating film 122 and the third insulating film 310. That is, the first insulating film 122 and the third insulating film 310 are provided as a single component. For example, the first insulating film 122 and the third insulating film 310 are combined to form an integrated film.

[0044] According to one embodiment of the present invention, a third insulating film 310 is provided under the support block 300 by oxidizing or nitriding a portion of the light-transmitting layer, and the third insulating film 310 is integrally coupled to the first insulating film 122. Therefore, the support block 300 is firmly attached or coupled to the first chip 100, thereby providing a semiconductor package with improved structural stability. In addition, the number of material layers through which light passes along path L of light passing through the light-transmitting layer and incident on the sensor unit 112 of the first chip 100 is reduced. Furthermore, because the interior of the support block 300, i.e., the light-transmitting layer, is formed of a single material layer, the material has high transmittance for light to be received by the first chip 100, resulting in less light loss. In other words, a semiconductor package with improved optical characteristics can be provided.

[0045] Continuing with reference to FIG. 1, a first molding film 400 is provided on the first chip 100. The first molding film 400 surrounds the second chip 200 and the support block 300 on the first chip 100. The second chip 200 and the support block 300 are exposed on the top surface of the first molding film 400. The top surfaces of the second chip 200 and the support block 300 are coplanar with the top surface of the first molding film 400. The first molding film 400 includes an insulating material. For example, the first molding film 400 includes an insulating polymer material such as epoxy molding compound (EMC).

[0046] A microlens layer 500 is provided on the first molding film 400. The microlens layer 500 covers both the first region R1 and the second region R2. More specifically, the microlens layer 500 covers the top surface of the second chip 200, the top surface of the first molding film 400, and the top surface of the support block 300. The microlens layer 500 has microlenses (ML) formed on the top surface of the microlens layer 500. For example, as shown in FIG. 1, the microlenses ML are provided in a recessed shape on the top surface of the microlens layer 500. The microlenses ML have a spherical shape with a bottom surface that bulges upward. Alternatively, the microlenses ML may have a spherical lens shape that protrudes upward from the top surface of the microlens layer 500. Alternatively, the microlenses ML may be provided in various shapes on the microlens layer 500 as needed. The microlenses ML are located above the sensor unit 112 in the second region R2. The microlens layer 500 transmits light that the first chip 100 is intended to receive. The microlens layer 500 may be made of silicon (Si), glass, or various other transparent materials. However, the present invention is not limited thereto. The microlens layer 500 may be made of various materials depending on the type of light that the first chip 100 is intended to receive. For example, the microlens layer 500 transmits light having a wavelength of 700 nm to 1500 nm.

[0047] The microlens layer 500 is bonded onto the first molding film 400. The microlens layer 500 is bonded to the top surface of the first molding film 400, the top surface of the second chip 200, and the top surface of the support block 300 using a first adhesive layer 510. The first adhesive layer 510 is interposed between the first molding film 400, the second chip 200, and the support block 300 and the microlens layer 500. The first adhesive layer 510 includes a transparent material to transmit light incident through the microlenses ML of the microlens layer 500 to the sensor unit 112 of the first chip 100. The first adhesive layer 510 transmits light having a wavelength of 700 nm to 1500 nm. The refractive index of the first adhesive layer 510 is 3.15 to 3.85. The first adhesive layer 510 includes an optical glue.

[0048] According to an embodiment of the present invention, the microlens layer 500 is bonded using the first adhesive layer 510, which simplifies the manufacturing process of the semiconductor package. In addition, defects such as voids in the first adhesive layer 510 can be reduced. Therefore, the loss of light passing through the first adhesive layer 510 can be reduced. In other words, a semiconductor package with improved optical characteristics can be provided. This will be described in more detail later along with a method for manufacturing a semiconductor package.

[0049] In the following embodiments, for the sake of simplicity, detailed descriptions of technical features that overlap with those previously described with reference to Figures 1 and 2 will be omitted, and differences will be described in detail. The same reference numerals will be used for the same components as those in the semiconductor package according to the previously described embodiment of the present invention.

[0050] FIG. 3 is a cross-sectional view illustrating a second example of a semiconductor package according to an embodiment of the present invention.

[0051] 3, a first molding film 400 is provided on the first chip 100. The first molding film 400 surrounds the second chip 200 and the support block 300 on the first chip 100. The first molding film 400 covers the second chip 200. The support block 300 is exposed on the top surface of the first molding film 400. The top surfaces of the second chip 200 and the support block 300 are coplanar with the top surface of the first molding film 400. The top surface of the second chip 200 is not exposed on the top surface of the first molding film 400.

[0052] A microlens layer 500 is provided on the first molding film 400. The microlens layer 500 covers both the first region R1 and the second region R2. More specifically, the microlens layer 500 covers the top surface of the first molding film 400 and the top surface of the support block 300.

[0053] The microlens layer 500 is bonded onto the first molding film 400. The microlens layer 500 is bonded to the top surface of the first molding film 400 and the top surface of the support block 300 using a first adhesive layer 510. The first adhesive layer 510 is spaced apart from the top surface of the second chip 200 via the first molding film 400.

[0054] 4 and 5 are cross-sectional views illustrating a third and fourth example of a semiconductor package according to an embodiment of the present invention.

[0055] 4, the support block 300 does not have the third insulating layer 310. In other words, the support block 300 is a material layer formed of a single material. For example, the support block 300 includes bulk silicon.

[0056] The support block 300 is adhered onto the first chip 100. The support block 300 is adhered to the upper surface of the first insulating film 122 in the second region R2 using a second adhesive layer 320. The second adhesive layer 320 is interposed between the support block 300 and the first insulating film 122. The second adhesive layer 320 includes a transparent material to transmit light incident through the microlenses ML of the microlens layer 500 to the sensor unit 112 of the first chip 100. The second adhesive layer 320 transmits light having a wavelength of 700 nm to 1500 nm. The refractive index of the second adhesive layer 320 is 3.15 to 3.85. The second adhesive layer 320 includes an optical glue.

[0057] 5, the first insulating layer 122 is not provided on the second region R2. In other words, the first insulating layer 122 covers the first semiconductor substrate 110 on the first region R1 and exposes the top surface of the first semiconductor substrate 110 on the second region R2. The first insulating layer 122 does not cover the sensor portion 112.

[0058] The support block 300 is attached to the first chip 100 in the second region R2. The support block 300 is attached to the upper surface of the first semiconductor substrate 110 exposed in the second region R2. The support block 300 is attached to the sensor unit 112. The support block 300 is attached to the upper surface of the first semiconductor substrate 110 in the second region R2 using a second adhesive layer 320. The second adhesive layer 320 is interposed between the support block 300 and the first semiconductor substrate 110.

[0059] FIG. 6 is a cross-sectional view illustrating a fifth example of a semiconductor package according to an embodiment of the present invention.

[0060] 6, the second chip 200 includes chip bumps 260 connected to the second chip pads 226 instead of the first connecting terminals 230. The chip bumps 260 are connected to the bottom surfaces of the second chip pads 226. The chip bumps 260 are connected to the top surfaces of the first chip pads 126. The chip bumps 260 include solder bumps. According to another embodiment, conductive posts connecting the first chip pads 126 and the second chip pads 226 are provided instead of the chip bumps 260.

[0061] The first underfill layer 240 (see FIG. 1) is not provided between the first chip 100 and the second chip 200. The first molding film 400 surrounds the second chip 200 on the first chip 100 and extends between the first chip 100 and the second chip 200. The first molding film 400 fills the space between the first chip 100 and the second chip 200 and surrounds the chip bumps 260.

[0062] FIG. 7 is a cross-sectional view illustrating a sixth example of a semiconductor package according to an embodiment of the present invention.

[0063] Referring to FIG. 7, the second chip 200 is directly bonded to the first chip 100 .

[0064] The first chip 100 has a first chip pad 126. The top surface of the first chip pad 126 is coplanar with the top surface of the first insulating layer 122.

[0065] The second chip 200 has second chip pads 226. The bottom surface of the second chip pads 226 is coplanar with the bottom surface of the second insulating film 222.

[0066] The second chip 200 is mounted on the first chip 100. The bottom surface of the second chip 200 contacts the top surface of the first chip 100. The first chip pads 126 and the second chip pads 226 are bonded at the interface between the first chip 100 and the second chip 200. At this time, the first chip pads 126 and the second chip pads 226 form a hybrid bond with the metal. For example, the bonded first chip pads 126 and the second chip pads 226 have a continuous structure, and the interface between the first chip pads 126 and the second chip pads 226 is visually invisible. For example, the first chip pads 126 and the second chip pads 226 are made of the same material (e.g., copper (Cu)), so there is no interface between the first chip pads 126 and the second chip pads 226. That is, the first chip pads 126 and the second chip pads 226 are provided as a single component. For example, the first chip pad 126 and the second chip pad 226 are coupled together to form an integrated unit. At the interface between the first chip 100 and the second chip 200, the first insulating film 122 and the second insulating film 222 contact each other.

[0067] FIG. 8 is a cross-sectional view illustrating a seventh example of a semiconductor package according to an embodiment of the present invention. 8, the first chip 100 further includes a wiring layer 130 provided on an inactive surface of the first chip 100. The wiring layer 130 includes a fourth insulating film 132 and a third device wiring part 134.

[0068] The lower surface of the first semiconductor substrate 110 is covered with a fourth insulating film 132. The fourth insulating film 132 covers the lower surface of the first semiconductor substrate 110. The fourth insulating film 132 includes an oxide, nitride, or oxynitride of a material that constitutes the first semiconductor substrate 110. The fourth insulating film 132 includes, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0069] A third element wiring portion 134 connected to the chip via 128 is provided in the fourth insulating film 132. The third element wiring portion 134 includes a wiring pattern embedded in the fourth insulating film 132. For example, the wiring pattern includes a rewiring pattern for horizontal wiring and a via pattern for vertical connection. The third element wiring portion 134 vertically penetrates the fourth insulating film 132 and is connected to the chip via 128. The third element wiring portion 134 is located between the upper surface and the lower surface of the fourth insulating film 132. The third element wiring portion 134 includes, for example, copper (Cu) or tungsten (W).

[0070] A third chip pad 136 is provided on the lower surface of the fourth insulating layer 132. The third chip pad 136 is exposed on the lower surface of the fourth insulating layer 132. The third chip pad 136 protrudes above the lower surface of the fourth insulating layer 132. Alternatively, the lower surface of the third chip pad 136 may be coplanar with the lower surface of the fourth insulating layer 132. The third chip pad 136 is connected to the third device wiring portion 134. The third chip pad 136 includes, for example, copper (Cu) or tungsten (W).

[0071] Connection terminals 105 are provided on the bottom surface of the wiring layer 130. The connection terminals 105 are connected to third chip pads 136. The connection terminals 105 include solder balls or solder bumps, and the semiconductor package is provided in the form of a ball grid array (BGA), a fine ball-grid array (FBGA), or a land grid array (LGA) depending on the type and arrangement of the connection terminals 105.

[0072] FIG. 9 is a cross-sectional view illustrating an eighth example of a semiconductor package according to an embodiment of the present invention.

[0073] 9, a package substrate 1000 is provided. The package substrate 1000 includes a printed circuit board (PCB) having a signal pattern on its upper surface. Alternatively, the package substrate 1000 has a structure in which insulating layers and wiring layers are alternately stacked. The package substrate 1000 has pads disposed on its upper surface.

[0074] External terminals 1002 are disposed under the package substrate 1000. Specifically, the external terminals 1002 are disposed on terminal pads disposed on the bottom surface of the package substrate 1000. The external terminals 1002 include solder balls or solder bumps, and the semiconductor package is provided in the form of a ball grid array (BGA), a fine ball grid array (FBGA), or a land grid array (LGA) depending on the type and arrangement of the external terminals 1002.

[0075] An interposer substrate 1100 is provided on the package substrate 1000. The interposer substrate 1100 is a silicon (Si) interposer substrate. For example, the interposer substrate 1100 includes a silicon layer 1112, interposer vias 1114 vertically penetrating the silicon layer 1112, interposer lower pads 1116 provided on the lower surface of the silicon layer 1112 and connected to the interposer vias 1114, an interposer protective film 1118 provided on the lower surface of the silicon layer 1112 and surrounding the interposer lower pads 1116, and an interposer wiring portion provided on the upper surface of the silicon layer 1112.

[0076] The silicon layer 1112 is a silicon (Si) substrate. The interposer via 1114 completely penetrates vertically through the silicon layer 1112. That is, the upper surface of the interposer via 1114 is exposed on the upper surface of the silicon layer 1112, and the lower surface of the interposer via 1114 is exposed on the lower surface of the silicon layer 1112. The interposer via 1114 contains a metal such as copper (Cu).

[0077] Interposer bottom pads 1116 are disposed on the bottom surface of silicon layer 1112 and on the bottom surface of interposer vias 1114. Interposer bottom pads 1116 include a metal such as copper (Cu).

[0078] An interposer protective film 1118 is disposed on the lower surface of the silicon layer 1112. The interposer protective film 1118 exposes the lower surfaces of the interposer lower pads 1116. The interposer protective film 1118 includes a photoimageable polymer (PID). For example, the photosensitive polymer includes at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer.

[0079] The interposer wiring portion includes at least one substrate wiring layer. Each substrate wiring layer includes a first substrate insulating pattern 1122 and a first substrate wiring pattern 1124 within the first substrate insulating pattern 1122. The first substrate wiring pattern 1124 is electrically connected to the interposer via 1114. The first substrate insulating pattern 1122 includes an insulating polymer or a photosensitive polymer (PID). The first substrate wiring pattern 1124 is provided within the first substrate insulating pattern 1122. The first substrate wiring pattern 1124 has a damascene structure. For example, the first substrate wiring pattern 1124 has a head portion and a tail portion that are integrally connected to each other. The head portion is a wiring portion or pad portion that horizontally extends the wiring within the substrate wiring layer. The tail portion is a via portion that vertically connects the wiring within the substrate wiring layer. The first substrate wiring pattern 1124 includes a conductive material. For example, the first substrate wiring pattern 1124 includes copper (Cu).

[0080] The head portions of the first substrate wiring pattern 1124 of the substrate wiring layer arranged at the top end of the substrate wiring layers correspond to the interposer upper pads of the interposer substrate 1100. The substrate pads are substrate pads for mounting the first chip structure 10, the chip stick CS, and the fourth semiconductor chip 700.

[0081] Unlike the embodiment shown in FIG. 9, the interposer substrate 1100 may be a redistribution substrate. For example, the interposer substrate 1100 includes at least two or more substrate wiring layers. Each of the substrate wiring layers includes a substrate insulating pattern and a substrate wiring pattern within the substrate insulating pattern. The substrate wiring pattern of any one substrate wiring layer is electrically connected to the substrate wiring pattern of another adjacent substrate wiring layer. The following description will continue based on the embodiment shown in FIG. 9.

[0082] The interposer substrate 1100 is mounted on the upper surface of the package substrate 1000. Substrate terminals 1102 are disposed on the lower surface of the interposer substrate 1100. The substrate terminals 1102 are provided between the pads of the package substrate 1000 and the interposer lower pads 1116 of the interposer substrate 1100. The substrate terminals 1102 electrically connect the interposer substrate 1100 to the package substrate 1000. For example, the interposer substrate 1100 is mounted on the package substrate 1000 using a flip chip method. The substrate terminals 1102 include solder balls, solder bumps, etc.

[0083] A first underfill film 1104 is provided between the package substrate 1000 and the interposer substrate 1100. The first underfill film 1104 fills the space between the package substrate 1000 and the interposer substrate 1100 and surrounds the substrate terminals 1102.

[0084] The chip structure 10 is disposed on the interposer substrate 1100. The chip structure 10 is the semiconductor package described with reference to FIGS.

[0085] The chip structure 10 is mounted on an interposer substrate 1100. For example, the chip structure 10 is connected to a first substrate wiring pattern 1124 of the interposer substrate 1100 through a connecting terminal 105 of the first chip 100. The connecting terminal 105 is provided between the first substrate wiring pattern 1124 of the interposer substrate 1100 and the wiring layer 130 of the first chip 100.

[0086] Although not shown, an underfill film is provided between the interposer substrate 1100 and the chip structure 10. The underfill film fills the space between the interposer substrate 1100 and the first chip 100 and surrounds the connecting terminals 105.

[0087] The chip stick CS and the fourth semiconductor chip 700 are disposed on the interposer substrate 1100. The chip stick CS and the fourth semiconductor chip 700 are disposed horizontally spaced apart from the first chip structure 10.

[0088] The chip stick CS includes a base substrate, a third semiconductor chip 620 stacked on the base substrate, and a second molding film 630 surrounding the third semiconductor chip 620. The configuration of the chip stick CS will be described in detail below.

[0089] The base substrate is a base semiconductor chip 610. For example, the base substrate is a wafer-level semiconductor substrate made of a semiconductor such as silicon (Si). Hereinafter, the base semiconductor chip 610 refers to the same components as the base substrate, and the same reference numerals are used for the base semiconductor chip and the base substrate.

[0090] The base semiconductor chip 610 includes a base circuit layer 612 and a base through-electrode 614. The base circuit layer 612 is provided on the bottom surface of the base semiconductor chip 610. The base circuit layer 612 includes an integrated circuit. For example, the base circuit layer 612 is a memory circuit. That is, the base semiconductor chip 610 is a memory chip such as a DRAM, SRAM, MRAM, or flash memory. The base through-electrode 614 penetrates the base semiconductor chip 610 in a direction perpendicular to the top surface of the interposer substrate 1100. The base through-electrode 614 and the base circuit layer 612 are electrically connected. The bottom surface of the base semiconductor chip 610 is an active surface. Although FIG. 9 illustrates the base substrate including the base semiconductor chip 610, the present invention is not limited thereto. According to one embodiment of the present invention, the base substrate does not include the base semiconductor chip 610.

[0091] The base semiconductor chip 610 further includes a passivation film and a base connection terminal 616. The passivation film is disposed on the bottom surface of the base semiconductor chip 610 and covers the base circuit layer 612. The passivation film includes silicon nitride (SiN). The base connection terminal 616 is provided on the bottom surface of the base semiconductor chip 610. The base connection terminal 616 is electrically connected to an input / output circuit (i.e., a memory circuit), a power circuit, or a ground circuit of the base circuit layer 612. The base connection terminal 616 is exposed from the passivation film.

[0092] The third semiconductor chip 620 is mounted on the base semiconductor chip 610. That is, the third semiconductor chip 620 forms a chip-on-wafer (COW) structure with the base semiconductor chip 610. The width of the third semiconductor chip 620 is smaller than the width of the base semiconductor chip 610.

[0093] The third semiconductor chip 620 includes a third circuit layer 622 and through-chip electrodes 624. The third circuit layer 622 includes a memory circuit. That is, the third semiconductor chip 620 is a memory chip such as DRAM, SRAM, MRAM, or flash memory. The third circuit layer 622 includes the same circuit as the base circuit layer 612, but the present invention is not limited thereto. The through-chip electrodes 624 penetrate the third semiconductor chip 620 in a direction perpendicular to the top surface of the interposer substrate 1100. The through-chip electrodes 624 are electrically connected to the third circuit layer 622. The bottom surface of the third semiconductor chip 620 is an active surface. First chip bumps 626 are provided on the bottom surface of the third semiconductor chip 620. The first chip bumps 626 electrically connect the base semiconductor chip 610 and the third semiconductor chip 620.

[0094] A plurality of third semiconductor chips 620 are provided. For example, a plurality of third semiconductor chips 620 are stacked on a base semiconductor chip 610. Four to thirty-two third semiconductor chips 620 are stacked. First chip bumps 626 are provided between the third semiconductor chips 620. At this time, the third semiconductor chip 620 arranged at the top does not include chip through electrodes 624. In addition, the thickness of the third semiconductor chip 620 arranged at the top is thicker than the thickness of the third semiconductor chip 620 arranged below it.

[0095] Although not shown, an adhesive layer is provided between the third semiconductor chips 620. The adhesive layer includes a non-conductive film (NCF). The adhesive layer is interposed between the first chip bumps 626 between the third semiconductor chips 620 to prevent electrical shorts from occurring between the first chip bumps 626.

[0096] A second molding film 630 is disposed on the top surface of the base semiconductor chip 610. The second molding film 630 covers the base semiconductor chip 610 and surrounds the third semiconductor chip 620. The top surface of the second molding film 630 is coplanar with the top surface of the uppermost third semiconductor chip 620, and the uppermost third semiconductor chip 620 is exposed through the second molding film 630. The second molding film 630 includes an insulating polymer material. For example, the second molding film 630 includes an epoxy molding compound (EMC).

[0097] The chip stick CS is mounted on the interposer substrate 1100. For example, the chip stick CS is connected to the first substrate wiring pattern 1124 of the interposer substrate 1100 through the base connecting terminal 616 of the base semiconductor chip 610. The base connecting terminal 616 is provided between the first substrate wiring pattern 1124 of the interposer substrate 1100 and the base circuit layer 612.

[0098] Although not shown, an underfill film is provided between the interposer substrate 1100 and the chip stack CS. The underfill film fills the space between the interposer substrate 1100 and the base semiconductor chip 610 and surrounds the base connection terminals 616.

[0099] A fourth semiconductor chip 700 is disposed on the interposer substrate 1100. The fourth semiconductor chip 700 is disposed spaced apart from the chip stick CS. The thickness of the fourth semiconductor chip 700 is substantially the same as the thickness of the chip stick CS. The fourth semiconductor chip 700 includes a semiconductor material such as silicon (Si). The fourth semiconductor chip 700 includes a fourth circuit layer 710. The fourth circuit layer 710 includes a logic circuit. That is, the fourth semiconductor chip 700 is a logic chip. For example, the fourth semiconductor chip 700 is a system on chip (SOC). A lower surface of the fourth semiconductor chip 700 is an active surface, and an upper surface of the fourth semiconductor chip 700 is an inactive surface.

[0100] Second chip bumps 702 are provided on the bottom surface of the fourth semiconductor chip 700. The second chip bumps 702 are electrically connected to an input / output circuit (i.e., logic circuit), a power circuit, or a ground circuit of a fourth circuit layer 710.

[0101] A fourth semiconductor chip 700 is mounted on the interposer substrate 1100. For example, the fourth semiconductor chip 700 is connected to the first substrate wiring pattern 1124 of the interposer substrate 1100 through the second chip bumps 702. The second chip bumps 702 are provided between the first substrate wiring pattern 1124 of the interposer substrate 1100 and the fourth circuit layer 710 of the fourth semiconductor chip 700.

[0102] Although not shown, an underfill film is provided between the interposer substrate 1100 and the fourth semiconductor chip 700. The underfill film fills the space between the interposer substrate 1100 and the fourth semiconductor chip 700 and surrounds the second chip bumps 702.

[0103] A third molding film 800 is provided on the interposer substrate 1100. The third molding film 800 covers the top surface of the interposer substrate 1100. The third molding film 800 surrounds the chip structure 10, the chip stick CS, and the fourth semiconductor chip 700. The third molding film 800 exposes the top surface of the first chip structure 10, the top surface of the chip stick CS, and the top surface of the fourth semiconductor chip 700. For example, the third molding film 800 includes an insulating material. For example, the third molding film 800 includes an epoxy molding compound (EMC).

[0104] FIG. 10 is a cross-sectional view illustrating a ninth example of a semiconductor package according to an embodiment of the present invention.

[0105] Although FIG. 9 shows the chip structure 10 mounted on the interposer substrate 1100, the present invention is not limited to this.

[0106] 10, the chip structure 10 is disposed on a package substrate 1000. The chip structure 10 is disposed horizontally spaced apart from an interposer substrate 1100. The chip structure 10 is mounted on the upper surface of the package substrate 1000. For example, the chip structure 10 is connected to a pad of the package substrate 1000 through a connection terminal 105 of the first chip 100. The connection terminal 105 is provided between the pad of the package substrate 1000 and the wiring layer 130 of the first chip 100. The connection terminal 105 electrically connects the chip structure 10 to the package substrate 1000. For example, the chip structure 10 is mounted on the package substrate 1000 using a flip chip method.

[0107] 11 to 19 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0108] Referring to FIG. 11, a first chip 100 is formed through a typical process. The first chip 100 is formed on a semiconductor wafer, for example, a first semiconductor substrate 110. For example, a first integrated device is formed on the top surface of the first semiconductor substrate 110. The first integrated device includes a photonic integrated circuit (PIC). A sensor unit 112 is formed on the top surface of the first semiconductor substrate 110 in the second region R2 of the first semiconductor substrate 110. The sensor unit 112 is exposed on the top surface of the first semiconductor substrate 110. A chip via 128 is formed on the top surface of the first semiconductor substrate 110 in the first region R1 of the first semiconductor substrate 110 by forming a hole in the top surface of the first semiconductor substrate 110 and filling the hole with a conductive material. An upper end of the chip via 128 is exposed on the top surface of the first semiconductor substrate 110. A lower end of the chip via 128 is located inside the first semiconductor substrate 110. A first circuit layer 120 is formed on the top surface of the first semiconductor substrate 110. For example, an insulating layer is formed to cover the upper surface of the first semiconductor substrate 110, and then the insulating layer is patterned to form the first insulating film 122. A conductive layer is formed on the first insulating film 122, and then the conductive layer is patterned to form the first element wiring part 124. The first insulating film 122 and the first element wiring part 124 are formed by repeatedly performing a process of depositing and patterning the insulating layer and a process of depositing and patterning the conductive layer.

[0109] 12, a second chip 200 is provided. The second chip 200 is substantially the same as or similar to the second chip 200 described with reference to FIGS.

[0110] The second chip 200 is mounted on the first chip 100. The second chip 200 is mounted on the first chip 100 using a flip chip method. First connecting terminals 230 are provided on the bottom surface of the second chip 200. The first connecting terminals 230 include solder balls or solder bumps. A first underfill layer 240 is provided on the bottom surface of the second chip 200, surrounding the first connecting terminals 230. For example, the first underfill layer 240 is a non-conductive adhesive or a non-conductive film. If the first underfill layer 240 is a non-conductive adhesive, it is formed by dispensing a liquid non-conductive adhesive onto the bottom surface of the second chip 200. If the first underfill layer 240 is a non-conductive film, it is formed by attaching the non-conductive film onto the bottom surface of the second chip 200. Thereafter, the second chip 200 is aligned so that the first connecting terminals 230 are positioned on the first chip pads 126 of the first chip 100, and then a reflow process is performed on the second chip 200.

[0111] According to another embodiment, as shown in FIG. 13, the second chip 200 is directly bonded onto the first chip 100. The second chip 200 is moved so that the bottom surface of the second chip 200 contacts the top surface of the first chip 100. The second chip pads 226 of the second chip 200 are aligned with the first chip pads 126 of the first chip 100. The second chip pads 226 and the first chip pads 126 contact each other. A heat treatment process is performed on the first chip 100 and the second chip 200. The second chip pads 226 and the first chip pads 126 are bonded together through the heat treatment process. For example, the second chip pads 226 and the first chip pads 126 are bonded together to form a single unit. The bonding between the second chip pads 226 and the first chip pads 126 may occur naturally. In detail, the second chip pad 226 and the first chip pad 126 are made of the same material (e.g., copper (Cu)), and are bonded to each other through a surface activation intermetallic hybrid bonding process at the interface between the second chip pad 226 and the first chip pad 126. The second chip pad 226 and the first chip pad 126 are bonded to each other through a heat treatment process. The following description will be continued based on the embodiment of FIG. 12.

[0112] 14, a support block 300 is formed. The support block 300 is a block formed of a single material. For example, the support block 300 includes bulk silicon (Bulk Si). A third insulating layer 310 is formed on the lower surface of the support block 300. For example, the third insulating layer 310 is formed by performing an oxidation process, a nitridation process, or an oxynitridation process on the lower surface of the support block 300. Alternatively, the third insulating layer 310 may be a layer formed by natural oxidation of the lower surface of the support block 300.

[0113] The support block 300 is disposed on the first chip 100. The support block 300 is disposed on the second region R2 of the first chip 100. The bottom surface of the support block 300, i.e., the bottom surface of the third insulating film 310, contacts the first insulating film 122. The third insulating film 310 and the first insulating film 122 are bonded to each other. A heat treatment process is performed on the third insulating film 310 and the first insulating film 122. The third insulating film 310 and the first insulating film 122 are bonded to each other through the heat treatment process. For example, the third insulating film 310 and the first insulating film 122 are bonded to each other to form a single unit. The bonding between the third insulating film 310 and the first insulating film 122 may occur naturally. In detail, the third insulating film 310 and the first insulating film 122 are made of the same material (for example, silicon oxide (SiO) or the like), and the third insulating film 310 and the first insulating film 122 are bonded to each other by material diffusion in oxide / nitride / oxynitride at the interface between the third insulating film 310 and the first insulating film 122 that contact each other. The third insulating film 310 and the first insulating film 122 are bonded to each other by a heat treatment process.

[0114] 15, a first molding layer 400 is formed. For example, the first molding layer 400 is formed by coating an insulating material on the first chip 100. The first molding layer 400 covers the second chip 200 and the support block 300.

[0115] 16, a grinding process is performed on the first molding film 400. A portion of the top of the first molding film 400 is removed. The grinding process is performed until the top surfaces of the second chip 200 and the support block 300 are exposed. The top surface of the first molding film 400 is coplanar with the top surfaces of the second chip 200 and the support block 300.

[0116] According to another embodiment, if the height of the support block 300 is higher than the height of the second chip 200, the grinding process is performed until the top surface of the support block 300 is exposed. At this time, the second chip 200 is embedded in the first molding film 400, and the second chip 200 is not exposed above the top surface of the first molding film 400. In this case, the semiconductor package described with reference to FIG. 3 is manufactured.

[0117] According to an embodiment of the present invention, the second chip 200 and the support block 300 are formed to have a thin thickness as needed. More specifically, after the second chip 200 is mounted on the first chip 100 and the support block 300 is bonded, a thinning process is performed together with the first molding film 400, thereby thinning the second chip 200 and the support block 300. Therefore, a miniaturized semiconductor package can be provided.

[0118] 17, a microlens layer 500 is provided. The microlens layer 500 is substantially the same as or similar to the microlens layer 500 described with reference to FIGS.

[0119] The microlens layer 500 is disposed on the first molding film 400. The microlens layer 500 is bonded to the upper surface of the first molding film 400. For example, a first adhesive layer 510 is provided on the lower surface of the microlens layer 500. The first adhesive layer 510 is coated or attached to the lower surface of the microlens layer 500 depending on the shape of the first adhesive layer 510. The microlens layer 500 is bonded to the upper surface of the first molding film 400, the upper surface of the second chip 200, and the upper surface of the support block 300 using the first adhesive layer 510.

[0120] According to an embodiment of the present invention, the first chip 100, the second chip 200, the support block 300, and the first molding film 400 are formed at a wafer level, and a thinning or grinding process is performed to form a flat coplanar top surface of the second chip 200, the support block 300, and the first molding film 400. The microlens layer 500 is also formed at a wafer level, and is bonded onto the second chip 200 and the support block 300 using a first adhesive layer 510. Therefore, defects such as voids in the first adhesive layer 510 during the bonding process of the microlens layer 500 can be reduced.

[0121] 18, a carrier substrate 900 is attached onto the microlens layer 500. The carrier substrate 900 is an insulating substrate including glass or polymer, or a conductive substrate including metal. Although not shown, an adhesive member is provided on one surface of the carrier substrate 900 to attach the microlens layer 500 to the carrier substrate 900. As an example, the adhesive member includes an adhesive tape.

[0122] The result of FIG. 17 is then flipped over so that the first chip 100 is positioned above the carrier substrate 900.

[0123] A grinding process is performed on the first chip 100. For example, the grinding process is performed on the top surface of the first semiconductor substrate 110 of the first chip 100. A portion of the top of the first semiconductor substrate 110 is removed. The grinding process is performed until the top surfaces of the chip vias 128 are exposed. The top surface of the first semiconductor substrate 110 is coplanar with the top surfaces of the chip vias 128.

[0124] 19, a wiring layer 130 is formed on a first semiconductor substrate 110. For example, an insulating layer covering an upper surface of the first semiconductor substrate 110 is formed, and then the insulating layer is patterned to form a fourth insulating layer 132. A conductive layer is formed on the fourth insulating layer 132, and then the conductive layer is patterned to form a third element wiring portion 134. The fourth insulating layer 132 and the third element wiring portion 134 are formed by repeatedly performing a deposition and patterning process of an insulating layer and a deposition and patterning process of a conductive layer. Then, the fourth insulating layer 132 is patterned to form a hole exposing the third element wiring portion 134, and then a third chip pad 136 connected to the third element wiring portion 134 is formed on the fourth insulating layer 132.

[0125] The connection terminals 105 are provided on the third chip pads 136. The connection terminals 105 are connected to the top surfaces of the third chip pads 136.

[0126] The carrier substrate 900 is then removed.

[0127] A cutting process is performed along the sawing lines SL to separate the semiconductor packages from one another.

[0128] 20 to 26 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention.

[0129] 20, a microlens layer 500 is provided. The microlens layer 500 is substantially the same as or similar to the microlens layer 500 described with reference to FIGS. 1 to 9. Microlenses ML are provided on the lower surface of the microlens layer 500.

[0130] A first adhesive layer 510 is provided on the upper surface of the microlens layer 500. The first adhesive layer 510 is coated or attached to the upper surface of the microlens layer 500 depending on the shape of the first adhesive layer 510.

[0131] 21, the second chip 200 and the support block 300 are bonded onto the microlens layer 500. The second chip 200 and the support block 300 are bonded to the upper surface of the microlens layer 500 using a first adhesive layer 510.

[0132] The second chip 200 is arranged face up, for example, with the second chip pads 226 of the second chip 200 facing upward.

[0133] Chip bumps 260 are formed on the second chip pads 226 of the second chip 200. The chip bumps 260 include solder bumps. In another embodiment, conductive posts connecting the first chip pads 126 and the second chip pads 226 are provided instead of the chip bumps 260.

[0134] 22, a first molding layer 400 is formed. For example, the first molding layer 400 is formed by coating an insulating material on the microlens layer 500. The first molding layer 400 covers the second chip 200 and the support block 300.

[0135] 23, a grinding process is performed on the first molding film 400. A portion of the top of the first molding film 400 is removed. The grinding process is performed until the top surfaces of the chip bumps 260 and the support block 300 are exposed. The top surface of the first molding film 400 is coplanar with the top surfaces of the chip bumps 260 and the support block 300.

[0136] 24, a third insulating film 310 is formed on the upper surface of the support block 300. For example, after the grinding process, an oxidation process, a nitridation process, or an oxynitridation process is performed on the exposed upper surface of the support block 300 to form the third insulating film 310. Alternatively, the third insulating film 310 may be a layer formed by natural oxidation of the upper surface of the support block 300.

[0137] 25, a first chip 100 is formed by performing a conventional process. The first chip 100 is formed on a semiconductor wafer. The process for forming the first chip 100 is substantially the same as that described with reference to FIG. 11.

[0138] The first chip 100 is disposed on the first molding film 400. The first chip 100 is bonded to the second chip 200 and the support block 300. The bonding of the first chip 100 will be described in more detail below.

[0139] The first chip 100 is directly bonded onto the second chip 200. The semiconductor wafer is moved so that the bottom surface of the first chip 100 contacts the top surface of the second chip 200. The first chip pads 126 of the first chip 100 are aligned with the second chip pads 226 of the second chip 200. The first chip pads 126 and the second chip pads 226 contact each other. A heat treatment process is performed on the first chip 100 and the second chip 200. The first chip pads 126 and the second chip pads 226 are bonded together through the heat treatment process. For example, the first chip pads 126 and the second chip pads 226 are bonded together to form a single unit. The bonding between the first chip pads 126 and the second chip pads 226 may occur naturally. In detail, the first chip pad 126 and the second chip pad 226 are made of the same material (e.g., copper (Cu)), and are bonded to each other at their interface by a surface activation intermetallic hybrid bonding process. The first chip pad 126 and the second chip pad 226 are then bonded to each other by a heat treatment process.

[0140] The bottom surface of the first chip 100, i.e., the bottom surface of the first insulating film 122, contacts the third insulating film 310 of the support block 300. The third insulating film 310 and the first insulating film 122 are bonded to each other. A heat treatment process is performed on the third insulating film 310 and the first insulating film 122. The third insulating film 310 and the first insulating film 122 are bonded to each other through the heat treatment process. For example, the third insulating film 310 and the first insulating film 122 are bonded to each other to form a single unit. The bonding between the third insulating film 310 and the first insulating film 122 may occur naturally. In particular, the third insulating film 310 and the first insulating film 122 are made of the same material (e.g., silicon oxide (SiO)), and the third insulating film 310 and the first insulating film 122 are bonded to each other at the interface between the third insulating film 310 and the first insulating film 122 by material diffusion within oxide / nitride / oxynitride. The third insulating film 310 and the first insulating film 122 are bonded together by the heat treatment process.

[0141] The process of bonding the first chip pad 126 and the second chip pad 226 and the process of bonding the third insulating film 310 and the first insulating film 122 are performed simultaneously.

[0142] 26, a grinding process is performed on the first chip 100. For example, a grinding process is performed on the top surface of the first semiconductor substrate 110 of the first chip 100. A portion of the top of the first semiconductor substrate 110 is removed. The grinding process is performed until the top surfaces of the chip vias 128 are exposed. The top surface of the first semiconductor substrate 110 is coplanar with the top surfaces of the chip vias 128.

[0143] The wiring layer 130 is formed on the first semiconductor substrate 110. For example, an insulating layer covering the upper surface of the first semiconductor substrate 110 is formed, and then the insulating layer is patterned to form the fourth insulating layer 132. A conductive layer is formed on the fourth insulating layer 132, and then the conductive layer is patterned to form the third element wiring portion 134. The fourth insulating layer 132 and the third element wiring portion 134 are formed by repeatedly performing a deposition and patterning process of the insulating layer and a deposition and patterning process of the conductive layer. Then, the fourth insulating layer 132 is patterned to form a hole exposing the third element wiring portion 134, and then a third chip pad 136 connected to the third element wiring portion 134 is formed on the fourth insulating layer 132.

[0144] The connection terminals 105 are provided on the third chip pads 136. The connection terminals 105 are connected to the top surfaces of the third chip pads 136.

[0145] Thereafter, a cutting process is performed along the sawing lines SL to separate the semiconductor packages from one another.

[0146] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0147] 10 Chip structure 100, 200 1st and 2nd chips 105 Connecting terminal 110, 210 First and second semiconductor substrates 112 Sensor section 120, 220, 622, 710 1st to 4th circuit layer 122, 222, 310, 132 First to fourth insulating films 124, 224, 134 First to third element wiring sections 126, 226, 136 1st to 3rd chip pads 128 chip vias 130 wiring layer 230 1st connection terminal 240 First underfill layer 260 Chip Bumps 300 support blocks 400, 630, 800 1st to 3rd molding films 500 microlens layers 510, 320 1st, 2nd (transparent) adhesive layer 610-based semiconductor chip 612 Base Circuit Layer 614 Base through electrode 616 Base connecting terminal 620, 700 3rd and 4th semiconductor chips 624 Chip through-electrode 626, 702 1st and 2nd chip bumps 900 Carrier Substrate 1000 package substrate 1002 External terminal 1100 Interposer Board 1102 PCB terminal 1104 First underfill film 1112 Silicon layer 1114 Interposer 1116 Interposer bottom pad 1118 Interposer protective film 1122 First board insulation pattern 1124 First board wiring pattern CS Chipstick ML Micro Lens

Claims

1. A substrate; a first chip mounted on the substrate and having a photonic integrated circuit (PIC); a second chip disposed on the first chip and having an electronic integrated circuit (EIC); a support block disposed on the first chip and horizontally spaced apart from the second chip and bonded to an upper surface of the first chip; a molding film on the first chip that surrounds the second chip and the support block and exposes an upper surface of the support block; a microlens layer on the molding film, the microlens layer covering the molding film, the first chip, and the support block; The semiconductor package, wherein the microlens layer is attached to the upper surface of the molding film and the upper surface of the support block using a first transparent adhesive layer provided on a lower surface of the microlens layer.

2. The semiconductor package of claim 1 , wherein the first transparent adhesive layer comprises an optical glue.

3. the molding film exposes a top surface of the second chip; The semiconductor package of claim 1 , wherein the microlens layer is attached to the top surface of the second chip using the first transparent adhesive layer.

4. the molding film covers a top surface of the second chip; The semiconductor package of claim 1 , wherein the microlens layer is attached to an upper surface of the molding film above the second chip.

5. 2. The semiconductor package of claim 1, wherein a lower surface of the support block directly contacts an upper surface of the first chip.

6. the first chip has a first insulating film provided on an upper surface of the first chip; the support block has a second insulating layer provided on a lower surface of the support block; the first insulating film and the second insulating film are in contact with each other, 6. The semiconductor package according to claim 5, wherein the first insulating film and the second insulating film are formed of the same material and are integrally configured.

7. 7. The semiconductor package of claim 6, wherein the first insulating film and the second insulating film include an oxide, a nitride, or an oxynitride of a material that constitutes the support block.

8. 2. The semiconductor package of claim 1, wherein the support block is attached to the top surface of the first chip using a second transparent adhesive layer provided on a bottom surface of the support block.

9. providing a first chip having a photonic integrated circuit (PIC) disposed on an active surface thereof, the first chip having a first chip pad and a sensor portion; mounting a second chip having an electronic integrated circuit (EIC) on the first chip so as to be connected to the first chip pads; bonding a support block positioned on the sensor portion onto the first chip; forming a molding layer on the first chip to cover the second chip and the support block; performing a thinning process on the molding film to expose an upper surface of the support block; and adhering a microlens layer to the upper surface of the molding film and the upper surface of the support block using a transparent adhesive layer.

10. providing a microlens layer; bonding a second chip having an electronic integrated circuit (EIC) and a support block to one surface of the microlens layer using a transparent adhesive layer; forming a molding layer on the microlens layer to cover the second chip and the support block; performing a thinning process on the molding film to expose top surfaces of the connection terminals of the second chip and the support block; bonding a first chip having a photonic integrated circuit (PIC) and a chip pad and a sensor portion disposed on an active surface thereof on the molding film, the second chip, and the support block; The chip pad is connected to an upper surface of the connection terminal, The method for manufacturing a semiconductor package, wherein the sensor unit is disposed on the support block.

Images