Power supply control device

Abstract

To reduce the size of a monitor circuit for detecting excess and deficiency of charging of a boot capacitor.SOLUTION: Through on / off control of the high-side and low-side transistors, a switch voltage (Vsw) generated at a connection node between the high-side and low-side transistors is rectified and smoothed using a coil and an output capacitor, thereby obtaining an output voltage (Vout) from an input voltage (Vin). A boot voltage (Vboot) is applied to a boot terminal connected to a connection node between the high-side and low-side transistors via a boot capacitor. The monitor circuit (17) sets the level of the boot voltage with respect to the switch voltage as a voltage to be monitored, and observes the voltage to be monitored only during the ON period of the low-side transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] In a switching power supply device having an output stage circuit configured by connecting a high-side transistor and a low-side transistor in series, a high-side driver that drives the gate of the high-side transistor, and a low-side driver that drives the gate of the low-side transistor, a boost circuit that may also be called a bootstrap circuit is used to generate a power supply voltage on the high potential side of the high-side driver (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-123643

[0004] [overview] There is room for improvement in the configuration of a power supply control device related to this type of booster circuit.

[0005] A power supply control device according to one aspect of the present disclosure is a power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage by DC / DC conversion, wherein the switching power supply device is provided with an output stage circuit having a high-side transistor provided between an application terminal of the input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal having a ground potential lower than the input voltage, and the output voltage is generated by rectifying and smoothing a switch voltage generated at the switch terminal through on / off control of the high-side transistor and the low-side transistor, and the current control device includes a high-side driver configured to drive a gate of the high-side transistor, a low-side driver configured to drive a gate of the low-side transistor, and a feedback voltage corresponding to the output voltage. the high-side transistor is turned off until a low voltage release signal indicating that the monitored voltage has reached a threshold voltage is supplied from the monitor circuit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating the overall configuration of a switching power supply device according to a first embodiment of the present disclosure. [Figure 2]FIG. 2 is a diagram showing the relationship between several signals within the power supply control device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing the relationship between the monitored voltage and the protection signal according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is an explanatory diagram of the normal mode and the sleep mode according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating an example of the internal configuration of a PWM circuit according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing how a control signal is generated by pulse width modulation according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a timing chart of an example EX1_1 belonging to the first embodiment of the present disclosure, near the start of switching control. [Figure 8] FIG. 8 is another timing chart around the start of switching control according to Example EX1_1 belonging to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a configuration diagram of a backflow detection circuit according to Example EX1_2 belonging to the first embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing how the current threshold of the backflow detection circuit is variably set according to Example EX1_2 belonging to the first embodiment of the present disclosure. [Figure 11] FIG. 11 is a timing chart of an example EX1_2 belonging to the first embodiment of the present disclosure, near the start of switching control. [Figure 12] FIG. 12 is a state transition diagram of a logic circuit according to Example EX1_3 belonging to the first embodiment of the present disclosure. [Figure 13] FIG. 13 is a state transition diagram of a logic circuit according to Example EX1_4 belonging to the first embodiment of the present disclosure. [Figure 14] FIG. 14 relates to Example EX1_4 belonging to the first embodiment of the present disclosure, and is an operation sequence diagram relating to the resumption of switching control (a case in which charging control of the boot capacitor is performed before resumption of switching control). [Figure 15] FIG. 15 is an operation sequence diagram relating to Example EX1_4 belonging to the first embodiment of the present disclosure and relating to the resumption of switching control (a case in which charging control of the boot capacitor is not performed before resumption of switching control). [Figure 16] FIG. 16 is an overall configuration diagram of a switching power supply device according to Example EX1_5 belonging to the first embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing a configuration of a monitor circuit according to Example EX2_1 belonging to the second embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram showing the configuration of the level shifter shown in FIG. [Figure 19] FIG. 19 is a diagram showing a configuration of a monitor circuit according to Example EX2_2 belonging to the second embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram showing a configuration of a monitor circuit according to Example EX2_3 belonging to the second embodiment of the present disclosure. [Figure 21] FIG. 21 is a diagram showing the relationship between the detection signal output from the comparator and the protection signal according to Example EX2_3 belonging to the second embodiment of the present disclosure. [Figure 22] FIG. 22 is a timing chart of an example EX2_3 belonging to the second embodiment of the present disclosure, near the start of switching control. [Figure 23] FIG. 23 is another timing chart around the start of switching control according to Example EX2_3 belonging to the second embodiment of the present disclosure. [Figure 24] FIG. 24 is yet another timing chart around the start of switching control according to Example EX2_3 belonging to the second embodiment of the present disclosure. [Figure 25] FIG. 25 relates to Example EX2_4 belonging to the second embodiment of the present disclosure and is a diagram showing the configuration of a monitor circuit. [Figure 26]FIG. 26 is an operation sequence diagram relating to Example EX2_4 belonging to the second embodiment of the present disclosure and relating to the resumption of switching control (a case in which charging control of the boot capacitor is performed before resumption of switching control). [Figure 27] FIG. 27 relates to Example EX2_4 belonging to the second embodiment of the present disclosure, and is an operation sequence diagram relating to the resumption of switching control (a case in which charging control of the boot capacitor is not performed before resumption of switching control).

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the boot voltage referred to by "Vboot" (see FIG. 1), described below, may be written as boot voltage Vboot or abbreviated as voltage Vboot, but they all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having an electric potential of 0 V (zero volts) as a reference, or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to the level (height) of the electric potential, and for any signal or voltage of interest, a high level has a higher electric potential than a low level. For any signal of interest, when the signal of interest has a high level, the inverted signal of the signal of interest has a low level, and when the signal of interest has a low level, the inverted signal of the signal of interest has a high level. For any signal or voltage of interest, a transition from a low level to a high level is sometimes referred to as a rising edge, and a transition from a high level to a low level is sometimes referred to as a falling edge.

[0010] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source. Hereinafter, the on and off states of any transistor may be simply referred to as on and off. Furthermore, for any transistor, the period in which the transistor is in the on state is referred to as the on period, and the period in which the transistor is in the off state is referred to as the off period.

[0011] For any signal having a high or low signal level, the period during which the signal level is high is called a high-level period, and the period during which the signal level is low is called a low-level period. The same applies to any voltage having a high or low voltage level.

[0012] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0013] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0014] <<First Embodiment>> The first embodiment of the present disclosure will be described. FIG. 1 is an overall configuration diagram of a switching power supply device 1 according to the first embodiment. The switching power supply device 1 includes a power supply control device 10 that controls the operation of the switching power supply device 1, and a group of discrete components provided outside the power supply control device 1.The group of discrete components includes a coil L1, an output capacitor Cout, a boot capacitor Cboot, and feedback resistors R1 and R2. The switching power supply device 1 is configured as a step-down switching power supply device (DC / DC converter) that generates a desired output voltage Vout from an input voltage Vin supplied from the outside. An output voltage Vout is generated at the output terminal OUT. That is, the output terminal OUT is an application terminal of the output voltage Vout (a terminal to which the output voltage Vout is applied). The output voltage Vout is supplied to a load LD connected to the output terminal OUT.

[0015] Except for the transient state, the input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12V, the output voltage Vout can be stabilized at a desired target voltage Vtg (for example, 3.3V or 5V) less than 12V by adjusting the resistance values of the feedback resistors R1 and R2. The current supplied to the load LD via the output terminal OUT is referred to as a load current Iout. The load current Iout corresponds to the output current of the switching power supply device 1.

[0016] The power supply control device 10 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and multiple external terminals that are exposed to the outside of the power supply control device 10 from the housing. The power supply control device 10 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Each circuit and element provided in the power supply control device 10 can be included in the semiconductor chip. While FIG. 1 shows only an input terminal IN, a switch terminal SW, a ground terminal GND, a feedback terminal FB, and a boot terminal BOOT as some of the multiple external terminals provided in the power supply control device 10, other external terminals (such as a power good terminal and an enable terminal) may also be provided in the power supply control device 10. The number of external terminals and the type of housing of the power supply control device 10 are arbitrary.

[0017] The external configuration of the power supply control device 10 will now be described. An input voltage Vin is supplied to the input terminal IN from outside the power supply control device 10. A coil L1 is connected in series between the switch terminal SW and the output terminal OUT. That is, a first terminal of the coil L1 is connected to the switch terminal SW, and a second terminal of the coil L1 is connected to the output terminal OUT. The output terminal OUT is connected to ground via an output capacitor Cout. That is, a first terminal of the output capacitor Cout is connected to the output terminal OUT, and a second terminal of the output capacitor Cout is connected to ground. The output terminal OUT is also connected to a first terminal of a feedback resistor R1, a second terminal of the feedback resistor R1 is connected to a first terminal of a feedback resistor R2, and a second terminal of the feedback resistor R2 is connected to ground. The connection node between the feedback resistors R1 and R2 is connected to a feedback terminal FB. A first terminal and a second terminal of a load LD are connected to the output terminal OUT and ground, respectively. The load LD is an arbitrary load driven based on the output voltage Vout. The ground terminal GND is connected to ground. A first end of the boot capacitor Cboot is connected to the boot terminal BOOT, and a second end of the boot capacitor Cboot is connected to the switch terminal SW. The current flowing through the coil L1 is referred to as the coil current IL. The coil current IL flowing from the switch terminal SW through the coil L1 toward the output terminal OUT has positive polarity, and the coil current IL flowing from the output terminal OUT toward the switch terminal SW through the coil L1 has negative polarity.

[0018] The internal configuration of the power supply control device 10 will be described. The power supply control device 10 includes an output stage circuit MM and a control drive block for controlling and driving the output stage circuit MM. The control drive block in the power supply control device 10 includes a switching control circuit 11 having a PWM circuit 12 and a logic circuit 13, a high-side driver 14, a low-side driver 15, a backflow detection circuit 16, a monitor circuit 17, a light load detection comparator 18, a switching management circuit 19, and a diode Dboot.

[0019] The output stage circuit MM includes a high-side transistor MH and a low-side transistor ML. The transistors MH and ML are configured by N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). Of these, the transistor MH functions as an output transistor, and the transistor ML functions as a synchronous rectifier transistor. The transistor MH is located on a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and receives the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and therefore to ground). However, a current detection resistor may be inserted between the source of the transistor ML and the ground terminal GND.

[0020] The switching control circuit 11 controls the switching of the output stage circuit MM using drivers 14 and 15. The switching control of the output stage circuit MM involves switching the transistors MH and ML so that they are alternately turned on and off. The switching control of the output stage circuit MM causes a square-wave switch voltage Vsw to appear at the switch terminal SW. The coil L1 and output capacitor Cout form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switch voltage Vsw appearing at the switch terminal SW to generate the output voltage Vout. The feedback resistors R1 and R2 form a feedback voltage generating circuit that divides the output voltage Vout to generate a feedback voltage Vfb corresponding to the output voltage Vout. The feedback voltage Vfb is proportional to the output voltage Vout, and the feedback voltage Vfb also rises and falls as the output voltage Vout rises and falls. The feedback voltage Vfb is input to the feedback terminal FB.

[0021] A modification may be made in which the output voltage Vout itself is used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout. The feedback voltage generating circuit (R1, R2) may also be provided within the power supply control device 10. In this case, the feedback terminal FB is connected to the output terminal OUT.

[0022] Although not specifically shown, the power supply control device 10 is provided with an internal power supply circuit that generates one or more internal power supply voltages based on the input voltage Vin. Each circuit within the power supply control device 10 can be driven using the internal power supply voltage or the input voltage Vin as a drive voltage. The one or more internal power supply voltages include a power supply voltage VDD having a predetermined positive DC voltage value. The switching control circuit 11 is driven based on the power supply voltage VDD with respect to the ground potential. However, the power supply voltage VDD may also be supplied to the power supply control device 10 from a voltage source external to the power supply control device 10.

[0023] Gate signals GH and GL are supplied to the gates of the transistors MH and ML as drive signals, respectively, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is on, and when the gate signal GH is at a low level, the transistor MH is off. Similarly, when the gate signal GL is at a high level, the transistor ML is on, and when the gate signal GL is at a low level, the transistor ML is off.

[0024] Basically, the transistors MH and ML are alternately turned on and off, but both transistors MH and ML may be maintained in the off state. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a both-off state (Hi-Z state). In the output high state, the transistor MH is on and the transistor ML is off. In the output low state, the transistor MH is off and the transistor ML is on. In the both-off state, both transistors MH and ML are off. The transistors MH and ML are never on at the same time. In the switching control by the switching control circuit 11, alternately turning the transistors MH and ML on and off refers to the concept of both being in the off state, taking into account dead time, etc., between the transition between the output low state and the output high state. At least one of the transistors MH and ML may be provided external to the power supply control device 10. The entire output stage circuit MM may also be provided external to the power supply control device 10.

[0025] The switching control circuit 11 is connected to the feedback terminal FB and receives a feedback voltage Vfb. In cooperation with drivers 14 and 15, the switching control circuit 11 controls the on / off states of the transistors MH and ML by controlling the levels of gate signals GH and GL based on the feedback voltage Vfb, thereby generating a desired output voltage Vout at the output terminal OUT. The switching control circuit 11 adjusts the output duty of the output stage circuit MM using pulse-width modulation so that the feedback voltage Vfb matches the reference voltage Vref1. When "Vfb = Vref1" is established, the output voltage Vout matches the target voltage Vtg. The output duty represents the ratio of the period during which the output stage circuit MM is in the high output state to the sum of the periods during which the output stage circuit MM is in the high output state and the low output state. The reference voltage Vref1 has a predetermined positive DC voltage value. The power supply control device 10 is provided with a reference voltage generation circuit (not shown) that generates one or more reference voltages based on the input voltage Vin or the power supply voltage VDD. The reference voltage Vref1 and any other reference voltages described below are generated by a reference voltage generating circuit.

[0026] The switching control circuit 11 is provided with a PWM circuit 12 and a logic circuit 13. A feedback voltage Vfb and a reference voltage Vref1 are input to the PWM circuit 12. The PWM circuit 12 generates a control signal Spwm, which is a pulse width modulation signal, so that the feedback voltage Vfb matches the reference voltage Vref1 (in other words, so that the error between the feedback voltage Vfb and the reference voltage Vref1 approaches zero), and outputs the control signal Spwm to the logic circuit 13. During a period in which the switching control circuit 11 performs switching control, the logic circuit 13 outputs drive instruction signals INH and INL in accordance with the control signal Spwm. The drive instruction signal INH from the logic circuit 13 is supplied to a high-side driver 14. The drive instruction signal INL from the logic circuit 13 is supplied to a low-side driver 15.

[0027] The high-side driver 14 is connected to the boot line W_boot and the gate and source of the transistor MH. The boot line W_boot is connected to the boot terminal BOOT. The voltage applied to the boot line W_boot and the boot terminal BOOT is called the boot voltage Vboot. The high-side driver 14 drives the gate of the transistor MH by supplying a high-level or low-level gate signal GH to the gate of the transistor MH based on the source potential of the transistor MH (and therefore based on the potential of the switch voltage Vsw), thereby setting the state of the transistor MH on or off. The boot voltage Vboot and the switch voltage Vsw function as the high-potential side power supply voltage and the low-potential side power supply voltage of the high-side driver 14, respectively. The low-side driver 15 is connected to the application terminal of the power supply voltage VDD and the gate and source of the transistor ML. The low-side driver 15 drives the gate of the transistor ML by supplying a high-level or low-level gate signal GL to the gate of the transistor ML based on the source potential of the transistor ML (and therefore based on the ground potential), thereby setting the state of the transistor ML on or off.

[0028] Figure 2 shows the relationship between the signals Spwm, INH, INL, GH, and GL. The signals Spwm, INH, and INL are binary signals that have either a high level or a low level. For the signals Spwm, INH, and INL, the high level has the potential of the power supply voltage VDD, and the low level has the ground potential. The gate signals GH and GL also have a high level or a low level. The high level of the gate signal GH has the potential of the boot voltage Vboot, and the low level of the gate signal GH has the potential of the switch voltage Vsw. The high level of the gate signal GL has the potential of the power supply voltage VDD, and the low level of the gate signal GL has the ground potential.

[0029] When switching control is performed by the switching control circuit 11, the logic circuit 13 sets the drive instruction signal INH to a high level while setting the drive instruction signal INL to a low level during a high-level period of the control signal Spwm, and sets the drive instruction signal INH to a low level while setting the drive instruction signal INL to a high level during a low-level period of the control signal Spwm. The high-side driver 14 sets the transistor MH to an on state by supplying a high-level gate signal GH to the gate of the transistor MH during a high-level period of the drive instruction signal INH, and sets the transistor MH to an off state by supplying a low-level gate signal GH to the gate of the transistor MH during a low-level period of the drive instruction signal INH. The low-side driver 15 sets the transistor ML to an on state by supplying a high-level gate signal GL to the gate of the transistor ML during a high-level period of the drive instruction signal INL, and sets the transistor ML to an off state by supplying a low-level gate signal GL to the gate of the transistor ML during a low-level period of the drive instruction signal INL.

[0030] In practice, when the output stage circuit MM transitions from a low output state to a high output state, the logic circuit 13 adjusts the timing of the level changes of the drive instruction signals INH and INL so that the transition to the high output state occurs after a short dead time has elapsed between both OFF states. The same process occurs when the output stage circuit MM transitions from a high output state to a low output state, but for the sake of convenience and simplification, the existence of the dead time is ignored here. Strictly speaking, after the drive instruction signal INH switches from a low level to a high level, the gate signal GH switches from a low level to a high level over a period of time that depends on the driving capability of the high-side driver 14 and the input capacitance of the transistor GH. However, for the sake of simplicity, the existence of such a period is ignored and assumed to be zero. The same process occurs when the gate signal GH switches from a high level to a low level, and when the gate signal GL switches between a high level and a low level.

[0031] The backflow detection circuit 16 (see FIG. 1) detects the presence or absence of a backflow current while the transistor ML is on, and generates a backflow detection signal Srvs indicating the detection result. The backflow detection signal Srvs is supplied to the logic circuit 13. The backflow current is a current that flows from the output terminal OUT through the coil L1, switch terminal SW, and transistor ML to ground, and corresponds to the negative coil current IL. During the execution period of switching control, when a backflow current is detected, the logic circuit 13 switches the transistor ML from on to off to block the backflow current, thereby improving efficiency under light loads.

[0032] The monitor circuit 17 monitors the level of the boot voltage Vboot relative to the switch voltage Vsw, and outputs a protection signal S_UVLO indicating the monitoring result. The protection signal S_UVLO is a low voltage protection signal related to the boot voltage Vboot. The protection signal S_UVLO from the monitor circuit 17 is input to the logic circuit 13. Hereinafter, the level of the boot voltage Vboot relative to the switch voltage Vsw will be referred to as the monitored voltage Vmnt. Therefore, "Vmnt = Vboot - Vsw".

[0033] Fig. 3 shows the relationship between the monitored voltage Vmnt and the protection signal S_UVLO. The protection signal S_UVLO is a binary signal having a high level or a low level. The high-level protection signal S_UVLO has the potential of the power supply voltage VDD, and the low-level protection signal S_UVLO has the ground potential. In the monitor circuit 17, a threshold voltage Vth_UVLO and a hysteresis width ΔHYS each having a positive voltage value are set in advance. The monitor circuit 17 has a function of comparing the monitored voltage Vmnt with the threshold voltage Vth_UVLO. The monitor circuit 17 outputs a high-level protection signal S_UVLO during the period when "Vmnt < Vth_UVLO - ΔHYS" holds. The voltage (Vth_UVLO - ΔHYS) refers to a voltage that is lower than the threshold voltage Vth_UVLO by the hysteresis width ΔHYS. When the monitored voltage Vmnt increases from the state where the protection signal S_UVLO has a high level and the state where "Vmnt < Vth_UVLO" holds switches to the state where "Vth_UVLO < Vmnt" or "Vth_UVLO ≤ Vmnt" holds, the monitor circuit 17 switches the level of the protection signal S_UVLO from the high level to the low level. When the monitored voltage Vmnt decreases from the state where the protection signal S_UVLO has a low level and the state where "Vth_UVLO - ΔHYS < Vmnt" holds switches to the state where "Vmnt < Vth_UVLO - ΔHYS" or "Vmnt ≤ Vth_UVLO - ΔHYS" holds, the monitor circuit 17 switches the level of the protection signal S_UVLO from the low level to the high level. Thus, it is desirable to provide the monitor circuit 17 with hysteresis characteristics, but it is also possible to set the hysteresis width ΔHYS to zero. The logic circuit 13 is configured to perform switching control only during the period when the protection signal S_UVLO has a low level, and prohibits switching control during the high-level period of the protection signal S_UVLO.

[0034] The light-load detection comparator 18 (see FIG. 1) is a comparator for detecting a light-load state. A light-load state corresponds to a state in which the load current Iout is relatively small. The light-load detection comparator 18 compares the feedback voltage Vfb input to its non-inverting input terminal with the reference voltage Vref2 input to its inverting input terminal, and outputs a sleep signal SLP indicating the comparison result. This comparison has a hysteresis. Starting from a state in which the feedback voltage Vfb is lower than the reference voltage Vref2 and the sleep signal SLP is at a low level, the comparator 18 outputs a high-level sleep signal SLP when the feedback voltage Vfb becomes higher than the reference voltage Vref2. Thereafter, when the feedback voltage Vfb becomes lower than the voltage (Vref2-ΔHYS2), the comparator 18 switches the level of the sleep signal SLP from high to low. The voltage (Vref2-ΔHYS2) is lower than the reference voltage Vref2 by a positive hysteresis voltage ΔHYS2.

[0035] The voltage (Vref2-ΔHYS2) may be higher than the reference voltage Vref1. In this case, the output voltage Vout is stabilized at a predetermined target voltage Vtg when the feedback voltage Vfb matches the reference voltage Vref1, and therefore the sleep signal SLP goes high only when the output voltage Vout exceeds the target voltage Vtg by a certain amount. However, the reference voltage Vref1 and the voltage (Vref2-ΔHYS2) may also match.

[0036] The sleep signal SLP is supplied to the logic circuit 13. Based on the premise that the command signal SW_EN described later has a high level, the logic circuit 13 can set the operation mode (hereinafter simply referred to as the operation mode) of the switching control circuit 11 including itself to the normal mode or the sleep mode based on the sleep signal SLP. Fig. 4 shows an example of the relationship between the output voltage Vout, the feedback voltage Vfb, the sleep signal SLP, the switching control, and the operation mode. It is assumed that when the output voltage Vout coincides with the predetermined voltage Vth_SLP, the feedback voltage Vfb coincides with the reference voltage Vref2, and when the output voltage Vout coincides with the voltage (Vth_SLP - ΔHYS3), the feedback voltage Vfb coincides with the voltage (Vref2 - ΔHYS2). Both the hysteresis widths ΔHYS2 and ΔHYS3 have positive predetermined voltage values. The voltage (Vth_SLP - ΔHYS3) represents a voltage lower than the predetermined voltage Vth_SLP by the hysteresis width ΔHYS3. Here, "Vtg < Vth_SLP - ΔHYS3 < Vth_SLP". However, "Vth_SLP - ΔHYS3 = Vtg" is possible.

[0037] After the output voltage Vout reaches the target voltage Vtg through the startup of the power control device 10, the switching of the operation mode will be described starting from the state where the load current Iout is sufficiently large. In the stabilized state where the load current Iout is correspondingly large and the output voltage Vout is stabilized at the target voltage Vtg, the sleep signal SLP is at a low level. Based on the premise that the command signal SW_EN described later has a high level, in the stabilized state, the logic circuit 13 sets the operation mode to the normal mode based on the low-level sleep signal SLP. In the normal mode, the above-described switching control is executed based on the signal Spwm.

[0038] After the transition from the stable state to the light load state, if switching control continues based on the low-level sleep signal SLP, the output voltage Vout exceeds the target voltage Vtg and rises to a predetermined voltage Vth_SLP, causing a rising edge to appear in the sleep signal SLP. The rising edge of the sleep signal SLP triggers the logic circuit 13 to switch the operation mode from the normal mode to the sleep mode. In the sleep mode, the logic circuit 13 performs sleep control (switching stop control) to stop the switching control. When stopping the switching control in the sleep mode, both the gate signals GH and GL are maintained at a low level, regardless of the control signal Spwm, thereby maintaining both the transistors MH and ML in an off state.

[0039] Subsequently, when the output voltage Vout drops below the voltage (Vth_SLP-ΔHYS3), a falling edge occurs in the sleep signal SLP. Assuming that the command signal SW_EN (described later) is at a high level, the logic circuit 13 switches the operating mode from sleep mode to normal mode in response to the falling edge of the sleep signal SLP. If a light load state is maintained, switching control resumes upon switching to normal mode, but the output voltage Vout reaches the predetermined voltage Vth_SLP in a short time. As a result, while a light load state is maintained, switching control is repeatedly stopped and resumed, causing the output voltage Vout to fluctuate roughly between the voltage Vth_SLP and the voltage (Vth_SLP-ΔHYS3). This control allows switching control to be performed intermittently under light load conditions, thereby reducing switching loss and improving efficiency. The logic circuit 13 may also reduce power consumption by halting the operation of some circuits in the switching control circuit 11 in sleep mode.

[0040] The switching management circuit 19 (see FIG. 1) supplies a command signal SW_EN to the switching control circuit 11, commanding execution or termination of switching control. The command signal SW_EN is a binary signal having a high level or a low level, similar to the sleep signal SLP. A high-level command signal SW_EN functions as an execution command signal commanding execution of switching control, while a low-level command signal SW_EN functions as a termination command signal commanding termination of switching control. The switching management circuit 19 may generate the command signal SW_EN based on the sleep signal SLP. In this case, the command signal SW_EN may be an inverted signal of the sleep signal SLP. Alternatively, the level of the command signal SW_EN may be determined based on an enable signal supplied to the power supply control device 10 from outside the power supply control device 10. The enable signal may be an input signal to an enable terminal included in the external terminals of the power supply control device 10. The level of the command signal SW_EN may be determined from a combination of the sleep signal SLP and the enable signal. Alternatively, the level of the instruction signal SW_EN may be determined based on a command signal supplied to the power supply control device 10 from a device external to the power supply control device 10 .

[0041] During the low level period of the command signal SW_EN, the logic circuit 13 maintains the output stage circuit MM in both OFF states. The logic circuit 13 can perform switching control of the output stage circuit MM only during the high level period of the command signal SW_EN. That is, during the period when the command signal SW_EN is high and the sleep signal SLP is low, the PWM circuit 12 generates and outputs a control signal Spwm having a PWM frequency, and the logic circuit 13 performs switching control of the output stage circuit MM in response to the control signal Spwm. Even if the command signal SW_EN is high, during the period when the sleep signal SLP is high, as described with reference to FIG. 4, switching control is stopped and the output stage circuit MM is maintained in both OFF states. Note that during the low level period of the command signal SW_EN, the PWM circuit 12 maintains the control signal Spwm at low level.

[0042] In the first embodiment and other embodiments described below, unless otherwise specified, it is assumed that the sleep signal SLP has a low level.

[0043] The anode of diode Dboot is connected to the power supply voltage VDD application terminal and receives the power supply voltage VDD. The cathode of diode Dboot is connected to the boot wiring W_boot. Therefore, when transistor ML is on, diode Dboot is conductive, and a charging current is supplied from the power supply voltage VDD application terminal to boot capacitor Cboot through diode Dboot and boot terminal BOOT. When transistor ML is off, diode Dboot is non-conductive. The supply of charging current to boot capacitor Cboot increases the voltage across boot capacitor Cboot. However, the upper limit of the voltage across boot capacitor Cboot is voltage (VDD-Vf). Vf represents the forward voltage of diode Dboot. By providing a bootstrap circuit including boot capacitor Cboot and diode Dboot, the magnitude of voltage (Vboot-Vsw) is maintained at approximately the same magnitude as voltage (VDD-Vf) while switching control is continuously performed. Because voltage (VDD-Vf) is sufficiently greater than the gate threshold voltage of transistor MH, transistor MH can be driven properly.

[0044] The diode Dboot functions as a rectifying element that is conductive during the on-period of the transistor ML, setting the switch terminal SW to a low potential side and supplying a charging current to the boot capacitor Cboot. Instead of the diode Dboot, a switching element made of a MOSFET may be used as the rectifying element. For example, instead of the diode Dboot, a P-channel MOSFET having a drain connected to the application terminal of the power supply voltage VDD and a source connected to the boot wiring W_boot may be provided as the rectifying element. In this case, the logic circuit 13 controls the on / off of the MOSFET so that the rectifying element is on only during the on-period of the transistor ML.

[0045] Fig. 5 schematically shows a configuration example of the PWM circuit 12. The PWM circuit 12 in Fig. 5 includes, as main components, an error amplifier 31, a differential amplifier 32, a ramp voltage generation circuit 33, and a comparator (PWM comparator) 34. The error amplifier 31 and the differential amplifier 32 are current output type transconductance amplifiers.

[0046] The inverting input terminal of the error amplifier 31 is connected to the feedback terminal FB to receive the feedback voltage Vfb. A predetermined reference voltage Vref1 is supplied to the non-inverting input terminal of the error amplifier 31. The error amplifier 31 generates an error voltage Verr on the wiring 35 according to the difference between the feedback voltage Vfb and the reference voltage Vref1. When "Vfb < Vref1" holds, the error amplifier 31 outputs a current from its output terminal toward the wiring 35 to increase the error voltage Verr, and when "Vfb > Vref1" holds, it draws a current from the wiring 35 toward its output terminal to decrease the error voltage Verr. Although not particularly shown, a phase compensation circuit for compensating the phase of the error voltage Verr is provided between the wiring 35 and the ground.

[0047] The coil current IL is detected by a current sensor (not shown) provided in the power control device 10, and a current detection signal Isns indicating the value of the coil current IL is generated. Since the current detection signal Isns is a voltage signal, the voltage represented by the current detection signal Isns may be referred to as voltage Isns. For example, the current sensor has a sense resistor provided between the source of the transistor ML and the ground terminal GND, and generates the voltage Isns by sampling the voltage drop of the sense resistor during the on period of the transistor ML. That is, the coil current IL can be detected by detecting the current flowing through the transistor ML. However, the current sensor may generate the voltage Isns by detecting the current flowing through the transistor MH or by directly detecting the current flowing through the coil L1.

[0048] The differential amplifier 32 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The output terminal of the differential amplifier 32 is connected to the wiring 36. The non-inverting input terminal of the differential amplifier 32 is connected to the wiring 35 to receive the supply of the error voltage Verr, and the voltage Isns is supplied to the inverting input terminal of the differential amplifier 32. The differential amplifier 32 generates a comparison voltage Vc corresponding to the difference between the error voltage Verr and the voltage Isns on the wiring 36. When "Isns < Verr" holds, the differential amplifier 32 outputs a current from its output terminal toward the wiring 36 to increase the comparison voltage Vc, and when "Isns > Verr" holds, it draws a current from the wiring 36 toward its output terminal to decrease the comparison voltage Vc. Although not particularly shown, a phase compensation circuit for compensating the phase of the comparison voltage Vc is provided between the wiring 36 and the ground.

[0049] The ramp voltage generation circuit 33 generates a ramp voltage Vramp whose voltage value changes periodically at a predetermined PWM period. The PWM period corresponds to the reciprocal of the PWM frequency. The ramp voltage Vramp has, for example, a voltage waveform of a triangular wave or a sawtooth wave. The period of the variation of the ramp voltage Vramp is the PWM period. Here, as shown in FIG. 6, in each PWM period, the ramp voltage Vramp linearly and monotonically increases with the passage of time starting from the lower limit voltage value Vramp_MIN and instantaneously returns to the lower limit voltage value Vramp_MIN when it reaches the upper limit voltage value Vramp_MAX. "Vramp_MIN < Vramp_MAX" holds.

[0050] The non-inverting input terminal of the comparator 34 is connected to the wiring 36 to receive the supply of the comparison voltage Vc. The ramp voltage Vramp is supplied to the inverting input terminal of the comparator 34. The comparator 34 compares the comparison voltage Vc with the ramp voltage Vramp and outputs a control signal Spwm indicating the comparison result. The control signal Spwm has a high level during the period when the comparison voltage Vc is higher than the ramp voltage Vramp and has a low level during the period when the comparison voltage Vc is lower than the ramp voltage Vramp.

[0051] The power supply control device 10 having the PWM circuit 12 of Figure 5 employs a current-mode control method that performs output feedback control based on both the output voltage Vout and the coil current IL. A voltage Isns corresponding to the coil current IL is fed back to the differential amplifier 32, and due to the action of the differential amplifier 32, the coil current IL increases when the error voltage Verr increases, and the coil current IL decreases when the error voltage Verr decreases. The circuit configuration of Figure 5 is merely an example, and various control methods (e.g., voltage-mode control, pulse frequency modulation, constant on-time control) may be employed in the power supply control device 10.

[0052] By providing the bootstrap circuit described above, the magnitude of the voltage (Vboot-Vsw) is maintained at approximately the same level as the power supply voltage VDD during the period when switching control is continuously performed. However, in the switching power supply device 1, the output stage circuit MM may be in the both-off state for a relatively long period of time. If the boot voltage Vboot decreases significantly due to the discharge of the boot capacitor Cboot during the period when the output stage circuit MM is in the both-off state, the transistor MH cannot be driven properly. The decrease in the boot voltage Vboot reduces the operating speed of the high-side driver 14, and this reduction in the operating speed of the high-side driver 14 may delay the turn-off of the transistor MH, causing a shoot-through current due to the simultaneous turn-on of the transistors MH and ML.

[0053] As a countermeasure, the monitor circuit 17 is assigned the function of checking whether the boot capacitor Cboot is charged to the required level. That is, before starting switching control, the logic circuit 13 sets the output stage circuit MM to an output low state and waits to execute switching control until the monitor circuit 17 outputs a signal indicating that the monitored voltage Vmnt, which corresponds to the voltage (Vboot-Vsw), has reached the threshold voltage Vth_UVLO, i.e., a low-level protection signal S_UVLO. Then, after receiving the low-level protection signal S_UVLO from the monitor circuit 17, the logic circuit 13 starts switching control.

[0054] The first embodiment includes the following Examples EX1_1 to EX1_5. In Examples EX1_1 to EX1_5, detailed configuration examples and operation examples related to operations based on the monitored voltage Vmnt are described. The matters described above in the first embodiment are applied to the following Examples EX1_1 to EX1_5 unless otherwise specified and unless there is a contradiction. However, in each Example, for matters that contradict the matters described above in the first embodiment, the description in that Example may take precedence. Furthermore, unless there is a contradiction, matters described in any Example among Examples EX1_1 to EX1_5 can also be applied to any other Example (i.e., any two or more Examples among multiple Examples can be combined).

[0055] <<Example EX1_1>> An example EX1_1 will be described. Fig. 7 shows a timing chart of the example EX1_1 around the time when switching control is started. Fig. 7 shows, from top to bottom, waveforms of a command signal SW_EN, a control signal Spwm, a gate signal GH, a gate signal GL, a switch voltage Vsw, a coil current IL, a monitored voltage Vmnt, a protection signal S_UVLO, and an output voltage Vout. As time progresses, at a time t A1 , t A2 , t A3 are visited in this order. At time t A1 Before time t, the command signal SW_EN is maintained at a low level for a long time. A1 Immediately before this, the coil current IL is 0 A (zero amperes), the output voltage Vout is 0 V (zero volts), and the monitored output voltage Vmnt is sufficiently low, so the protection signal S_UVLO is at a high level. The switching control circuit 11 according to the embodiment EX_1 executes a charge control CC1 to charge the boot capacitor Cboot. The significance of the charge control CC1 will become clear in comparison with a charge control CC2 according to the embodiment EX1_2 described later.

[0056] time t A1A rising edge occurs in the command signal SW_EN. In response to the rising edge of the command signal SW_EN, the PWM circuit 12 starts the generation and output operation of the control signal Spwm having a PWM frequency. In the example of FIG. 7, at time t A1 a rising edge occurs in the control signal Spwm. The logic circuit 13 according to the embodiment EX1_1 responds to the rising edge of the command signal SW_EN and, at time t A1 switches the output stage circuit MM from the both-off state to the output-low state. When the output stage circuit MM is set to the output-low state, the monitored voltage Vmnt rises due to the charging of the bootstrap capacitor Cboot, and at time t A2 when the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, a falling edge occurs in the protection signal S_UVLO. Note that the monitored voltage Vmnt reaching the threshold voltage Vth_UVLO means a transition from the state where "Vmnt < Vth_UVLO" holds to the state where "Vmnt > Vth_UVLO" or "Vmnt ≧ Vth_UVLO" holds.

[0057] Upon receiving the falling edge of the protection signal S_UVLO, the logic circuit 13 reaches a state where it permits the execution of switching control (in other words, a state where it permits setting the output stage circuit MM to the output-high state), and thereafter, executes switching control for the output stage circuit MM according to the control signal Spwm having a PWM frequency. In the example of FIG. 7, at time t A2 the control signal Spwm has a low level, and the next rising edge in the control signal Spwm occurs at time t A3 Therefore, the logic circuit 13 switches the output stage circuit MM from the output-low state to the both-off state at time t A2 in response to the falling edge of the protection signal S_UVLO, and then, at time t A3 switches the output stage circuit MM from the both-off state to the output-high state at the timing of the rising edge of the control signal Spwm at time t

[0058] When the logic circuit 13 according to the embodiment EX1_1 receives a rising edge of the command signal SW_EN, it keeps the output stage circuit MM in the output low state until a falling edge occurs in the protection signal S_UVLO, regardless of whether a reverse current is occurring (and therefore regardless of the reverse current detection signal Srvs). Therefore, when a rising edge occurs in the command signal SW_EN while the output voltage Vout has a relatively high voltage, a relatively large negative coil current IL may be generated.

[0059] 8 shows another timing chart of the embodiment EX1_1 around the time when switching control is started. From top to bottom, FIG. 8 shows waveforms of the command signal SW_EN, the control signal Spwm, the gate signal GH, the gate signal GL, the switch voltage Vsw, the coil current IL, the monitored voltage Vmnt, the protection signal S_UVLO, and the output voltage Vout. As time progresses, the waveforms of the command signal SW_EN, the control signal Spwm, the gate signal GH, the gate signal GL, the switch voltage Vsw, the coil current IL, the monitored voltage Vmnt, the protection signal S_UVLO, and the output voltage Vout are shown. B1 , t B2 After the switching control is performed, the operation mode of the switching control circuit 11 is set to the sleep mode, and the command signal SW_EN is maintained at a low level for a certain period of time. B1 At time t B1 Just before time t, the coil current IL is 0 A (zero amperes). B1 Immediately before, the monitoring output voltage Vmnt is sufficiently low so that the protection signal S_UVLO has a high level, but the output voltage Vout has a positive voltage close to the target voltage Vtg.

[0060] time t B1 In response to the rising edge of the command signal SW_EN, the PWM circuit 12 starts generating and outputting a control signal Spwm having a PWM frequency. B1 The logic circuit 13 according to the embodiment EX1_1 responds to the rising edge of the command signal SW_EN at time t B1At time t B2 When the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, a falling edge occurs in the protection signal S_UVLO.

[0061] In response to the falling edge of the protection signal S_UVLO, the logic circuit 13 enters a state in which it is permitted to perform switching control (in other words, a state in which it is permitted to set the output stage circuit MM to an output high state), and thereafter performs switching control on the output stage circuit MM in response to the control signal Spwm having a PWM frequency. In the example of FIG. 8, at time t B2 Since the control signal Spwm is at a high level at time t B2 At time t B2 Then, the switching control for the output stage circuit MM is resumed, and thereafter, the switching control is continuously executed.

[0062] In the example of Figure 8, time t B1 until the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO (i.e., time t B2 Since the output stage circuit MM is maintained in the output low state (until the output voltage Vout reaches 1 V), a relatively large negative coil current IL is generated. An excessively large absolute value of the coil current IL is not desirable for protecting the transistor ML. In addition, an excessive decrease in the output voltage Vout due to a large negative coil current IL may adversely affect the normal operation of the load LD.

[0063] The logic circuit 13 according to the embodiment EX1_1 may set the output stage circuit MM to a low output state for a certain period of time (e.g., 2 microseconds) in response to a rising edge of the command signal SW_EN, and then perform switching control in response to the control signal Spwm. In this case, the certain period of time is set in advance so that the output stage circuit MM's low output state, triggered by the rising edge of the command signal SW_EN, is sufficient to allow the monitored voltage Vmnt to reach the threshold voltage Vth_UVLO with ample time to spare. Even with this method, a large negative coil current IL and an excessive drop in the output voltage Vout may occur.

[0064] <<Example EX1_2>> An example EX1_2 will be described. In the example EX1_2, the backflow detection circuit 16 is used to suppress an excessively large negative coil current IL during the period until the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO.

[0065] FIG. 9 shows the configuration of the reverse current detection circuit 16. The reverse current detection circuit 16 in FIG. 9 includes a comparator 41, resistors 42 to 44, and a current source 45. The resistor 42 is a sense resistor for detecting the current flowing through the transistor ML during the on-period of the transistor ML, i.e., the coil current IL. Note that FIG. 9 illustrates, as an example, a situation in which the polarity of the coil current IL is positive (the same applies to FIG. 10, which will be described later). A first terminal of the sense resistor 42 is connected to the source of the transistor ML, and a second terminal of the sense resistor 42 is connected to ground. A first terminal of the resistor 43 is connected to the first terminal of the sense resistor 42, and a second terminal of the resistor 43 is connected to the non-inverting input terminal of the comparator 41. A first terminal of the resistor 44 is connected to the second terminal of the sense resistor 42 (and therefore connected to ground in the configuration of FIG. 9), and a second terminal of the resistor 44 is connected to a node 46 and to the inverting input terminal of the comparator 41. The resistors 43 and 44 have the same resistance value. The current source 45 is inserted between the application terminal of the power supply voltage VDD and the node 46, and is configured to be able to supply a prescribed shift current Isft from the application terminal of the power supply voltage VDD to the node 46.

[0066] Under the control of the logic circuit 13, the current source 45 is configured such that the shift current Isft can be switched between the shift current Isft1 and the shift current Isft2 (see FIG. 10). Here, the shift current Isft2 is larger than the shift current Isft1. The shift current Isft1 may be zero or may have a minute current value close to zero. When the shift current Isft1 is zero, a switch is provided between the current source 45 and the node 46, and the shift current Isht from the current source 45 to the node 46 may be switched between the shift current Isft2 and zero by on / off control of the switch.

[0067] During the on-period of the transistor ML, a voltage drop corresponding to the magnitude and polarity of the coil IL occurs across both ends of the sense resistor 42. The voltage at the non-inverting input terminal of the comparator 41 is referred to as voltage Va, and the voltage at the inverting input terminal of the comparator 41 is referred to as voltage Vb. The comparator 41 compares the voltages Va and Vb, and outputs a high-level reverse current detection signal Srvs when "Va > Vb" holds, and outputs a low-level reverse current detection signal Srvs when "Va < Vb" holds. When "Va = Vb" holds, the reverse current detection signal Srvs has a high level or a low level. The reverse current detection signal Srvs carries significant information only during the on-period of the transistor ML, and the reverse current detection signal Srvs is invalid during the off-period of the transistor ML.

[0068] 10, the logic circuit 13 sets the shift current Isft1 to the shift current Isft during the UVLO release period related to the boot voltage Vboot, and sets the shift current Isft2 to the shift current Isft during the UVLO effective period related to the boot voltage Vboot. The UVLO effective period is a period during which the monitored voltage Vmnt has not reached the threshold voltage Vth_UVLO and therefore the protection signal S_UVLO is at a high level. The UVLO release period is a period during which the monitored voltage Vmnt is maintained at or above (voltage Vth_UVLO-ΔHYS) after it has increased to or above the threshold voltage Vth_UVLO. The backflow detection signal Srvs during the UVLO release period is particularly referred to as the backflow detection signal Srvs1, and the backflow detection signal Srvs during the UVLO effective period is particularly referred to as the backflow detection signal Srvs2. In the example of FIG. 11 described later, at time t C1 From time t C4 The period immediately before time t belongs to the UVLO valid period. C4 The period after this belongs to the UVLO release period. Switching control is not performed during the UVLO effective period, and switching control is performed only during the UVLO release period.

[0069] During the on-period of the transistor ML, the comparator 41 outputs a high-level reverse current detection signal Srvs when the coil current IL has negative polarity and the magnitude (absolute value) of the coil current IL is equal to or greater than the current threshold Ith. During the on-period of the transistor ML, the comparator 41 outputs a low-level reverse current detection signal Srvs when the coil current IL has positive polarity, when the coil current IL is zero, or when the coil current IL has negative polarity but the magnitude (absolute value) of the coil current IL is less than the current threshold Ith_rvs. The current threshold Ith is also switched by switching the shift current Isft between shift currents Isft1 and Isft2. The current threshold Ith during the UVLO release period, i.e., the period when "Isft = Isht1", is the current threshold Ith1. The current threshold Ith during the UVLO enable period, i.e., the period when "Isft = Isht2", is the current threshold Ith2. The current thresholds Ith1 and Ith2 have positive values, and the current threshold Ith2 is greater than the current threshold Ith1. By setting "Isft2>Isft1", "Ith2>Ith1" is realized.

[0070] During a period that belongs to the UVLO release period and in which switching control of the output stage circuit MM is performed in response to the control signal Spwm, the logic circuit 13 monitors the level of the backflow detection signal Srvs1, and executes the backflow prevention operation J1 when a rising edge of the backflow detection signal Srvs1 occurs while the transistor ML is set to on. During the backflow prevention operation J1, the logic circuit 13 immediately switches the state of the output stage circuit MM from the output low state to the both off state, regardless of the level of the control signal Spwm. After executing the backflow prevention operation J1, when a rising edge occurs in the control signal Spwm, the logic circuit 13 switches the state of the output stage circuit MM from the both off state to the output high state. The backflow prevention operation J1 can improve efficiency under light loads.

[0071] Meanwhile, during the UVLO effective period, the logic circuit 13 monitors the level of the reverse current detection signal Srvs2, and when a rising edge of the reverse current detection signal Srvs2 occurs while the transistor ML is set to on (i.e., while the output stage circuit MM is set to the output low state), the logic circuit 13 executes the reverse current limiting operation J2. In the reverse current limiting operation J2, the logic circuit 13 switches the state of the output stage circuit MM from the output low state to the both off state, and then maintains the output stage circuit MM in the both off state for a predetermined waiting time Tw (e.g., 50 nanoseconds) before returning it to the output low state. This makes it possible to suppress excessively large negative coil current IL when charging the boot capacitor Cboot.

[0072] 11 shows a timing chart of the embodiment EX1_2 around the time when switching control is started. From top to bottom, FIG. 11 shows waveforms of the command signal SW_EN, the control signal Spwm, the gate signal GH, the gate signal GL, the switch voltage Vsw, the coil current IL, the monitored voltage Vmnt, the protection signal S_UVLO, and the output voltage Vout. As time progresses, the waveforms of the command signal SW_EN, the control signal Spwm, the gate signal GH, the gate signal GL, the switch voltage Vsw, the coil current IL, the monitored voltage Vmnt, the protection signal S_UVLO, and the output voltage Vout are shown. C1 , t C2 , t C3 , t C4 As mentioned above, at time t C1 From time t C4 The period immediately before time t belongs to the UVLO valid period. C4 The period that follows belongs to the UVLO release period (see Figure 10 as appropriate).

[0073] After the switching control is performed, the operation mode of the switching control circuit 11 is set to the sleep mode, and the command signal SW_EN is maintained at a low level for a certain period of time. C1 At time t C1 Just before time t, the coil current IL is 0 A (zero amperes). C1 Immediately before, the monitoring output voltage Vmnt is sufficiently low so that the protection signal S_UVLO has a high level, but the output voltage Vout has a positive voltage close to the target voltage Vtg.

[0074] time tC1 In response to the rising edge of the command signal SW_EN, the PWM circuit 12 starts generating and outputting the control signal Spwm having a PWM frequency. C1 The logic circuit 13 according to the embodiment EX1_2 responds to the rising edge of the command signal SW_EN at time t C1 At time t, the output stage circuit MM is switched from both OFF states to the output low state. When the output stage circuit MM is in the output low state, the boot capacitor Cboot is charged and the monitored voltage Vmnt rises. On the other hand, when the output voltage Vout is relatively high, the transistor ML is turned on, generating a negative coil current IL, and at time t C1 As a result, the magnitude (absolute value) of the coil current IL increases.

[0075] The time t before the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO C2 In this state, the reverse current detection circuit 16 detects a specific reverse current state with the transistor ML set to ON. The specific reverse current state is a state in which the coil current IL has negative polarity and the magnitude (absolute value) of the coil current IL is equal to or greater than the current threshold value Ith2. The occurrence of a rising edge in the reverse current detection signal Srvs2 during the UVLO effective period corresponds to the detection of the specific reverse current state (detection that a specific reverse current state exists). Therefore, at time t C2 A rising edge occurs in the reverse current detection signal Srvs2 (see FIG. 10) at time t When the output stage circuit MM is set to the output low state and a specific reverse current state is detected before the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO (i.e., when a rising edge occurs in the reverse current detection signal Srvs2), the logic circuit 13 executes the above-mentioned reverse current limiting operation J2. C2 The state of the output stage circuit MM is switched from the output low state to the both-off state at time t. After that, the state of the output stage circuit MM is maintained in the both-off state for a predetermined waiting time Tw, and then it is returned to the output low state. The time when the state of the output stage circuit MM is returned to the output low state is time t. C3 Therefore, at time t C2 and tC3 The time difference between them corresponds to the waiting time Tw.

[0076] time t C3 At time t C3 After that, the specific backflow state is not detected again until time t C4 When the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO at time t, a fall edge occurs in the protection signal S_UVLO. In response to the fall edge of the protection signal S_UVLO, the logic circuit 13 enters a state in which execution of switching control is permitted (in other words, a state in which the output stage circuit MM is permitted to be set to an output high state), and starts switching control for the output stage circuit MM based on the control signal Spwm, which is generated in response to the feedback voltage Vfb and has a PWM frequency. That is, the logic circuit 13 starts switching control for the output stage circuit MM at time t C4 11, the switching control for the output stage circuit MM is resumed from time t C4 Since the control signal Spwm is at a high level at time t C4 In response to the control signal Spwm, the output stage circuit MM is switched from the low output state to the high output state.

[0077] In the example of Figure 11, time t C2 The magnitude of the coil current IL decreases toward zero due to the reverse current limiting operation J2 that starts at time t C2 and t C3 In the first half of the period, a negative coil current IL flows through the parasitic diode of the transistor MH, causing the switch voltage Vsw to become equal to the sum of the input voltage Vin and the forward voltage of the parasitic diode. C2 and t C3This shows how the switch voltage Vsw resonates near the output voltage Vout when "IL = 0" occurs in the latter half of the period. After the specific backflow state is detected, when the transistor ML is turned on again after a certain time (Tw), the magnitude of the coil current IL begins to increase again from 0 A. In this way, the magnitude of the negative coil current IL is limited by the backflow limiting operation J2, so the negative coil current IL does not become excessive. Furthermore, during the UVLO effective period, a charge equivalent to the time integration of the coil current IL is extracted from the output capacitor Cout. However, in Example EX1_2 (FIG. 11), the coil current IL related to the backflow is smaller than in Example EX1_1 (FIG. 8), so the decrease in the output voltage Vout can be kept small. For example, suppose the magnitude of the negative coil current IL increases to 3 A in Example EX1_1 (FIG. 8), and the current threshold Ith2 is set to 300 mA in Example EX1_2 (FIG. 11). As a result, in the embodiment EX1_2, the amount of decrease in the output voltage Vout can be suppressed to 1 / 10 compared to the embodiment EX1_1.

[0078] Furthermore, time t C3 After that, if the specific backflow state is detected again before the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, the logic circuit 13 executes the second backflow limiting operation J2. C3 If the specific backflow state is detected again before the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, the logic circuit 13 switches the state of the output stage circuit MM from the output low state back to the both-off state, and then maintains the state of the output stage circuit MM in the both-off state for a predetermined waiting time Tw before returning it to the output low state again. The same applies to the third and subsequent backflow limiting operations J2, and the magnitude of the coil current IL is returned to zero each time a backflow limiting operation J2 is performed.

[0079] Although the situation is different from that shown in Fig. 11, at time t C1After that, if the monitored voltage Vmnt rises to the threshold voltage Vth_UVLO without ever detecting a specific reverse current state and a falling edge occurs in the protection signal S_UVLO, the logic circuit 13 starts the switching control of the output stage circuit MM based on the control signal Spwm without ever executing the reverse current limit operation J2.

[0080] In this way, when the switching control circuit 11 receives the rising edge of the command signal SW_EN, after setting the output stage circuit MM to the output low state in the established state of "Vmnt < Vth_UVLO", it maintains the output stage circuit MM in the output low state until the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO through the rise of the monitored voltage Vmnt or a specific reverse current state is detected. When a specific reverse current state is detected before the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO in the state where the output stage circuit MM is set to the output low state, the switching control circuit 11 executes the reverse current limit operation J2 that switches the state of the output stage circuit MM from the output low state to the both-off state and keeps the output stage circuit MM in the both-off state for a predetermined standby time Tw and then returns to the output low state. Then, the switching control circuit 11 permits setting the output stage circuit MM to the output high state when the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO. Therefore, after the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, the switching control based on the control signal Spwm is started. The start of the switching control can be the resumption of the switching control.

[0081] By such a method, when charging the boost capacitor Cboot, the generation of a large coil current IL with a negative polarity can be suppressed. Since the flow of the large coil current IL through the transistor ML is suppressed, the protection of the transistor ML is achieved. Also, the excessive decrease in the output voltage Vout due to the large negative coil current IL is suppressed, and the adverse effect on the load LD due to the decrease in the output voltage Vout is also suppressed.

[0082] The execution period of the switching control belongs to the UVLO release period. During the execution period of the switching control, the reverse current detection circuit 16 can detect a reverse current state (hereinafter referred to as the first reverse current state) in which the magnitude of the reverse current (negative coil current IL) exceeds the current threshold value th1. The switching control circuit 11 sets the output stage circuit MM to the output low state based on the control signal Spwm during the execution period of the switching control, and then executes a reverse current suppression operation J1 that switches the output stage circuit MM from the output low state to the both-off state regardless of the control signal Spwm when the first reverse current state is detected by the reverse current detection circuit 16. The reverse current detection circuit 16 can detect a reverse current state (hereinafter referred to as the second reverse current state) in which the magnitude of the reverse current (negative coil current IL) exceeds the current threshold value Ith2 as a specific reverse current state using a circuit common to the circuit for detecting the first reverse current state. As described above, “Ith1 < Ith2” holds.

[0083] The reverse current suppression operation J1 associated with the detection of the first reverse current state improves the efficiency during light load. By using a circuit common to the reverse current detection circuit 16 provided for improving the efficiency during light load and shifting the current threshold value, it is possible to detect a specific reverse current state (second reverse current state) when charging the boost capacitor Cboot. Therefore, the circuit to be added to realize the reverse current limit operation J2 is very small (the increase in chip cost is negligible).

[0084] To improve efficiency under light loads, it is preferable to set the current threshold Ith1 for detecting the first reverse current state as close to zero as possible. On the other hand, if a current threshold Ith2 close to zero is used during the UVLO active period, the magnitude (absolute value) of the negative coil current IL reaches the current threshold Ith2 immediately after turning on the transistor ML, preventing the boot capacitor Cboot from charging quickly. Therefore, the current threshold Ith2 is shifted upward relative to the current threshold Ith1. The current threshold can be shifted by supplying the necessary current to the resistor 44 using the current source 45 (see FIGS. 9 and 10). For example, if the values ​​of the resistors 42 and 44 are set to 10 mΩ and 1 kΩ, respectively, and the shift current Isht2 is set to 3 μA, the current threshold Ith2 becomes 300 mA. Although the value of resistor 43 does not affect the current thresholds (Ith1, Ith2), it is preferable to install resistor 43 having the same resistance value as resistor 44 in order to match the impedance of the differential signal (signal of voltages Va and Vb) input to comparator 41. However, resistor 43 can also be omitted.

[0085] 9, instead of providing the sense resistor 42 separately from the transistor ML, the on-resistance of the transistor ML may be used as the sense resistor 42. In this case, a first end of a resistor 43 is connected to the drain of the transistor ML, a second end of the resistor 43 is connected to the non-inverting input terminal of the comparator 41, and a first end of a resistor 44 is connected to the source of the transistor ML, a second end of the resistor 44 is connected to the inverting input terminal of the comparator 41.

[0086] 9 may also be provided in the power supply control device 10 of the embodiment EX1_1. However, it is understood that in the embodiment EX1_1, the shift current Isht is fixed at the shift current Isht1.

[0087] As described above, a high-level command signal SW_EN functions as an execution command signal instructing the execution of switching control, and a low-level command signal SW_EN functions as a stop command signal instructing the termination of switching control. The switching control circuit 11 follows the command of the command signal SW_EN. Therefore, during the low-level period of the command signal SW_EN, the switching control circuit 11 stops the switching control. During the low-level period of the command signal SW_EN, the switching control circuit 11 maintains the output stage circuit MM in both off states. When the switching control circuit 11 starts switching control in response to a high-level command signal SW_EN (an execution command signal instructing the execution of switching control), it performs charging control before starting the switching control. The charging control is control for charging the boot capacitor Cboot, and in the charging control, the logic circuit 13 continuously or intermittently sets the output stage circuit MM to an output low state without setting it to an output high state (i.e., keeping the transistor MH off and setting the transistor ML on continuously or intermittently). In the charging control, when the output stage circuit MM is intermittently set to the output low state, the state of the output stage circuit MM is switched between the output low state and both off states without being set to the output high state. The charging control performed in the embodiment EX1_2 is particularly referred to as charging control CC2. In the example of FIG. 11, C1 and t C4 The switching control circuit 11 according to the embodiment EX1_2 performs the charge control CC2 before starting the switching control in response to the rising edge of the command signal SW_EN after the stop period of the switching control has elapsed.

[0088] On the other hand, the charge control performed in the embodiment EX1_1 is particularly referred to as charge control CC1. When starting the switching control in response to the rising edge of the command signal SW_EN after a period during which the switching control is stopped, the switching control circuit 11 according to the embodiment EX1_1 performs charge control CC1 before starting the switching control. In the example of FIG. 7, A1 and t A3 In the example of FIG. 8, the charging control CC1 is performed during the time tB1 and t B2 During this period, charging control CC1 is performed. In charging control CC1, after the switching control circuit 11 sets the output stage circuit MM to the output low state in the state where "Vmnt < Vth_UVLO" holds, until the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO through the increase of the monitored voltage Vmnt, regardless of the magnitude of the coil current IL, the output stage circuit MM is maintained in the output low state.

[0089] In contrast, in charging control CC2, after the switching control circuit 11 sets the output stage circuit MM to the output low state in the state where "Vmnt < Vth_UVLO" holds, it executes the operation of maintaining the output stage circuit MM in the output low state until the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO or a specific reverse current state is detected through the increase of the monitored voltage Vmnt. And when a specific reverse current state is detected before the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO in the state where the output stage circuit MM is set to the output low state, it executes a reverse current limiting operation J2 of switching the state of the output stage circuit MM from the output low state to the both-off state, keeping the output stage circuit MM in the both-off state for a predetermined standby time Tw, and then returning to the output low state. Then, after the start of charging control CC2, the switching control circuit 11 permits setting the output stage circuit MM to the output high state after the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO and starts switching control based on the control signal Spwm. The start of switching control can be a restart of switching control.

[0090] <<Example EX1_3>> Example EX1_3 will be described. In Example EX1_3 and the subsequent Examples EX1_4 and EX1_5 below, the technology shown in Example EX1_2 is applied, and thus charging control CC2 is performed.

[0091] FIG. 12 shows a state transition diagram of the logic circuit 13 according to the embodiment EX1_3. The state of the logic circuit 13 is one of a plurality of states including states ST1 to ST5. It can be understood that a state machine that monitors the state of the logic circuit 13 is provided in the logic circuit 13. Note that FIG. 12 conceptually shows the state transition according to the embodiment EX1_3, and states other than states ST1 to ST5 may be added to the plurality of states in order to perform more precise control, and various signals may be changed depending on the control method adopted in the switching control circuit 11 (the same applies to the embodiment EX1_4 described later).

[0092] State ST1 is the DISABLE state. In state ST1, the logic circuit 13 sets the output stage circuit MM to both OFF states. States ST2 and ST3 both belong to the standby state. In the standby state, it is determined whether the boot capacitor Cboot is charged or whether charging of the boot capacitor Cboot is completed. In state ST2, the logic circuit 13 sets the output stage circuit MM to an output low state. In state ST3, the logic circuit 13 sets the output stage circuit MM to both OFF states. States ST4 and ST5 both belong to the switching execution state. In the switching execution state, switching control is executed. In state ST4, the logic circuit 13 sets the output stage circuit MM to an output high state. In state ST5, the logic circuit 13 sets the output stage circuit MM to an output low state.

[0093] In the initial state of the power supply control device 10, the logic circuit 13 is in state ST1. When a rising edge occurs in the command signal SW_EN while the logic circuit 13 is in state ST1, a transition from state ST1 to state ST2 occurs (transition F1). In state ST2, the boot capacitor Cboot is charged. After the transition to state ST2, the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, causing a falling edge to occur in the protection signal S_UVLO (or the protection signal S_UVLO has a low level). This is expressed as the completion of charging of the boot capacitor Cboot, or simply as "charging completion." In contrast, "charging incomplete" refers to a state in which the monitored voltage Vmnt is lower than the threshold voltage Vth_UVLO and the protection signal S_UVLO has a high level.

[0094] After transitioning to state ST2, if charging of the boot capacitor Cboot is completed without detecting a specific backflow state and the control signal Spwm is high, the state transitions from state ST2 to state ST4. However, if a specific backflow state is detected before charging is completed, the state transitions from state ST2 to state ST3, waits for a waiting time Tw, and then returns to state ST2. This operation is repeated until charging is completed. After transitioning between states ST2 and ST3, once charging is completed, transitions between states ST4 and ST5 are repeated in accordance with the control signal Spwm. If the command signal SW_EN goes low during the repeated transitions between states ST4 and ST5, the state returns to state ST1.

[0095] The transitions between states will be described in more detail. When the logic circuit 13 is in state ST2, if a rising edge occurs in the reverse current detection signal Srvs2 while the protection signal S_UVLO is at a high level, a transition from state ST2 to state ST3 occurs (transition F2). When the protection signal S_UVLO is at a low level while the logic circuit 13 is in state ST2, the logic circuit 13 transitions from state ST2 to state ST4 on the condition that the control signal Spwm is at a high level (transition F3). Note that when the logic circuit 13 is in state ST2, if the protection signal S_UVLO is at a low level but the control signal Spwm is at a low level, the logic circuit 13 transitions from state ST2 to state ST4 after waiting for the level of the control signal Spwm to switch to a high level. When the logic circuit 13 is in state ST2, if the command signal SW_EN is at a low level, the logic circuit 13 transitions from state ST2 to state ST1 (transition F4).

[0096] After transitioning from state ST2 to state ST3, if the protection signal S_UVLO remains high for the waiting time Tw, the logic circuit 13 returns from state ST3 to state ST2 (transition F5). If the protection signal S_UVLO remains low while the logic circuit 13 is in state ST3, the logic circuit 13 transitions from state ST3 to state ST4 (transition F6) on the condition that the control signal Spwm remains high. While the logic circuit 13 normally does not complete charging of the boot capacitor Cboot while in state ST3 after transitioning to state ST3, a fall edge may occur in the protection signal S_UVLO in state ST3 due to signal delays, noise, or other factors. Transition F6 is provided to take this into consideration. Note that if the protection signal S_UVLO remains low but the control signal Spwm remains low while the logic circuit 13 is in state ST3, the logic circuit 13 waits for the control signal Spwm to switch to a high level before transitioning from state ST3 to state ST4.

[0097] When the logic circuit 13 is in state ST4, if it is determined that the control signal Spwm has a low level (a falling edge occurs in the control signal Spwm), a transition from state ST4 to state ST5 occurs (transition F7). When the logic circuit 13 is in state ST5, if it is determined that the control signal Spwm has a high level (a rising edge occurs in the control signal Spwm), a transition from state ST5 to state ST4 occurs (transition F8). When the logic circuit 13 is in state ST5 and the command signal SW_EN has a low level, the logic circuit 13 transitions from state ST5 to state ST1 (transition F9). Note that when the command signal SW_EN switches from a high level to a low level while the logic circuit 13 is in state ST4, the logic circuit 13 transitions from state ST4 to state ST5 in response to the falling edge of the control signal Spwm, and then transitions to state ST1 based on the low-level command signal SW_EN.

[0098] The period when the logic circuit 13 is in state ST1 corresponds to the stop period of the switching control. The charging control CC2 (see FIG. 11) described in the embodiment EX1_2 includes transitions between states ST2 and ST3. The switching control circuit 11 according to the embodiments EX1_2 and EX1_3 performs the charging control CC2 before starting the switching control when starting the switching control based on receiving a high-level command signal SW_EN (execution command signal) after the stop period of the switching control. After the start of the switching control, the charging control CC2 is not performed (the charging control CC2 is prohibited) during the execution period of the switching control. This is because the monitored voltage Vmnt does not drop significantly during the period when the switching control is continuously executed after the start of the switching control (i.e., during the period when the transition between states ST4 and ST5 is repeated). Therefore, when the logic circuit 13 is in state ST4 or ST5, there is no need to check the completion of charging (i.e., the logic circuit 13 does not need to check the level of the protection signal S_UVLO).

[0099] <<Example EX1_4>> Example EX1_4 will be described. Example EX1_4 is a partial modification of Example EX1_3. For matters not specifically described in Example EX1_4, the matters shown in Example EX1_3 also apply to Example EX1_4 unless there is a contradiction.

[0100] FIG. 13 shows a state transition diagram of the logic circuit 13 according to the embodiment EX1_4. The state of the logic circuit 13 is one of a plurality of states including states ST1 to ST6. In the embodiment EX1_4, a state ST6 is added in comparison with the embodiment EX1_3 (FIG. 12). The state ST6 is a WAIT state for waiting for a certain period of time before causing a transition to the state ST1 after the switching control is stopped after the switching control is executed. In the state ST6, the logic circuit 13 sets the output stage circuit MM to a both-off state.

[0101] The transitions between states shown in FIG. 13 will be described. The process of transitioning from state ST1 through state ST2 or through states ST2 and ST3 to state ST4 is as described in Example EX1_3. Switching control begins at the transition to state ST4. Switching control involves repeated transitions between states ST4 and ST5. In Example EX1_4, after the start of switching control, if the logic circuit 13 is in state ST5 and the command signal SW_EN is at a low level, the logic circuit 13 transitions from state ST5 to state ST6 instead of state ST1 (transition F11). Note that if the command signal SW_EN switches from a high level to a low level when the logic circuit 13 is in state ST4, the logic circuit 13 transitions from state ST4 to state ST5 in response to the falling edge of the control signal Spwm, and then transitions to state ST6 based on the low-level command signal SW_EN.

[0102] When state ST5 transitions to state ST6, the logic circuit 13 starts measuring the elapsed time Tstp using its own timer (not shown). The elapsed time Tstp is the time that has elapsed since the transition from state ST5 to state ST6. The time that has elapsed since the transition from state ST5 to state ST6 is the time that has elapsed since the switching control due to the repeated transitions between states ST4 and ST5 was stopped (stop time of switching control). In state ST6, the logic circuit 13 monitors whether the elapsed time Tstp has reached a predetermined discharge reference time Tdis. In state ST6, the logic circuit 13 (state machine within the logic circuit 13) causes a transition from state ST6 to state ST1 if the elapsed time Tstp reaches the discharge reference time Tdis while the command signal SW_EN is maintained at a low level (transition F12), while causing a transition from state ST6 to state ST4 if the command signal SW_EN switches to a high level and the control signal Spwm is set to a high level before the elapsed time Tstp reaches the discharge reference time Tdis (transition F13).

[0103] In the state transition diagram of Example EX1_3 (see FIG. 12), the transition to state ST4 in response to the rising edge of the command signal SW_EN always passes through state ST2, which may result in a deterioration in power efficiency. Furthermore, the output stage circuit MM is temporarily set to the output low state in state ST2, which may result in a deterioration in response. On the other hand, even if switching control is stopped in response to the falling edge of the command signal SW_EN after switching control has been performed, the charging voltage of the boot capacitor Cboot does not drop significantly if the switching control is stopped for a short period of time. Taking this into consideration, state ST6 is added, and if the switching control is stopped for a short period of time, a direct transition from state ST6 to state ST4 is performed. On the other hand, if the switching control is stopped for a long period of time, a transition from state ST6 to state ST1 is performed. To transition to state ST4 after transitioning to state ST1, the system first transitions to state ST2, checks the charging state of the boot capacitor Cboot, and then transitions to state ST4.

[0104] 13, when the command signal SW_EN has a low level while the logic circuit 13 is in state ST2, the logic circuit 13 transitions from state ST2 to state ST6 instead of state ST1 (transition F14). The operation after the transition from state ST2 to state ST6 is the same as the operation after the transition from state ST5 to state ST6. However, the elapsed time Tstp when the logic circuit 13 transitions from state ST2 to state ST6 refers to the elapsed time from the time of transition from state ST2 to state ST6. However, when the command signal SW_EN has a low level while the logic circuit 13 is in state ST2, in consideration of the possibility that charging may be insufficient, the logic circuit 13 may transition from state ST2 to state ST1 instead of state ST6, as in example EX1_3 (see FIG. 13).

[0105] 14 and 15, the flow of operations related to state ST6 will be further explained. When the logic circuit 13 receives an execution command signal (high-level command signal SW_EN) commanding execution of switching control while the logic circuit 13 is in state ST1, the switching control circuit 11 transitions to state ST4 via charge control CC2 and starts switching control. The charge control CC2 involves at least a transition to state ST2. Thereafter, when the switching control circuit 11 receives a stop command signal (low-level command signal SW_EN) commanding termination of switching control, the switching control circuit 11 stops the switching control and measures the elapsed time Tstp since termination of the switching control based on the stop command signal. When the switching control circuit 11 receives the execution command signal (high-level command signal SW_EN) again after the elapsed time Tstp reaches the discharge reference time Tdis, the switching control circuit 11 again passes through charge control CC2 and resumes switching control, as shown in FIG. 14. On the other hand, if the execution command signal is received again before the elapsed time Tstp reaches the discharge reference time Tdis, as shown in FIG. 15, the switching control circuit 11 resumes the switching control without going through the charge control CC2 again.

[0106] <<Example EX1_5>> Example EX1_5 will be described. The switching power supply device 1 shown in Fig. 1 is provided with the following circuit blocks (hereinafter referred to as unit circuit blocks BLK). With reference to Figs. 5 and 16 as well, the unit circuit block BLK includes a differential amplifier 32, a ramp voltage generation circuit 33, and a comparator 34, as well as a logic circuit 13, a high-side driver 14, a low-side driver 15, a reverse current detection circuit 16, a monitor circuit 17, an output stage circuit MM, a boot capacitor Cboot, a coil L1, a diode Dboot, a switch terminal SW, and a boot terminal BOOT.

[0107] FIG. 16 is an overall configuration diagram of a switching power supply 1A, which is a switching power supply 1 according to Example EX1_5. The switching power supply 1A includes unit circuit blocks BLK for multiple channels. Similar to the switching power supply 1 of FIG. 1, the switching power supply 1A also includes an output capacitor Cout, feedback resistors R1 and R2, an error amplifier 31, and a feedback terminal FB, the connections of which are as already described. In the switching power supply 1A, the output capacitor Cout, feedback resistors R1 and R2, error amplifier 31, and feedback terminal FB are shared by the unit circuit blocks BLK of multiple channels. The power supply control device 10 provided in the switching power supply 1A includes unit circuit blocks BLK for multiple channels, an error amplifier 31, a feedback terminal FB, and a switching management circuit 19A. However, it is understood that the boot capacitor Cboot and coil L1 of each channel are provided outside the power supply control device 10.

[0108] Although the switching power supply device 1A shown in FIG. 16 has two channels of unit circuit blocks BLK, it may have three or more channels of unit circuit blocks BLK. The two channels of unit circuit blocks BLK are composed of first and second channel unit circuit blocks BLK. The internal configuration of each unit circuit block BLK and the operation of the components in each unit circuit block BLK are as described above with reference to FIG. 1 etc. In particular, the operations shown in Examples EX1_2 to EX1_4 are applied to each unit circuit block BLK in the switching power supply device 1A. Here, a first end of the coil L1 of the first channel is connected to the switch terminal SW of the first channel and a first end of the coil L1 of the second channel is connected to the switch terminal SW of the second channel, while a second end of the coil L1 of the first channel and a second end of the coil L1 of the second channel are connected to a common output terminal OUT, and an output capacitor Cout common to the first and second channels is provided between the common output terminal OUT and ground.

[0109] In the switching power supply device 1A, switching control can be performed individually in the unit circuit blocks BLK of multiple channels, and in this case, multi-phase control can be performed by shifting the phase of the switching control between the multiple channels. When switching control is performed in the first channel, the unit circuit block BLK of the first channel controls the output duty of the output stage circuit MM of the first channel so that the voltage difference (Vfb-Vref1) approaches zero. When switching control is performed in the second channel, the unit circuit block BLK of the second channel controls the output duty of the output stage circuit MM of the second channel so that the voltage difference (Vfb-Vref1) approaches zero. The same applies when unit circuit blocks BLK of other channels are provided.

[0110] The switching management circuit 19A includes the functions of the above-described switching management circuit 19. The switching management circuit 19A outputs a command signal SW_EN to the unit circuit block BLK of each channel. The operation of the unit circuit block BLK (particularly the operation of the logic circuit 13) in response to the command signal SW_EN is as described above, and in each channel, switching control is performed only during the period when the corresponding command signal SW_EN is at a high level, and switching control is stopped during the period when the corresponding command signal SW_EN is at a low level. In each channel, after a rising edge occurs in the corresponding command signal SW_EN, switching control is started after the above-described charging control CC2 (see FIG. 11).

[0111] The command signal SW_EN that the switching management circuit 19A outputs to the unit circuit block BLK of the first channel is particularly referred to as command signal SW_EN[1]. The command signal SW_EN that the switching management circuit 19A outputs to the unit circuit block BLK of the second channel is particularly referred to as command signal SW_EN[2]. A high-level command signal SW_EN[i] functions as an execution command signal that commands the unit circuit block BLK of the i-th channel to execute switching control, and a low-level command signal SW_EN[i] functions as a stop command signal that commands the unit circuit block BLK of the i-th channel to stop switching control. Here, i represents 1 or 2. The above-mentioned multi-phase control can be performed during a period when both the command signals SW_EN[1] and SW_EN[2] are at high levels.

[0112] The switching management circuit 19A can adjust the number of operating channels NUM by controlling the levels of the command signals SW_EN[1] and SW_EN[2]. The number of operating channels NUM is the total number of unit circuit blocks BLK for which switching control is performed in the switching power supply device 1A. When focusing only on the first and second channels, the switching management circuit 19A can set the number of operating channels NUM to 1 by setting the command signal SW_EN[1] to a high level and the command signal SW_EN[2] to a low level. At this time, switching control is performed in the unit circuit block BLK of the first channel, while switching control is stopped in the unit circuit block BLK of the second channel. The switching management circuit 19A can set the number of operating channels NUM to 2 by setting both the command signals SW_EN[1] and SW_EN[2] to a high level. At this time, switching control is performed in both the unit circuit blocks BLK of the first and second channels.

[0113] For example, the switching management circuit 19A can adjust the number of active channels NUM in response to the load current Iout. Alternatively, the switching management circuit 19A can adjust the number of active channels NUM based on a command signal supplied to the power supply control device 10 from a device external to the power supply control device 10. Assume that the command signal SW_EN[1] is set high and the command signal SW_EN[2] is set low for a long period of time, and switching control is performed only by the unit circuit block BLK of the first channel, stabilizing the output voltage Vout at a target voltage Vtg of 5V. Assume also that the power supply voltage VDD is 5V. In this situation, the output stage circuit MM of the second channel is both off, so the switch voltage Vsw of the second channel is 5V. Therefore, the boot capacitor Cboot of the second channel is not charged. If the command signal SW_EN[2] is switched high to enable switching control in the second channel, a temporary large drop in the output voltage Vout may occur if charge control CC1 is performed in the second channel (see FIG. 8). In contrast, if charge control CC2 is performed in the second channel in response to the command signal SW_EN[2] switching to high level (if charge control CC2 is performed before starting switching control and switching control of the second channel is started after the monitored voltage Vmnt of the second channel reaches the threshold voltage Vth_UVLO), the number of operating channels NUM can be increased with almost no decrease in the output voltage Vout.

[0114] <<Second embodiment>> A second embodiment of the present disclosure will be described. The second embodiment is based on the first embodiment, and the matters described in the first embodiment may also be applied to the second embodiment unless there is a contradiction. However, when interpreting the technology described in the second embodiment, the description in the second embodiment may take precedence over matters that contradict the matters described in the first embodiment.

[0115] The charge control used in the second embodiment may be charge control CC1 or charge control CC2 (see FIGS. 8 and 11). The second embodiment shows a configuration example of the monitor circuit 17. Any configuration example of the monitor circuit 17 shown in the second embodiment may be applied to the monitor circuit 17 of the first embodiment. In addition, any technique shown in the second embodiment may be applied to the first embodiment.

[0116] The second embodiment includes the following Examples EX2_1 to EX2_5. In Examples EX2_1 to EX2_5, a technique related to the monitor circuit 17 will be described.

[0117] <<Example EX2_1>> An example EX2_1 will be described. Fig. 17 shows the configuration of a monitor circuit 17a which is the monitor circuit 17 according to the example EX2_1. The monitor circuit 17a includes voltage dividing resistors 51 and 52, a comparator 53, a reference voltage source 54, and a level shifter 55. In the monitor circuit 17a, the comparator 53 monitors the voltage difference between the boot terminal BOOT and the switch terminal SW, and converts the output level of the comparator 53 into the input level of the logic circuit 13 using the level shifter 55.

[0118] The configuration and operation of the monitor circuit 17a will be described in detail. A first end of the voltage-dividing resistor 51 is connected to the boot terminal BOOT and the boot wiring W_boot and receives the boot voltage Vboot. A second end of the voltage-dividing resistor 51 and a first end of the voltage-dividing resistor 52 are commonly connected at a node 56. A second end of the voltage-dividing resistor 52 is connected to the switch terminal SW. Therefore, the switch voltage Vsw is applied to the second end of the voltage-dividing resistor 52. The voltage at the node 56 is a voltage (Vsw+Vx1). The voltage (Vsw+Vx1) is higher than the switch voltage Vsw by a voltage Vx1. The voltage Vx1 is the voltage across the voltage-dividing resistor 52.

[0119] The voltage dividing circuit composed of voltage dividing resistors 51 and 52 generates a voltage Vx1 by dividing the differential voltage between the boot voltage Vboot and the switch voltage Vsw. The inverting input terminal of the comparator 53 is connected to the node 56 and receives the voltage (Vsw + Vx1). The reference voltage source 54 generates a predetermined positive reference voltage Vy1 based on the potential of the switch terminal SW, and supplies a voltage (Vsw + Vy1), which is a voltage higher than the reference voltage Vy1 by Vy1 as seen from the switch voltage Vsw, to the non-inverting input terminal of the comparator 53. The comparator 53 operates with the boot voltage Vboot as the power supply voltage on the high potential side and the switch voltage Vsw as the power supply voltage on the low potential side. The comparator 53 compares the voltage (Vsw + Vx1) at its inverting input terminal with the voltage (Vsw + Vy1) at its non-inverting input terminal, and outputs a signal OUT53 indicating their high and low relationship. The signal OUT53 is a binary signal having a high level or a low level. The high level in the signal OUT53 has the potential of the boot voltage Vboot, and the low level in the signal OUT53 has the potential of the switch voltage Vsw. The signal OUT53 is input to the level shifter 55. The comparator 53 outputs a signal OUT53 of low level when "Vsw + Vx1 > Vsw + Vy1" holds, and outputs a signal OUT53 of high level when "Vsw + Vx1 < Vsw + Vy1" holds. When "Vsw + Vx1 = Vsw + Vy1" holds, the signal OUT53 has a low level or a high level. In practice, the comparator 53 may be provided with a hysteresis characteristic. Each constant in the monitor circuit 17a is set so that the level of the signal OUT53 switches from the high level to the low level at the point when the voltage (Vboot - Vsw) rises and reaches the threshold voltage Vth_UVLO.

[0120] The level shifter 55 is supplied with the boot voltage Vboot, the switch voltage Vsw, the power supply voltage VDD, and the ground voltage, and generates and outputs the protection signal S_UVLO by level-shifting the signal OUT53 based on the supplied voltages. The high level of the protection signal S_UVLO output from the level shifter 55 has the potential of the power supply voltage VDD, and the low level has the ground potential. The level shifter 55 outputs the protection signal S_UVLO at a high level when the signal OUT53 has a high level, and outputs the protection signal S_UVLO at a low level when the signal OUT53 has a low level. The protection signal S_UVLO from the level shifter 55 is supplied to the logic circuit 13. The logic circuit 13 operates based on the power supply voltage VDD with respect to the ground potential, and can properly read the logical value of the protection signal S_UVLO from the level shifter 55.

[0121] Fig. 18 shows a configuration example of the level shifter 55. The level shifter 55 in Fig. 18 includes an inverter circuit 55_1, transistors 55_2 and 55_3, resistors 55_4 and 55_5, and a buffer circuit 55_6. The transistor 55_2 is a P-channel MOSFET, and the transistor 55_3 is an N-channel MOSFET.

[0122] The inverter circuit 55_1 operates using the boot voltage Vboot and the switch voltage Vsw as positive and negative power supply voltages, and outputs an inverted signal of the signal OUT53 to the gate of the transistor 55_2. In the output signal of the inverter circuit 55_1, the high level has the potential of the boot voltage Vboot, and the low level has the potential of the switch voltage Vsw.

[0123] A boot voltage Vboot is supplied to a first terminal of the resistor 55_4. A second terminal of the resistor 55_4 is connected to the source of the transistor 55_2. A drain of the transistor 55_2 is connected to the drain of the transistor 55_3. A source of the transistor 55_3 is connected to a first terminal of the resistor 55_5 and to an input terminal of the buffer circuit 55_6. A second terminal of the resistor 55_5 is connected to ground. A power supply voltage VDD is supplied to the gate of the transistor 55_3. The buffer circuit 55_6 is driven based on the power supply voltage VDD with respect to the ground potential. The buffer circuit 55_6 outputs a high-level signal S_UVLO if the voltage at its input terminal (i.e., the source voltage of the transistor 55_3) is equal to or higher than the boundary voltage, and outputs a low-level signal S_UVLO if it is lower than the boundary voltage. The boundary voltage is approximately half the power supply voltage VDD.

[0124] The operation of the level shifter 55 in FIG. 18 will be described. During a high-level period of the signal OUT53, the inverter circuit 55_1 supplies a low-level signal (a signal having the potential of the switch voltage Vsw) to the gate of the transistor 55_2 to turn on the transistor 55_2. When the transistor 55_2 is on, the drain current of the transistor 55_2 flows through the transistor 55_3 and the resistor 55_5, and a voltage higher than the boundary voltage is applied to the input terminal of the buffer circuit 55_6 due to the current, resulting in the protection signal S_UVLO becoming high. Conversely, during a low-level period of the signal OUT53, the inverter circuit 55_1 supplies a high-level signal (a signal having the potential of the boot voltage Vboot) to the gate of the transistor 55_2 to turn off the transistor 55_2. When the transistor 55_2 is off, a voltage lower than the boundary voltage (a voltage of 0 V) ​​is applied to the input terminal of the buffer circuit 55_6, resulting in the protection signal S_UVLO becoming low. Incidentally, by providing the transistor 55_3, the input voltage to the buffer circuit 55_6 is limited to a voltage lower than the power supply voltage VDD by the gate threshold voltage of the transistor 55_3, thereby protecting the buffer circuit 55_6.

[0125] In the level shifter 55 of FIG. 18, high-voltage elements must be used as the transistors 55_2 and 55_3. The high-voltage elements are resistant to voltages exceeding the power supply voltage VDD. Because the element size of the high-voltage elements is relatively large, the use of high-voltage elements increases the cost of the semiconductor chip. Furthermore, a relatively large parasitic capacitance is added between the source and drain of the transistor formed as the high-voltage element and the semiconductor substrate of the semiconductor chip. When the switch voltage Vsw fluctuates, a current flows through the parasitic capacitance, which easily generates noise within the level shifter 55. Therefore, it is preferable to add a malfunction prevention circuit to the level shifter 55 of FIG. 18 to suppress the effects of such noise.

[0126] <<Example EX2_2>> An example EX2_2 will be described. FIG. 19 shows the configuration of a monitor circuit 17b, which is the monitor circuit 17 according to the example EX2_2. The monitor circuit 17b includes transistors 61 and 62, resistors 63 and 64, a comparator 65, and a reference voltage source 66. The transistor 61 is a P-channel MOSFET, and the transistor 62 is an N-channel MOSFET. The monitor circuit 17b shifts the voltage between the boot terminal BOOT and the switch terminal SW to a voltage (Vx2) having an appropriate level before supplying it to the comparator 65.

[0127] The configuration and operation of the monitor circuit 17b will be described in detail. A first end of the resistor 63 is connected to the boot terminal BOOT and the boot wiring W_boot and receives the boot voltage Vboot. A second end of the resistor 63 is connected to the source of the transistor 61. A drain of the transistor 61 is connected to the drain of the transistor 62. A source of the transistor 62 is connected to a first end of a resistor 64 at a node 67, and a second end of the resistor 64 is connected to ground. A gate of the transistor 61 is connected to the switch terminal SW and receives the switch voltage Vsw. A signal EN0 is supplied to the gate of the transistor 62. An inverting input terminal of the comparator 65 is connected to the node 67 and receives a voltage Vx2 at the node 67. The voltage Vx2 is equal to the voltage drop across the resistor 64. A reference voltage source 66 generates a predetermined positive reference voltage Vy2 with respect to the ground potential and supplies the voltage Vy2 to the non-inverting input terminal of the comparator 65.

[0128] The comparator 65 compares the voltage Vx2 at its inverting input terminal with the voltage Vy2 at its non-inverting input terminal, and outputs a signal indicating the relative levels of the two as the protection signal S_UVLO. The comparator 65 operates based on the power supply voltage VDD with respect to the ground potential, and the high level of the protection signal S_UVLO output by the comparator 65 has the potential of the power supply voltage VDD, and the low level has the ground potential.

[0129] The signal EN0 is a binary signal having a high level or a low level. When the signal EN0 is at a low level, it has ground potential. Therefore, during the low-level period of the signal EN0, the transistor 62 is off and the voltage Vx2 is 0 V. As a result, the protection signal S_UVLO from the comparator 65 has a high level. When the signal EN0 is at a high level, it has a potential sufficiently higher than the gate threshold voltage of the transistor 62. Therefore, during the high-level period of the signal EN0, the transistor 62 is on, and a current corresponding to the voltage (Vboot-Vsw) flows through the resistor 64 via the transistor 62. The signal EN0 is output from the logic circuit 13, and the level of the signal EN0 is basically fixed at a high level. For example, during the low-level period of the command signal SW_EN, the signal EN0 may have a low level. However, the signal EN0 is switched to a high level upon the rising edge of the command signal SW_EN, and thereafter, the signal EN0 is continuously maintained at a high level from immediately before the start of switching control, through the start of switching control, and throughout the execution period of switching control. In the embodiment EX2_2, unless otherwise stated, it is assumed that the signal EN0 has a high level.

[0130] When the charging of the boot capacitor Cboot progresses to a certain extent, a current flows through the resistor 63 and the transistor 61, and the voltage drop that occurs in the resistor 63 at this time is a voltage (Vboot-Vsw-Vth61). Here, Vth61 represents the gate threshold voltage of the transistor 61. The voltage (Vboot-Vsw-Vth61) and the ratio (R 64 / R 63 ) is the voltage Vx2. Therefore, assuming that the gate threshold voltage Vth61 is sufficiently low, the voltage (Vboot-Vsw) can be monitored using the voltage Vx2. 63 and R 64 represent the resistance values ​​of the resistors 63 and 64, respectively.

[0131] The transistor 62 functions as a switch and also has a voltage clamp function that limits the voltage Vx2 to a voltage lower than the high level of the signal EN0 by the gate threshold voltage of the transistor 62 so that the voltage Vx2 does not exceed the withstand voltage of the comparator 65. Typically, the high level of the signal EN0 has the potential of the power supply voltage VDD, but it may have a different potential. The constants in the monitor circuit 17b are set so that the output signal (S_UVLO) of the comparator 65 switches from high to low when the voltage (Vboot-Vsw) rises and reaches the threshold voltage Vth_UVLO.

[0132] In the monitor circuit 17b of FIG. 19, high-voltage elements must be used as the transistors 61 and 62. High-voltage elements are resistant to voltages exceeding the power supply voltage VDD. Because high-voltage elements are relatively large in size, using high-voltage elements increases the cost of the semiconductor chip. Furthermore, a relatively large parasitic capacitance is added between the source and drain of a transistor formed as a high-voltage element and the semiconductor substrate of the semiconductor chip. When the switch voltage Vsw fluctuates, a current flows through the parasitic capacitance, which easily generates noise in the monitor circuit 17b. Therefore, it is preferable to add a malfunction prevention circuit to the monitor circuit 17b of FIG. 19 to suppress the effects of such noise.

[0133] <<Example EX2_3>> An example EX2_3 will be described. FIG. 20 shows the configuration of a monitor circuit 17c, which is the monitor circuit 17 according to the example EX2_3. The monitor circuit 17c includes voltage-dividing resistors 71 and 72, a transistor 73 (insertion transistor), a comparator 74, a reference voltage source 75, and a latch circuit 76. The transistor 73 is an N-channel MOSFET. Here, the voltage on the reference wiring W_VSS is referred to as voltage VSS. The reference wiring W_VSS is connected to the ground terminal GND (see FIG. 1) and therefore has ground potential (the same applies to other examples described later). In other words, the voltage VSS is 0V.

[0134] In Example EX2_3, we focused on the fact that overdischarge of the boot capacitor Cboot occurs only during periods when switching control is stopped. It is sufficient to check whether the boot capacitor Cboot is fully charged or insufficiently charged before the start of switching control—strictly speaking, immediately before transistor MH is first switched on during switching control. The monitor circuit 17c in FIG. 20 has a circuit configuration partially similar to that of the monitor circuit 17b in FIG. 19, but their operations are completely different. In FIG. 20, transistor 73 performs both a switch function and a voltage clamp function. During the on-period of transistor 73, the boot voltage Vboot is divided with respect to the ground potential, and a voltage Vx3 having the divided value is input to the comparator 74. In other words, while the monitor circuit 17b in FIG. 19 detects the difference between the voltages Vboot and Vsw, the monitor circuit 17c in FIG. 20 detects the difference between the voltages Vboot and VSS. However, during the on-period of transistor ML, the switch voltage Vsw is approximately equal to the voltage VSS, so detecting the difference between the voltages Vboot and VSS is equivalent to detecting the difference between the voltages Vboot and Vsw. That is, in the monitor circuit 17c of FIG. 20, if the signal EN1 is set to high level to turn on the transistor 73 while the transistor ML is on, the difference between the voltages Vboot and Vsw can be observed from the voltage drop across the voltage dividing resistor 72.

[0135] The configuration and operation of the monitor circuit 17c will be described in detail. The first end of the voltage dividing resistor 71 is connected to the boot terminal BOOT and the boot wiring W_boot to receive the boot voltage Vboot. The second end of the voltage dividing resistor 71 is connected to the node ND1. The first end of the voltage dividing resistor 72 is connected to the node ND2. The second end of the voltage dividing resistor 72 is connected to the reference wiring W_VSS. A transistor 73 is inserted between the nodes ND1 and ND2. That is, the drain of the transistor 73 is connected to the node ND1, and the source of the transistor 73 is connected to the node ND2. A signal EN1 is supplied from the logic circuit 13 to the gate of the transistor 73. The inverting input terminal of the comparator 74 is connected to the node ND2 to receive the voltage Vx3 at the node ND2. The voltage Vx3 is equal to the voltage drop generated by the voltage dividing resistor 72. The reference voltage source 75 generates a predetermined positive reference voltage Vy3 based on the ground potential and supplies it to the non-inverting input terminal of the comparator 74.

[0136] The comparator 74 compares the voltage Vx3 at its inverting input terminal with the voltage Vy3 at its non-inverting input terminal and outputs a detection signal S_DET indicating their high and low relationship. The detection signal S_DET has a high level when "Vx3 < Vy3" holds, a low level when "Vx3 > Vy3" holds, and a low level or a high level when "Vx3 = Vy3" holds. A protection signal S_UVLO based on the detection signal S_DET is output from the latch circuit 76 to the logic circuit 13. The comparator 74 and the latch circuit 76 operate based on the power supply voltage VDD with reference to the ground potential. In the detection signal S_DET and the protection signal S_UVLO, the high level has the potential of the power supply voltage VDD, and the low level has the ground potential.

[0137] The signal EN1 is a binary signal having a high level or a low level. The low-level signal EN1 has ground potential. Therefore, during the low-level period of the signal EN1, the transistor 73 is off, the voltage Vx3 is 0 V, and as a result, the detection signal S_DET from the comparator 74 is high. The high-level signal EN1 has a potential sufficiently higher than the gate threshold voltage of the transistor 73. Therefore, during the high-level period of the signal EN1, the transistor 73 is on, and a current corresponding to the difference between the voltages Vboot and VSS, i.e., a current corresponding to the voltage (Vboot - VSS), flows through the voltage-dividing resistor 72 via the transistor 73. The logic circuit 13 can set the signal EN1 to a high level during the on-period of the transistor ML. The logic circuit 13 sets the signal EN1 to a low level during the period when the output stage circuit MM is set to the output high state and during the period when the output stage circuit MM is set to both the output high state and both the output stage circuit MM is set to both the off state. However, the signal EN1 may also be set to a high level during the period when the output stage circuit MM is set to the output high state or both the off state. However, since a voltage equivalent to the difference between the voltages Vboot and Vsw appears at node ND2 only during the on period of transistor ML, the detection signal S_DET is invalid during the period when output stage circuit MM is set to the output high state or both off states.

[0138] In the initial state of the power supply control device 10, the protection signal S_UVLO from the latch circuit 76 is at a high level, and the protection signal S_UVLO generally remains at a high level. The latch circuit 76 monitors the level of the detection signal S_DET during the high-level period of the signal EN1 (hence, during the on-period of the transistors ML and 73). When a falling edge occurs in the detection signal S_DET during the high-level period of the signal EN1, as shown in FIG. 21, the latch circuit 76 latches the low-level of the detection signal S_DET, thereby switching the level of the protection signal S_UVLO from a high level to a low level. The latch circuit 76 disables the detection signal S_DET during the low-level period of the signal EN1 and does not respond to the detection signal S_DET during the low-level period of the signal EN1. Note that the latch circuit 76 may be incorporated into the logic circuit 13. Hereinafter, the low-level detection signal S_DET or the low-level protection signal S_UVLO will be referred to as an undervoltage release signal. The undervoltage release signal is a signal indicating that the state in which the monitored voltage Vmnt is too low has been released, and is also a signal that releases the prohibition on controlling the transistor MH, and the logic circuit 13 can control the transistor MH to be on only after receiving the undervoltage release signal. The low-level detection signal S_DET or protection signal S_UVLO can also be said to be a signal indicating that charging of the boot capacitor Cboot has been completed, and therefore the undervoltage release signal may be interpreted as a charging completion signal.

[0139] The voltage dividing resistors 71 and 72 constitute a voltage dividing circuit that divides the voltage between the reference wiring W_VSS and the boot wiring W_boot, i.e., the voltage (Vboot-VSS). However, the voltage division in the voltage dividing circuit is realized only while the transistor 73 is on. If the drain-source voltage of the transistor 73 is sufficiently small and ignored while the transistor 73 is on, the voltage Vx3 is expressed as "Vx3=(Vboot-VSS)×R 72 / (R 71 +R 72 )”, where R 71 and R 72represent the resistance values ​​of the voltage dividing resistors 71 and 72, respectively. The voltage Vx3 during the ON period of the transistors ML and 73 is particularly referred to as the evaluation voltage Vx3. As described above, during the ON period of the transistor ML, the switch voltage Vsw is approximately equal to the voltage VSS, and therefore the evaluation voltage Vx3 is given by "Vx3=(Vboot-Vsw)×R 72 / (R 71 +R 72 )". That is, the voltage dividing circuit consisting of voltage dividing resistors 71 and 72 divides the voltage between the reference wiring W_VSS and the boot wiring W_boot while transistors ML and 73 are on, thereby generating an evaluation voltage Vx3 corresponding to the monitored voltage Vmnt (=Vboot-Vsw) at node ND2. The monitor circuit 17c compares the evaluation voltage Vx3 with the reference voltage Vy3 to determine whether or not to supply an undervoltage release signal to the logic circuit 13.

[0140] The transistor 73 functions as a switch and also has a voltage clamp function that limits the voltage Vx3 to a voltage lower than the high level of the signal EN1 by the gate threshold voltage of the transistor 73 so that the voltage Vx3 does not exceed the withstand voltage of the comparator 74. Typically, the high level of the signal EN1 has the potential of the power supply voltage VDD, but it may have a different potential. Assuming that the transistors ML and 73 are on, the constants in the monitor circuit 17c are set so that the detection signal S_DET of the comparator 74 switches from high to low when the voltage (Vboot-Vsw) rises and reaches the threshold voltage Vth_UVLO.

[0141] The transistor 73 is a high-voltage element. The monitor circuit 17c of FIG. 20 does not require any other high-voltage element besides the transistor 73. Therefore, the size of the monitor circuit on the semiconductor chip can be reduced in the monitor circuit 17c of FIG. 20 compared to the monitor circuits 17a and 17b shown in Examples EX2_1 and EX2_2. Furthermore, the monitor circuit 17c of FIG. 20 monitors the voltage (Vboot-Vsw) only during the on-period of the transistor ML. This allows the monitor circuit 17c to be stopped in sleep mode (see FIG. 4) in which both transistors are maintained in the off-state. Therefore, the magnitude of the circuit current is less of an issue, and resistors with sufficiently low resistance values ​​can be used as the resistors 71 and 72. As a result, although a relatively large parasitic capacitance is added to the drain of the transistor 73, which is a high-voltage element, the low resistance of the resistors 71 and 72 reduces the influence of the parasitic capacitance. Furthermore, because the monitor circuit 17c monitors the voltage (Vboot-Vsw) only during the on-period of the transistor ML, malfunctions do not occur during transitions of the switch voltage Vsw.

[0142] 22 is a timing chart relating to the first case, showing the timing around the start of switching control. From top to bottom, FIG. 22 shows the waveforms of the command signal SW_EN, the control signal Spwm, the gate signal GH, the gate signal GL, the switch voltage Vsw, the coil current IL, the monitored voltage Vmnt, the detection signal S_DET, the protection signal S_UVLO, and the signal EN1 (the same applies to FIG. 23 described later). As time progresses, at time t D1 , t D2 , t D3 In the timing chart of Fig. 22, it is assumed that the charging control CC1 is used (the same applies to Fig. 23 described later).

[0143] After the switching control is performed, the operation mode of the switching control circuit 11 is set to the sleep mode, and the command signal SW_EN is maintained at a low level for a certain period of time. D1 Although it is not clear from FIG. D1Just before that, it is assumed that the output voltage Vout has a positive voltage close to the target voltage Vtg. The logic circuit 13, at the time t D1 before, upon the instruction signal SW_EN being set to the low level, or, at the time t D1 before, after the instruction signal SW_EN is switched from the high level to the low level and a certain period of time has elapsed, the latch of the protection signal S_UVLO by the latch circuit 76 is released. By releasing the latch of the protection signal S_UVLO, the level of the protection signal S_UVLO is set to the high level which is the initial level. Just before the time t D1 the protection signal S_UVLO has the high level. Also, just before the time t D1 before, the coil current IL is 0 A (zero ampere).

[0144] At the time t D1 a rising edge occurs in the instruction signal SW_EN. In response to the rising edge of the instruction signal SW_EN, the PWM circuit 12 starts the generation and output operation of the control signal Spwm having the PWM frequency. In the example of FIG. 22, at the time t D1 a rising edge occurs in the control signal Spwm. The logic circuit 13, in response to the rising edge of the instruction signal SW_EN, switches the output stage circuit MM from the both-off state to the output-low state at the time t D1 . By the output stage circuit MM being set to the output-low state, the monitored voltage Vmnt rises due to the charging of the boost capacitor Cboot. On the other hand, when the transistor ML is turned on in a state where the output voltage Vout is relatively high, a negative coil current IL is generated, and from the time t D1 the magnitude (absolute value) of the coil current IL increases.

[0145] At the time t D2 the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO. As already described, the monitored voltage Vmnt reaching the threshold voltage Vth_UVLO means the transition from the state where "Vmnt < Vth_UVLO" holds to the state where "Vmnt > Vth_UVLO" or "Vmnt ≧ Vth_UVLO" holds. In the example of FIG. 22, the logic circuit 13, at the time tD1 The time t when the undervoltage release signal (low-level detection signal S_DET) is output D2 Until time t D1 and t D2 The monitor circuit 17c monitors the monitored voltage Vmnt during the time t D2 When the monitored voltage Vmnt reaches the threshold voltage Vth_UVLO, a fall edge occurs in the detection signal S_DET, and a fall edge also occurs in the protection signal S_UVLO in conjunction with the fall edge of the detection signal S_DET. The logic circuit 13 switches the transistor ML from on to off in response to the fall edge of the protection signal S_UVLO, and generates a fall edge in the signal EN1.

[0146] In response to the falling edge of the protection signal S_UVLO, the logic circuit 13 enters a state in which it is permitted to perform switching control (in other words, a state in which it is permitted to set the output stage circuit MM to an output high state), and thereafter performs switching control on the output stage circuit MM in response to the control signal Spwm having a PWM frequency. In the example of FIG. 22, at time t D2 At time t, the control signal Spwm has a low level, and the next rising edge of the control signal Spwm occurs at time t D3 Therefore, the logic circuit 13 generates a D3 At the rising edge of the control signal Spwm at time t, the output stage circuit MM is switched from both OFF states to the output high state, and thereafter the switching control is continued. Once the low voltage release signal is output and the switching control is started, the monitored voltage Vmnt does not drop significantly during the switching control, so the monitored voltage Vmnt is not monitored (detected). In the timing chart of FIG. 22, at time t D2 and t D3 In the first half of the period, a negative coil current IL flows through the parasitic diode of the transistor MH, causing the switch voltage Vsw to become equal to the sum of the input voltage Vin and the forward voltage of the parasitic diode. D2 and tD3 In the latter half of this period, "IL=0" occurs, and the switch voltage Vsw resonates near the output voltage Vout.

[0147] The logic circuit 13 detects the time t D3 After that, when the command signal SW_EN is set to a low level, or at time t D3 Thereafter, when a certain time has elapsed since the fall edge occurred in the command signal SW_EN, the latch circuit 76 can unlatch the protection signal S_UVLO and return the level of the protection signal S_UVLO to the initial level (high level).

[0148] 23 is a timing chart showing the timing around the start of switching control, and is a timing chart relating to the second case. E1 , t E2 , t E3 However, they will be visited in this order.

[0149] After the switching control is performed, the operation mode of the switching control circuit 11 is set to the sleep mode, and the command signal SW_EN is maintained at a low level for a certain period of time. E1 Although it is not clear from Figure 23, at time t E1 The output voltage Vout is assumed to be a positive voltage close to the target voltage Vtg immediately before time t E1 , or at time t E1 After the command signal SW_EN is switched from high level to low level before time t, the latch circuit 76 unlatches the protection signal S_UVLO after a certain period of time has elapsed. By unlatching the protection signal S_UVLO, the level of the protection signal S_UVLO is set to the initial high level. E1 The protection signal S_UVLO has a high level just before the time t E1 Immediately before this, the coil current IL is 0 A (zero amperes).

[0150] time t E1 In response to the rising edge of the command signal SW_EN, the PWM circuit 12 starts generating and outputting the control signal Spwm having the PWM frequency. E1 In response to the rising edge of the command signal SW_EN, the logic circuit 13 E1 At time t E1 The time t when the undervoltage release signal (low-level detection signal S_DET) is output E2 Until time t E1 and t E2 During this time, the monitor circuit 17c observes the monitored voltage Vmnt.

[0151] In the second case corresponding to FIG. 23, the period during which the switching control is stopped before the rising edge of the command signal SW_EN is shorter than the first case corresponding to FIG. 22. Therefore, at time t E1 The monitored voltage Vmnt at time t is equal to or greater than the threshold voltage Vth_UVLO, or E1 Immediately after the time t E1 The time t immediately after E2 A fall edge occurs in the detection signal S_DET at time t E2 In response to the falling edge of the detection signal S_DET at time t, a falling edge also occurs in the protection signal S_UVLO, and then a falling edge also occurs in the signal EN1. In this second case, the logic circuit 13 starts the detection signal S_DET at time t without waiting for the next cycle of the control signal Spwm. E2 The time t immediately after E3 In response to the high-level control signal Spwm, the transistor MH is switched from off to on (at time t E1 At time t E2 and tE3 (The falling edge of the control signal Spwm occurs after time t E1 After the output stage circuit MM is set to the output low state at time t E3 (However, there is a setting of both OFF states due to dead time.) This makes it possible to reduce the drop in the output voltage Vout.

[0152] The logic circuit 13 detects the time t E3 After that, when the command signal SW_EN is set to a low level, or at time t E3 Thereafter, when a certain time has elapsed since the fall edge occurred in the command signal SW_EN, the latch circuit 76 can unlatch the protection signal S_UVLO and return the level of the protection signal S_UVLO to the initial level (high level).

[0153] 24 is a timing chart relating to the third case, showing the timing around the start of switching control after a short period of stopping of the switching control. After the switching control is performed and the switching control is stopped at the falling edge of the command signal SW_EN, if a rising edge occurs in the command signal SW_EN before the length of the stopping period of the switching control reaches the above-mentioned discharge reference time Tdis (see FIGS. 13 to 15), it is considered that the discharge of the boot capacitor Cboot has hardly progressed. Therefore, as shown in FIG. 24, the logic circuit 13 may directly transition the output stage circuit MM from the both-off state to the output high state without performing charge control that involves turning on the transistor ML.

[0154] <<Example EX2_4>> An example EX2_4 will be described. FIG. 25 shows the configuration of a monitor circuit 17d, which is the monitor circuit 17 according to the example EX2_4. The monitor circuit 17d includes a transistor 77 (insertion transistor), a comparator 74, a reference voltage source 75, and a latch circuit 76. The transistor 77 is an N-channel MOSFET. In the monitor circuit 17c of FIG. 20, the voltage between the voltages Vboot and VSS is divided before being input to the comparator 74. However, in the monitor circuit 17d of FIG. 25, the boot voltage Vboot is clamped by the transistor 77, thereby preventing an overvoltage from being input to the comparator 74.

[0155] Specifically, the drain of the transistor 77 is connected to the boot terminal BOOT and the boot wiring W_boot and receives the boot voltage Vboot. The source of the transistor 77 is connected to the node ND3. That is, the transistor 77 is provided between the boot wiring W_boot and the node ND3. The power supply voltage VDD of the switching control circuit 11 is input to the gate of the transistor 77. The voltage at the node ND3 is referred to as a voltage Vx4. The transistor 77 limits the voltage Vx4 to a voltage (VDD-Vth77) or less so that the voltage Vx4 does not exceed the withstand voltage of the comparator 74. The voltage (VDD-Vth77) is a voltage lower than the power supply voltage VDD by the gate threshold voltage Vth77 of the transistor 77. The lower of the boot voltage Vboot and the voltage (VDD-Vth77) is applied to the node ND3.

[0156] The comparator 74, reference voltage source 75, and latch circuit 76 in the monitor circuit 17d have the same configuration and perform the same operations as the comparator 74, reference voltage source 75, and latch circuit 76 in the monitor circuit 17c (FIG. 20). However, in the monitor circuit 17d, the inverting input terminal of the comparator 74 is connected to the node ND3 and receives the voltage Vx4 at the node ND3. Also, in the monitor circuit 17d, the reference voltage source 75 generates a predetermined positive reference voltage Vy4 based on the ground potential and supplies it to the non-inverting input terminal of the comparator 74. Therefore, the comparator 74 in the monitor circuit 17d compares the voltage Vx4 at its inverting input terminal with the voltage Vy4 at its non-inverting input terminal and outputs a detection signal S_DET indicating their high and low relationship. The detection signal S_DET in the monitor circuit 17d has a high level when "Vx4 < Vy4" holds, a low level when "Vx4 > Vy4" holds, and a low level or a high level when "Vx4 = Vy4" holds. The reference voltage Vy4 is lower than the voltage (VDD - Vth77).

[0157] The voltage Vx4 during the on-period of the transistor ML is particularly referred to as the evaluation voltage Vx4. As described above, since the switch voltage Vsw substantially coincides with the voltage VSS during the on-period of the transistor ML, if "Vboot < VDD - Vth77", the evaluation voltage Vx4 is substantially equal to the monitored voltage Vmnt. That is, the monitor circuit 17d can generate an evaluation voltage Vx4 corresponding to the monitored voltage Vmnt (= Vboot - Vsw) at the node ND3 during the on-period of the transistor ML. The monitor circuit 17d determines whether to supply the above low-voltage release signal to the logic circuit 13 by comparing the evaluation voltage Vx4 with the reference voltage Vy4. If "Vboot ≧ VDD - Vth77" during the on-period of the transistor ML, a voltage (VDD - Vth77) higher than the reference voltage Vy4 is supplied to the inverting input terminal of the comparator 74 and a low-level detection signal S_DET is generated. However, since the state where "Vboot ≧ VDD - Vth77" during the on-period of the transistor ML corresponds to the state where "Vmnt ≧ Vth_UVLO", there is no problem.

[0158] The detection signal S_DET is invalid when the output stage circuit MM is in the output high state or both OFF states. The logic circuit 13 supplies the latch circuit 76 with a signal EN1 for controlling the latch operation of the latch circuit 76. When controlling the charging of the boot capacitor Cboot, the logic circuit 13 only needs to set the signal EN1 to a high level during the ON period of the transistor ML. The logic circuit 13 sets the signal EN1 to a low level during the period when the output stage circuit MM is set to the output high state and during the period when the output stage circuit MM is set to the both OFF states. The latch circuit 76 invalidates the detection signal S_DET during the low level period of the signal EN1, and does not respond to the detection signal S_DET during the low level period of the signal EN1.

[0159] In the initial state of the power supply control device 10, the protection signal S_UVLO from the latch circuit 76 has a high level, and the protection signal S_UVLO generally has a high level. The latch circuit 76 monitors the level of the detection signal S_DET during the high-level period of the signal EN1 (thus during the on-period of the transistor ML). Then, during the high-level period of the signal EN1, when a falling edge occurs in the detection signal S_DET, the latch circuit 76 latches the low level of the detection signal S_DET, thereby switching the level of the protection signal S_UVLO from high to low (see FIG. 21). As described above, the low-level detection signal S_DET or the low-level protection signal S_UVLO functions as an undervoltage release signal (charging completion signal). The latch circuit 76 may be built into the logic circuit 13. Assuming that the transistor ML is on, each constant in the monitor circuit 17d is set so that the detection signal S_DET of the comparator 74 switches from high level to low level when the voltage (Vboot-Vsw) rises and reaches the threshold voltage Vth_UVLO.

[0160] The transistor 77 is a high-voltage element. The monitor circuit 17d of FIG. 25 does not require any other high-voltage element besides the transistor 77. Therefore, the size of the monitor circuit on the semiconductor chip can be reduced in the monitor circuit 17d of FIG. 25 compared to the monitor circuits 17a and 17b shown in Examples EX2_1 and EX2_2. The monitor circuit 17c of FIG. 20 uses voltage division, allowing the reference voltage Vy3 supplied to the comparator 74 to be freely set. In contrast, the monitor circuit 17d of FIG. 25 is constrained by the requirement that the reference voltage Vy4 be set lower than the voltage (VDD-Vth77). However, because the monitor circuit 17d does not use a voltage-dividing resistor, the input signal (Vx4) to the comparator 74 can have low impedance. As a result, the monitor circuit 17d is even less susceptible to the effects of parasitic capacitance than the monitor circuit 17c. Furthermore, the circuit current flowing through the voltage-dividing resistor is zero in the monitor circuit 17d.

[0161] <<Example EX2_5>> An example EX2_5 will be described. An explanation will be added about the operation when the monitor circuit 17c according to the example EX2_3 and the monitor circuit 17d according to the example EX2_4 are used as the monitor circuit 17 in FIG.

[0162] Both monitor circuits 17c and 17d employ a method of observing the monitored voltage Vmnt (=Vboot-Vsw) only during the on-period of transistor ML, and a voltage corresponding to the monitored voltage Vmnt is not generated in monitor circuits 17c and 17d during the off-period of transistor ML. The switching control circuit 11 maintains transistor MH in the off-state until an undervoltage release signal indicating that the monitored voltage Vmnt has reached the threshold voltage Vth_UVLO is supplied from monitor circuit 17c or 17d. The advantages of employing a method of observing the monitored voltage Vmnt only during the on-period of transistor ML are as shown in Example EX2_3 or EX2_4.

[0163] When the switching control circuit 11 starts the switching control in response to an execution command signal (high-level command signal SW_EN) commanding the execution of the switching control after keeping the transistors MH and ML off by stopping the switching control, the switching control circuit 11 executes charging control accompanied by observation of the monitored voltage Vmnt before starting the switching control. In the charging control, the switching control circuit 11 charges the boot capacitor Cboot by providing a charging period in which the transistor ML is turned on while keeping the transistor MH off, and causes the monitor circuit 17c or 17d to observe the monitored voltage Vmnt during the charging period.

[0164] As the charge control here, it is assumed that the charge control CC1 is used in the embodiment EX2_3 (see FIG. 22). The charge control CC1 may also be used in the embodiment EX2_4. In the charge control CC1, the switching control circuit 11 keeps the transistor ML on continuously until the low voltage release signal is output from the monitor circuit 17c or 17d.

[0165] However, in Examples EX2_3 and EX2_4, the charge control CC2 (see FIG. 11, etc.) described in the first embodiment may be used. In this case, the switching control circuit 11 may set the transistor ML to be intermittently on in the charge control CC2 until the monitor circuit 17c or 17d outputs an undervoltage release signal. Details of the operation of the switching control circuit 11 related to the charge control CC2 are as shown in the first embodiment.

[0166] In the second embodiment, when the charge control CC2 is used, the state transition of the logic circuit 13 may be as shown in FIG. 12 or FIG. 13. That is, when the switching control circuit 11 starts the switching control based on the reception of an execution command signal (high-level command signal SW_EN) after keeping the transistors MH and ML off by stopping the switching control, the switching control circuit 11 executes the charge control CC2 (operation of only state ST2 or operation involving a transition between states ST2 and ST3) before the start of the switching control, and does not execute the charge control CC2 during the execution period of the switching control. The same applies when the charge control CC1 is used in the second embodiment, and the state transition diagram of the logic circuit 13 is similar to FIG. 12 or FIG. 13. However, when the charge control CC1 is used, state ST3 is deleted from the state transition diagrams of FIG. 12 and FIG. 13, and it is understood that there is no transition between states ST2 and ST3. When the charging control CC1 is used, as when the charging control CC2 is used, the switching control circuit 11 keeps the transistors MH and ML off by stopping the switching control, and then, when starting the switching control based on receiving an execution command signal (high-level command signal SW_EN), executes the charging control CC1 (operation only in state ST2) before starting the switching control, and does not execute the charging control CC1 during the execution period of the switching control.

[0167] In the second embodiment, when the logic circuit 13 uses the charge control CC1 or CC2 and the state transition of the logic circuit 13 conforms to FIG. 13 , the switching control circuit 11 operates as follows. That is, when the logic circuit 13 receives an execution command signal (high-level command signal SW_EN) commanding execution of switching control while the logic circuit 13 is in state ST1, the switching control circuit 11 transitions through charge control CC1 or CC2 to state ST4 and starts switching control. The charge control CC1 is realized only in state ST2. The charge control CC2 may be realized only in state ST2, or may involve a transition between states ST2 and ST3. Thereafter, when the switching control circuit 11 receives a stop command signal (low-level command signal SW_EN) commanding termination of the switching control, the switching control circuit 11 stops the switching control and measures the elapsed time Tstp since termination of the switching control based on the stop command signal. When the switching control circuit 11 receives an execution command signal (high-level command signal SW_EN) again after the elapsed time Tstp reaches the discharge reference time Tdis, the switching control circuit 11 resumes switching control after going through charge control CC1 or CC2 again, as shown in Fig. 26. On the other hand, when the switching control circuit 11 receives an execution command signal again before the elapsed time Tstp reaches the discharge reference time Tdis, the switching control circuit 11 resumes switching control without going through charge control CC1 or CC2 again, as shown in Fig. 27.

[0168] <<Supplementary Information>> Supplementary notes regarding the above-described embodiments will be explained below.

[0169] 1 can be mounted in any electrical equipment, such as electrical equipment mounted in a vehicle such as an automobile, a computer, a home appliance, or an industrial device.

[0170] A composite power supply may be formed that includes the switching power supply 1. The composite power supply may include a plurality of switching power supplies, or may include one or more switching power supplies (switching regulators) and one or more linear regulators. The power supply control device provided in the composite power supply may be a so-called PMIC (Power Management IC).

[0171] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0172] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0173] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0174] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0175] <<Addendum 1>> The first appendix will be provided mainly regarding the technology corresponding to the first embodiment.

[0176] A power supply control device according to one aspect of the present disclosure (see FIGS. 1 and 11) is a power supply control device (10) provided in a switching power supply device (1) configured to generate an output voltage (Vout) from an input voltage (Vin) by DC / DC conversion, wherein the switching power supply device is provided with an output stage circuit (MM) having a high-side transistor (MH) provided between an application terminal (IN) of the input voltage and a switch terminal (SW) and a low-side transistor (ML) provided between the switch terminal and a ground terminal (GND) having a ground potential lower than the input voltage, and the output voltage is generated by rectifying and smoothing a switch voltage (Vsw) generated at the switch terminal through on / off control of the high-side transistor and the low-side transistor using a coil (L1) and an output capacitor (Cout), and the current control device includes a high-side driver (14) configured to drive a gate of the high-side transistor, a low-side driver (15) configured to drive a gate of the low-side transistor, and a feedback voltage (Vfb) corresponding to the output voltage. a boot terminal (BOOT) connected to the switch terminal via a boot capacitor (Cboot) and configured to receive a boot voltage (Vboot) that functions as a high-potential-side power supply voltage in the high-side driver; a rectifier element (Dboot) configured to supply a charging current to the boot capacitor by bringing the switch terminal to a low potential side during an on-period of the low-side transistor; a backflow detection circuit (16) configured to detect a specific backflow state in which a predetermined amount or more of backflow current flows from an output terminal (OUT) to which the output voltage is applied toward the low-side transistor via the coil and the switch terminal; and a monitor circuit (17) configured to monitor the level of the boot voltage relative to the switch voltage as a monitored voltage (Vmnt), and the switching control circuit controls the state of the output stage circuit to be one of an output high state in which the high-side transistor is on and the low-side transistor is off,The switching control circuit is configured to set the output stage circuit to the output low state in which the high-side transistor is off and the low-side transistor is on, or to a double-off state in which both the high-side transistor and the low-side transistor are off, and after setting the output stage circuit to the output low state when the monitored voltage is lower than a threshold voltage (Vth_UVLO), maintains the output stage circuit in the output low state until the monitored voltage reaches the threshold voltage or the specific backflow state is detected, and if the specific backflow state is detected before the monitored voltage reaches the threshold voltage while the output stage circuit is set to the output low state, performs a backflow limiting operation (J2) that switches the state of the output stage circuit to the double-off state and maintains the output stage circuit in the double-off state for a predetermined waiting time (Tw) before returning to the output low state, and allows the output stage circuit to be set to the output high state when the monitored voltage reaches the threshold voltage (hereinafter referred to as configuration A1).

[0177] This prevents large reverse currents from occurring when charging the boot capacitor, protecting the low-side transistor from excessive reverse current. It also prevents excessive drops in output voltage due to reverse current, and reduces the adverse effects of a drop in output voltage on the load (a load driven by the output voltage).

[0178] In the power supply control device according to the above-described configuration A1 (see FIGS. 1 and 11), the switching control circuit may be configured to start switching control for alternately turning on and off the high-side transistor and the low-side transistor based on a control signal (Spwm) generated according to the feedback voltage after the monitored voltage reaches the threshold voltage (hereinafter referred to as configuration A2).

[0179] In the power supply control device according to the above-described configuration A2 (see FIG. 9 and FIG. 10), the backflow detection circuit is configured to be able to detect a first backflow state in which the magnitude of the backflow current exceeds a first current threshold (Isht1) during the period in which the switching control is being executed, and the switching control circuit sets the output stage circuit to the output low state based on the control signal during the period in which the switching control is being executed, and then, when the first backflow state is detected by the backflow detection circuit, executes a backflow prevention operation (J1) in which the output stage circuit is switched from the output low state to the both-off state regardless of the control signal, and the backflow detection circuit may be configured to detect, as the specific backflow state, a second backflow state in which the magnitude of the backflow current exceeds a second current threshold (Isht2) that is larger than the first current threshold, using a circuit common to the circuit for detecting the first backflow state (hereinafter referred to as configuration A3).

[0180] Efficiency is improved under light loads by the backflow prevention operation that occurs when the first backflow state is detected. By using a circuit that is also used to improve efficiency under light loads and shifting the current threshold, it is possible to detect a specific backflow state (second backflow state) when charging the boot capacitor. As a result, the amount of circuitry that needs to be added to achieve backflow limiting operation is minimal (and the increase in chip cost is minimal).

[0181] In the power supply control device according to the above configuration A2 or A3 (see FIG. 11), when the switching control circuit starts the switching control in response to an execution command signal (high-level command signal SW_EN) commanding the execution of the switching control, the switching control circuit executes charging control (CC2) before the start of the switching control, and in the charging control, the switching control circuit sets the output stage circuit to the output low state when the monitored voltage is lower than the threshold voltage, and then performs an operation of maintaining the output stage circuit in the output low state until the monitored voltage reaches the threshold voltage or the specific backflow state is detected, and performs the backflow limiting operation when the specific backflow state is detected before the monitored voltage reaches the threshold voltage when the output stage circuit is set to the output low state, and the switching control circuit may be configured to start the switching control after the monitored voltage reaches the threshold voltage after the start of the charging control (hereinafter referred to as configuration A4).

[0182] In the power supply control device according to the above-mentioned configuration A4 (see Figures 11 and 12), the switching control circuit may be configured to execute the charging control before the start of the switching control when the switching control is started based on receipt of the execution command signal after a period in which the switching control is stopped, and not execute the charging control during the period in which the switching control is executed (hereinafter referred to as configuration A5).

[0183] In the power supply control device according to the above configuration A4 or A5 (see Figures 13 to 15), the switching control circuit may be configured to receive the execution command signal, go through the charging control, and then start the switching control, and when it receives a stop command signal (low-level command signal SW_EN) instructing the stopping of the switching control, stop the switching control and measure the elapsed time (Tstp) since the switching control was stopped, and when it receives the execution command signal again after the elapsed time reaches a predetermined time (Tdis), it goes through the charging control again and resumes the switching control, and when it receives the execution command signal again before the elapsed time reaches the predetermined time, it resumes the switching control without going through the charging control again (hereinafter referred to as configuration A6).

[0184] This is expected to improve power efficiency or response performance compared to when charging control is always performed before switching control is started every time an execution command signal is received.

[0185] <<Second Note>> A second supplementary note is provided mainly regarding the technology corresponding to the second embodiment.

[0186] A power supply control device according to another aspect of the present disclosure (see FIG. 1 and FIG. 20 or FIG. 25) is a power supply control device (10) provided in a switching power supply device (1) configured to generate an output voltage (Vout) from an input voltage (Vin) by DC / DC conversion, wherein the switching power supply device is provided with an output stage circuit (MM) having a high-side transistor (MH) provided between an application terminal (IN) of the input voltage and a switch terminal (SW) and a low-side transistor (ML) provided between the switch terminal and a ground terminal (GND) having a ground potential lower than the input voltage, and the output voltage is generated by rectifying and smoothing a switch voltage (Vsw) generated at the switch terminal through on / off control of the high-side transistor and the low-side transistor, and the current control device includes a high-side driver (14) configured to drive a gate of the high-side transistor, a low-side driver (15) configured to drive a gate of the low-side transistor, and a feedback voltage (Vfb) corresponding to the output voltage. a boot terminal (BOOT) connected to the switch terminal via a boot capacitor (Cboot) and configured to receive a boot voltage (Vboot) that functions as a high-potential-side power supply voltage in the high-side driver; a rectifying element (Dboot) configured to set the switch terminal to a low potential side and supply a charging current to the boot capacitor during an on-period of the low-side transistor; and a monitor circuit (17) configured to monitor the level of the boot voltage relative to the switch voltage as a monitored voltage (Vmnt), wherein the monitor circuit observes the monitored voltage only during an on-period of the low-side transistor, and the switching control circuit maintains the high-side transistor in an off state until an undervoltage release signal indicating that the monitored voltage has reached a threshold voltage (Vth_UVLO) is supplied from the monitor circuit (hereinafter referred to as configuration B1).

[0187] During the on-period of the low-side transistor, the voltage between the boot terminal and the switch terminal is substantially equal to the voltage between the boot terminal and the ground terminal. Therefore, by detecting the voltage between the boot terminal and the ground terminal during the on-period of the low-side transistor, it is possible to observe the voltage between the boot terminal and the switch terminal (i.e., the monitored voltage). By adopting this method, it is possible to reduce the number of high-voltage elements used, and therefore the size of the monitor circuit.

[0188] In the power supply control device according to the above-described configuration B1 (see FIG. 20), the monitor circuit may have a voltage divider circuit (71, 72) provided between a reference wiring (W_VSS) having the ground potential and a boot wiring (W_boot) to which the boot voltage is applied, and the voltage divider circuit divides the voltage between the reference wiring and the boot wiring during the on-period of the low-side transistor to generate an evaluation voltage (Vx3) corresponding to the voltage to be monitored, and may have a configuration (hereinafter referred to as configuration B2) that determines whether or not to supply the low voltage release signal to the switching control circuit based on the evaluation voltage.

[0189] This allows for a reduction in the number of high-voltage elements used, thereby enabling a reduction in the size of the monitor circuit. Furthermore, by adopting a method of observing the voltage to be monitored only during the on-period of the low-side transistor, the operation of the monitor circuit can be stopped in sleep mode, etc. Therefore, the magnitude of the circuit current is less of an issue, and the voltage divider circuit can be formed using resistors with sufficiently low resistance values. As a result, although a relatively large parasitic capacitance is added to the high-voltage element, the influence of the parasitic capacitance is unlikely to occur. In addition, by adopting a method of observing the voltage to be monitored only during the on-period of the low-side transistor, there is no risk of malfunction during transitions in the switch voltage.

[0190] In the power supply control device according to the above-described configuration B2, the voltage divider circuit may include a first voltage dividing resistor (71) provided between the boot wiring and the first node, a second voltage dividing resistor (72) provided between the second node and the reference wiring, and an insertion transistor (73) inserted between the first node and the second node and controlled to be on during an on-period of the low-side transistor, and the monitor circuit may be configured to use the voltage at the second node during an on-period of the low-side transistor and the insertion transistor as the evaluation voltage, and to determine whether or not to supply the undervoltage release signal to the switching control circuit by comparing the evaluation voltage with a voltage (Vy3) that is higher by a predetermined voltage than the ground potential (hereinafter referred to as configuration B3).

[0191] In the power supply control device according to the above-described configuration B1 (see FIG. 25), the monitor circuit may have an insertion transistor (77) that is arranged between a boot wiring (W_boot) to which the boot voltage is applied and a specific node (ND3) and that is configured to receive a power supply voltage (VDD) of the switching control circuit at its gate, and may generate an evaluation voltage (Vx4) corresponding to the monitored voltage at the specific node during the on-period of the low-side transistor, and determine whether or not to supply the low voltage release signal to the switching control circuit based on the evaluation voltage (hereinafter referred to as configuration B4).

[0192] This allows for a reduction in the number of high-voltage elements used, thereby enabling a reduction in the size of the monitor circuit. Although relatively large parasitic capacitance is added to the high-voltage elements, the absence of voltage-dividing resistors allows for low signal impedance at specific nodes, making the effects of parasitic capacitance less likely to occur. Furthermore, because the method of observing the monitored voltage only during the on-period of the low-side transistor is adopted, there is no risk of malfunction during transitions in the switch voltage.

[0193] In the power supply control device according to the above-described configuration B4, the lower of the boot voltage and a voltage that is lower than the power supply voltage of the switching control circuit by the gate threshold voltage of the insertion transistor may be applied to the specific node, and the monitor circuit may be configured to determine whether to supply or not supply the low voltage release signal to the switching control circuit by comparing the evaluation voltage with a voltage (Vy4) that is higher than the ground potential by a predetermined voltage (hereinafter referred to as configuration B5).

[0194] In the power supply control device according to any of the above configurations B1 to B5, the switching control circuit may be capable of performing switching control to alternately turn on and off the high-side transistor and the low-side transistor based on a control signal (Spwm) generated according to the feedback voltage, and may be configured to start the switching control after receiving the low voltage release signal (hereinafter referred to as configuration B6).

[0195] In the power supply control device according to the above-described configuration B6, when the switching control circuit starts the switching control in response to an execution command signal (high-level command signal SW_EN) that commands the execution of the switching control after keeping the high-side transistor and the low-side transistor off by stopping the switching control, the switching control circuit executes charging control (CC1 or CC2) that involves observing the voltage to be monitored before the start of the switching control, and the switching control circuit charges the boot capacitor by providing a charging period in which the high-side transistor is kept off and the low-side transistor is turned on in the charging control, and the switching control circuit may have the monitor circuit observe the voltage to be monitored during the charging period (hereinafter referred to as configuration B7).

[0196] In the power supply control device according to the above-described configuration B7, the switching control circuit may be configured to keep the low-side transistor on continuously during the charging control until the low voltage release signal is output from the monitor circuit (hereinafter referred to as configuration B8).

[0197] In the power supply control device according to the above-mentioned configuration B7, the switching control circuit may be configured to intermittently turn on the low-side transistor during the charging control until the low voltage release signal is output from the monitor circuit (hereinafter referred to as configuration B9).

[0198] In the power supply control device according to any of the above configurations B7 to B9, the switching control circuit may be configured to execute the charging control before the start of the switching control when the switching control is started based on receipt of the execution command signal after a period during which the switching control is stopped, and not execute the charging control during the period during which the switching control is executed (hereinafter referred to as configuration B10).

[0199] In the power supply control devices according to the above configurations B7 to B9 (see Figures 26 and 27), the switching control circuit may be configured to receive the execution command signal, go through the charging control, and then start the switching control, and when it receives a stop command signal (low-level command signal SW_EN) commanding the stopping of the switching control, stop the switching control and measure the elapsed time (Tstp) since the switching control was stopped, and when it receives the execution command signal again after the elapsed time reaches a predetermined time (Tdis), it goes through the charging control again and resumes the switching control, and when it receives the execution command signal again before the elapsed time reaches the predetermined time, it resumes the switching control without going through the charging control again (hereinafter referred to as configuration B11).

[0200] This is expected to improve power efficiency or response performance compared to when charging control is always performed before switching control is started every time an execution command signal is received. [Explanation of symbols]

[0201] 1. 1A switching power supply 10 Power supply control device Vin Input voltage Vout Output voltage Vsw Switch voltage Vfb Feedback voltage Vboot Boot voltage VDD power supply voltage IL Coil current Iout Load current IN input terminal SW Switch terminal GND Ground terminal BOOT Boot terminal FB Feedback terminal OUT output terminal L1 coil R1, R2 feedback resistors Cout Output capacitor LD load MM output stage circuit MH, ML transistors 11 Switching control circuit 12 PWM circuit 13 Logic Circuits 14 High-side driver 15 Low-side driver 16 Backflow detection circuit 17 Monitor circuit 18 Light Load Detection Comparator 19, 19A Switching Management Circuit Dboot diode Vref1, Vref2 reference voltage SPWM control signal INH, INL drive command signal GH, GL gate signals Srvs Backflow detection signal S_UVLO protection signal SLP Sleep signal SW_EN, SW_EN[1], SW_EN[2] command signals Vmnt Monitored voltage Vth_UVLO threshold voltage 31 Error amplifier 32 Differential Amplifier 33 Lamp voltage generation circuit 34 Comparator Verr error voltage Isns voltage Vc comparison voltage Vramp Ramp voltage 41 Comparator 42 Sense resistor 43, 44 Resistance 45 Current source Isht, Isht1, Isht2 shift current BLK Unit circuit block 17a, 17b, 17c, 17d Monitor circuits W_boot Boot wiring W_VSS Reference wiring 51, 52 Voltage dividing resistor 53 Comparator 54 Reference voltage source 55 Level Shifter 55_1 Inverter circuit 55_2, 55_3 Transistors 55_4, 55_5 Resistor 55_6 Buffer circuit 61 Transistor 63, 64 Resistor 65 Comparator 66 Reference Voltage Source 71, 72 Voltage dividing resistor 73, 77 Transistor (insertion transistor) 74 Comparator 75 Reference voltage source 76 Latch Circuit Vx1~Vx4 voltage Vy1~Vy4 reference voltage

Claims

1. A power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage by DC / DC conversion, wherein the switching power supply device is provided with an output stage circuit having a high-side transistor provided between an application terminal of the input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal having a ground potential lower than the input voltage, and the output voltage is generated by rectifying and smoothing a switch voltage generated at the switch terminal through on / off control of the high-side transistor and the low-side transistor, The current control device comprises: a high-side driver configured to drive a gate of the high-side transistor; a low-side driver configured to drive a gate of the low-side transistor; a switching control circuit configured to control an on / off state of the high-side transistor and the low-side transistor using the low-side driver and the high-side driver based on a feedback voltage corresponding to the output voltage; a boot terminal connected to the switch terminal via a boot capacitor and configured to receive a boot voltage that functions as a high-potential side power supply voltage in the high-side driver; a rectifying element configured to supply a charging current to the boot capacitor by setting the switch terminal to a low potential side during an on-period of the low-side transistor; a monitor circuit configured to monitor the level of the boot voltage relative to the switch voltage as a monitored voltage; the monitor circuit observes the monitored voltage only during an on-period of the low-side transistor; The switching control circuit maintains the high-side transistor in an off state until an undervoltage release signal indicating that the monitored voltage has reached a threshold voltage is supplied from the monitor circuit. , power control device.

2. The monitor circuit has a voltage divider circuit provided between a reference wiring having the ground potential and a boot wiring to which the boot voltage is applied, and generates an evaluation voltage corresponding to the voltage to be monitored by dividing the voltage between the reference wiring and the boot wiring by the voltage divider circuit during an on-period of the low-side transistor, and determines whether to supply or not supply the undervoltage release signal to the switching control circuit based on the evaluation voltage. The power supply control device according to claim 1 .

3. the voltage dividing circuit includes a first voltage dividing resistor provided between the boot wiring and a first node, a second voltage dividing resistor provided between a second node and the reference wiring, and an insertion transistor inserted between the first node and the second node and controlled to be on during an on period of the low-side transistor; The monitor circuit uses the voltage at the second node during an on-period of the low-side transistor and the insertion transistor as the evaluation voltage, and determines whether to supply or not supply the undervoltage release signal to the switching control circuit by comparing the evaluation voltage with a voltage that is a predetermined voltage higher than the ground potential. The power supply control device according to claim 2 .

4. The monitor circuit has an insertion transistor that is provided between a boot line to which the boot voltage is applied and a specific node and that is configured to receive a power supply voltage of the switching control circuit at its gate, and generates an evaluation voltage corresponding to the monitored voltage at the specific node during an on-period of the low-side transistor, and determines whether to supply or not supply the undervoltage release signal to the switching control circuit based on the evaluation voltage. The power supply control device according to claim 1 .

5. a lower voltage of the boot voltage and a voltage that is lower than a power supply voltage of the switching control circuit by a gate threshold voltage of the insertion transistor is applied to the specific node; The monitor circuit determines whether to supply or not supply the undervoltage release signal to the switching control circuit by comparing the evaluation voltage with a voltage that is a predetermined voltage higher than the ground potential. The power supply control device according to claim 4 .

6. The switching control circuit is capable of performing switching control for alternately turning on and off the high-side transistor and the low-side transistor based on a control signal generated in response to the feedback voltage, and starts the switching control after receiving the low voltage release signal.

6. The power supply control device according to claim 1.

7. the switching control circuit, after maintaining the high-side transistor and the low-side transistor in an off state by stopping the switching control, executes charging control accompanied by observation of the monitored voltage before starting the switching control when starting the switching control in response to an execution command signal commanding execution of the switching control; the switching control circuit charges the boot capacitor by providing a charging period in which the high-side transistor is kept off and the low-side transistor is turned on in the charging control; The switching control circuit causes the monitor circuit to observe the monitored voltage during the charging period. The power supply control device according to claim 6 .

8. In the charging control, the switching control circuit continuously keeps the low-side transistor on until the low voltage release signal is output from the monitor circuit. The power supply control device according to claim 7 .

9. In the charging control, the switching control circuit intermittently turns on the low-side transistor until the low-voltage release signal is output from the monitor circuit. The power supply control device according to claim 7 .

10. When the switching control is started based on the reception of the execution command signal after a period during which the switching control is stopped, the switching control circuit executes the charging control before the start of the switching control, and does not execute the charging control during a period during which the switching control is executed. The power supply control device according to claim 7 .

11. The switching control circuit receives the execution command signal, performs the charging control, and then starts the switching control. When it receives a stop command signal instructing the stopping of the switching control, it stops the switching control and measures the elapsed time since the stopping of the switching control. When it receives the execution command signal again after the elapsed time reaches a predetermined time, it resumes the switching control after performing the charging control again. When it receives the execution command signal again before the elapsed time reaches the predetermined time, it resumes the switching control without performing the charging control again. The power supply control device according to claim 7 .

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