Semiconductor package

Abstract

To provide a semiconductor package in which an upper side wall of a mold via has large surface roughness and adhesion between the upper side wall of the mold via and a mold film is improved to prevent peeling between them.SOLUTION: A first substrate RD1, a semiconductor element CH disposed on the first substrate RD1, a mold layer RD1 covering the first substrate MD1 and the semiconductor element CH, a second substrate RD2 disposed on the mold layer MD1, and a mold via MV passing through the mold layer RD1 and connecting the first substrate RD2 to the second substrate SW3, wherein the mold via MV includes an upper sidewall, a lower sidewall, and a middle sidewall therebetween, SW1 SW2, A roughness of the upper sidewall SW3 is greater than a roughness of at least one of the lower sidewall SW1 and the middle sidewall SW2.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package with improved reliability. [Background technology]

[0002] Semiconductor packages are provided for mounting integrated circuit chips for use in electronic products. A semiconductor package typically comprises a semiconductor die mounted on a printed circuit board (PCB) and electrically connected to the board using bonding wires or bumps.

[0003] With the development of the electronics industry, improving the reliability and durability of semiconductor packages has become a constant challenge, and various research efforts in this area are underway. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,559,539 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned problems with conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package with improved reliability. [Means for solving the problem]

[0006] In order to achieve the above object, the semiconductor package according to the present invention comprises a first substrate, a semiconductor device disposed on the first substrate, a mold film covering the first substrate and the semiconductor device, a second substrate disposed on the mold film, and a mold via penetrating the mold film to connect the first substrate to the second substrate, wherein the mold via includes an upper sidewall and a lower sidewall, and the surface roughness of the upper sidewall is greater than the surface roughness of the lower sidewall.

[0007] In order to achieve the above object, the present invention provides a semiconductor package comprising a first substrate, a semiconductor device disposed on the first substrate, a mold film covering the first substrate and the semiconductor device, a second substrate disposed on the mold film, and a mold via penetrating the mold film to connect the first substrate to the second substrate, wherein the mold via includes an upper sidewall, a middle sidewall, and a lower sidewall, and the middle sidewall is not aligned with the upper sidewall or the lower sidewall.

[0008] In addition, a semiconductor package according to the present invention, which has been made to achieve the above-mentioned object, includes a first rewiring substrate, a semiconductor device disposed on the first rewiring substrate, a mold film covering the first rewiring substrate and the semiconductor device, a second rewiring substrate disposed on the mold film, and a mold via that penetrates the mold film and connects the first rewiring substrate to the second rewiring substrate, wherein the first rewiring substrate includes a plurality of first rewiring insulating films stacked on each other, and a first conductive pad and a second conductive pad that are disposed on an uppermost first rewiring insulating film in the first rewiring insulating film, the first conductive pad being connected to the semiconductor device, the second conductive pad being in contact with the mold via, the first conductive pad having a first width, and the second conductive pad having a second width larger than the first width, and the second rewiring substrate includes a plurality of second rewiring insulating films stacked on each other, and a second rewiring pattern that penetrates a lowermost second rewiring insulating film in the second rewiring insulating film and contacts the mold via.

[0009] A method for manufacturing a semiconductor package according to an embodiment of the present invention includes forming a first substrate including first and second conductive pads, forming a first photoresist film on the first substrate, forming a second photoresist film on the first photoresist film, patterning the first and second photoresist films to form a mold via hole exposing the second conductive pad, forming a mold via in the mold via hole, removing the second photoresist film, performing a roughness forming process on an upper surface and an upper sidewall of the mold via, removing the first photoresist film to expose the first substrate, mounting a semiconductor device on the first substrate, and forming a mold film covering the first substrate, the semiconductor device, and the mold via. [Effects of the Invention]

[0010] In the semiconductor package according to the present invention, the upper sidewall of the molded via has a large surface roughness, which improves the adhesive strength between the upper sidewall of the molded via and the mold film, thereby preventing peeling therebetween. Therefore, the reliability of the semiconductor package is improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view taken along line AA' of FIG. 1, showing a schematic configuration of the semiconductor package according to the embodiment of the present invention. [Figure 3A] FIG. 3 is an enlarged cross-sectional view of a portion 'P1' in FIG. 2. [Figure 3B] FIG. 3 is an enlarged cross-sectional view of a portion 'P1' in FIG. 2. [Figure 3C] FIG. 3 is an enlarged cross-sectional view of a portion 'P1' in FIG. 2. [Figure 4A] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4B] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4C] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4D] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4E] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4F] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4G] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4H] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4I] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4J] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4K] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 4L] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 5A] FIG. 4D is an enlarged cross-sectional view of a portion 'P2' of FIG. 4C. [Figure 5B] FIG. 4D is an enlarged cross-sectional view of a portion 'P2' of FIG. 4C. [Figure 6A] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 6B] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 6C] 3A to 3C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention. [Figure 7] FIG. 6C is an enlarged cross-sectional view of a portion 'P2' of FIG. 6B. [Figure 8A] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 8B] FIG. 8B is an enlarged cross-sectional view of a portion 'P1' of FIG. 8A. [Figure 9A] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 9B] FIG. 9B is an enlarged cross-sectional view of a portion 'P1' of FIG. 9A. [Figure 10] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] Next, specific examples of embodiments for carrying out a semiconductor package according to the present invention will be described with reference to the drawings.

[0013] In this specification, terms indicating a sequence such as first, second, etc. are used to distinguish components having the same / similar functions from each other, and the numbers may be changed according to the order in which they are mentioned.

[0014] FIG. 1 is a plan view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line A-A' showing a schematic configuration of the semiconductor package of FIG. 1 according to an embodiment of the present invention, and FIGS. 3A to 3C are cross-sectional views showing an enlarged view of portion 'P1' of FIG. 2. 1 and 2, a semiconductor package 1000 according to an embodiment of the present invention includes a first substrate RD1, a semiconductor device CH, a first molding film MD1, a second substrate RD2, and a mold via MV.

[0015] Each of the first substrate RD1 and the second substrate RD2 may be a rewiring board, or a double-sided or multi-layer printed circuit board. The first substrate RD1 may be referred to as a 'first redistribution substrate', and the second substrate RD2 may be referred to as a 'second redistribution substrate'. The first substrate RD1 includes first insulating films (10a to 10e), under-bumps UBM, a first substrate internal pattern RC1, and first and second conductive pads (RP1, RP2). Each of the first insulating films (10a to 10e) can preferably be a PID (Photo-Imageable Dielectric). The under bump UBM, the first substrate inner pattern RC1, and the first and second conductive pads RP1 and RP2 are each formed of a conductive material. Each of the under bump UBM, the first substrate internal pattern RC1, and the first and second conductive pads (RP1, RP2) may include at least one metal selected from titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, nickel, and gold.

[0016] The under bump UBM penetrates the first insulating film 10a, which is the lowest of the first insulating films (10a to 10e). External connection terminals SB are bonded to the under bumps UBM. The external connection terminals SB may be, for example, at least one of a solder ball, a conductive bump, or a conductive pillar. The external connection terminals SB may contain, for example, at least one of tin, nickel, silver, copper, gold, and aluminum.

[0017] The first internal substrate pattern RC1 is interposed between the first insulating films (10a to 10e) and penetrates part of them. The first and second conductive pads (RP1, RP2) are arranged on the uppermost first insulating film 10e among the first insulating films (10a to 10e), and penetrate the uppermost first insulating film 10e. The second substrate RD2 includes second insulating films (20a to 20c), a second substrate internal pattern RC2, and a third conductive pad RP3. Each of the second insulating films (20a to 20c) is preferably a PID (Photo-Imageable Dielectric). The second substrate internal pattern RC2 and the third conductive pad RP3 are each formed of a conductive material. Each of the second substrate internal pattern RC2 and the third conductive pad RP3 may include at least one of titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, nickel, and gold.

[0018] Referring to FIG. 3A, each of the first substrate internal pattern RC1 and the second substrate internal pattern RC2 includes a diffusion barrier film BM and a wiring portion EP. The diffusion barrier film BM covers the lower surface of the wiring portion EP. The diffusion barrier film BM may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The wiring portion EP includes a metal such as copper, aluminum, nickel, or gold. Each of the first substrate internal pattern RC1 and the second substrate internal pattern RC2 includes a via portion VP that penetrates one of the first insulating films (10a to 10e) and the second insulating films (20a to 20c), and a line portion LP and a pad portion PP thereon. The width of the via portion VP becomes narrower as it goes downward. Each of the first substrate internal pattern RC1 and the second substrate internal pattern RC2 is also called a 'rewiring pattern'.

[0019] Referring to FIGS. 1 to 3A, the first to third conductive pads (RP1, RP2, RP3) also include a diffusion barrier film BM. The first conductive pad RP1 is disposed in the center of the first substrate RD1 and overlaps the semiconductor device CH. The second conductive pads RP2 are arranged on the edge of the first substrate RD1 and are in contact with the mold vias MV, respectively. Each of the first and second conductive pads (RP1, RP2) also includes a via portion VP and a pad portion PP, like the first and second substrate internal patterns RC1 and RC2. Each of the first and second conductive pads (RP1, RP2) is also called a 'redistribution pad'. Each of the first conductive pads RP1 has a first width W1. Each of the second conductive pads RP2 has a second width W2 that is greater than the first width W1.

[0020] The semiconductor device CH is also called a semiconductor chip or a semiconductor die. The semiconductor device CH may be one selected from a memory element chip such as a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, a ReRAM chip, an HBM (high bandwidth memory) chip, an HMC (hybrid memory cubic) chip, etc., a MEMS (microelectromechanical system) element chip, or a custom semiconductor (Application-Specific Integrated Circuit: ASIC) chip. The semiconductor device CH has chip conductive pads 30 arranged at the bottom end.

[0021] The first internal connection member IB1 is interposed between the chip conductive pad 30 and the first conductive pad RP1 to connect them to each other. The first internal connection member IB1 may be, for example, at least one of a solder ball, a conductive bump, or a conductive pillar. The first internal connection member IB1 may include, for example, at least one of tin, nickel, silver, copper, gold, and aluminum.

[0022] An underfill film UF is interposed between the semiconductor device CH and the first substrate RD1. The underfill film UF is made of a non-conductive film (NCF). The underfill film UF includes a thermosetting resin or a photocurable resin. The underfill film UF may further include an organic filler or an inorganic filler. The organic filler includes, for example, a polymeric material. The inorganic filler includes, for example, silicon oxide (SiO2). A first molding layer MD1 covers the semiconductor device CH and the first substrate RD1. The first molding layer MD1 may include an insulating resin such as an epoxy molding compound (EMC). The first molding layer MD1 may further include a filler, which may be dispersed within the insulating resin.

[0023] Referring to FIG. 3A, each of the mold vias MV penetrates the first mold film MD1. The mold vias MV electrically connect the first substrate RD1 to the second substrate RD2. Each mold via MV has a lower portion MP1 and an upper portion MP3 that are integrally formed with each other, and a middle portion MP2 therebetween. Each mold via MV has a lower sidewall SW1 and an upper sidewall SW3 connected to each other, and an intermediate sidewall SW2 therebetween. The lower sidewall SW1, the middle sidewall SW2, and the upper sidewall SW3 are vertically aligned with each other. The surface roughness of the upper sidewall SW3 is greater than the surface roughness of at least one of the lower sidewall SW1 and the middle sidewall SW2. Each of the mold vias MV has a first vertical length H1. The upper sidewall SW3 has a second vertical length H2. The second vertical length H2 corresponds to 1 / 12 to 11 / 12 of the first vertical length H1. In the present invention, the surface roughness of the upper sidewall SW3 of the mold via MV is large, so that the adhesive strength between the upper sidewall SW3 of the mold via MV and the first mold film MD1 is increased, preventing peeling therebetween. Therefore, the reliability of the semiconductor package 1000 is improved.

[0024] Referring to FIG. 3B, the middle sidewall SW2 of the mold via MV may not be vertically aligned with at least one of the bottom sidewall SW1 and the top sidewall SW3. Alternatively, the bottom sidewall SW1 may not be vertically aligned with at least one of the middle sidewall SW2 and the top sidewall SW3. The rest of the structure is identical to that of FIG. 3A.

[0025] Referring to FIG. 3C, each mold via MV further includes a first insert portion MP12 between the lower portion MP1 and the middle portion MP2, which are integrally formed with each other, and a second insert portion MP23 between the middle portion MP2 and the upper portion MP3. The edges (PT1, PT2) of the first insertion portion MP12 and the second insertion portion MP23 protrude further laterally than the side walls (SW1 to SW3). Each of the edges (PT1, PT2) of the first insert part MP12 and the second insert part MP23 is called a 'protrusion'. The rest of the structure is identical to that of FIG. 3A.

[0026] 4A to 4L are sequential cross-sectional views illustrating the process of manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention, and FIGS. 5A and 5B are enlarged cross-sectional views of the 'P2' portion of FIG. 4C. Referring to FIG. 4A, a sacrificial substrate 100 is provided. The sacrificial substrate 100 can be, for example, a tape, a transparent glass substrate, or a bare wafer. A sacrificial film 110 is formed on a sacrificial substrate 100 . The sacrificial film 110 includes an epoxy resin. The sacrificial film 110 has, for example, photodecomposable or thermodecomposable properties.

[0027] On the sacrificial film 110, a first substrate RD1 is formed. The first substrate RD1 is formed to include first insulating films (10a to 10e), under-bumps UBM, a first substrate internal pattern RC1, and first and second conductive pads (RP1, RP2). The first insulating films (10a to 10e) are preferably each made of a PID (Photo-Imageable Dielectric) and are formed through coating, baking, exposure, and development processes. The under bump UBM, the first substrate inner pattern RC1, and the first and second conductive pads RP1 and RP2 are formed through a plating process. The first and second conductive pads (RP1, RP2) are formed on the uppermost first insulating film 10e among the first insulating films (10a to 10e).

[0028] Referring to FIG. 4B, first to third photoresist films (PR1 to PR3) are sequentially stacked on the uppermost first insulating film 10e among the first insulating films (10a to 10e) and the first and second conductive pads (RP1, RP2). Each of the first to third photoresist films (PR1 to PR3) is formed through a coating and baking process. Each of the first to third photoresist films (PR1 to PR3) is formed to a thickness of, for example, 100 to 120 μm. In the present invention, the first to third photoresist films (PR1 to PR3) are formed in three layers, but the present invention is not limited to this, and one or more photoresist films may be formed. The number of layers and thicknesses of the first to third photoresist films (PR1 to PR3) can be changed along the vertical length of the mold via MV to be formed.

[0029] Referring to FIGS. 4C, 5A, and 5B, the exposure step and the development step are alternately repeated to form mold via holes MH in the first to third photoresist films (PR1 to PR3). The mold via hole MH exposes the top surface of the second conductive pad RP2. Specifically, a first exposure process and a first development process are performed on the uppermost third photoresist film PR3 to form a first opening in the third photoresist film PR3 and expose the sidewall (PR3_S) of the third photoresist film PR3. Next, a second exposure process and a second development process are performed on the second photoresist film PR2 below the first opening to form a second opening in the second photoresist film PR2 and expose the sidewall (PR2_S) of the second photoresist film PR2. Next, a third exposure process and a third development process are performed on the first photoresist film PR1 under the second opening to form a third opening in the first photoresist film PR1 and expose the sidewall (PR1_S) of the first photoresist film PR1. Therefore, a molded via hole MH is formed where the first to third openings are aligned. The reason why the exposure process and development process are performed multiple times on the first to third photoresist films (PR1 to PR3) is because it is difficult for light to pass through all of the first to third photoresist films (PR1 to PR3) at once.

[0030] If no misalignment occurs in the position of the photomask during the exposure process, the sidewalls (PR1_S to PR3_S) of the first to third photoresist films (PR1 to PR3) exposed in the mold via holes MH will be aligned as shown in FIG. 5A. At this time, the mold via MV formed in the mold via hole MH of FIG. 5A has sidewalls (SW1 to SW3) aligned with each other as in FIG. 3A. However, if misalignment occurs in the position of the photomask during the exposure process, the sidewalls (PR1_S to PR3_S) of the first to third photoresist films (PR1 to PR3) exposed to the mold via hole MH may not be aligned, as shown in Figure 5B. The molded via MV formed in the molded via hole MH of FIG. 5B has an intermediate sidewall SW2 that is shifted laterally as in FIG. 3B.

[0031] Referring to FIGS. 5A and 4D, a plating process is performed to form mold vias MV in the mold via holes MH, respectively. In the plating process, the top surface of the second conductive pad RP2 exposed at the bottom of the mold via hole MH serves as a seed. Each of the mold vias MV has a lower sidewall SW1, a middle sidewall SW2, an upper sidewall SW3, and an upper surface (MV_U). The lower sidewall SW1, the middle sidewall SW2, the upper sidewall SW3, and the upper surface (MV_U) are smooth. The lower sidewall SW1 contacts the sidewall (PR1_S) of the first photoresist film PR1. The intermediate sidewall SW2 contacts the sidewall (PR2_S) of the second photoresist film PR2. The upper sidewall SW3 contacts the sidewall (PR3_S) of the third photoresist film PR3.

[0032] Referring to FIG. 4E, the third photoresist film PR3 is removed to expose the top surface of the second photoresist film PR2. At this time, the smooth upper sidewall SW3 and upper surface MV_U of the mold via MV are exposed. The step of removing the third photoresist film PR3 is performed in an ashing step.

[0033] Referring to FIGS. 4F and 4G, a roughness forming process (PLZ) (or CZ process) is performed on the upper sidewall SW3 and upper surface (MV_U) of the mold via MV. Therefore, the surface roughness of the upper sidewall SW3 and upper surface (MV_U) of the mold via MV increases. The roughening step (PLZ) is carried out using an etchant or plasma. During the roughness forming process (PLZ), the first and second photoresist films (PR1, PR2) serve to protect the first conductive pads RP1 and the first insulating films (10a to 10e) on the surface of the first substrate RD1.

[0034] Referring to FIG. 4H, the first and second photoresist films PR1 and PR2 are removed to expose the first substrate RD1, and also the lower sidewall SW1 and middle sidewall SW2 of the mold via MV. The first and second photoresist films (PR1, PR2) are removed by an ashing process.

[0035] Referring to FIG. 4I, the semiconductor device CH is bonded onto the first conductive pad RP1 of the first substrate 1 using the first internal connection member IB1. Then, an underfill film UF is formed between the semiconductor device CH and the first substrate 1. A first molding film MD1 is formed so as to cover the semiconductor device CH, the first substrate RD1, and the mold vias MV.

[0036] Referring to FIG. 4J, a grinding process is performed on the first mold film MD1 to remove a portion of the first mold film MD1. During the grinding process, the upper part of the mold via MV is also partially removed. Therefore, the upper surface (MV_U) of the mold via MV is exposed. The upper surface MV_U of the mold via MV is formed to be coplanar with the upper surface of the first mold film MD1. The grinding process reduces the surface roughness of the upper surface (MV_U) of the mold via MV. Because the surface roughness of the upper sidewall SW3 of the mold via MV is large, the bonding force between the first mold film MD1 and the upper sidewall SW3 of the mold via MV is increased, and therefore peeling between the first mold film MD1 and the mold via MV does not occur during the grinding process.

[0037] Referring to FIG. 4K, a second substrate RD2 is formed on the first molding film MD1. The second substrate RD2 includes second insulating films (20a to 20c), a second substrate internal pattern RC2, and a third conductive pad RP3. The second insulating films (20a to 20c) are preferably each made of a PID (Photo-Imageable Dielectric) and are formed through coating, baking, exposure, and development processes. The second substrate internal pattern RC2 and the third conductive pad RP3 are formed through a plating process. Since there is no peeling between the first mold film MD1 and the mold vias MV in the grinding process, the second substrate RD2 can be manufactured without any defects. Therefore, the reliability of the semiconductor package 1000 is improved, and the yield can be improved.

[0038] Referring to FIG. 4L, the sacrificial film 110 and the sacrificial substrate 100 are separated from the bottom surface of the first substrate RD1. Next, referring to FIG. 2, the external connection terminals SB are bonded to the under bumps UBM of the first substrate RD1. Then, a single galling process is performed to manufacture the semiconductor package 1000.

[0039] 6A to 6C are cross-sectional views sequentially illustrating a process for manufacturing the semiconductor package of FIG. 2 according to an embodiment of the present invention, and FIG. 7 is an enlarged cross-sectional view showing a portion 'P2' of FIG. 6B.

[0040] Referring to FIG. 6A, in the state of FIG. 4A, a first photoresist film PR1, a first protective film SN1, a second photoresist film PR2, a second protective film SN2, and a third photoresist film PR3 are sequentially stacked on the topmost first insulating film 10e among the first insulating films (10a to 10e) and the first and second conductive pads (RP1, RP2). The first protective film SN1 and the second protective film SN2 are also called 'anti-reflection films'. The first protective film SN1 and the second protective film SN2 may be formed of silicon oxide, silicon nitride, or a material having etching selectivity with the photoresist film. Each of the first protective film SN1 and the second protective film SN2 is formed to have a thickness smaller than that of each of the first to third photoresist films (PR1 to PR3).

[0041] 6B and 7, the third photoresist film PR3, the second protective film SN2, the second photoresist film PR2, the first protective film SN1, and the first photoresist film PR1 are sequentially patterned to form a mold via hole MH. At this time, the first to third photoresist films (PR1 to PR3) are patterned by alternately repeating an exposure step and a development step. The first protective film SN1 and the second protective film SN2 are patterned by an isotropic etching process or an anisotropic etching process. When the first protective film SN1 and the second protective film SN2 are patterned by an isotropic etching process, the sidewalls (SN1_S) of the first protective film SN1 and the sidewalls (SN2_S) of the second protective film SN2 are rounded in the mold via hole MH.

[0042] Referring to FIG. 6C, the third photoresist film PR3 is removed to expose the top surface of the second passivation film SN2. At this time, the second protective film SN2 has etching selectivity with the second and third photoresist films PR2 and PR3, and therefore protects the second photoresist film PR2 when the third photoresist film PR3 is removed. Therefore, the degree to which the desired mold vias MV are exposed can be more accurately adjusted. Subsequently, the same / similar steps as those described with reference to FIGS. 4F to 4L are performed to manufacture the semiconductor package 1000 of FIG. At this time, the formed mold via MV has first and second protrusions PT1 and PT2 as shown in FIG. 3C. In this example, the first protective film SN1 can be omitted, in which case the mold via MV has only the second protruding portion PT2.

[0043] FIG. 8A is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention, and FIG. 8B is an enlarged cross-sectional view showing a portion 'P1' of FIG. 8A. 8A and 8B, in a semiconductor package 1001 according to this example, the shape of the first substrate RD1 is different from that in FIG.

[0044] The first substrate RD1 includes first insulating films (10a to 10d), under-bumps UBM, a first substrate inner pattern RC1, and first and second substrate upper patterns (RT1, RT2). Each of the first substrate internal pattern RC1 and the first and second substrate upper patterns RT1 and RT2 includes a via portion VP, a line portion LP, and a pad portion PP, just like the second substrate internal pattern RC2. However, in each of the first substrate inner pattern RC1 and the first and second substrate upper patterns (RT1, RT2), the line portion LP and the pad portion PP are disposed below the via portion VP. The width of the via portion VP of the first and second substrate upper patterns (RT1, RT2) becomes narrower as it goes up. Each of the first and second substrate upper patterns (RT1, RT2) is also called a 'rewiring pattern'. The first substrate upper pattern RT1 contacts each of the chip conductive pads 30 of the semiconductor device CH. The second substrate upper pattern RT2 contacts the lower surfaces of the mold vias MV. The lower surface of the semiconductor device CH is in contact with the upper surface of the first substrate RD1. The first internal connection member IB1 and the underfill film UF are not interposed between the semiconductor device CH and the first substrate RD1. The rest of the structure is the same / similar to that described above.

[0045] FIG. 9A is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention, and FIG. 9B is an enlarged cross-sectional view showing a portion 'P1' of FIG. 9A. 9A and 9B, the molded vias MV of the semiconductor package 1002 according to this example have a different structure from the molded vias MV of the semiconductor package 1001 of FIGS. 8A and 8B.

[0046] The surface roughness of the lower sidewall SW1 of the mold via MV according to this example is greater than the surface roughness of at least one of the middle sidewall SW2 and the upper sidewall SW3. The surface roughness of the upper side wall SW3 is small. Therefore, the adhesive strength between the lower sidewall SW1 of the mold via MV and the first mold film MD1 is improved, and peeling between them can be prevented. The lower sidewall SW1 of the mold via MV has a third vertical length H3. The third vertical length H3 of the lower sidewall SW1 corresponds to 1 / 12 to 11 / 12 of the first vertical length H1 of the mold via MV. The rest of the structure is the same / similar to that described with reference to Figures 8A and 8B. In the manufacturing process of semiconductor package 1002 according to this example, semiconductor device CH, first molding film MD1, and mold vias MV are formed first, and then first substrate RD1 is formed below first molding film MD1 and mold vias MV. Since there is no peeling between the first mold film MD1 and the mold vias MV, the first substrate RD1 can be formed without any defects.

[0047] FIG. 10 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 10, a semiconductor package 1003 according to this example has a package-on-package structure including a first sub-semiconductor package 400 and a second sub-semiconductor package 200 mounted thereon. The first sub-semiconductor package 400 has the same / similar structure as the semiconductor package 1000 described with reference to FIG.

[0048] The second sub-semiconductor package 200 is bonded to the third conductive pads RP3 of the second substrate RD2 of the first sub-semiconductor package 400 via second internal connection members IB2. The second sub-semiconductor package 200 includes a first sub-package substrate PS1, a second semiconductor device CH2 disposed thereon, a first adhesive film AD1 interposed between them, a second molding film MD2 covering them, and a first wire WR1 connecting the first sub-package substrate PS1 and the second semiconductor device CH2. The first subpackage substrate PS1 can be a double-sided or multi-layer printed circuit board. Alternatively, the first subpackage substrate PS1 may be another rewiring substrate. The second semiconductor device CH2 may be one selected from, for example, an image sensor chip such as a CIS (CMOS imaging sensor), a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, a ReRAM chip, an HBM (high bandwidth memory) chip, an HMC (hybrid memory cubic) chip, a MEMS (microelectromechanical system) element chip, or an ASIC (Application-Specific Integrated Circuit, custom semiconductor) chip.

[0049] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 11, a semiconductor package 1004 according to this example has a package-on-package structure including a first sub-semiconductor package 401 and a second sub-semiconductor package 200 mounted thereon. The first sub-semiconductor package 401 has a structure similar to that of the semiconductor package 1000 of FIG.

[0050] A passive element 300 is bonded to the bottom surface of the first substrate RD1 of the first sub-semiconductor package 401. The first substrate RD1 includes a first under bump UBM1 and a second under bump UBM2. The first under bump UBM1 and the second under bump UBM2 are formed of the same conductive material. The width of each of the second under bumps UBM2 is smaller than the width of each of the first under bumps UBM1. The height of each of the second under bumps UBM2 is the same as the height of each of the first under bumps UBM1. The external connection terminals SB are bonded to the first under bumps UBM1. The passive element 300 is bonded to the second under bump UBM2 via a third internal connection member IB3. The passive element 300 may be a capacitor or a resistor. A first underfill film UF1 is interposed between the semiconductor device CH and the first substrate RD1. A second underfill film UF2 is interposed between the passive element 300 and the first substrate RD1. The rest of the structure is the same / similar to that described with reference to FIG.

[0051] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. Moreover, the embodiments shown in FIGS. 1 to 11 can be combined with each other. [Explanation of symbols]

[0052] 1000 Semiconductor Packages 10a to 10e First insulating film 20a to 20c Second insulating film 30 Chip conductive pad BM diffusion barrier membrane CH Semiconductor Devices EP wiring section IB1 First internal connection member LP Line Section MD1 First mold film MD2 First mold film MP12 1st Insertion Section MP23 Second Insertion Section MV Moldvia PP pad PT1 1st protrusion PT2 2nd protrusion RC1 First board internal pattern RC2 Second board internal pattern RD1 First board RD2 2nd board RP1 First conductive pad RP2 Second conductive pad RP3 3rd conductive pad SB external connection terminal SW1 Lower Sidewall SW2 Intermediate side wall SW3 upper sidewall UBM Underbump UF underfill film VP Beer Department

Claims

1. a first substrate; a semiconductor device disposed on the first substrate; a molding film covering the first substrate and the semiconductor device; a second substrate disposed on the mold film; a mold via that penetrates the mold film and connects the first substrate to the second substrate; the molded via includes an upper sidewall and a lower sidewall; The semiconductor package has a surface roughness of the upper sidewall that is greater than a surface roughness of the lower sidewall.

2. the mold via further includes an intermediate sidewall between the upper sidewall and the lower sidewall; 2. The semiconductor package of claim 1, wherein the molded via has a protrusion that protrudes laterally from the middle sidewall and the lower sidewall.

3. the mold via further includes an intermediate sidewall between the upper sidewall and the lower sidewall; 2. The semiconductor package of claim 1, wherein the middle sidewall is not aligned with the top sidewall or the bottom sidewall.

4. 4. The semiconductor package of claim 3, wherein the surface roughness of the upper sidewall is greater than the surface roughness of the middle sidewall.

5. 2. The semiconductor package of claim 1, wherein the vertical length of the upper sidewall corresponds to 1 / 12 to 1 1 / 12 of the vertical length of the molded via.

6. The first substrate is a plurality of first insulating films stacked on top of each other; a first conductive pad and a second conductive pad disposed on a topmost first insulating film among the first insulating films; the first conductive pad is connected to the semiconductor device; the second conductive pad contacts the mold via; the first conductive pad has a first width; The semiconductor package of claim 1 , wherein the second conductive pad has a second width greater than the first width.

7. 2. The semiconductor package of claim 1, wherein an upper surface of the mold film is coplanar with an upper surface of the mold via.

8. 2. The semiconductor package of claim 1, wherein the surface roughness of the upper surface of the molded via is less than the surface roughness of the upper sidewall of the molded via.

9. a first substrate; a semiconductor device disposed on the first substrate; a molding film covering the first substrate and the semiconductor device; a second substrate disposed on the mold film; a mold via that penetrates the mold film and connects the first substrate to the second substrate; the molded via includes an upper sidewall, a middle sidewall, and a lower sidewall; The semiconductor package, wherein the middle sidewall is not aligned with the upper sidewall or the lower sidewall.

10. a first rewiring substrate; a semiconductor device disposed on the first rewiring substrate; a molding film covering the first rewiring substrate and the semiconductor device; a second rewiring substrate disposed on the molding film; a mold via that penetrates the mold film and connects the first rewiring substrate to the second rewiring substrate; The first rewiring substrate is a plurality of first redistribution insulating films stacked on top of each other; a first conductive pad and a second conductive pad disposed on an uppermost first redistribution insulating film in the first redistribution insulating film; the first conductive pad is connected to the semiconductor device; the second conductive pad contacts the mold via; the first conductive pad has a first width; the second conductive pad has a second width greater than the first width; The second rewiring substrate is a plurality of second redistribution insulating films stacked on top of each other; a second redistribution pattern that penetrates a lowermost second redistribution insulating film among the second redistribution insulating films and contacts the mold via.

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