Semiconductor equipment

Abstract

To provide a programmable logic device capable of achieving low power consumption while suppressing reduction in operation speed.SOLUTION: A first circuit, a second circuit, a first transistor which controls electrical connection between the first circuit and the second circuit in accordance with a potential of a gate of the first transistor, a first switch which controls supply of a signal to a first node, and a second switch which controls supply of the signal to a second node, wherein one of a source and a drain and a gate of the first transistor are electrically connected to the first node; A second transistor in which the other of the source and the drain is electrically connected to the second node; and a capacitor configured to hold a potential of the signal supplied to the first node.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device. and a programmable logic device capable of performing the above-mentioned programmable logic device. This invention relates to a semiconductor device using a chair. [Background technology]

[0002] Programmable Logic Device (PLD) The device is a logic circuit (logic block, programmable logic element) of an appropriate size. Each logic block is electrically connected to the other logic blocks by wiring resources. The feature of this technology is that the functions of the logic blocks and the connection structure between the logic blocks can be changed after manufacturing. The functions of each logic block and the interconnection structure between the logic blocks configured by the wiring resources are shown. is defined by the configuration data, and The data is stored in the registers of each logic block or the registers of the routing resources. Below, the register for storing configuration data is referred to as the configuration register. This is called ration memory.

[0003] In the following Non-Patent Document 1, an SRAM cell is passed through an isolator transistor. The circuit connected to the gate of the transistor configures the wiring resources of the FPGA (Fi The Field Programmable Gate Array (FGE) is described. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] F. Eslami and M. Sima, “Capacitive Boosting for FPGA Interconnection Networks” Int. Conf. on Field Programmable Logic and Applications, 2011, pp. 453-458. Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, low power consumption and high speed operation are the key factors behind programmable Both are important points when evaluating the performance of semiconductor devices such as logic devices. However, when the power supply voltage is reduced to reduce the power consumption of a semiconductor device, the transistor Since the on-state current is reduced, the operating speed of the semiconductor device is also reduced. There is a trade-off between reducing power consumption and increasing operating speed. It is not possible to simply reduce the power supply voltage just to reduce power consumption.

[0006] Also, a high voltage is applied to a node in a semiconductor device via an n-channel transistor. The potential of the bell drops by the threshold voltage of the transistor. Therefore, if the power supply voltage of the semiconductor device is reduced, the potential at the node inside the semiconductor device will be lowered. If the voltage becomes too high, the logic level of the signal output from the semiconductor device will change, resulting in data unreliability. Sexuality is likely to decline.

[0007] In light of the above-described technical background, one aspect of the present invention is to provide a low-power semiconductor memory device that can operate at a low speed while suppressing a decrease in operating speed. Programmable logic devices, programmable switches, Another object of the present invention is to provide a semiconductor device. programmable logic devices, and One of the objects is to provide a marble switch or a semiconductor device. [Means for solving the problem]

[0008] In one aspect of the present invention, a semiconductor device is provided by storing charge at a first node through a first switch. Data is written to the semiconductor device. Also, a charge is applied to the second node via the second switch. The data is written to the semiconductor device by storing the first The gates of the transistors are connected together. The first node and the second node are electrically connected together. The connection is controlled by a second transistor having a gate electrically connected to the first node. In addition, a capacitor is electrically connected to the first node.

[0009] In one aspect of the present invention, the first switch and the second switch have extremely small off-state currents. In addition, the off-state current of the second transistor is extremely small. By this configuration, when the first switch and the second transistor are in a non-conducting state, the first node is connected to another voltage. The above structure allows the capacitor to be in a floating state with extremely high insulation between the capacitor and the electrodes and wiring. By this configuration, when the second switch and the second transistor are in a non-conducting state, the second node is connected to another voltage. Therefore, the first When the switch, the second switch, and the second transistor are in a non-conductive state, the first node At the second node, the potential of a signal containing data is held.

[0010] When the potential of the signal is at a high level, the first switch and the second switch When the switch and the second transistor are in a non-conductive state, the voltage at the second node When the potential drops, the charge stored in the storage capacitor is transferred to the second node via the second transistor. Since the potential of the second node is supplied to the second node, a drop in the potential of the second node can be prevented.

[0011] Furthermore, in the semiconductor device according to one aspect of the present invention, the gate is electrically connected to the second node. A first transistor is connected to the source and drain of the first transistor. When the potential of one node rises from low to high, the second node is in a floating state. and the capacitance C formed between the source and gate of the first transistor causes the first The potential of the gate of the transistor, i.e., the potential of the second node, also rises.

[0012] Therefore, when the potential of the signal is at a high level, the second switch Even if the potential of the second node drops by the threshold voltage of the transistor in the switch, The above operation can raise the potential of the second node. The gate voltage of the first transistor electrically connected to the first transistor is made sufficiently larger than the threshold voltage. Therefore, the first transistor can be kept in a conductive state. In the semiconductor device according to one aspect, even if the power supply voltage supplied to the semiconductor device is reduced, This can prevent the operating speed of the semiconductor device from decreasing.

[0013] Specifically, in a semiconductor device according to one embodiment of the present invention, the selection of conduction or non-conduction is performed by the gate. a first transistor controlled according to a potential; and a first transistor controlling the supply of a signal to a first node. a second switch for controlling the supply of the signal to a second node; One of the inputs and the gate are electrically connected to the first node, and a second transistor, the other of which is electrically connected to the second node; and a capacitive element that holds the potential of the signal supplied to the first node.

[0014] Specifically, a programmable logic device according to one aspect of the present invention includes a first circuit; a second circuit, and a control circuit for controlling electrical connection between the first circuit and the second circuit in accordance with the potential of the gate; a first transistor for controlling the supply of a signal to the first node; a first switch for controlling the supply of a signal to the second node; a second switch for controlling the supply of the signal to the gate; is electrically connected to the first node, and a second transistor, the other of which is electrically connected to the second node; and a capacitance element that holds the potential of the supplied signal. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a processor capable of realizing low power consumption while suppressing a decrease in operation speed is provided. Alternatively, the present invention may provide a programmable logic device or semiconductor device. By this method, it is possible to realize low power consumption while ensuring normal operation. A logic device or a semiconductor device can be provided. [Brief explanation of the drawings]

[0016] [Figure 1] 1A and 1B are diagrams illustrating a configuration of a semiconductor device. [Figure 2] 1A and 1B are diagrams illustrating a configuration of a semiconductor device. [Figure 3] Timing chart. [Figure 4] 1A and 1B are diagrams illustrating a configuration of a semiconductor device. [Figure 5] 1A and 1B are diagrams illustrating a configuration of a semiconductor device. [Figure 6] A diagram showing the configuration of the initialization switch and latch. [Figure 7] FIG. 2 is a diagram showing the configuration of a logical block. [Figure 8] FIG. 1 is a diagram showing the configuration of a PLD. [Figure 9] FIG. 1 is a diagram showing the configuration of a PLD. [Figure 10] 1A and 1B are diagrams showing a cross-sectional structure of a semiconductor device. [Figure 11] Electronic equipment illustration. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and methods thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0018] Note that the semiconductor device of one embodiment of the present invention can be used in a microprocessor, an image processing circuit, a semiconductor display, Display device controller, DSP (Digital Signal Processor) ), microcontrollers, control circuits or protection circuits for batteries such as secondary batteries The semiconductor element of one embodiment of the present invention also includes various semiconductor integrated circuits. The semiconductor device is a device such as an RF tag or a semiconductor display device using the semiconductor integrated circuit. The semiconductor display devices include liquid crystal display devices and light-emitting devices such as organic light-emitting devices. Light-emitting devices with a pixel element, electronic paper, DMD (Digital Microdevices) rror Device), PDP (Plasma Display Panel), F ED (Field Emission Display) and other semiconductor devices in the drive circuit Other semiconductor display devices having the same are included in this category.

[0019] In this specification, connection means electrical connection, and is not limited to current, voltage, or potential. Therefore, the connected state is the state where the It does not necessarily refer to a state of being connected, but rather to a state in which a current, voltage or potential can be supplied or or can be transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes the state in which the components are electrically connected.

[0020] The source of a transistor is a part of the semiconductor film that functions as an active layer. The source electrode is electrically connected to the semiconductor film. The drain of a transistor is the drain region, or the part of the semiconductor film that functions as the active layer. means a drain electrode electrically connected to the semiconductor film. It means pole.

[0021] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name changes depending on the level of the potential applied. Generally, n-channel transistors In a capacitor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drive The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. However, in reality, the names of source and drain are interchanged according to the above potential relationship. Bad.

[0022] <Configuration Example 1 of Semiconductor Device> First, a structural example of a semiconductor device according to one embodiment of the present invention will be described. 1 illustrates a configuration of a semiconductor device 10 according to one embodiment of the present invention.

[0023] A semiconductor device 10 according to one aspect of the present invention includes a first switch 11, a second switch 12, and The first switch 11 includes a transistor 13, a transistor 14, and a capacitance element 15. The signal BL is a signal including data, and the signal BL has a function of controlling the supply of the signal to the node ND1. In FIG. 1A, the first switch 11 and the second switch 12 are turned on or off. In the illustrated example, the selection of the line is performed according to the potential of the signal supplied to the wiring WL. The first switch 11 and the second switch 12 are switched in accordance with signals supplied via separate wiring. , a selection of conducting or non-conducting may be made.

[0024] The potential of the signal is supplied to the node ND1 via the first switch 11, and the potential of the signal is The charge corresponding to the potential is accumulated in the node ND1, and data is written to the node ND1. The second switch 12 is connected to the node ND The potential of the signal is supplied to the node 2 via the second switch 12. When the potential is supplied to node ND2, a charge corresponding to the potential is accumulated in node ND2, and Data is written to ND2.

[0025] The transistor 13 has one of its source and drain and its gate electrically connected to the node ND1. The other of the source and drain of the transistor 13 is connected to the node ND2. The capacitance element 15 is electrically connected to the node ND1 via the first switch 11. Specifically, the capacitor element 15 has a pair of electrodes. One electrode of the transistor is electrically connected to a node ND1.

[0026] The node ND2 is connected to the wiring DL. Specifically, the wiring DL is connected to the transistor 14 When transistor 14 is in a conducting state, A terminal 16a connected to one of the source and drain of the transistor 14, The terminal 16b is electrically connected to the other of the source and drain. When transistor 14 is in a non-conductive state, one of the source or drain of transistor 14 A terminal 16a connected to the other of the source and drain of the transistor 14 is connected to the other of the source and drain of the transistor 14. The terminal 16b is electrically isolated from the terminal 16a.

[0027] In one aspect of the present invention, the off-current of the first switch 11 and the second switch 12 is significantly Specifically, the transistor of the first switch 11 and the transistor of the second switch The off-state current of the transistor included in the switch 12 is extremely small. In one embodiment, the off-state current of the transistor 13 is extremely small.

[0028] A semiconductor with a wider bandgap and lower intrinsic carrier density than silicon The transistor in which the channel formation region is formed is made of ordinary silicon or germanium. The off-state current can be significantly reduced compared to transistors made of any semiconductor. Therefore, the transistor is connected to the first switch 11 and the second switch 12. Such a semiconductor is suitable for use as the transistor 13. Examples include oxide semiconductors and gallium nitride, which have a band gap more than twice that of silicon. can be done.

[0029] With the above configuration, when the first switch 11 and the transistor 13 are in a non-conductive state, ND1 can be placed in a floating state with extremely high insulation between it and other electrodes and wiring. Furthermore, with the above configuration, when the second switch 12 and the transistor 13 are in a non-conductive state, The node ND2 can be placed in a floating state with extremely high insulation between it and other electrodes and wiring. Therefore, the first switch 11, the second switch 12, and the transistor 13 are non-conductive. When in a conducting state, the voltage of a signal containing data is applied to the nodes ND1 and ND2. The position is maintained.

[0030] Unless otherwise specified, the off-state current in this specification refers to the amount of current that flows through a transistor in a cutoff region. This refers to the current that flows between the source and drain of a transistor.

[0031] Next, a configuration example of a PLD according to one embodiment of the present invention will be described. The configuration of a PLD 10a according to one embodiment of the present invention is shown as an example.

[0032] In the PLD 10a shown in FIG. 1B, the terminal 16a of the semiconductor device 10 shown in FIG. The output terminal of the logic block 18a is connected to the terminal 16b, and the input terminal of the logic block 18b is connected to the terminal 16c. In FIG. 1B, in PLD 10a, the node ND2 The potential of the logic block 18a and the logic block 18b is determined according to the potential of the wiring DL. This illustrates a case where an electrical connection is defined.

[0033] Therefore, the data supplied to PLD10a from the wiring BL is the configuration data. If it is a node, it will be configured according to the configuration data stored in node ND2. This makes it possible to control the electrical connection between the logic block 18a and the logic block 18b.

[0034] <Specific Configuration Example of Semiconductor Device> Next, a more specific example of the configuration of the semiconductor device 10 shown in FIG. 1(A) will be described. 2 illustrates an example of the structure of a semiconductor device 10 according to one embodiment of the present invention.

[0035] The semiconductor device 10 shown in FIG. 2 includes a transistor 11t functioning as the first switch 11 and a , a transistor 12t functioning as the second switch 12, a transistor 13, and a transistor The circuit includes a resistor 14 and a capacitance element 15.

[0036] The gate of the transistor 11t is connected to the wiring WL. t has one of its source and drain connected to the wiring BL, and the other of its source and drain connected to the wiring BL. The gate of the transistor 12t is connected to the wiring WL. In addition, one of the source and the drain of the transistor 12t is connected to the wiring BL. The other of the source and drain is connected to node ND2. 3 has one of its source and drain and its gate connected to node ND1. The other of the source and drain of the transistor 13 is connected to a node ND2. The node ND2 is connected to the wiring DL, which is connected to the gate of the transistor 14. The transistor 14 has one of its source and drain connected to a terminal 16a. The other of the source and drain is connected to the terminal 16b.

[0037] <Example of operation of semiconductor device> Next, an example of the operation of the semiconductor device 10 shown in FIG. 2 will be described with reference to the timing chart shown in FIG. The explanation will be given using a chart. However, transistor 11t, transistor 12t, As an example, the case where the transistors 13 and 14 are all n-channel types is taken. The operation of the device 10 will now be described.

[0038] First, a high-level potential VDD is applied to the wiring WL, and the transistors 11t and The transistor 12t is turned on. A high-level potential VDD corresponding to the high level is applied to the node ND1 via the transistor 11t. , and are respectively provided to node ND2 via transistor 12t. ND1 is a potential obtained by subtracting the threshold voltage of the transistor 11t from the potential VDD. The node ND2 is at a potential (potential VDD minus the threshold voltage of the transistor 12t) The voltage is set to VDD-Vth.

[0039] When the transistors 11t and 12t are in a conductive state, the wiring BL A low-level potential (for example, ground potential GND) corresponding to the logic level of "0" is supplied to In this case, the node ND1 and the node ND2 are supplied with the ground potential GND. Then, the potential VDD corresponding to the logic level of "1" flows from the wiring BL to the node ND1 and the node The operation of the semiconductor device 10 will be described by taking the case where the voltage is applied to ND2 as an example.

[0040] Next, a low-level potential is applied to the wiring WL, and the transistors 11t and 11t are turned on. The transistor 12t is turned off. Therefore, the nodes ND1 and ND2 are The data corresponding to the logic level of "1" is held. Also, transistor 13 is in a non-conductive state. Therefore, the nodes ND1 and ND2 are in a floating state. Similarly to node ND2, the potential V is the potential VDD minus the threshold voltage of transistor 12t. DD-Vth is maintained.

[0041] Next, at time T1, the potential of the terminal 16a rises from the ground potential GND to the potential VDD. Then, the capacitive coupling of the capacitance C formed between the source and gate of the transistor 14 As a result, as the potential at the terminal 16a rises, the gate of the transistor 14, i.e., the wiring DL The potential of the node ND2 also starts to rise. The capacitance C formed between the source and gate of the transistor 14 is significantly smaller than the ideal condition. In this case, the potential of the wiring DL and the node ND2 is changed from the potential VDD to the threshold voltage of the transistor 12t. The potential VDD-Vth obtained by subtracting the voltage is the difference between the ground potential GND and the potential VDD. The voltage rises to the sum of the potentials 2VDD-Vth. The gate voltage of the transistor 14 can be made sufficiently larger than the threshold voltage, and the transistor 14 is turned on. Therefore, the potential of the terminal 16a is supplied to the terminal 16b. .

[0042] In the semiconductor device 10 according to one aspect of the present invention, the power supply voltage supplied to the semiconductor device 10 is low. Even if the potential difference between the potential VDD and the ground potential GND becomes small, 14 from decreasing in on-current, thereby decreasing the operating speed of the semiconductor device 10. This can prevent this.

[0043] The potential rise of the node ND2 is due to the parasitic capacitance added to the node ND2 and the The capacitance C formed between the source and gate of MOSFET 4 varies depending on the capacitance ratio. The smaller the parasitic capacitance added to the node ND2 is compared to the capacitance C, the smaller the potential of the node ND2 is. The increase is large, and the larger the parasitic capacitance added to node ND2 is compared to capacitance C, the Therefore, the smaller the parasitic capacitance of the node ND2, The on-current of the transistor 14 can be increased, and the operating speed of the semiconductor device 10 can be increased. It can be said that this is possible.

[0044] The longer the potential corresponding to the data can be held at the node ND2, the greater the semiconductor The data retention time in the device 10 can also be extended. To ensure a long time, a capacitor with a larger capacitance is connected to node ND2. However, as mentioned above, the capacitance C of the transistor 14 To increase the gate potential rise, the node ND2 must have a capacitance including parasitic capacitance. It is not desirable to connect a large capacitance element. The increase in the potential of the gate due to the capacitive coupling of the capacitance C and the data retention time in the semiconductor device 10 are It can be said that there is a trade-off between time holding and the speed.

[0045] In the semiconductor device 10 according to one aspect of the present invention, a capacitance element 15 is connected to the node ND1. Furthermore, the transistor 13 whose gate is connected to the node ND1 The connection between node ND1 and node ND2 is controlled. Therefore, transistor 13 is non-conductive. In this state, the node ND2 and the capacitance element 15 are electrically isolated from each other. The increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14 is The capacitance value of the transistor 12t is not involved. current flowing between the gate and the source or drain of the transistor 14, etc. Therefore, when the potential of the node ND2 is about to drop below the potential of the node ND1, A potential is supplied from the node ND1 to the node ND2 via the resistor 13. The capacitor 15 contributes to maintaining the potential at the node ND2. In one embodiment, the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C is It can be said that the data retention time in the semiconductor device 10 can be increased while improving the reliability. can.

[0046] The capacitance of the capacitive element 15 connected to the node ND1 is Since the capacitance value is larger than the parasitic capacitance, the transistor that controls the supply of potential to node ND1 The channel width of the transistor 11t is set to be equal to that of the transistor 12t that controls the supply of potential to the node ND2. It is desirable that the channel width of the transistor 13 be larger than that of the transistor 11 .

[0047] At time T2, when the potential of the terminal 16a changes from the potential VDD to the ground potential GND, the transistor The potential of the node ND2 is changed from the potential VDD to the potential of the transistor 14 by the capacitive coupling of the capacitor C of the transistor 14. The potential drops to VDD-Vth, which is the potential obtained by subtracting the threshold voltage of 12t.

[0048] <Configuration Example 2 of Semiconductor Device> Next, another example of the configuration of the semiconductor device 10 shown in FIG. 4A) shows an example of a semiconductor device 10. The semiconductor device 10 shown in FIG. Similar to the semiconductor device 10 shown in FIG. 1, the switch 11, the switch 12, the transistor 13, and However, the semiconductor device 10 shown in FIG. 4A includes a capacitor element 1 and a transistor 14. 5, an inverter 30 and an inverter 31 are provided to maintain the potential of the node ND1. The configuration is different from that of the semiconductor device 10 shown in FIG. 1(A) in that

[0049] Specifically, in FIG. 4A, the input terminal of the inverter 30 and the output terminal of the inverter 31 is electrically connected to the node ND1, and the output terminal of the inverter 30 and the inverter 3 In the semiconductor device 10 shown in FIG. In this configuration, the potential of the node ND1 is maintained by the inverters 30 and 31. It is possible.

[0050] Next, another example of the configuration of the semiconductor device 10 shown in FIG. 4B) shows an example of the semiconductor device 10. The semiconductor device 10 shown in FIG. Similar to the semiconductor device 10 shown in FIG. 1, a switch 11, a transistor 13, and a transistor 14 4B, the semiconductor device 10 has a switch 1 and a capacitor 15. 2, and the transistor 13 is a pair of gate electrodes overlapping each other with a semiconductor film sandwiched therebetween. The configuration differs from the semiconductor device 10 shown in FIG. 1(A) in that it has a recess.

[0051] Specifically, in FIG. 4B, one gate (front gate) of the transistor 13 ) is connected to the node ND1, and the other gate of the transistor 13 is connected to the wiring BG The node ND1 and the node ND2 are connected to the potential of a signal including data. When supplying the voltage, a potential higher than that of the source and drain of the transistor 13 is supplied to the wiring BG. By supplying the voltage Vout, the threshold voltage of the transistor 13 is shifted in the negative direction. Therefore, when the node ND2 is held at a high level potential, the switch 12 is not provided. At least, a low-level potential can be supplied to the node ND2 via the transistor 13. can.

[0052] The semiconductor device 10 shown in FIGS. 4A and 4B may include a transistor, It may further include other circuit elements such as diodes, resistors, capacitors, and inductors. It's okay to be there.

[0053] <Configuration Example 3 of Semiconductor Device> Next, a plurality of semiconductor devices 10 shown in FIG. 2 are combined, and the terminals 16a and 16b are An example of the configuration of a semiconductor device 10b that controls electrical connections will be described.

[0054] FIG. 5 shows an example of a semiconductor device 10b. The semiconductor device 10b is the same as the semiconductor device shown in FIG. In FIG. 5, the semiconductor device 10b includes the semiconductor device 10-1 and the semiconductor device 10-2. 10 shows an example in which two semiconductor devices indicated as device 10-2 are provided.

[0055] The semiconductor device 10b also includes a control circuit for controlling the electrical connection between the terminals 16a and 16b. The transistor 17-1 is connected in series with the transistor 14 of the semiconductor device 10-1. Furthermore, the semiconductor device 10b restricts the electrical connection between the terminal 16a and the terminal 16b. The transistor 17-2 for controlling the semiconductor device 10-2 is the transistor 14. The gate of the transistor 17-1 is connected to a wiring CL1. The gate of the transistor 17-2 is connected to a line CL2.

[0056] In the semiconductor device 10-1 and the semiconductor device 10-2, the voltages held at the node ND2 and the wiring DL are The transistor 14 is selected to be conductive or non-conductive according to the potential of the signal containing data. Therefore, either one of the wiring CL1 and the wiring CL2 is selected and a high level voltage is applied. By positioning the terminal 16a and the terminal 16b, the connection between the semiconductor device 10-1 and the semiconductor device 10-2 is controlled in accordance with the potential of a signal containing data. This results in:

[0057] Specifically, a high-level potential is supplied to the wiring CL1, and a low-level potential is supplied to the wiring CL2. When the voltage Vcc is supplied, the transistor 17-1 is in a conducting state and the transistor 17-2 is in a non-conducting state. Therefore, the voltage of the signal including the data held in the semiconductor device 10-1 is According to the position, the transistor 14 of the semiconductor device 10-1 connects the terminal 16a and the terminal 1 A low level potential is supplied to the wiring CL1, and a high level potential is supplied to the wiring CL2. When a potential of the level is supplied, the transistor 17-2 is in a conducting state, and the transistor Therefore, the data held in the semiconductor device 10-2 is The transistor 14 of the semiconductor device 10-2 supplies a voltage to the terminal 1 in accordance with the potential of the signal including the The connection between terminal 6a and terminal 16b is controlled.

[0058] <More detailed example of PLD configuration> In the PLD according to one aspect of the present invention, a voltage at the terminal 16b is set to initialize the potential at the terminal 16b. A switch or a latch for maintaining the potential of the terminal 16b is electrically connected to the A switch 20 for initializing the potential of the terminal 16b and a 6 shows how the latch 22 for holding the terminal 16b is electrically connected to the terminal 16b. .

[0059] The switch 20 electrically connects the terminal 16b to the wiring 21 to which the initialization potential is applied. In one embodiment of the present invention, the switch 20 is electrically connected to the terminal 16b. By connecting the terminal 16b, the potential of the terminal 16b is set to low level after the PLD is powered on. Therefore, an intermediate potential can be prevented from being applied to the terminal 16b. As a result, a through current occurs in the logic block 18b whose input terminal is connected to the terminal 16b. This can prevent this.

[0060] 6, the latch 22 controls the potential of the terminal 16b to either a high level or a low level. Specifically, the latch 22 includes an inverter 23 and a p-channel The input terminal of the inverter 23 is electrically connected to the terminal 16b. The output terminal of the inverter 23 is electrically connected to the gate of the transistor 24. One of the source and drain of the transistor 24 is applied with a higher potential than the wiring 21. The other end is electrically connected to the wiring 25 connected to the terminal 16b. .

[0061] In one embodiment of the present invention, the latch 22 having the above configuration is electrically connected to the terminal 16b. By doing so, after the PLD is powered on, the potential of the terminal 16b can be set to either a high level or a low level. Since the terminals can be held at either side of the bell, an intermediate potential can be applied to terminal 16b. As a result, the logic block 18b whose input terminal is connected to the terminal 16b This can prevent a through current from occurring in the

[0062] FIG. 7A illustrates an example of a logic block (LB) 40. The block 40 includes a LUT (look-up table) 41, a flip-flop 42, and a memory. The LUT 41 stores the configuration data stored in the storage device 43. The logical operation to be performed is defined according to the data. One output value is determined for each input value of multiple input signals given to LUT4. A signal including the output value is output from the flip-flop 42. and outputs an output signal corresponding to the signal in synchronization with the signal CLK. The signal is output from the output terminal 45 and the second output terminal 46 .

[0063] It should be noted that the logic block 40 further includes a multiplexer circuit. By this, it is possible to select whether the output signal from the LUT 41 passes through the flip-flop 42 or not. It may be possible to do so.

[0064] Also, the type of flip-flop 42 can be defined by the configuration data. Specifically, the flip Flop 42 is a D-type flip-flop, a T-type flip-flop, and a JK-type flip-flop. Alternatively, the flip-flop may have the function of either a flip-flop or an RS flip-flop.

[0065] FIG. 7B illustrates another example of the logic block 40. The logic block 40 is the same as the logic block 40 shown in FIG. 7(A) except that an AND circuit 47 is added. The AND circuit 47 receives the signal from the flip-flop 42 as a positive logic The signal INIT2 for initializing the potential of the wiring DL is given as an input of The above configuration provides an output signal from logic block 40. Therefore, a large amount of current flows between the logic blocks 40. This can prevent leakage and prevent damage to the PLD.

[0066] FIG. 7C illustrates another example of the logic block 40. The logic block 40 is the same as the logic block 40 shown in FIG. 7A except that a multiplexer 48 is added. The logic block 40 shown in FIG. The LUT 41 has two storage devices 43, designated by storage device 43b and storage device 43b. The logical operation to be performed is defined according to the configuration data held by 3a. The multiplexer 48 also receives the output signal from the LUT 41 and the output signal from the flip-flop 42. The multiplexer 48 receives the output signal of the memory device 43b. Depending on the configuration data, one of the two output signals above is The output signal from the multiplexer 48 is output from the first output terminal The signal is output from the first output terminal 45 and the second output terminal 46.

[0067] FIG. 8(A) shows a schematic example of a part of the structure of the PLD 50. The PLD 50 includes a plurality of logic blocks (LBs) 40 and one of the plurality of logic blocks 40. and a switch that controls the connection between the wirings that make up the wiring group 51. The wiring group 51 and the switch circuit 52 correspond to the wiring resource 53. .

[0068] 8B shows a configuration example of the switch circuit 52. The switch circuit 52 shown in FIG. has a function of controlling the connection structure of the wiring 55 and the wiring 56 included in the wiring group 51. In general, the switch circuit 52 includes transistors 57 to 62. The transistors 57 to 62 correspond to the transistor 14 of the semiconductor device 10. Although not shown, the gates of the transistors 57 to 62 are made of a plurality of semiconductors. The wiring DL and the node ND2 of the device 10 are connected to each other. The selection (switching) of the conductive or non-conductive state of the transistors 57 to 62 is performed by a semiconductor device. It is determined by the data held in the node ND2 of the conductor device 10 and the wiring DL.

[0069] The transistor 57 is connected to Point A of the wiring 55 and Point B of the wiring 56. The transistor 58 has a function of controlling the electrical connection of the wiring 55. It has the function of controlling the electrical connection between intB and Point C in the wiring 56. The transistor 59 is connected to Point A in the wiring 55 and Point D in the wiring 56. The transistor 60 has a function of controlling the electrical connection. It has the function of controlling the electrical connection between Point B and Point D in the wiring 56. The resistor 61 controls the electrical connection between Point A and Point B in the wiring 55. The transistor 62 functions to connect the voltages at Points C and D on the wiring 56. It has the function of controlling electrical connections.

[0070] The switch circuit 52 electrically connects the wiring group 51 to the terminal 54 of the PLD 50. It has the function of controlling.

[0071] FIG. 9 shows an example of the overall configuration of the PLD 50. In FIG. 9, the PLD 50 includes an I / O element. Element 70, PLL (phase lock loop) 71, RAM 72, multiplier 7 The I / O element 70 receives signals from external circuits of the PLD 50. or has a function as an interface that controls the output of signals to an external circuit. The PLL 71 has a function of generating a signal CLK. The RAM 72 is used for logical operations. The multiplier 73 corresponds to a logic circuit dedicated to multiplication. If D50 includes a multiplication function, the multiplier 73 does not necessarily have to be provided.

[0072] <Example of cross-sectional structure of semiconductor device> Next, the transistor 13 and the transistor 14 included in the semiconductor device 10 shown in FIG. An example of the cross-sectional structure of 14 is shown in FIG.

[0073] Note that in FIG. 10, the transistor 13 having a channel formation region in an oxide semiconductor film is A transistor 14 having a channel forming region on a single crystal silicon substrate is formed on the transistor 14. The case is illustrated.

[0074] The transistor 14 may be amorphous, microcrystalline, polycrystalline, or single crystalline silicon or gel. A channel formation region may be formed in a semiconductor film or a semiconductor substrate such as aluminum. Alternatively, the transistor 14 may have a channel formation region in an oxide semiconductor film or an oxide semiconductor substrate. All the transistors may be formed on an oxide semiconductor film or an oxide semiconductor substrate. If the transistor 13 has a channel forming region, the transistor 13 is stacked on the transistor 14. The transistors 13 and 14 may not be formed in the same layer. It's okay to be there.

[0075] When the transistor 14 is formed using a thin film of silicon, the thin film is Amorphous silicon, amorphous silicon produced by vapor deposition methods such as the VD method or sputtering method Polycrystalline silicon, which is silicon crystallized by processes such as laser annealing, and single-crystal silicon The wafer is made of single-crystal silicon, etc., which has had its surface peeled off by injecting hydrogen ions etc. can be done.

[0076] The semiconductor substrate 400 may be, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate. In FIG. 10, a single crystal silicon substrate is used as the semiconductor substrate 400. This section provides examples of how the term can be used.

[0077] The transistor 14 is electrically isolated by an element isolation method. Then, the selective oxidation method (LOCOS method: Local Oxidation of Silic on method), trench isolation method (STI method: Shallow Trench Isolati method) In FIG. 10, a transistor 14 is formed using trench isolation. Specifically, in FIG. 10, an electrode is formed on a semiconductor substrate 400. After forming a trench by etching or the like, an insulating material containing silicon oxide or the like is filled into the trench. The transistor 14 is isolated by the element isolation region 401 formed by embedding. The case is illustrated.

[0078] In addition, an n-channel transistor 14 is formed between the element isolation regions 401. In the region to be formed, a p-well 402 in which an impurity element that imparts p-type conductivity is selectively introduced is formed. is provided.

[0079] The transistor 14 then has a source region or drain region formed in the p-well 402. impurity regions 404 and 405 functioning as gate regions, and a gate electrode 406; The semiconductor device has a gate insulating film 407 provided between a semiconductor substrate 400 and a gate electrode 406 . The gate electrode 406 is connected to the impurity region 404 and the impurity region 405 with a gate insulating film 407 sandwiched therebetween. It overlaps with the channel forming region formed between 405.

[0080] An insulating film 411 is provided over the transistor 14. The insulating film 411 has an opening. In the opening, impurity regions 404 and 405 are formed. A conductive film 412 and a conductive film 413 are formed, which are electrically connected to each other.

[0081] The conductive film 412 is electrically connected to a conductive film 418 formed over the insulating film 411. The conductive film 413 is electrically connected to a conductive film 419 formed over the insulating film 411. It is being done.

[0082] An insulating film 420 is formed over the conductive film 418 and the conductive film 419. An opening is formed in the conductive film 419, and a conductive film 419 electrically connected to the conductive film 419 is inserted into the opening. 421 is formed.

[0083] In FIG. 10, the transistor 13 is formed on the insulating film 420 .

[0084] The transistor 13 has a semiconductor film 430 including an oxide semiconductor over an insulating film 420. A conductive film 432 and a conductive film 433 functioning as a source electrode or a drain electrode are provided on the conductive film 430. 433, a gate insulating film 431 over the semiconductor film 430, the conductive film 432, and the conductive film 433, The semiconductor film 43 is located on the gate insulating film 431 and is between the conductive film 432 and the conductive film 433. 0 and a conductive film 434 which functions as a gate electrode. 433 is electrically connected to the conductive film 421 .

[0085] Then, an insulating film 441 and an insulating film 442 are stacked in this order over the transistor 13. An opening is provided in the insulating film 441 and the insulating film 442. A conductive film 443 in contact with the conductive film 432 and the conductive film 434 is provided on the insulating film 442. It is being used.

[0086] 10, the transistor 13 has a conductive film 434 on one side of the semiconductor film 430. It is sufficient to have at least a pair of gate electrodes sandwiching the semiconductor film 430 therebetween. The semiconductor device may have a ground electrode.

[0087] The transistor 13 has a pair of gate electrodes sandwiching a semiconductor film 430 therebetween. When the transistor is connected to one of the gate electrodes, a signal is applied to control whether the transistor is in a conducting or non-conducting state. The other gate electrode may be in a state where a potential is applied from another source. The pair of gate electrodes may be given the same potential, or the other gate electrode may be given the same potential. A fixed potential such as a ground potential may be applied only to the gate electrode of the other side. By controlling the height of the gate, the threshold voltage of the transistor can be controlled.

[0088] 10, the transistor 13 has one channel type corresponding to one conductive film 434. However, the transistor has a single gate structure. 13 has a plurality of electrically connected gate electrodes, thereby forming a channel-shaped active layer. It may have a multi-gate structure having a plurality of gate regions.

[0089] <About semiconductor films> In addition, impurities such as water or hydrogen, which act as electron donors, are reduced, and The oxide semiconductor is highly purified by reducing oxygen vacancies. i-type (intrinsic semiconductor) or very close to i-type Therefore, a transistor having a channel formation region in a highly purified oxide semiconductor film , the off-state current is remarkably small and the reliability is high.

[0090] Specifically, a transistor having a channel formation region in a highly purified oxide semiconductor film The small off-state current can be proven by various experiments. For example, when the channel width is 1× 10 6 Even in a device with a channel length of 10 μm, the voltage between the source and drain electrodes is In the range of drain voltage from 1V to 10V, the off-state current is Below the measurement limit of the analyzer, i.e., 1×10 -13 You can get the trait of A or below. In this case, the off-state current normalized by the channel width of the transistor is 100 zA / μm or less. In addition, by connecting the capacitor and the transistor, The off-state current is measured using a circuit that controls the charge flowing out of the capacitor with the transistor. In this measurement, a highly purified oxide semiconductor film was used as the channel of the transistor. The on / off state of the transistor is determined based on the change in the amount of charge per unit time of the capacitance element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. In this case, it was found that an even smaller off-state current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for a channel formation region has an off-state The current is significantly smaller than that of a transistor using crystalline silicon.

[0091] When an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor is at least It is preferable that the oxide semiconductor also contains indium (In) or zinc (Zn). As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to these, it is preferable to have gallium (Ga). It is preferable to have tin (Sn). Also, hafnium (Hf) is used as a stabilizer. It is preferable that the stabilizer contains aluminum (Al). It is also preferable that the stabilizer contains zirconium (Zr). .

[0092] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are Unlike silicon carbide, gallium nitride, or gallium oxide, sputtering and wet deposition This method makes it possible to fabricate transistors with excellent electrical characteristics, and is suitable for mass production. In addition, unlike silicon carbide, gallium nitride, or gallium oxide, The In-Ga-Zn oxide is used to form transistors with excellent electrical properties on glass substrates. It is also possible to manufacture larger substrates.

[0093] Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), aluminium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more of lutetium (Lu).

[0094] For example, oxide semiconductors include indium oxide, gallium oxide, tin oxide, zinc oxide, In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide oxides (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides , Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Pr-Zn oxide, I n-Nd-Zn oxide, In-Ce-Zn oxide, In-Sm-Zn oxide, In -Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In- Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-T m-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn -Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf -Al-Zn oxides can be used.

[0095] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In-Ga-Zn oxides have a sufficiently high resistance in the absence of an electric field, and The current can be made sufficiently small, and the mobility is also high.

[0096] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, even in In-Ga-Zn oxides, the mobility can be improved by reducing the defect density in the bulk. It can be raised.

[0097] The structure of the oxide semiconductor film will be described below.

[0098] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Compound semiconductor film, CAAC-OS (C Axis Aligned Crystallin e Oxide Semiconductor) film, etc.

[0099] An amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not contain crystalline components. The oxide semiconductor film does not have any crystalline parts even in the microscopic regions, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0100] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) with a size of 1 nm or more and less than 10 nm. Therefore, a microcrystalline oxide semiconductor film has a higher crystallinity than an amorphous oxide semiconductor film. The atomic arrangement is highly regular. Therefore, the microcrystalline oxide semiconductor film has a higher atomic regularity than the amorphous oxide semiconductor film. It has the advantage of having a lower defect level density than silicon.

[0101] The CAAC-OS film is one of the oxide semiconductor films with multiple crystal parts. The crystal part is small enough to fit inside a cube with a side length of less than 100 nm. The crystals contained in the OS film are cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller size than the microcrystalline oxide semiconductor film. The CAAC-OS film has the advantage of having a low density of defect states. cormorant.

[0102] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron ​​microscope, clear boundaries between the crystalline parts are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0103] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0104] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. , including cases where the angle is between 85° and 95°.

[0105] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0106] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0107] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0108] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0109] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0110] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0111] Furthermore, the crystallinity of the CAAC-OS film may not be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface to be formed. When impurities are added to the AC-OS film, the crystallinity of the region where the impurities are added changes, and the Regions of differing crystallinity may be formed.

[0112] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0113] Transistors using CAAC-OS films show that their electrical characteristics change when irradiated with visible or ultraviolet light. The fluctuation is small, and therefore the transistor is highly reliable.

[0114] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0115] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0116] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the processing chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas having a temperature of −80° C. or lower, preferably −100° C. or lower is used.

[0117] In addition, by increasing the substrate heating temperature during film formation, the microstructure of sputtered particles is improved after they reach the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When plate-shaped or pellet-shaped sputtering particles reach the substrate, they migrate on the substrate. Sputtering occurs and the flat surface of the sputtered particle adheres to the substrate.

[0118] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0119] As an example of the target, an In-Ga-Zn oxide target will be described below.

[0120] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. After that, it is heat-treated at a temperature between 1000℃ and 1500℃ to form polycrystalline In-G The target is a-Zn-based oxide, where X, Y, and Z are any positive numbers. The predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2:2 :1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed can be changed depending on the target to be produced. That's fine.

[0121] Note that alkali metals are not elements that constitute an oxide semiconductor and are therefore considered impurities. Potassium earth metals are also impurities when they are not elements that constitute oxide semiconductors. Among alkali metals, Na is preferable when the insulating film in contact with the oxide semiconductor film is an oxide. Na diffuses into the insulating film + In addition, Na is contained in the oxide semiconductor film. It breaks the bond between the metal and oxygen that make up the semiconductor, or it interrupts the bond. As a result, for example, the threshold voltage shifts in the negative direction to become normally on, and the mobility This causes degradation of the electrical characteristics of the transistor, such as a decrease in capacitance, and also causes variations in characteristics. Specifically, the measured value of Na concentration by secondary ion mass spectrometry was 5 × 10 16 / cm 3 Below Below, preferably 1 x 10 16 / cm 3 or less, more preferably 1 × 10 15 / cm 3 and Similarly, the measured value of Li concentration is 5×10 15 / cm 3 Below, preferably 1x 10 15 / cm 3 Similarly, the measured value of the K concentration should be 5 x 10 15 / cm 3 Less than 1 × 10 15 / cm 3 The following would be appropriate.

[0122] In addition, when a metal oxide containing indium is used, the bond energy with oxygen Silicon and carbon, which have larger bonds than indium, break the bond between indium and oxygen, forming an oxygen deficiency. Therefore, if silicon or carbon is mixed into the oxide semiconductor film, As with alkali metals and alkaline earth metals, the electrical characteristics of transistors are degraded. Therefore, it is desirable that the concentrations of silicon and carbon in the oxide semiconductor film are low. Specifically, measurements of C concentration by secondary ion mass spectrometry or Si concentration are preferable. The value is 1 x 10 18 / cm 3 With the above structure, the transistor can be electrically This makes it possible to prevent deterioration of the characteristics and improve the reliability of the semiconductor device.

[0123] In addition, depending on the conductive material used for the source and drain electrodes, The metal in the drain electrode may extract oxygen from the oxide semiconductor film. In the oxide semiconductor film, the region in contact with the source electrode and the drain electrode is subject to the formation of oxygen vacancies. It becomes more n-type.

[0124] The n-type region functions as a source region or a drain region, so the oxide semiconductor The contact resistance between the body film and the source and drain electrodes can be reduced. Therefore, the formation of an n-type region increases the mobility and on-current of the transistor. This allows for high-speed operation of a switch circuit using transistors. It is possible.

[0125] The extraction of oxygen by the metal in the source and drain electrodes This can occur when forming the drain electrode by sputtering or the like, and can also occur when forming the source electrode and This can also occur due to a heat treatment performed after forming the drain electrode.

[0126] In addition, the region to be made n-type is made of a conductive material that easily bonds with oxygen as the source electrode and drain electrode. The conductive material can be, for example, Al, Examples include Cr, Cu, Ta, Ti, Mo, and W.

[0127] In addition, the oxide semiconductor film is not limited to being composed of a single metal oxide film, but may be composed of a stack of metal oxide films. For example, the first to third metal oxide films may be In the case of semiconductor films stacked in this order, the first metal oxide film and the third metal oxide film are The metal oxide film of claim 2 contains at least one of the metal elements constituting the metal oxide film of claim 1 as a constituent element thereof, and has a conduction band The lower end energy is 0.05 eV or more, 0.07 eV or more, or 0.08 eV or more than the second metal oxide film. 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, or 0.5 eV or less The second metal oxide film is an oxide film having a potential of 0.4 eV or less, which is close to the vacuum level. It is preferable to contain at least indium, since this increases carrier mobility.

[0128] When a transistor has a semiconductor film having the above structure, a voltage is applied to a gate electrode. When an electric field is applied to the semiconductor film, the second semiconductor film with the lowest energy at the bottom of the conduction band A channel region is formed in the metal oxide film. That is, the second metal oxide film and the gate insulating film The third metal oxide film is provided between the gate insulating film and the second metal oxide film. A channel region can be formed in the second metal oxide film.

[0129] The third metal oxide film contains at least one of the metal elements constituting the second metal oxide film. Since the second metal oxide film and the third metal oxide film contain one of these as their constituent elements, Surface scattering is unlikely to occur. Therefore, the movement of carriers is unlikely to be hindered at the interface. , the field effect mobility of the transistor increases.

[0130] Furthermore, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, Since a channel region is also formed in the region near the surface, the threshold voltage of the transistor changes. However, the first metal oxide film contains a small amount of the metal elements that make up the second metal oxide film. Since the second metal oxide film contains at least one of the above-mentioned elements, the interface between the second metal oxide film and the first metal oxide film Therefore, with the above configuration, the threshold voltage of the transistor, etc. Therefore, the variation in the electrical characteristics can be reduced.

[0131] In addition, the presence of impurities between the metal oxide films causes the flow of carriers at the interface between the films. To prevent the formation of interface states that hinder the formation of oxide semiconductor films, a plurality of oxide semiconductor films are stacked. If impurities exist between the layers of the laminated metal oxide film, the metal oxide film The continuity of the energy at the bottom of the conduction band between the two regions is lost, and the carriers This is because the impurities are wrapped or disappear due to recombination. By reducing the amount of the metal oxide film, it is possible to obtain a plurality of metal oxide films each having at least one metal as a main component. Rather than simply stacking them, we have a continuous junction (where the energy of the bottom of the conduction band is especially In this case, the formation of a U-shaped well structure (which changes continuously at the interface) is likely to occur.

[0132] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without being exposed to the atmosphere. Each chamber in the sputtering equipment is indispensable for oxide semiconductors. An adsorption type vacuum pump such as a cryopump is used to remove as much water as possible. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent gas from flowing back into the chamber.

[0133] In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate each chamber to a high vacuum, but also to In addition, it is also important to increase the purity of the gas used in sputtering. The dew point of the gas or argon gas is -40°C or less, preferably -80°C or less, more preferably By setting the temperature at -100°C or lower and using highly purified gas, moisture and other substances can be prevented from entering the oxide semiconductor film. Specifically, the second metal oxide film is made of In. -M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), the second gold In the target used to deposit the metal oxide film, the atomic ratio of the metal elements is In:M :If Zn=x1:y1:z1 、 x1 / y1 is greater than or equal to 1 / 3 and less than or equal to 6, or greater than or equal to 1 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, or even 1 or more and 6 or less. It is preferable that z1 / y1 is 1 or more and 6 or less, and thus the second metal oxide film can be made of C. AAC-OS film is easily formed. Typical examples of the atomic ratio of the target metal elements are: Examples include In:M:Zn=1:1:1 and In:M:Zn=3:1:2.

[0134] Specifically, the first metal oxide film and the third metal oxide film are In-M-Zn oxide (M is In the case of Ga, Y, Zr, La, Ce, or Nd, the first metal oxide film, the third metal oxide film, In the target used to deposit the oxide film, the atomic ratio of the metal elements is In:M:Z. If n=x2:y2:z2 、 x2 / y2 <x1 / y1であって、z2 / y2は、1 / It is preferable that z2 / y2 is 3 or more and 6 or less, and more preferably 1 or more and 6 or less. 6 or less, the first metal oxide film and the third metal oxide film can be CAAC-OS films. A typical example of the atomic ratio of the target metal elements is In:M: Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In: Examples include M:Zn=1:3:8.

[0135] The thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less. The thickness of the second metal oxide film is preferably 3 nm or more and 50 nm or less. nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably is 3 nm or more and 50 nm or less.

[0136] In the three-layer semiconductor film, the first metal oxide film, the second metal oxide film, the third metal oxide film, and the third metal oxide film are amorphous. The second metal oxide on which the channel region is formed may be either crystalline or amorphous. The crystalline nature of the oxide film allows the transistor to have stable electrical characteristics. Therefore, the second metal oxide film is preferably crystalline.

[0137] Note that the channel formation region is a region of the semiconductor film of the transistor that overlaps with the gate electrode. The channel region is the region sandwiched between the source electrode and the drain electrode. This refers to the region in the channel formation region where current mainly flows.

[0138] For example, the first metal oxide film and the third metal oxide film are formed by sputtering. When the formed In-Ga-Zn oxide film is used, the first metal oxide film and the third metal The oxide film was formed using In-Ga-Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio]). The film forming conditions are, for example, as the film forming gas, Argon gas was used at 30 sccm and oxygen gas at 15 sccm, and the pressure was set to 0.4 Pa. The temperature is set to 200°C and the DC power is set to 0.5kW.

[0139] When the second metal oxide film is a CAAC-OS film, the formation of the second metal oxide film is The material is an In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]). It is preferable to use a target containing a polycrystalline In-Ga-Zn oxide. For example, the deposition gas is argon gas at 30 sccm and oxygen gas at 15 sccm. The pressure is set to 0.4 Pa, the substrate temperature to 300°C, and the DC power to 0.5 kW. can.

[0140] The transistor may have a structure in which the edge of the semiconductor film is inclined. The conductive film may have a rounded structure at its edges.

[0141] In addition, when a semiconductor film having a plurality of stacked metal oxide films is used for a transistor, In the above case, the regions in contact with the source electrode and the drain electrode may be made n-type. This structure increases the mobility and on-current of the transistor, and improves the semiconductor device using the transistor. Furthermore, the device can achieve high-speed operation. When the semiconductor film is used for a transistor, the region to be made n-type is the second The fact that the metal oxide film is reached increases the mobility and on-current of the transistor, and This is more preferable in terms of realizing even higher speed operation of the body device.

[0142] <Examples of electronic devices> The PLD or semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, , an image reproducing device equipped with a recording medium (typically DVD: Digital Versatile A device that plays recording media such as a DVD and has a display that can display the images. In addition, the PLD or semiconductor device according to one aspect of the present invention can be used in Electronic devices that can be used include mobile phones, portable game consoles, personal digital assistants, Children's books, video cameras, digital still cameras, goggle-type displays (H head-mounted displays), navigation systems, audio playback devices (car audio , digital audio players, etc.), copiers, fax machines, printers, printers These include multifunction machines, automated teller machines (ATMs), and vending machines. A specific example of the equipment is shown in Figure 11.

[0143] FIG. 11A shows a portable game machine, which includes a housing 5001, a housing 5002, and a display unit 5003. , a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, The portable game machine shown in FIG. 11(A) has two tables. The portable game machine has a display unit 5003 and a display unit 5004. , but is not limited to this.

[0144] FIG. 11B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display The first display unit 5603, the second display unit 5604, the connection unit 5605, the operation keys 5606, etc. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other by a connecting portion 5602. 605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5605. 5, the switching is performed according to the angle between the first housing 5601 and the second housing 5602. In addition, at least one of the first display unit 5603 and the second display unit 5604 may have the following display. A display device with a function as a position input device may be used. The function as an input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device may be to display a photoelectric conversion element also known as a photosensor. It can also be added by providing it in the pixel portion of the device.

[0145] FIG. 11C shows a notebook personal computer, which includes a housing 5401 and a display unit 540. 2, a keyboard 5403, a pointing device 5404, etc.

[0146] FIG. 11(D) shows an electric refrigerator-freezer, which includes a housing 5301, a refrigerator door 5302, and a freezer door 5303. It has a door 5303 and the like.

[0147] FIG. 11(E) shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 5 803, operation keys 5804, a lens 5805, a connection part 5806, etc. The lens 5805 and the lens 5804 are provided in the first housing 5801, and the display unit 5803 is provided in the second housing. The first housing 5801 and the second housing 5802 are connected to each other. The first housing 5801 and the second housing 5802 are connected by a portion 5806, and the angle between the first housing 5801 and the second housing 5802 is The image on the display unit 5803 can be changed by the connection unit 5806. 6, and a configuration in which the switching is performed according to the angle between the first housing 5801 and the second housing 5802. You can do that.

[0148] FIG. 11(F) shows a standard automobile, which includes a body 5101, wheels 5102, and a dashboard 51 03, Light 5104, etc. [Explanation of symbols]

[0149] 10 Semiconductor devices 10-1 Semiconductor Devices 10-2 Semiconductor Devices 10a PLD 10b Semiconductor device 11 Switch 11t transistor 12 Switch 12t transistor 13 Transistor 14 Transistor 15 Capacitor element 16a terminal 16b terminal 17-1 Transistor 17-2 Transistor 18a Logical Block 18b Logic Block 20 Switch 21 Wiring 22 Latch 23 Inverter 24 transistors 25 Wiring 30 inverters 31 Inverter 40 logical blocks 41 LUT 42 Flip-Flop 43 Storage device 43a Storage device 43b Storage device 44 input terminals 45 Output terminal 46 Output terminal 47 AND Circuit 48 Multiplexer 50 PLD 51 Wiring group 52 Switch Circuit 53 Routing Resources 54 terminals 55 Wiring 56 Wiring 57 Transistor 58 transistors 59 Transistor 60 transistors 61 Transistor 62 transistors 70 I / O elements 71 PLL 72 RAM 73 Multiplier 400 Semiconductor Substrates 401 Element isolation region 402 p-well 404 Impurity region 405 Impurity region 406 Gate electrode 407 Gate insulating film 411 Insulating film 412 Conductive film 413 Conductive Film 418 Conductive Film 419 Conductive Film 420 insulating film 421 Conductive Film 430 Semiconductor Film 431 Gate insulating film 432 Conductive film 433 Conductive Film 434 Conductive Film 441 Insulating Film 442 insulating film 443 Conductive Film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Car body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Refrigerator door 5303 Freezer door 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display section 5604 Display section 5605 Connection 5606 Operation Key 5801 Housing 5802 Housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection

Claims

1. A semiconductor device having a first circuit and a second circuit, Each of the first and second circuits comprises a first to fourth transistor and a capacitive element. The source or drain of the first transistor is always in electrical contact with the source or drain of the second transistor. The gate of the first transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the third transistor is always in contact with the gate of the third transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. One electrode of the capacitive element is always in electrical contact with the gate of the third transistor. When one of the source or drain of the first transistor and the gate of the third transistor are conductive through at least the channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are conductive through at least the channel formation region of the second transistor, the potential of one of the source or drain of the first transistor is input to the gate of the third transistor through at least the channel formation region of the first transistor, and the potential is input to the gate of the fourth transistor through at least the channel formation region of the second transistor, A first signal is input to the gates of the first transistor and the second transistor in the first circuit. The gates of the first transistor and the second transistor in the second circuit are input to a second signal. The source or drain of the fourth transistor in the first circuit is always in contact with the source or drain of the fourth transistor in the second circuit. Semiconductor equipment.

2. A semiconductor device having a first circuit and a second circuit, Each of the first and second circuits comprises a first to fourth transistor and a capacitive element. The source or drain of the first transistor is always in electrical contact with the source or drain of the second transistor. The gate of the first transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the third transistor is always in contact with the gate of the third transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. One electrode of the capacitive element is always in electrical contact with the gate of the third transistor. When one of the source or drain of the first transistor and the gate of the third transistor are conductive through at least the channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are conductive through at least the channel formation region of the second transistor, the potential of one of the source or drain of the first transistor is input to the gate of the third transistor through at least the channel formation region of the first transistor, and the potential is input to the gate of the fourth transistor through at least the channel formation region of the second transistor, The first transistor is in a non-conductive state, the second transistor is in a non-conductive state, the gate of the third transistor is floating, and the gate of the fourth transistor is floating for a period of time. A first signal is input to the gates of the first transistor and the second transistor in the first circuit. The gates of the first transistor and the second transistor in the second circuit are input to a second signal. The source or drain of the fourth transistor in the first circuit is always in contact with the source or drain of the fourth transistor in the second circuit. Semiconductor equipment.

3. A semiconductor device having a first circuit and a second circuit, Each of the first and second circuits comprises a first to fourth transistor and a capacitive element. Each of the first transistor and the second transistor functions as a switch. The source or drain of the first transistor is always in electrical contact with the source or drain of the second transistor. The gate of the first transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the third transistor is always in contact with the gate of the third transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. One electrode of the capacitive element is always in electrical contact with the gate of the third transistor. When one of the source or drain of the first transistor and the gate of the third transistor are conductive through at least the channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are conductive through at least the channel formation region of the second transistor, the potential of one of the source or drain of the first transistor is input to the gate of the third transistor through at least the channel formation region of the first transistor, and the potential is input to the gate of the fourth transistor through at least the channel formation region of the second transistor, A first signal is input to the gates of the first transistor and the second transistor in the first circuit. The gates of the first transistor and the second transistor in the second circuit are input to a second signal. The source or drain of the fourth transistor in the first circuit is always in contact with the source or drain of the fourth transistor in the second circuit. Semiconductor equipment.

4. A semiconductor device having a first circuit and a second circuit, Each of the first and second circuits comprises a first to fourth transistor and a capacitive element. Each of the first transistor and the second transistor functions as a switch. The source or drain of the first transistor is always in electrical contact with the source or drain of the second transistor. The gate of the first transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the third transistor is always in contact with the gate of the third transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. One electrode of the capacitive element is always in electrical contact with the gate of the third transistor. When one of the source or drain of the first transistor and the gate of the third transistor are conductive through at least the channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are conductive through at least the channel formation region of the second transistor, the potential of one of the source or drain of the first transistor is input to the gate of the third transistor through at least the channel formation region of the first transistor, and the potential is input to the gate of the fourth transistor through at least the channel formation region of the second transistor, The first transistor is in a non-conductive state, the second transistor is in a non-conductive state, the gate of the third transistor is floating, and the gate of the fourth transistor is floating for a period of time. A first signal is input to the gates of the first transistor and the second transistor in the first circuit. The gates of the first transistor and the second transistor in the second circuit are input to a second signal. The source or drain of the fourth transistor in the first circuit is always in contact with the source or drain of the fourth transistor in the second circuit. Semiconductor equipment.

5. In any one of Claims 1 to 4, In each of the first and second circuits, all transistors have the same polarity. Semiconductor equipment.

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