Low power asynchronous handshake circuit with test circuit

Abstract

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit with a test circuit, which comprises a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate and an OR gate; the function of the low-power-consumption asynchronous handshake circuit is realized in a function mode, and the low-power-consumption asynchronous handshake circuit is tested in a test mode. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit under the premise of meeting the asynchronous handshake circuit test.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a low-power asynchronous handshake circuit with a test circuit. Background Technology

[0002] Asynchronous circuits are digital circuits that operate independently of a global clock signal. Data transmission and processing in asynchronous circuits can occur at any point in time, unrestricted by clock signals. Instead of relying on a global clock, asynchronous circuits coordinate the operation of various components through asynchronous handshake circuits. Existing asynchronous handshake circuits require checking the setup time and hold time of flip-flops, as well as their recovery time and removal time. Therefore, existing asynchronous handshake circuits are complex in structure, consume a lot of power, and have slow timing convergence. Furthermore, existing technologies require additional test circuits to test the asynchronous handshake circuits, further increasing the complexity of the circuit structure and power consumption. Therefore, how to reduce the power consumption of asynchronous handshake circuits and improve their timing convergence speed while meeting testing requirements is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a low-power asynchronous handshake circuit with a test circuit, which reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit while meeting the testing requirements.

[0004] This invention provides a low-power asynchronous handshake circuit with a test circuit, including a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, and an OR gate;

[0005] The clock control circuit is used to transmit a single pulse signal to the clock port of the first flip-flop and a second clock signal to the clock ports of the second and third flip-flops in the functional mode. The clock control circuit is also used to transmit a test clock signal to the clock ports of the first, second, and third flip-flops in the test mode.

[0006] The data port of the first trigger is connected to VDD, the output port of the first trigger is connected to the data port of the second trigger, and the output port of the second trigger is connected to the data port of the third trigger.

[0007] If the first flip-flop is an asynchronous low-level active reset port, the asynchronous handshake circuit also includes an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the first input pin of the OR gate.

[0008] If the first flip-flop is an asynchronous high-level active reset port, then the output port of the third flip-flop is directly connected to the first input pin of the OR gate;

[0009] The second input pin of the OR gate is used to receive the test mode signal. The output pin of the OR gate is connected to the first input pin of the AND gate. The second input pin of the AND gate is connected to the output pin of the third selector. The output pin of the AND gate is connected to the reset port of the first flip-flop.

[0010] The first selection pin of the third selector is connected to a high-level signal. The second pin of the third selector is used to receive a test reset signal. The enable pin of the third selector is used to receive a test mode signal. When the test mode signal is high, the second selection pin of the third selector is enabled. When the test mode signal is low, the first selection pin of the third selector is enabled. The test mode signal is high in test mode and low in function mode.

[0011] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the low-power asynchronous handshake circuit with test circuitry provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It possesses at least the following beneficial effects:

[0012] The asynchronous handshake circuit of this invention has a simple structure and low power consumption. In functional mode, the asynchronous handshake circuit implements the handshake function; in test mode, it enables testing of the asynchronous handshake circuit. In functional mode, the clock port of the first flip-flop is controlled by a single pulse signal, and the data port of the first flip-flop is connected to VDD. There is no need to perform setup and hold time checks between the data port and the clock port of the first flip-flop, nor is there a need to perform clear and restore time checks between the reset port and the clock port of the first flip-flop. Furthermore, there is no need to define a clock on the clock port of the first flip-flop. This invention reduces the power consumption of the asynchronous handshake circuit and improves its timing convergence speed while meeting testing requirements. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1This is a schematic diagram of a low-power asynchronous handshake circuit with a test circuit, provided as an embodiment of the present invention, where the trigger is an asynchronous low-level active reset port. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides a low-power asynchronous handshake circuit with a test circuit, including a clock control circuit, a third selector (M3), a first flip-flop (R0), a second flip-flop (R1), a third flip-flop (R2), an AND gate (I1), and an OR gate (I0).

[0017] The clock control circuit is used to transmit a single pulse signal to the clock port of the first flip-flop and a second clock signal to the clock ports of the second and third flip-flops in the functional mode. The clock control circuit is also used to transmit a test clock signal to the clock ports of the first, second, and third flip-flops in the test mode.

[0018] As one example, such as Figure 1As shown, the clock control circuit includes a first selector (M1) and a second selector (M2). The first selector's first selection pin receives a second clock signal, and its second selection pin receives a test clock signal. The first selector's enable pin receives a test mode signal (AT). When the test mode signal is high, the second selection pin of the first selector is enabled. When the test mode signal is low, the first selection pin of the first selector is enabled. The test mode signal is high in test mode and low in function mode. In function mode, a low-power asynchronous handshake circuit with test circuitry implements the handshake function. In test mode, the low-power asynchronous handshake circuit with test circuitry tests the handshake function circuit. The output pin of the first selector is connected to the second selection pin of the second selector, the clock port of the second flip-flop, and the clock port of the third flip-flop, respectively. The first selection pin of the second selector receives a single pulse signal generated based on the first clock. The first and second clocks are asynchronous clocks. The enable pin of the second selector is used to receive the test mode signal. When the test mode signal is high, the second selection pin of the second selector is enabled; when the test mode signal is low, the first selection pin of the second selector is enabled. The output pin of the second selector is connected to the clock port of the first flip-flop. In functional mode, the clock port of the first flip-flop is controlled by a single pulse signal. It should be noted that the clock port of a traditional handshake circuit is controlled by a continuous pulse signal, i.e., a clock signal. In this embodiment of the invention, the clock port of the first flip-flop is controlled by a single pulse signal, eliminating the need to define a clock at the clock port of the first flip-flop, thus improving the timing convergence speed of the asynchronous handshake circuit.

[0019] In another embodiment, the clock control circuit includes a first selector and a second selector. The first selector's first selection pin receives a second clock signal, and its second selection pin receives a test clock signal. The first selector's enable pin receives a test mode signal; when the test mode signal is high, the second selection pin is enabled, and when the test mode signal is low, the first selection pin is enabled. The first selector's output pin is connected to the clock ports of the second and third flip-flops, respectively. The second selector's first selection pin receives a single pulse signal generated based on the first clock, and its second selection pin receives the test clock signal. The second selector's enable pin receives the test mode signal; when the test mode signal is high, the second selection pin is enabled, and when the test mode signal is low, the first selection pin is enabled. The second selector's output pin is connected to the clock port of the first flip-flop.

[0020] The data port of the first flip-flop is connected to Vdd. In functional mode, the setup and hold times between the clock and data ports of the first flip-flop must not violate timing rules; otherwise, the circuit will malfunction. In this embodiment of the invention, the data port of the first flip-flop is connected to Vdd, where Vdd represents the positive power supply voltage. Connecting the data port of the first flip-flop to Vdd ensures that the data port of the first flip-flop is always tied (high), preventing timing violations between the setup and hold times of the clock and data ports.

[0021] If the first flip-flop is an asynchronous low-level active reset port, then the asynchronous handshake circuit also includes an inverter (I2), such as... Figure 1 As shown, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the first input pin of the OR gate. An asynchronous low-level active reset port means that the reset port is asynchronous and active low. An asynchronous reset port means that the flip-flop can be reset even without a clock signal when the reset signal arrives. A low-level active reset port means that when the reset port of the first flip-flop is low, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1. When the reset port of the first flip-flop is high, the first flip-flop is in a released state and can proceed to the next handshake operation.

[0022] If the first flip-flop has an asynchronous high-level active reset port, then the output port of the third flip-flop is directly connected to the first input pin of the OR gate. An asynchronous reset port means that the flip-flop can be reset even without a clock signal when a reset signal arrives. A high-level active reset port means that when the reset port of the first flip-flop is high, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1. When the reset port of the first flip-flop is low, the first flip-flop is in a released state and can proceed to the next handshake operation.

[0023] The second input pin of the OR gate is used to receive the test mode signal. The output pin of the OR gate is connected to the first input pin of the AND gate. It should be noted that by setting the OR gate and the test mode signal, the signal output of the inverter in the test mode is blocked to prevent the output of the inverter in the test mode from affecting the reset port of the first flip-flop.

[0024] The second input pin of the AND gate is connected to the output pin of the third selector, and the output pin of the AND gate is connected to the reset port of the first flip-flop.

[0025] The first selection pin of the third selector is connected to a high-level signal. The second pin of the third selector is used to receive a test reset signal. The enable pin of the third selector is used to receive a test mode signal. When the test mode signal is high, the second selection pin of the third selector is enabled; when the test mode signal is low, the first selection pin of the third selector is enabled. It should be noted that by configuring the AND gate and the third selector, the reset port of the first flip-flop is controlled by the test reset signal in test mode. In function mode, if the first flip-flop is an asynchronous low-level active reset port, its reset port is controlled by the output signal of the inverter; if the first flip-flop is an asynchronous high-level active reset port, its reset port is controlled by the output port of the third flip-flop. This makes the reset port of the first flip-flop controllable in both function mode and test mode.

[0026] As one embodiment, in functional mode, the first pin of the third selector is turned on, the second input pin of the OR gate is always input with a low level, the second input pin of the AND gate is always input with a high level, and the output of the AND gate is always consistent with the output level of the inverter.

[0027] The first flip-flop is an asynchronous low-level active reset port. In functional mode, if the first flip-flop is in a handshake initial state (where the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is high), then when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop acquires the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop acquires the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. When the second rising edge of the second clock arrives, the third flip-flop acquires the 1 stored in the second flip-flop and updates the value stored in the third flip-flop to 1. It should be noted that during this process, after the value stored in the first flip-flop is updated to 1, it remains 1, which is equivalent to converting the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly acquire the single pulse signal received by the clock port of the first flip-flop. The inverter obtains a 1 from the third flip-flop and outputs a low level. The reset port of the first flip-flop receives the low level output from the AND gate. This is equivalent to the third flip-flop sending a clear signal to the first flip-flop through the inverter after sampling, thus clearing the high level of the first flip-flop's reset port. The first flip-flop resets its stored value to 0; that is, it pulls down the high level of the first flip-flop, preparing for the next handshake operation. When the third rising edge of the second clock arrives, the second flip-flop obtains the 0 stored in the first flip-flop and updates its stored value to 0. When the fourth rising edge of the second clock arrives, the third flip-flop obtains the 0 stored in the second flip-flop and updates its stored value to 0. The inverter obtains the 0 from the third flip-flop and outputs a high level. The reset port of the first flip-flop receives the high level output from the AND gate, releasing the first flip-flop and completing one handshake operation, ready for the next handshake operation. Furthermore, releasing the first flip-flop prepares for the next handshake operation. When the clock port of the first flip-flop receives another single pulse signal, the next handshake operation can proceed according to the above process.

[0028] In another embodiment, the first flip-flop is an asynchronous high-level active reset port. In functional mode, if the first flip-flop is in a handshake initial state (where the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is low), then when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop acquires the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop acquires the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. When the second rising edge of the second clock arrives, the third flip-flop acquires the 1 stored in the second flip-flop and updates the value stored in the third flip-flop to 1. It should be noted that during this process, after the value stored in the first flip-flop is updated to 1, it remains 1, which is equivalent to converting the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly acquire the single pulse signal received by the clock port of the first flip-flop. The output port of the third flip-flop sends a high level to the reset port of the first flip-flop, and the first flip-flop resets its stored value to 0. When the third rising edge of the second clock arrives, the second flip-flop retrieves the 0 stored in the first flip-flop and updates the value stored in the second flip-flop to 0. When the fourth rising edge of the second clock arrives, the third flip-flop retrieves the 0 stored in the second flip-flop and updates the value stored in the third flip-flop to 0. The output port of the third flip-flop sends a low level to the reset port of the first flip-flop, releasing the first flip-flop and completing a handshake operation.

[0029] In the initial state, the value stored in the first flip-flop may be 0 or 1. If the value stored in the first flip-flop is 0 in the initial state, the first flip-flop can immediately perform the handshake transmission. If the value stored in the first flip-flop is 1 in the initial state, it is necessary to wait for two clock cycles corresponding to the second clock before the first flip-flop can be reset to 0. As an embodiment, in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level active reset port, the reset port of the first flip-flop is high; if the first flip-flop is an asynchronous high-level active reset port, the reset port of the first flip-flop is low. If the value stored in the first flip-flop is 0, it is determined that the first flip-flop is in the initial handshake state. If the value stored in the first flip-flop is 1, after the reset signal of the second clock domain is withdrawn, the state of the first flip-flop after waiting for two clock cycles corresponding to the second clock is determined as the initial handshake state.

[0030] Since the initial state of the first flip-flop is not fixed, in order to ensure the reliable operation of the asynchronous handshake circuit, as another embodiment, in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level active reset port, then the reset port of the first flip-flop is high-level; if the first flip-flop is an asynchronous high-level active reset port, then the reset port of the first flip-flop is low-level. In the initial state of the asynchronous handshake circuit, after uniformly removing the reset signal of the second clock domain, the state of the first flip-flop after waiting for two clock cycles corresponding to the second clock is determined as the initial handshake state.

[0031] Furthermore, in digital circuits, timing issues can cause certain signals to be in an uncertain state at the sampling time, resulting in metastability. This state can lead to abnormal circuit function or data errors. The structure of the second and third flip-flops also plays a role in eliminating metastability, ensuring the stability of circuit function and the correctness of acquired data.

[0032] In a preferred embodiment, the clock frequency of the first clock is greater than or equal to the clock frequency of the second clock, that is, the first clock is a fast clock and the second clock is a slow clock.

[0033] As one embodiment, the asynchronous handshake circuit further includes a finite state machine (FSM) connected to a first clock, which is used to generate a single pulse signal based on the first clock and transmit it to the clock port of the first flip-flop.

[0034] In functional mode, timing violations of the clear time and recovery time are not allowed when the reset port of the first flip-flop sends a low level. Once such a violation occurs, the circuit will not function properly. Therefore, in the prior art, it is necessary to check whether there is a timing violation of the clear time and recovery time between the reset port and the clock port of the first flip-flop. In order to avoid timing violations of the clear time and recovery time when the inverter sends a low level to the reset port of the first flip-flop, as an example, the time interval between the generation of a single pulse signal by the first clock is greater than a preset time interval, which is twice the second clock cycle. This makes the time interval between the generation of two single pulse signals by the first clock sufficiently large, so that there will be no timing violation of the recovery time and removal time between the clock port and the reset port of the first flip-flop. Therefore, it is not necessary to check the recovery time and removal time of the flip-flop.

[0035] It should be noted that the convergence of the asynchronous handshake circuit requires convergence of two timing aspects: first, setup and hold checks between the data port (i.e., the data port) and the clock port of the first flip-flop; second, removal and recovery checks between the reset port and the clock port of the first flip-flop. In this embodiment of the invention, by always connecting the data port of the first flip-flop to VDD and staggering the interval between clock reset and clock, i.e., when a pulse arrives at the first flip-flop, no reset signal arrives, and when a reset signal arrives, no clock signal arrives, the asynchronous handshake circuit described in this embodiment of the invention does not need to check the above two timing aspects of the first flip-flop. It can be understood that since these two timing aspects do not need to be checked, the timing of the one-step handshake circuit of this invention meets the requirements, therefore, there is no need to define clock constraints for the clock port of the first flip-flop, thus improving the timing convergence speed of the asynchronous handshake circuit.

[0036] As one embodiment, in test mode, the second selection pin of the first selector is turned on, the second selection pin of the second selector is turned on, and the clock ports of the first flip-flop, the second flip-flop, and the third flip-flop are all used to receive the test clock signal and are controlled by the test clock signal.

[0037] In test mode, the test mode signal is high, the output of the OR gate is always high, the output of the AND gate is controlled by the output of the third selector, the second select pin of the third selector is turned on, and the reset port of the first flip-flop is controlled by the test reset signal.

[0038] As one embodiment, the asynchronous handshake circuit further includes a fourth selector (M4). The first selection pin of the fourth selector is used to receive a second clock reset signal, the second selection pin is used to receive a test reset signal, and the enable pin is used to receive a test mode signal. When the test mode signal is high, the second selection pin of the fourth selector is enabled; when the test mode signal is low, the first selection pin of the fourth selector is enabled. The output pins of the fourth selector are connected to the reset ports of the second and third flip-flops, respectively. Figure 1 In the example shown, the reset ports of both the second and third flip-flops are asynchronous low-level active reset ports. It should be noted that when the first flip-flop is set to an asynchronous high-level active reset port, the reset ports of the second and third flip-flops can also be set to asynchronous high-level active reset ports. Figure 1 For example, as shown in the example,

[0039] In test mode, the second selection pin of the fourth selector is turned on, and the reset ports of the second and third flip-flops are controlled by the test reset signal. During the test, if a reset operation needs to be performed on the reset ports of the second and third flip-flops, a low-level signal is sent to their respective reset ports via the test reset signal.

[0040] by Figure 1 Taking the example shown, in functional mode, the first selection pin of the fourth selector is turned on, and the reset ports of the second and third flip-flops are controlled by the second clock reset signal. Specifically, when it is necessary to reset the second and third flip-flops in the initial state or during operation, the second clock reset signal is set to a low level. It should be noted that in the initial state, the values ​​stored in the second and third flip-flops need to be set to 0, therefore the second clock reset signal needs to be set to a low level. During operation, if the second and / or third flip-flops malfunction or other abnormal conditions require reset, the second clock reset signal is also directly set to a low level to quickly reset the second and third flip-flops. At other times during operation, the second clock reset signal is set to a high level, so that the second and third flip-flops are in the released state and can work normally.

[0041] The asynchronous handshake circuit of this invention has a simple structure and low power consumption. In functional mode, the asynchronous handshake circuit implements the handshake function; in test mode, it enables testing of the asynchronous handshake circuit. In functional mode, the clock port of the first flip-flop is controlled by a single pulse signal, and the data port of the first flip-flop is connected to VDD. There is no need to perform setup time checks and hold time checks between the data port and the clock port of the first flip-flop, nor is there a need to perform clear time checks and recovery time checks between the reset port and the clock port of the first flip-flop. Furthermore, there is no need to define a clock on the clock port of the first flip-flop. This invention reduces the power consumption of the asynchronous handshake circuit and improves its timing convergence speed while meeting testing requirements.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-power asynchronous handshake circuit with test circuit, characterized in that, comprising a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate and an OR gate; wherein the clock control circuit is configured to transmit a single pulse signal to the clock port of the first flip-flop, a second clock signal to the clock port of the second flip-flop and the clock port of the third flip-flop in a functional mode, and transmit a test clock signal to the clock port of the first flip-flop, the clock port of the second flip-flop and the clock port of the third flip-flop in a test mode; the data port of the first flip-flop is connected to a positive power supply voltage vdd, the output port of the first flip-flop is connected to the data port of the second flip-flop, and the output port of the second flip-flop is connected to the data port of the third flip-flop; if the first flip-flop is an asynchronous low-level active reset port, the asynchronous handshake circuit further comprises an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the first input pin of the OR gate; if the first flip-flop is an asynchronous high-level active reset port, the output port of the third flip-flop is directly connected to the first input pin of the OR gate; the second input pin of the OR gate is configured to receive a test mode signal, the output pin of the OR gate and the first input pin of the AND gate are connected, the second input pin of the AND gate is connected to the output pin of the third selector, and the output pin of the AND gate is connected to the reset port of the first flip-flop; the first selection pin of the third selector is connected to a high-level signal, the second pin of the third selector is configured to receive a test reset signal, and the enable pin of the third selector is configured to receive a test mode signal, when the test mode signal is high, the second selection pin of the third selector is enabled, when the test mode signal is low, the first selection pin of the third selector is enabled, and the test mode signal is high in the test mode and low in the functional mode.

2. The asynchronous handshake circuit of claim 1, characterized in that, the clock control circuit comprises a first selector and a second selector, wherein the first selection pin of the first selector is configured to receive a second clock signal, the second selection pin of the first selector is configured to receive a test clock signal, the enable pin of the first selector is configured to receive a test mode signal, when the test mode signal is high, the second selection pin of the first selector is enabled, when the test mode signal is low, the first selection pin of the first selector is enabled, and the output pin of the first selector is connected to the second selection pin of the second selector, the clock port of the second flip-flop and the clock port of the third flip-flop, respectively; the first selection pin of the second selector is configured to receive a single pulse signal generated based on a first clock, the enable pin of the second selector is configured to receive a test mode signal, when the test mode signal is high, the second selection pin of the second selector is enabled, when the test mode signal is low, the first selection pin of the second selector is enabled, and the output pin of the second selector is connected to the clock port of the first flip-flop.

3. The asynchronous handshake circuit of claim 1, wherein the clock control circuit comprises a first selector and a second selector, wherein a first selection pin of the first selector is configured to receive the second clock signal, a second selection pin of the first selector is configured to receive the test clock signal, an enable pin of the first selector is configured to receive a test mode signal, the second selection pin of the first selector is enabled when the test mode signal is high, the first selection pin of the first selector is enabled when the test mode signal is low, and an output pin of the first selector is connected to a clock port of the second flip-flop and a clock port of the third flip-flop, respectively.

4. The asynchronous handshake circuit of claim 2 or 3, wherein a clock frequency of the first clock is greater than or equal to a clock frequency of the second clock, and a time interval of the single pulse signal generated by the first clock is greater than a preset time interval, the preset time interval being twice a period of the second clock.

5. The asynchronous handshake circuit of claim 4, wherein in the functional mode, the first pin of the third selector is enabled, or the second input pin of the AND gate always inputs a low level, the second input pin of the NAND gate always inputs a high level, and an output of the NAND gate always keeps the same level as an output of the inverter.

6. The asynchronous handshake circuit of claim 5, wherein the first flip-flop is an asynchronous low active reset port, and in the functional mode, if the first flip-flop is in a handshake initial state in which a value stored in the first flip-flop is 0 and a reset port of the first flip-flop is high, when the clock port of the first flip-flop receives the single pulse signal, a data port of the first flip-flop obtains a value of vdd, the value stored in the first flip-flop is updated to 1, when a first rising edge of the second clock arrives, the second flip-flop obtains the value of 1 stored in the first flip-flop, the value stored in the second flip-flop is updated to 1, when a second rising edge of the second clock arrives, the third flip-flop obtains the value of 1 stored in the second flip-flop, the value stored in the third flip-flop is updated to 1, the inverter obtains the value of 1 from the third flip-flop and outputs a low level, the reset port of the first flip-flop receives the low level output by the NAND gate, and the value stored in the first flip-flop is reset to 0. ​ ​ ​ ​ ​ When the third rising edge of the second clock comes, the second flip-flop acquires the 0 stored in the first flip-flop, updates the value stored in the second flip-flop to 0, when the fourth clock rising edge of the second clock comes, the third flip-flop acquires the 0 stored in the second flip-flop, updates the value stored in the third flip-flop to 0, the inverter acquires the 0 from the third flip-flop and outputs a high level, the reset port of the first flip-flop receives the high level output by the AND gate, releases the first flip-flop, and completes a handshake operation.

7. The asynchronous handshake circuit of claim 5, wherein, the first flip-flop is an asynchronous high-level effective reset port, in the functional mode, if the first flip-flop is in a handshake initial state, that is, the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is a low level, when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop acquires the value of vdd, updates the value stored in the first flip-flop to 1, when the first rising edge of the second clock comes, the second flip-flop acquires the 1 stored in the first flip-flop, updates the value stored in the second flip-flop to 1, when the second rising edge of the second clock comes, the third flip-flop acquires the 1 stored in the second flip-flop, updates the value stored in the third flip-flop to 1, and the output port of the third flip-flop sends a high level to the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0; When the third rising edge of the second clock comes, the second flip-flop acquires the 0 stored in the first flip-flop, updates the value stored in the second flip-flop to 0, when the fourth clock rising edge of the second clock comes, the third flip-flop acquires the 0 stored in the second flip-flop, updates the value stored in the third flip-flop to 0, the output port of the third flip-flop sends a low level to the reset port of the first flip-flop, releases the first flip-flop, and completes a handshake operation.

8. The asynchronous handshake circuit of claim 4, wherein, in the test mode, the second selection pin of the first selector is connected, the second selection pin of the second selector is connected, the clock ports of the first flip-flop, the second flip-flop, and the third flip-flop are used to receive a test clock signal, and are controlled by the test clock signal; in the test mode, the test mode signal is a high level, the output of the OR gate is always a high level, the output of the AND gate is controlled by the output of the third selector, the second selection pin of the third selector is connected, and the reset port of the first flip-flop is controlled by a test reset signal.

9. The asynchronous handshake circuit of claim 1, wherein, The asynchronous handshake circuit further comprises a fourth selector, a first selection pin of the fourth selector is used for receiving a second clock reset signal, a second selection pin of the fourth selector is used for receiving a test reset signal, an enable pin of the fourth selector is used for receiving a test mode signal, when the test mode signal is high, the second selection pin of the fourth selector is enabled, when the test mode signal is low, the first selection pin of the fourth selector is enabled; and an output pin of the fourth selector is connected with a reset port of the second flip-flop and a reset port of the third flip-flop respectively.

10. The asynchronous handshake circuit of claim 9, wherein, in the test mode, the second selection pin of the fourth selector is enabled, and the reset port of the second flip-flop and the reset port of the third flip-flop are controlled by the test reset signal; in the functional mode, the first selection pin of the fourth selector is enabled, and the reset port of the second flip-flop and the reset port of the third flip-flop are controlled by the second clock reset signal.

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