Semiconductor equipment

Abstract

By incorporating a holding circuit into the logic circuit, power gating becomes possible. [Solution] The holding circuit comprises a first terminal, a node, a capacitive element, and first to third transistors It has a terminal. The first transistor controls the conduction state between the first terminal and the input terminal of the logic circuit. The second transistor controls the conduction state between the output terminal of the logic circuit and the node. The 3 transistors control the conduction state between the node and the input terminal of the logic circuit. Transistor 1 The gate of the zista and the gate of the second transistor are electrically connected. Data retention period During this time, the node is electrically floating. The voltage at the node is maintained by the capacitive element.

Description

Technical Field

[0001] One aspect of the invention disclosed in the specification, drawings, and claims of the present application (hereinafter referred to as this specification, etc.) relates to a semiconductor device (e.g., sequential circuit, holding circuit, memory circuit, logic circuit, etc.), its driving method, manufacturing method, and the like. One aspect of the present invention is not limited to the exemplified technical field. For example, one aspect of the present invention relates to a memory device, a processing device, an imaging device, a display device, a light-emitting device, a power storage device, or their driving methods, or their manufacturing methods. For example, one aspect of the present invention relates to a memory device, a processing device, an imaging device, a display device, a light-emitting device, a power storage device, or their driving methods, or their manufacturing methods.

Background Art

[0002] To reduce the power consumption of semiconductor devices, power gating and clock gating are used to stop circuits that do not need to be operated. A flip-flop (FF) is one of the sequential circuits (memory circuits for holding states) often included in semiconductor devices. Therefore, reducing the power consumption of FF leads to reducing the power consumption of semiconductor devices incorporating FF. Generally, when the power supply of a typical FF is cut off, the state (data) it holds is lost. A holding circuit that can hold data even when the power supply is cut off has been proposed by utilizing the characteristic that the off-current of a transistor (hereinafter sometimes referred to as an OS transistor) in which the semiconductor region is formed of an oxide semiconductor is extremely small. For example, Patent Documents 1-3 describe that by incorporating a holding circuit in which an OS transistor is applied into an FF, power gating of the FF becomes possible. For example, Non-Patent Document 1 provides a holding circuit in which an OS transistor is used for an FF and an SRAM, and performs power gating of a processor.

[0003] When the semiconductor region is formed of an oxide semiconductor, the off-current of the transistor (hereinafter sometimes referred to as an OS transistor) is extremely small. By utilizing this characteristic, a holding circuit that can hold data even when the power supply is cut off has been proposed. For example, Patent Documents 1-3 describe that by incorporating a holding circuit in which an OS transistor is applied into an FF, power gating of the FF becomes possible. For example, Non-Patent Document 1 provides a holding circuit in which an OS transistor is used for an FF and an SRAM, and performs power gating of a processor. ​​​​​​​It is stated that this happened. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2012-257192 [Patent Document 2] Japanese Patent Publication No. 2013-9297 [Patent Document 3] Japanese Patent Publication No. 2013-175708 [Non-patent literature]

[0005] [Non-Patent Document 1] H. Tamura et al., “Embedded SRAM and Cortex-M0 Core with Backup Circuits Using a 60-nm Crystalline Oxide Semiconductor for Power Gating,” IEEE COOL Chips XVII, Apr. 2014. [Overview of the project] [Problems that the invention aims to solve]

[0006] The object of one embodiment of the present invention is to provide a novel semiconductor device or a novel method for driving a semiconductor device. The objective of one embodiment of the present invention is to enable power gating. And, to be able to retain data without supplying power, reduce power consumption, small Examples include standardization and simplifying the design process.

[0007] The description of multiple problems does not preclude the existence of each other. Furthermore, one embodiment of the present invention is... It is not necessary to solve all of these problems. Furthermore, other problems not listed may not be described in this specification, etc. This becomes clear from the facts, and these problems can also be addressed by one embodiment of the present invention. [Means for solving the problem]

[0008] One embodiment of the present invention is a logic circuit having a first circuit and a second circuit, wherein the first circuit is It has 1 to nth input terminals and a first output terminal (where n is an integer greater than or equal to 2), and the second circuit has nth input terminals. It has a +1 input terminal, a first node, a first capacitive element, and first to third transistors, Circuit 1 selects one of the first to nth input terminals and uses the same logic as the selected input terminal. It has the function of outputting logic data from the first output terminal, and the capacitive element is electrically connected to the first node. Connected, the first transistor controls the conduction state between the (n+1)th input terminal and the first input terminal. The second transistor has the function of controlling the conduction state between the first output terminal and the first node. The third transistor has the function of controlling the conduction state between the first node and the first input terminal. It has the function of electrically connecting the gate of the first transistor and the gate of the second transistor. Subsequently, the second and third transistors have semiconductor regions formed by an oxide semiconductor layer. It is being done.

[0009] In the above configuration, the first capacitive element and the first to third transistors form the first circuit They may be stacked on a region that is being constructed. In the above embodiment, the first transistor is a semiconductor The region may be formed of an oxide semiconductor layer, in which case the first to third transistors The oxide semiconductor layer preferably has crystals oriented along the c-axis.

[0010] Furthermore, in the logic circuit according to the above configuration, the first circuit comprises a selection circuit and a first logic circuit. The first logic circuit has the n+2th input terminal and the first output terminal, and the first logic circuit has the It has the function of outputting data with the same logic as the n+2 input terminals from the first output terminal, and the selection circuit is It has a second output terminal, and the selection circuit selects any one of the first to nth input terminals to the second output terminal. It has the function of electrically connecting, and the second output terminal is electrically connected to the (n+2)th input terminal. It's okay to be there. [Effects of the Invention]

[0011] One embodiment of the present invention provides a novel semiconductor device or a novel method of operating a semiconductor device. This becomes possible. Alternatively, according to one embodiment of the present invention, power gating becomes possible. This will enable data retention without a power supply and reduce power consumption. This makes miniaturization possible, or simplifies the design process.

[0012] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention is: It is not necessarily required to have all of the effects exemplified. Furthermore, with respect to one embodiment of the present invention, For issues, effects, and novel features other than those described herein, please refer to the descriptions and drawings provided herein. This becomes clear. [Brief explanation of the drawing]

[0013] [Figure 1] A: Block diagram showing an example of the configuration of a logic circuit. B: Block diagram showing an example of the configuration of circuit 10 in Figure 1A. [Figure 2] A, B: Block diagrams showing examples of logic circuit configurations. [Figure 3] A block diagram showing an example of a logic circuit configuration. [Figure 4] A circuit diagram showing an example configuration of a scan flip-flop (SFF). [Figure 5] Circuit diagram showing an example of an SFF configuration. [Figure 6] Timing chart showing an example of SFF operation. [Figure 7] Timing chart showing an example of SFF operation. [Figure 8] Circuit diagram showing an example of an SFF configuration. [Figure 9] Circuit diagram showing an example of an SFF configuration. [Figure 10] Circuit diagram showing an example of an SFF configuration. [Figure 11] Circuit diagram showing an example of an SFF configuration. [Figure 12] Circuit diagram showing an example of an SFF configuration. [Figure 13] A block diagram showing an example of the configuration of the processing unit. [Figure 14] A block diagram showing an example of a processor core configuration. [Figure 15] A diagram showing the device structure of an SFF. [Figure 16] A: A flowchart showing an example of an electronic component manufacturing method. B: A schematic perspective diagram showing an example of an electronic component configuration. [Figure 17] AF: A diagram showing an example of electronic equipment. [Figure 18] A: Plan view showing an example of transistor configuration. BD: Cross-sectional view of the transistor in Figure 18A. [Figure 19] A: A magnified view of a portion of the transistor in Figure 18B. B: Energy band diagram of the transistor. [Figure 20] AC: Cross-sectional view showing an example of transistor configuration. [Figure 21] A, B: Cross-sectional diagrams showing examples of transistor configurations. [Figure 22] A cross-sectional view showing an example of the chip's configuration. [Figure 23] A cross-sectional view showing an example of the chip's configuration. [Modes for carrying out the invention]

[0014] In this specification, a semiconductor device is a device that utilizes semiconductor properties, and a semiconductor element ( This refers to circuits containing transistors, diodes, etc., and devices having such circuits. It also refers to semiconductors. This refers to any device that can function by utilizing its characteristics. For example, an integrated circuit, or a device equipped with an integrated circuit. A chip is an example of a semiconductor device. It is also used in memory devices, display devices, light-emitting devices, lighting devices, and Electronic devices, etc., are themselves semiconductor devices and may contain semiconductor devices.

[0015] Furthermore, if it is explicitly stated in this specification, etc., that X and Y are connected. This refers to the case where X and Y are electrically connected, and the case where X and Y are functionally connected. The cases in which X and Y are directly connected are disclosed in this specification, etc. Therefore, the connection relationships are not limited to predetermined relationships, such as those shown in the diagram or text. Connections other than those shown in the diagram or text are also included as those described in the diagram or text. X and Y are the object (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). Let's assume that it is the case.

[0016] A transistor has three terminals called the gate, source, and drain. A node functions as a control node that controls the conduction state of a transistor. The two input / output nodes, which function as either a drain or a spool, have transistor types and each terminal Depending on the applied potential, one becomes the source and the other the drain. Therefore, In this specification, the terms source and drain may be used interchangeably. In this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. There is a match.

[0017] Depending on the circuit configuration and device structure, the node may consist of terminals, wiring, electrodes, conductive layers, conductors, and other components. It can be rephrased as "pure matter region," etc. Also, terminals, wiring, etc. can be rephrased as "nodes." This is possible.

[0018] Voltage is the difference between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). It often refers to the difference in potential. Therefore, it is possible to rephrase voltage as electric potential. Electric potential is relative. Therefore, even if it is described as ground potential, it does not necessarily mean 0. It may not always mean V.

[0019] In this specification, the terms "membrane" and "layer" may be used interchangeably, depending on the context. These can be interchanged depending on the situation. For example, the term "conductive layer" In some cases, it is possible to change the term "insulating film" to "conductive film". For example, "insulating film" In some cases, it may be possible to change the term to "insulating layer."

[0020] In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. They may be added for the purpose of adding, and in that case, they are not limited to a specific number, nor are they limited in order. It's not something you should do.

[0021] In this specification, for example, the clock signal CLK may be abbreviated as signal CLK, CLK, etc. This may be included. This refers to other components (e.g., signals, voltages, potentials, circuits, elements, The same applies to electrodes, wiring, etc.

[0022] In drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawing schematically represents an ideal example. This is an example, and is not limited to the shapes or values ​​shown in the drawings. For example, noise-induced signals Variations in the number, voltage, or current, or timing differences in the signal, voltage, or This can include variations in current, etc.

[0023] In this specification, terms indicating placement, such as "above" and "below," refer to the positional relationship between components. In some cases, diagrams are used for convenience when explaining things. Also, the position of the components. The relationships change as appropriate depending on the direction in which each component is described. Therefore, they are explained in the specification. The words used are not limited to those already mentioned, and can be appropriately rephrased depending on the situation.

[0024] The arrangement of each circuit block in the block diagram shown in the drawing is intended to identify the positional relationship for explanatory purposes. Therefore, even if it is shown that different circuit blocks will achieve different functions, the actual circuit block In locks, the same circuit block is designed to allow different functions to be implemented within it. There are also combinations. Furthermore, the functions of each circuit block are identified for explanatory purposes, and are not all the same. Even though it is shown as a circuit block, in an actual circuit block, one circuit block is In some cases, the process to be performed may be designed to be carried out by multiple circuit blocks.

[0025] Embodiments of the present invention are shown below. However, embodiments described herein may be combined as appropriate. It is possible to combine them. Also, within one embodiment, there can be multiple configuration examples (operation examples, manufacturing examples). If examples of methods are provided, it is possible to combine the configuration examples as appropriate. Furthermore, the present invention can be implemented in many different forms, and its spirit and scope It is easy for anyone skilled in the art to understand that its form and details can be changed in various ways without deviation. Therefore, the present invention is interpreted to be limited to the contents described in the following embodiments. There isn't one.

[0026] [Embodiment 1] <<Example of logic circuit configuration>> Figure 1A shows an example of a logic circuit configuration. The logic circuit 100 shown in Figure 1A holds data (state). It is a semiconductor device capable of doing so. Depending on the circuit structure, it can also be called a sequential circuit. The logic circuit 100 is a semiconductor device capable of clock gating and power gating. The logic circuit 100 has circuit 10 and circuit RC1. Circuit RC1 processes the data. This is a holding circuit that has a holding function. Circuit RC1 reads the state (data) of circuit 10. It has the function of retaining that data. Furthermore, circuit RC1 transmits the retained data to circuit 10. It has a reading function.

[0027] <Circuit 10> Circuit 10 has terminals D1-Dn (where n is an integer greater than or equal to 2), terminal Q, terminal QB, and terminal EN. Terminals D1-Dn are data input terminals. Terminals Q and QB are data output terminals. The child EN is the terminal to which the control signal E0 is input. Circuit 10 can be any logic circuit. 10 selects one of terminals D1-Dn according to the logic of terminal EN, and the selected terminal It should have a calculation function that outputs data with the same logic as the data input to it from terminal Q. Terminal QB is a terminal that outputs data that is the inverse of the logic of terminal Q. In the example in Figure 1A, Circuit 10 does not necessarily have to have terminal QB.

[0028] Figure 1B shows an example of the configuration of circuit 10. The circuit 10 shown in Figure 1B consists of selection circuit 20 and circuit 3 It has 0. Terminal T1 of selection circuit 20 is electrically connected to terminal T2 of circuit 30. Terminal T1 is the output terminal of the selection circuit 20, and terminal T2 is the input terminal of the circuit 30.

[0029] Signal E0 is the control signal of the selection circuit 20. The selection circuit 20 controls terminal D1 according to signal E0. -It has the function of selecting one of the Dn options and electrically connecting it to terminal T1.

[0030] Circuit 30 can be any logic circuit. Circuit 30 will have the same logic as the data input to terminal T2. It is sufficient to have a calculation function that can output data from terminal Q. For example, circuit 3 0 represents a sequential circuit whose internal state is updated by a control signal such as a clock signal CLK. It is possible. For example, circuit 30 can include latches, flip-flops, shift registers, and It can be used as a counter circuit, a frequency divider, etc.

[0031] <Circuit RC1> Circuit RC1 consists of node FN, terminal D0, terminal T0, switch SW1, switch SW2, and It has a switch SW3 and a capacitive element C1. Terminals D0 and T0 are input terminals.

[0032] Node FN is a node that can be electrically floating, and the data from circuit RC1 ( This node functions as a state-holding unit. One terminal of the capacitive element C1 is connected to node FN, The other terminal is electrically connected to terminal T0. Capacitive element C1 maintains the voltage at node FN. It can function as a retaining capacitance. A signal or a constant voltage is applied to terminal T0. This can be done. For example, the low power supply voltage of circuit 10 can be input to terminal T0.

[0033] Switch SW1 controls the conductivity between terminals D0 and D1, and switch SW2 controls the terminals Controls the conduction state between Q and node FN. Signal E2 controls switches SW1 and SW2. The on / off state is controlled. Switch SW3 controls the conductivity between node FN and terminal D1. Control. The on / off state of switch SW3 is controlled by signal E3.

[0034] (normal operation) When circuit 10 processes the input data, switch SW3 is turned OFF. SW1 should be turned on as needed. The data processed by circuit 10 includes the data from terminal D1. If it is not included, switch SW1 should be turned off. If data is included in terminal D1, simply turn on switch SW1. State 2 can be either on or off. In the example in Figure 1A, the switch SW is controlled by signal E2. Switch 2 also turns on in conjunction with switch SW1. Control signal between switch SW1 and switch SW2 You can also turn off switch SW2 by assigning a different number to switch SW1 and switch SW2. By using a common control signal, the number of wires and components can be reduced, leading to a reduction in power consumption. ru.

[0035] (Backup operation) To back up the state of circuit 10, input signals such as CLK to circuit 10 as needed. The force is stopped to prevent the logic (state) of terminal Q from being changed. Next, switch SW2 Turn on and turn off switch SW3. Node FN is electrically connected to terminal Q. Therefore, the logic of node FN is the same as that of terminal Q. If the logic of terminal Q is "1", then no Node FN also becomes "1", and if the logic of terminal Q is "0", then node FN will also be "0". By turning off switches SW2 and SW3, node FN is electrically isolated, Once the queuing is complete, circuit RC1 enters a data holding state.

[0036] Once the backup is complete, it becomes possible to cut off the power supply to circuit 10. In other words, by providing circuit RC1, the clock gating and power gating of circuit 10 are performed. This will make it possible to do so.

[0037] (Restore operation) When restoring the state of circuit 10, power is supplied to circuit 10 and signal E0 is used. The circuit 10 is configured so that the data from terminal D1 can be output from terminal Q. Terminal D Since point 1 is electrically connected to node FN, its logic level will be the same as node FN. Therefore, circuit 10 receives data with the same logic as the data held at node FN from terminal Q. It can output data. In other words, the state of logic circuit 100 has been restored.

[0038] Turn off switch SW3. If necessary, restart the supply of signal CLK to restore logic. Circuit 100 returns to a state where it can operate normally. Note that before resuming the supply of signal CLK, If the logic of child Q needs to be the same as the logic of node FN for the data retention period, then switch Before turning off SW3, supply a control signal such as CLK to allow circuit 10 to operate normally. Then, write the data from terminal D1 to terminal Q.

[0039] Circuit RC1 can hold data while circuit 10 is power-gated. It just needs to have the necessary retention characteristics. To retain data for a long time in circuit RC1, To minimize the potential fluctuations (especially potential drops) of electrically floating node FN. This is preferable. As one means to achieve this, switches SW2 and SW3 are in a non-conductive state. One approach is to use transistors with very low drain current (off current).

[0040] To lower the transistor's off-current, for example, the semiconductor region has a wide energy cap. It can be formed from a semiconductor. The energy gap of a semiconductor is 2.5 eV or more, or 2. It is preferable that the voltage is 7 eV or higher, or 3 eV or higher. Such semiconductors include oxide semiconductors. A conductor is an example. For instance, switches SW2 and SW3 have semiconductor regions made of oxide semiconductors. It should be a transistor (OS transistor) that is configured. Normalized by channel width. The leakage current of an OS transistor is calculated with a source-drain voltage of 10V and room temperature (around 25°C). ) in the state of 10x10 -21 It is possible to set it to A / μm (10 Zept A / μm) or less. The leakage current of the OS transistor applied to switches SW2 and SW3 is at room temperature (25°C). (At approximately °C) 1 × 10 -18 A or less, or 1 × 10 -21 A or less, or 1 × 10 - 24 A or less is preferable. Alternatively, the leakage current is 1 × 10 at 85°C. -15 A or less, or 1 x 10 -18 A or less, or 1 × 10 -21 It is preferable that it is A or less.

[0041] Oxide semiconductors have a large energy gap, making electrons difficult to excite, and the effective mass of holes... It is a semiconductor with a large size. For this reason, OS transistors are not made of silicon or other materials. Compared to Ranjista, avalanche collapse and other similar events may be less likely to occur. By suppressing hot carrier degradation caused by this, the OS transistor has high drain This provides voltage resistance, allowing it to be driven at a high drain voltage. Therefore, the circuit By applying an OS transistor to RC1, the potential level of the signal and input timing can be controlled. The margin of the dynamic conditions can be increased. For example, the node in the data retention state This also makes it possible to drive the FN voltage higher.

[0042] The oxide semiconductor of the OS transistor is at least one of In, Ga, Sn, and Zn. It is preferable that the oxide contains more than 10 elements. Examples of such oxides include In -Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Z Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In oxide, Sn oxide Examples include Zn oxide. Furthermore, elements and compounds other than the constituent elements of these oxides can be added to them. Materials containing, for example, oxide semiconductors containing SiO2, can be used.

[0043] Furthermore, the OS transistor has a gate insulating layer thickened to approximately 11 nm in terms of oxide film thickness. Even when the channel length is shortened to about 50 nm, it exhibits very good off-current characteristics and subthreading. It is possible to have a Skold characteristic. Therefore, OS transistors can form logic circuits. Because it can use a thicker gate insulating layer than a typical Si transistor, Leakage current through the gate insulating layer is reduced, and electrical characteristics due to variations in the thickness of the gate insulating layer are improved. This also helps to suppress variations. Details of the OS transistor will be explained in Embodiment 4.

[0044] There are no particular restrictions on the switch SW1 and the transistors that make up the circuit 10; standard A common transistor can be used in a docell, for example, if the semiconductor region is It can be a transistor formed from Group 14 elements (Si, Ge, C). A typical example of a transistor is a transistor in which the semiconductor region is formed by silicon. It is a Si transistor. Also, for the purpose of improving the mobility of Si transistors, etc. Alternatively, a strain transistor in which Ge is added to a semiconductor region made of Si may be used.

[0045] Switch SW1, like switches SW2 and SW3, is constructed with an OS transistor. It may be constructed as such, or it may be constructed using a CMOS circuit such as an analog switch. Switch SW1 By using an OS transistor, the logic circuit is created by adding circuit RC1, as described below. It is possible to reduce the area overhead of path 100 to zero. Also, switch SW1 Analog switch (a switch in which an n-type transistor and a p-type transistor are connected in parallel) If this is the case, by stacking n-type OS transistors on top of p-type Si transistors In terms of the logic circuit 100, compared to when the analog switch is constructed using only Si transistors... This can suppress the product increase. Note that analog switches are also called transfer gates. It is being done.

[0046] In logic circuit 100, the change in the circuit configuration of circuit 10 due to the provision of circuit RC1 is not It is necessary. For example, in the configuration example shown in Figure 1B, the selection circuit 20 has a selector or A common circuit, such as a multiplexer, can be applied. Circuit 30 includes: Common sequential circuits such as latches and flip-flops can be applied. Circuit 10 Since it is possible to stack circuit RC1, the design and layout of circuit 10 can be modified. It is possible to install circuit RC1 without making any changes.

[0047] As described above, the holding circuit of this embodiment allows for the circuit configuration and layout of the logic circuit. A backup function can be added to the logic circuit without making any changes. Furthermore, the retention cycle... By using a circuit, a backup function can be added to the logic circuit without substantially degrading the performance during normal operation. It is possible to add them. Furthermore, a holding circuit can be stacked in the region where the logic circuit is formed. Therefore, it is possible to eliminate the area overhead caused by adding a holding circuit. be.

[0048] <Modified example of a holding circuit> The logic circuit 101 shown in Figure 2A has circuit RC2 instead of circuit RC1. This is the same as circuit RC1 with the inverter 42 added. The input terminals of inverter 42 are terminal It is electrically connected to the sub-QB, and its output terminal is electrically connected to switch SW2. Circuit RC2 will hold the logically inverted data of child QB. Therefore, circuit RC2 It holds data with the same logic as terminal Q, and writes the held data to terminal D1. Yes, it is possible. Inverter 42 should only be powered during backup operation.

[0049] The logic circuit 102 shown in Figure 2B has circuit RC3 instead of circuit RC1. This is the same as circuit RC1 with inverters 43 and 44 added. The input terminal of inverter 43 The child is electrically connected to switches SW1 and SW3, and its output terminal is electrically connected to terminal D1. The input terminal of inverter 44 is electrically connected to terminal D0, and the output terminal is connected to S Switch SW1 is electrically connected. Switch SW2 is connected between terminal QB and node FN. It controls the conduction state between them. Due to the backup operation, circuit RC3 operates on the same principle as terminal QB. It holds the data. The data written to terminal D1 by the restore operation is inverter This is the inversion of the logic of node FN by DATA 43. In other words, it is the same logic as terminal Q. The data can be written to terminal D1.

[0050] The circuit 10 shown in Figures 2A and 2B does not necessarily have to have terminal Q.

[0051] <Modified examples of logic circuits> The logic circuit 103 shown in Figure 3 is a modified version of the logic circuit 101. Circuit 10 is a single-input circuit. It has been changed to 15. Circuit 15 is a logic circuit. Circuit 15 has the same logic as terminal D1. It is sufficient to have a calculation function that can output data. Circuit 15 may have, if necessary Control signals such as CLK may be input. Also, circuit 15 may have terminal QB. Good. Circuit 15 could be a buffer circuit, for example.

[0052] Circuit RC4 is a variation of circuit RC1. Switches SW1-SW3 are connected to different signals E It is controlled by 1-E3. This means that only switch SW1 is controlled during the normal operation of logic circuit 103. It can be turned on, and SW1 can be turned off during backup operation.

[0053] [Embodiment 2] <<Configuration Example of Scan Flip-Flop>> A more specific circuit configuration example and driving method example of the logic circuit 100 will be described. Here an example where the logic circuit 100 is a scan flip-flop is shown. The scan flip flop (SFF) 110 shown in FIG. 4 has a scan flip-flop (SFF) 11 and a circuit RC11. SFF11 has a selection circuit (SEL) 21 and a flip-flop (FF) 31. The circuit RC11 is a holding circuit having a function of holding data. SFF110 can be called a scan FF with a backup function. SFF1 110 can be provided in a power domain where power gating is performed.

[0054] <Configuration Example of SFF11> FIG. 5 shows a circuit configuration example of SFF11. The SFF11 shown in FIG. 5 has SEL21, FF31 and terminals VH, VL, D, Q, QB, SD, SE, CK, RT.

[0055] The terminal VH is a power supply terminal for the high power supply voltage VDD, and the terminal VL is a power supply terminal for the low power supply voltage VSS. VDD and VSS are supplied to the inverter of SEL21, the inverter of FF31, and the N AND circuit (hereinafter referred to as "NAND"). The input of VDD to the terminal VH is performed via a power switch.

[0056] The terminals D and SD are data input terminals. The terminal D is electrically connected to the output terminal of a logic circuit (for example, a combinational circuit ), and data DIN is input. To the terminal SD, restoration data or scan test data SCNIN is input via the circuit RC11 (see FIG. 4). The terminal Q is a data output terminal. The terminal Q is for another SFF110 of the data output terminal. Terminal SD_IN is electrically connected to the data input terminal of the logic circuit. Terminal QB is, It outputs data with the logic of terminal Q inverted. Terminal QB is a data input terminal for other logic circuits. It is electrically connected to it. Terminal QB can be provided as needed.

[0057] Terminals SE, CK, and RT are input terminals for control signals. Terminal SE is connected to ScanEnable The signal SEsig is input. SE is electrically connected to SEL21. Terminal CK A clock signal CLK is input to this terminal. Terminal CK is electrically connected to circuit 31a. The reset signal RSTsig is input to terminal RT. Terminal RT is the NAND of FF31. It is electrically connected to it.

[0058] (SEL21) SEL21 selects either terminal D or SD based on the voltage (logic) of terminal SE, and F It has the function of electrically connecting to the input terminal of F31. When performing a scan test, signal S Set E to a high voltage ("H") and electrically connect terminal SD to the input terminal of FF31. To operate SFF11 as a flip-flop normally, set terminal SE to a low level voltage ( Set it to “L” and electrically connect terminal D to the input terminal of FF31.

[0059] (FF31) FF31 has two latches 32M, 33S, and circuit 31a. Latch 32M is The master latch is latch 32S, the slave latch is latch 32M and latch 32M. 32S is electrically connected in series. Circuit 31a is a circuit for clock signal input. It has terminals CK1 and CKB1. Terminal CK1 outputs the non-inverting clock signal of signal CLK. This is the terminal. Terminal CKB1 is the terminal that outputs the inverted clock signal of the signal CLK. Terminals CK1 and CKB1 are electrically connected to the analog switches of the FF31, respectively. It is being done.

[0060] <Example of a holding circuit configuration 1> The circuit RC11 shown in Figure 4 has terminals SD_IN, RE, BK and PL, node FN11, It has transistors M1-M3 and a capacitive element C11. Circuit RC11 is a component of circuit RC1 The circuit is composed of switches SW1-SW3, each made up of transistors M1-M3. In the following explanation, terminal VH may sometimes be referred to simply as VH. The same applies to other terminals. Also, node FN11 is sometimes simply referred to as FN11.

[0061] SD_IN is the input terminal for scan test data SCNIN. BK and RE are control signals. This is the input terminal for the number. BK is the signal that controls the backup operation (backup signal). BKsig) is input. BK is electrically connected to the gates of transistors M1 and M2. The RE receives a signal (restore signal REsig) that controls the restore operation. RE is electrically connected to the gate of transistor M3.

[0062] Of the two terminals of the capacitive element C11, one is electrically connected to FN11, and the other is connected to PL. They are electrically connected. VSS is input to PL. Transistors M1-M3 are It is an n-type transistor, and in this case it is an OS transistor. Transistor M1 has SD_IN and SD and It is a pass transistor for electrically connecting Q and FN1. Transistor M2 is connected to Q and FN1. This is a pass transistor for electrically connecting to 1. Transistor M3 is FN1 This is a pass transistor for electrically connecting 1 and SD.

[0063] Because transistors M2 and M3 are OS transistors, FN11 receives the data "1". Even when held in place, the voltage drop at FN11 can be suppressed. Therefore, the circuit RC It is possible to make 11 function as a non-volatile memory circuit for backup of SFF11. This will result in power gating for semiconductor devices equipped with the SFF110. This makes it possible to reduce the power consumption of semiconductor devices.

[0064] Note that during the data retention period of circuit RC11, transistors M2 and M3 are completely off. In some cases, such a voltage may be continuously applied to the gate. Alternatively, transistors M2 and M If a back gate is provided at 3, transistors M2 and M3 will be in a normally-off state. In some cases, such a voltage may continue to be supplied to the back gate. In such cases, the retention period During this time, voltage is supplied to circuit RC11, but almost no current flows. Therefore, circuit RC11 consumes almost no power. Consequently, the predetermined voltage during the holding period Even if power is supplied to circuit RC11, circuit RC11 consumes very little power. Therefore, circuit RC11 can be considered non-volatile.

[0065] <<Example of ScanFlipFlop Operation>> Figures 6 and 7 are timing charts showing an example of SFF110 operation. Figure 6 shows SFF1 When a semiconductor device incorporating 10 transitions from active mode to sleep mode The following shows an example of SFF110 operation; Figure 7 shows the transition from sleep mode to active mode. The following shows an example of the operation of the SFF110 during the process. Figures 6 and 7 show terminals VH, CK, Q, and SE. Figure 6 shows the voltage (logic) changes at SD, BK, RE, and node FN11. In 7, the maximum voltage is VDD and the minimum voltage is VSS. Also, t1-t10 is It represents the time.

[0066] <Active Mode (Normal Operation Mode)> In active mode, the SFF110 operates normally. The SFF110 is derived from the logic circuit. It functions as a flip-flop that temporarily holds the output data. Here, logic circuits The output data will be input to terminal D. During normal operation, RE and BK are "L". Therefore, transistors M1-M3 are off. SE is "L", and SEL21 Therefore, terminal D is connected to the input terminal of FF31. RT is "H". Signal C is connected to CK. LK is input. As CK becomes "H", the voltage (logic) of Q changes.

[0067] <Scan Mode> In scan mode, multiple SFF110s are electrically connected in series, forming a scan chain. This is formed. In circuit RC11, transistors M1 and M2 are turned on, and the transistor M3 is turned off. Since SE is "H", SEL21 causes SD to receive FF31 input. It is electrically connected to the terminal. In other words, in scan mode, the output data of Q of SFF11 However, this will be input to the SD card of the next stage, SFF11.

[0068] (Scan test) To perform a scan test, switch to scan mode and select the first stage of the scan chain, SFF1 Input scan test data SCNIN to SD_IN 10. The CLK input will trigger... Perform a scan chain shift operation and scan test on SFF110 of the scan chain. Write the data SCNIN. Next, operate the SFF110 normally and output the logic circuit data. The data is held in SFF110. Switch back to scan mode and scan chain. The process is performed. From the data output from Q of the final stage SFF110, the logic circuit and It is possible to determine whether or not the SFF110 is faulty.

[0069] (Backup sequence) The backup sequence is performed by switching from active mode to sleep mode. In the backup sequence, clock gating (clock stop) is performed. Data backup and power gating (power off) are performed. Clock support The device enters sleep mode when the power supply is stopped.

[0070] In the example in Figure 6, at t1, clock gating of SFF11 begins, and in circuit RC11... The backup process has started. Specifically, on t1, CK will be "L" and BK will be "H" The period during which BK is "H" is the backup operation period. As a result, transistor M2 electrically connects FN11 to Q. Therefore, Q becomes "0 If so, FN11 remains "L", and if Q is "1", the voltage of FN11 is higher It rises to "H". In other words, during the period when BK is "H", the logic of FN11 is the same as Q. This is possible. BK allows the voltage of FN11 to rise to a logic level of "1". We just need to determine the period during which it is "H". At t2, set BK to "L" and transistors M1 and M2 By turning it off, FN11 becomes electrically floating, and circuit RC11 enters a data holding state. To become.

[0071] At t3, the power is turned off and RT is set to "L". The voltage of VH gradually drops from VDD, V This will result in SS. Power may be cut off at t2. Power should be cut off only as needed. The configuration of the power domain of the semiconductor device into which the SFF110 is incorporated, and the sleep mode Depending on the duration, the power saved by shutting off the power may outweigh the power saved by sleep mode. In some cases, the power required to return from dormant mode to active mode may be greater. In this case, the power gating effect cannot be obtained, so the power is not available in sleep mode. It is preferable to simply stop the clock supply without completely shutting down the system.

[0072] (Restore sequence) During the restore sequence, which transitions from sleep mode to active mode, the power supply is... Then, data restoration and clock supply are performed. By starting the clock supply... It then enters active mode.

[0073] Turn on the power at t4. The voltage of VH gradually rises from VSS to VDD. VH After VDD is activated, the restore operation will begin. Set SE and RE to "H" at t5. Also, R Set T to "H". The restore operation is performed while RE is "H". Transistor M3 The FN11 is turned on, and the FN11 and SD card are connected. If the FN11 is set to "L", then the SD card is set to "L". It remains the same. If FN11 is "H", the voltage of SD rises and becomes "H". Set SE to "H". SE and SEL21 electrically connect SD to the FF31 input terminal. The connection is established. In other words, by setting RE to "H", the data held in FN11 is S It will be written to D.

[0074] Furthermore, at t5, it is also possible to set SE to "H" along with RE. As shown in Figure 7, F If N11 is "H", then the voltage of SD rises to the logic level of "1", and then SE It is preferable to set it to "H". With this drive, a through current flows through SFF11. This can prevent that from happening.

[0075] To write the data from FN11 to the SD card by capacity distribution, FN11 is in the "H" state, F When N11 is connected to SD, the voltage of FN11 drops due to the parasitic capacitance of SD. Therefore, the capacity of C11 may need to be significantly larger than the parasitic capacity of SD. The capacity of 11 should be determined by considering the characteristics of the logic circuit into which the SD data is input. For example, if the threshold voltage of this logic circuit is VDD / 2, the capacitance of C11 is the parasitic capacitance of SD. It needs to be more than the specified amount.

[0076] After the SD logic becomes the same as FN11, set CK to "H" for a certain period (t7 to t8). In the example in Figure 7, CLK is input to CK for one clock cycle. CK becomes "H" at t7. As a result, the data from latch 32M is written to latch 32S. When SD is "0" at t7 If the value is 0, then Q will be "0", and if the value is 1, then Q will be "1". In other words, the FN11's The data is written to Q, and the CLK supply to SFF110 is stopped (it enters sleep mode). (ru) Restore to the state immediately before. Set SE and RE to "L" in t9 to terminate the restore operation. SEL21 electrically connects D to the input terminal of FF31. In circuit RC11, The M3 transistor turns off, and node FN11 enters a floating state.

[0077] After setting SE and RE to "L", at t10, after a certain period of time (for example, 1 clock cycle), Resume CLK input and put SFF110 into active mode. SFF110 normally operates To carry out a project.

[0078] As mentioned above, the SFF110 enables high-speed data backup and restore. For example, completing backup and restore operations within a few clock cycles (2 to 5 clock cycles). It is possible to complete this. The programming operation of circuit RC11 is performed by the transistors M1-M3. The switching operation is an operation to charge or discharge FN11, and the read operation is a switch operation. This operation involves charging or discharging the SD card through the switching action of transistors M1-M3. Therefore, the energy required for these operations is small, similar to that of DRAM cells. Therefore, since there is no need to supply power to circuit RC1, the standby power consumption of SFF110 is reduced. It can be eliminated. Similarly, power supply to circuit RC11 is not required during normal operation. Therefore, the dynamic power of the SFF110 due to the provision of circuit RC11 is effectively It does not increase. By providing circuit RC11, the parasitic capacitance due to transistor M1 is reduced. This will be added to sub-Q, but it will be small compared to the parasitic capacitance caused by the logic circuit connected to terminal Q. Therefore, the normal operation of the SFF110 is not affected, and by providing the RC11 circuit, the active This does not substantially degrade the performance of the SFF110 in live mode.

[0079] The following describes other circuit configuration examples for a holding circuit, using a scan flip-flop as an example.

[0080] <Example of a holding circuit configuration 2> The SFF112 shown in Figure 8 has circuits RC12 and SFF11. Circuit RC12 is This is a modified example of path RC11 (Figure 4), and capacitive coupling is performed between node FN11 and terminal RE. It has a capacitive element C12. With this circuit configuration, the power of RE during restore operation By setting the voltage to VDD ("H"), the voltage at node FN11 can be increased. Therefore, circuit RC12 can maintain a high voltage for a longer period than circuit RC11. This becomes possible. However, in this case, if node FN11 is holding a "L" voltage However, the voltage at node FN11 will rise. Therefore, in this case, the "L" of node FN11 When the voltage of " is written to the SD card, the SD card's voltage will be at a logical level of "0", The capacitance of element C12 is set. Therefore, the capacitance of capacitive element C12 is smaller than that of C11.

[0081] <Examples of holding circuit configurations 3 and 4> The SFF113 shown in Figure 9 has circuits RC13 and SFF11. The SF shown in Figure 10 F114 has circuits RC14 and SFF11.

[0082] In the circuit RC12 shown in Figure 8, the capacitance ratio of capacitive elements C12 and C11 determines the node at SD. When the voltage of FN11 is written to "H", if the voltage of SD exceeds the logic level of "1", There is a match. In such cases, if circuit RC13 or circuit RC14 is used as the holding circuit Good. Circuit RC13 adds buffer 45 (hereinafter referred to as BUF45) to circuit RC12. This is the added circuit. The input terminal of BUF45 is connected to the drain (or source) of transistor M3. ) is electrically connected to the SD card, and the output terminal of the BUF45 is electrically connected to the SD card. 45 transistors are preferably high-voltage types that can withstand gate voltages exceeding VDD. It's nice.

[0083] The circuit RC14 shown in Figure 10 is a modified version of the circuit RC13. As shown in Figure 10, the capacitance element The connection position of sub-C12 has been changed. One terminal of the capacitive element C12 is connected to transistor M. It is electrically connected to the drain (or source) of terminal 3, and the other terminal is the input terminal of BUF45. It is electrically connected to it. If necessary, BUF45 can be installed in circuit RC14.

[0084] <Examples of holding circuit configurations 5 and 6> The SFF115 shown in Figure 11 has circuits RC15 and SFF11. The S shown in Figure 12 FF116 has circuits RC16 and SFF11. Circuits RC15 and RC1 6 is a modified version of circuit RC11, with transistor M1- having a back gate. It has M3.

[0085] Circuit RC15 is configured such that the back gates of transistors M1-M3 are electrically connected to terminal OBG. It is configured to accept a signal or a constant potential as input to the OBG. Alternatively, OB A capacitive element may be connected to G. This capacitive element should be charged, and transistors M1-M3 The back gate voltage of transistors M1-M3 may be maintained. The threshold voltage of transistors M1-M3 can be adjusted by the voltage of the circuit. This is the result.

[0086] In circuit RC16, the back gate is electrically connected to the gates of transistors M1-M3. This device structure allows for the on-current characteristics of transistors M1-M3 to be determined. This can improve it.

[0087] In circuit RC15, back gates were added to transistors M1-M3, but some of them A transistor without a back gate may also be used. Alternatively, transistor M1 may be provided with a back gate. In this case, the back gate may be connected to terminal OBG, or the gate of transistor M1 may be connected to They may be electrically connected. This also applies to transistors M2 and M3. Yes, it exists. Circuit RC16 is similar.

[0088] <<Example of processing unit configuration>> An example of a semiconductor device having a scan flip-flop is described. The semiconductor device shown in Figure 13 is a processing device. It has a (PU)200 and a power supply circuit 210. The PU200 has the function of executing instructions. This is a circuit. The PU200 has multiple functional circuits integrated on a single chip. 00 consists of a processor core 201, a power management unit (PMU) 202, and a power switch (PS). Figure 13 shows that the power supply circuit 210 is connected to the PU200. This shows an example where it is provided on a different chip. Terminal 220 is a power supply terminal, and power The power supply voltage VDD is input from circuit 210. Terminals 221 and 222 are signal input terminals. Yes. Terminal 221 receives the master clock signal MCLK. Terminal 222 receives the IN signal. The input is T. The signal INT is an interrupt signal that requests interrupt processing. Signal INT This is input to processor core 201 and PMU202.

[0089] <Processor Cores> The processor core 201 is a circuit that has the function of processing instructions, and is an arithmetic processor. It can also be called a circuit or processor (processing unit). 20 processor cores Unit 1 has logic circuits 240 and SFF (scan FF) 250, etc., and Various functional circuits are configured. For example, logic circuit 240 is a combinational circuit. It is possible. For example, SFF250 is included in the register. SFF250 is SFF5 It has 0 and circuit RC50. SFF50 only needs to have the function of a scan flip-flop. It can be constructed using scan flip-flops available in a standard circuit library. Circuit RC50 is a holding circuit for backup of SFF50, and circuits RC11-RC14 This can be applied. Terminal Q of SFF250 is electrically connected to the input terminal of logic circuit 240. To connect to and form a scan chain, the other SFF250 terminal SD_IN It is electrically connected to the SFF250. Clock gating and power gating are now possible, reducing the power consumption of the PU200. It can be reduced.

[0090] Figure 14 shows an example configuration of processor core 201. The processor core 201 shown in Figure 14 is Control device 231, program counter 232, pipeline register 233, pipeline Register 234, Register File 235, ALU (Arithmetic Logic Unit) 236, and It has a data bus 237. It has a processor core 201 and a PMU 202 and a cache, etc. Data exchange with edge circuits is performed via data bus 237.

[0091] The control device 231 includes a program counter 232, a pipeline register 233, and a pipeline Operation of In Register 234, Register File 235, ALU 236, and Data Bus 237 By comprehensively controlling it, the life contained in the input application or other program It has the function of decoding and executing commands. The ALU236 performs various operations such as arithmetic and logical operations. It has the function of performing seed calculations. The program counter 232 is the addition of the next instruction to be executed. This is a register that has the function of storing a response.

[0092] Pipeline register 233 is a register that has the function of temporarily storing instruction data. Yes. Register file 235 has multiple registers, including general-purpose registers, Data read from in-memory, or data obtained as a result of the ALU236's arithmetic processing. It can store things like "ta". Pipeline register 234 is used for calculations of ALU236. Data used for processing, or data obtained from the ALU236's calculations, etc., are temporarily stored. This is a register that has the function of storing data.

[0093] <Power management> The PMU202 has functions to control power gating, clock gating, etc. More specifically, the PMU202 consists of processor core 201, PSW203, and clock speed It has the function to control circuit 204. PMU202 is a processor core 2 01 has the function of outputting control signals such as BKsig, REsig, and SEsig.

[0094] The PMU202 has a circuit 205. The circuit 205 has the function of measuring time. The PMU202 performs power management based on time data obtained from circuit 205. It has the ability to perform the following: For example, by making circuit 205 a timer circuit, PM You may also configure U202 to generate the timer interrupt request signal. Circuit 2 as needed. It is only necessary to provide 05.

[0095] The PSW203 has a function of controlling the supply of VDD to the PU200 in accordance with the control signal of the PMU202. In the example of FIG. 13, the processor core 201 may have a plurality of power domains. In this case, the power supply to the plurality of power domains may be independently controlled by the PSW203. Further, the processor core 201 may have a power domain in which power gating is not performed. In this case, VDD may be supplied to this power domain without going through the PSW203.

[0096] The clock control circuit 204 has a function of generating a gated clock signal from the signal MCLK and outputting it. The clock control circuit 204 has a function of blocking the supply of the clock signal to the processor core 201 in accordance with the control signal of the PMU202. The power supply circuit 210 may have a function of changing the magnitude of VDD in accordance with the control signal of the PMU202.

[0097] A signal SLP is output from the processor core 201 to the PMU202. The signal SLP is a signal that serves as a trigger for shifting the processor core 201 to the sleep mode. In accordance with the signal SLP, in the processor core 201, the backup sequence of the SFF250 is executed. The backup sequence of the SFF250 can be executed in the same manner as the backup sequence of the SFF110 shown in FIG. 6. When the signal SLP is input, the PMU202 outputs a control signal for shifting from the active mode to the sleep mode to the functional circuit to be controlled. The PMU202 controls the clock control circuit 204 and the processor​​​​ Stop supplying the clock signal to the SACOA 201. Also, the PMU 202 controls the PSW 203 to stop supplying power to the processor core 201.

[0098] The process for returning the processor core 201 from the sleep mode to the active mode is executed by the input of the signal INT. In accordance with the signal INT, in the processor core 201, S the restore sequence of the SFF 250 is executed. The restore sequence of the SFF 250 can be executed in the same manner as the restore sequence of the SFF 110 shown in FIG. 7 is. When the signal INT is input, the PMU 202 outputs a control signal for transitioning from the sleep mode to the active mode to the functional circuit to be controlled. The PMU 202 controls the PSW 20 3 to resume supplying power to the processor core 201, and also controls the clock control circuit 204 to resume supplying the clock signal to the processor core 201.

[0099] The backup sequence may be made executable triggered by the signal INT or the interrupt request signal of the PMU 202 . Also, the restore sequence may be made executable triggered by the interrupt request signal of the PMU 2 02.

[0100] <<Device Structure of SFF250>> FIG. 15 shows the device structure of the SFF 250. In FIG. 15, the circuit RC50 has the same circuit configuration as the circuit RC 11 (FIG. 4). The transistors M1 - M3 are OS transistors . The SFF 250 can have a three - dimensional device structure in which the circuit RC50 is stacked on the SFF50 . W1, W k , W k+1 , W hThese are the first wiring layer, the kth wiring layer, and These are the k+1th wiring layer and the hth wiring layer. k is an integer greater than or equal to 1, and h is an integer greater than or equal to k+2. Yes, it exists. Terminals D, SD, Q, SE, and CK of the SFF50 are on wiring layer W. k It is provided in the circuit RC5 Terminal 0, SD_IN, is on wiring layer W h It is located at [location].

[0101] The FET layer 260 is provided with an SFF50 transistor. The transistor can be fabricated using a standard CMOS process. Wiring layer W1–W k to the conductor Therefore, the transistors in FET layer 260 are electrically connected. Wiring layer W k+1 ―W h of The conductor electrically connects SFF50 and circuit RC50.

[0102] Circuit RC50 has significantly fewer elements compared to SFF50, so stacking Circuit RC50 To achieve this, no changes to the circuit configuration or layout of the SFF50 are necessary. In other words, the circuit RC 50 is a highly versatile backup circuit. Also, SFF50 is formed Since the circuit RC50 can be installed within the region, even if the circuit RC50 is installed, SFF The area overhead for 250 is zero.

[0103] <<Integrated circuit incorporating circuit RC50>> Therefore, in the processor core 201 shown in Figure 13, circuit RC50 is in the shadow of the SFF50 arrangement. The SFF50 can be positioned to allow for efficient scan testing without causing interference. In other words, by using circuit RC50 as a backup circuit, a backup function is provided. The integrated circuit design is easy, and ease of testing is also ensured.

[0104] In the processor core 201, like SFF50, other standard cells such as NAND circuits are provided in the FET layer 260 and the wiring layers W1 - W k Wiring layers W1 - W k has circuits Since conductors for connecting RC50 and the terminals SD and Q are formed, the wiring of other standard cells needs to be laid out bypassing these conductors, and for this reason, the area of the processor core 201 may increase. SFF250 is one of the standard cells that are mounted more on the processor core 201, but the area overhead of SFF250 due to the mounting of the circuit RC50 is 0. Therefore, the increase in the area of the processor core 201 is only due to the change in the layout of the wiring between other standard cells, and the area overhead of the processor core 20 1 can be suppressed to less than a few percent. This was confirmed by designing a processor core with the circuit RC5 0 mounted. Also, through simulation, it was confirmed that the processor core with the circuit RC50 mounted is power-saving.

[0105] <Area and Power of Processor Core> A processor core with a scan FF having the circuit RC50 was designed. This processor core will be called an "OS-FF mounted processor", and the scan FF having the circuit RC50 will be called OS-FF. For comparison, a CPU core with a scan FF without the circuit RC 50 mounted was designed. This processor core will be called a "Si-FF mounted processor" .

[0106] The designed processor core is a RISC processor core. The OS-FF mounted processor The Si-FF-equipped processor and this processor have the same circuit configuration, except for the presence or absence of the RC50 circuit. Circuits other than RC50 are composed of Si transistors. The channel length is 60nm and the channel length of the OS transistor is 60nm in the design log. The processor core was designed using this method. The area of ​​the Si-FF-equipped processor is 275μm x 27 The thickness is 2 μm, and the area of ​​the OS-FF-equipped processor is 275 μm × 272 μm. The flip-flop (FF) occupies nearly half of the logic circuits of the processor core. OS-FF equipped processors... Even with circuit RC50 provided for each scan FF, the area overhead is kept to 3%. It is being obtained.

[0107] In the simulation, the dynamometer of the Si-FF-equipped processor when the power supply voltage is 1.2V The dynamic power is 19μA / MHz, and the dynamic power of the OS-FF-equipped processor is also The current is 19 μA / MHz, and the dynamic power has not increased due to the inclusion of the RC50 circuit. Furthermore, the standby power consumption of the OS-FF-equipped processor when power gating is 0 It was estimated to be 0.03 μA.

[0108] The performance of the designed OS-FF was confirmed by simulation. OS transistor channel If the length is 65 nm and the threshold voltage is 1.6 V, then the OS-FF at room temperature The retention time exceeds 30 days. In other words, the sleep period of the OS-FF equipped processor, OS- It was confirmed that FF has sufficient retention performance as a non-volatile memory circuit.

[0109] In the simulation, the backup time of the OS-FF at an operating frequency of 50MHz was... The time for both the clock cycle and the restore time is 2 clock cycles. Power game of OS-FF equipped processor Since the overhead time due to the processing operation is sufficiently short, OS-FF is the processor It was confirmed that this does not substantially degrade the performance.

[0110] The simulation showed the power saving effect of OS-FF-equipped processors through power gating. I confirmed that the active period was 1 msec, while the sleep period was 1 msec, 1 se The power consumption was estimated for operating conditions c and 100 sec. The power supply voltage was It is 1.2V. Under operating conditions 1 (active period 1 msec, sleep period 1 msec) The power consumption is 570 μW. Operating conditions 2 (active period 1 msec, sleep period) The power consumption at 1 sec is 1.2 μW. Operating condition 3 (active period 1 msec, The power consumption during the sleep period (100 sec) is 0.05 μW. Gating can effectively reduce the power consumption of OS-FF-equipped processors. This was confirmed.

[0111] The scan flip-flop of this embodiment has a holding circuit, which provides, for example, the following excellent effects: It is effective. In this scan flip-flop, the area overhead due to the inclusion of a holding circuit is 0 This is possible. By providing a holding circuit, the power consumption during normal operation is almost Furthermore, it is possible to achieve virtually no decrease in normal operating performance. Low power consumption and high speed It can be backed up and restored. It can retain data without a power supply. Yes, it is. Furthermore, this scan flip-flop can be designed using the scan flip-flop from the circuit library as is. Because it can be done this way, it is easy to design. Therefore, the integrated circuit equipped with this scan flip-flop is Even when this scan FF is used to configure a scan chain, the ease of testing is not compromised. .

[0112] Thus, this scan FF is very well suited for normally-off computing. Even with this scan flip-flop installed, the increase in dynamic power of the integrated circuit and the performance degradation are minimal. It is possible to prevent this from happening. Therefore, the collection equipped with this scan FF The integrated circuit effectively reduces power consumption through power gating while maintaining performance. This is possible.

[0113] Here, we have described a form of sequential circuit where the sequential circuit is a scan flip-flop, but the above effect can also be applied to other sequential circuits. You can obtain results.

[0114] [Embodiment 3] In this embodiment, as an example of a semiconductor device, an electronic component and an electronic device equipped with the electronic component are used. Let's explain the utensils and other items.

[0115] <Examples of methods for manufacturing electronic components> Figure 16A is a flowchart showing an example of an electronic component manufacturing method. Electronic components are semiconductor components. Also called a package, or IC package. This electronic component has terminals that can be taken out in a specific direction, and the terminals are also packaged. Depending on the shape of the child, there are multiple standards and names. Therefore, in this embodiment, one example is presented. I will now explain this.

[0116] A semiconductor device composed of transistors goes through an assembly process (back-end process) to a printed circuit board. It is completed by combining several detachable parts. For subsequent processes, see each of the steps shown in Figure 16A. It can be completed by going through a process. Specifically, the element substrate obtained in the previous process is completed After completion (step S1), the back surface of the substrate is ground (step S2). At this stage the substrate By thinning the film, we can reduce warping of the substrate during the previous processing stage and miniaturize the components.

[0117] The back surface of the substrate is ground down to perform a dicing process, which separates the substrate into multiple chips. Die bonding involves individually picking up chips, mounting them onto a lead frame, and then joining them together. The process is carried out (step S3). The chip and lead frame in the die bonding process and The bonding method should be selected to suit the product. For example, bonding can be done with resin or tape. It can be done as is. The die bonding process involves mounting the chips on the interposer and bonding them together. In the wire bonding process, the leads of the lead frame and the electrodes on the tip are bonded to a metal... Connect electrically with thin wires (step S4). For the thin metal wires, use silver or gold wires. It can be used. Wire bonding is a combination of ball bonding and wedge bonding. Either of the following is acceptable.

[0118] The wire-bonded chips are then sealed with epoxy resin or the like in a molding process. (Step S5). The molding process fills the inside of the electronic component with resin. This reduces damage to the internal circuitry and wires caused by mechanical external forces. Furthermore, it can reduce the deterioration of properties due to moisture and dust. The lead is then cut and shaped (step S6). This prevents lead rust and ensures more reliable soldering when mounting to a printed circuit board later. This can be done. Printing (marking) is applied to the surface of the package (Step S7). Inspection The electronic component is completed (step S9) after going through the process (step S8). By incorporating a semiconductor device, it is possible to provide small electronic components with low power consumption. ru.

[0119] Figure 16B shows a schematic perspective view of the completed electronic component. Figure 16B shows an example of an electronic component. Figure 16B shows a schematic, oblique view of a QFP (Quad Flat Package). As shown, the electronic component 7000 has a lead 7001 and a circuit section 7003. Section 7003 contains, for example, the scan flip-flop (SFF) of Embodiment 2 and other logic circuits. It is being manufactured. The electronic component 7000 is mounted on a printed circuit board 7002, for example. Multiple such electronic components 7000 are combined, and each is powered on the printed circuit board 7002. By being electrically connected, it can be mounted on electronic devices. The completed circuit board 7004 is They are installed inside electronic devices, etc. For example, the electronic component 7000 is a loop that stores data. Dumb access memory, CPU, MCU (microcontroller unit), FPGA, none It can be used in processing units that perform various processes such as line ICs. By installing product 7000, the power consumption of electronic devices can be reduced. Alternatively, This makes it easier to miniaturize the sub-devices.

[0120] Therefore, electronic component 7000 is used in digital signal processing, software-defined radio, and avionics. (Electronic equipment related to aviation, such as communication equipment, navigation systems, autopilot systems, and flight management systems), ASIC prototyping, medical image processing, speech recognition, cryptography, bioinformatics Kus (biominformatics), mechanical device emulators, and radio telescopes in radio astronomy This can be applied to electronic components (IC chips) in a wide range of electronic devices. Such electronic devices include display devices, personal computers (PCs), and recording media. Image playback device (recording media such as DVD, Blu-ray disc, flash memory, HDD, etc.) Examples include a device for playing back audio and a device having a display unit for displaying images. In addition, electronic devices that can use an electronic component according to one embodiment of the present invention include portable devices. Telephones, game consoles including portable devices, portable data terminals, e-readers, cameras (video cameras, Digital still cameras, etc., wearable display devices (head-mounted, goggles, (Eyeglass type, armband type, bracelet type, necklace type, etc.), navigation system, sound reproduction Audio equipment (car audio, digital audio players, etc.), photocopiers, facsimile machines, Examples include printers, multifunction printers, automated teller machines (ATMs), and vending machines. These electronic devices are shown in Figure 17.

[0121] The portable game console 900 shown in Figure 17A consists of a casing 901, a casing 902, a display unit 903, and a display unit. Unit 904, microphone 905, speaker 906, operation key 907, and stylus 9 It has 08, etc.

[0122] The portable information terminal 910 shown in Figure 17B consists of a housing 911, a housing 912, a display unit 913, and a display unit It has 914, a connection part 915, and an operation key 916, etc. The display unit 913 is located in the housing 911. A display unit 914 is provided on the housing 912. The housing 911 is connected by a connection unit 915. The housing 912 is connected to the housing 911, and the angle between the housing 911 and the housing 912 is determined by the connecting part 915. It is changeable. Therefore, the connection between housing 911 and housing 912 at the connection part 915 It may be configured to switch the image displayed on the display unit 913 according to the angle. Also, a display device with a touch panel may be used for the display unit 913 and / or the display unit 914. .

[0123] The notebook PC 920 shown in FIG. 17C includes a housing 921, a display unit 922, a keyboard 923, and a pointing device 924, etc.

[0124] The electric refrigerator-freezer 930 shown in FIG. 17D includes a housing 931, a refrigerator door 932, and a freezer door 933, etc.

[0125] The video camera 940 shown in FIG. 17E includes a housing 941, a housing 942, a display unit 943, an operation key 944, a lens 945, and a connection part 946, etc. The operation key 944 and the lens 945 are provided on the housing 941, and the display unit 943 is provided on the housing 942. Then, the housing 941 and the housing 942 are connected by the connection part 946, and the connection part 94 6 is structured such that the angle between the housing 941 and the housing 942 can be changed. According to the angle of the housing 942 with respect to the housing 941, the orientation of the image displayed on the display unit 943 may be changed, and the display / non-display of the image may be switched, etc.

[0126] The automobile 950 shown in FIG. 17F includes a vehicle body 951, wheels 952, a dashboard 953, and headlights 954, etc.

[0127] [Embodiment 4] In this embodiment, an oxide semiconductor, an OS transistor, etc. will be described.

[0128] <<Configuration Example 1 of OS Transistor>> Figure 18 shows an example of the configuration of an OS transistor. This is a top view illustrating an example. Figure 18B is a cross-sectional view along the line y1-y2, and Figure 18C is a cross-sectional view along the line x1-x2. This is a cross-sectional view, and Figure 18D is a cross-sectional view along the line x3-x4. Here, the direction of the line y1-y2 The direction of x1-x2 is sometimes referred to as the channel length direction, and the direction of x1-x2 lines is sometimes referred to as the channel width direction. Figure 18B shows the cross-sectional structure of the OS transistor in the channel length direction, and Figure 18C Figure 18D shows the cross-sectional structure of the OS transistor in the channel width direction. To clarify the device structure, some components have been omitted in Figure 18A.

[0129] The OS transistor 501 is formed on an insulating surface. Here, it is formed on an insulating layer 511. The insulating layer 511 is formed on the surface of the substrate 510. The OS transistor 501 is It is covered with insulating layer 514 and insulating layer 515. Note that insulating layers 514 and 515 are O It can also be considered a component of the S transistor 501. The OS transistor 501 is an absolute Edge layer 512, insulating layer 513, oxide semiconductor (OS) layer 521-523, conductive layer 530, conductive It has an electrical layer 541 and a conductive layer 542. The insulating layer 513 functions as a gate insulating layer. It has a region. The conductive layer 530 functions as a gate electrode. Here, OS layer 521, O S layer 522 and OS layer 523 are collectively referred to as OS layer 520.

[0130] As shown in Figures 18B and 18C, OS layer 520 consists of OS layer 521, OS layer 522, and OS It has a portion where layers 523 are stacked in that order. The insulating layer 513 covers this stacked portion. The conductive layer 531 overlaps with the laminated portion via the insulating layer 513. Conductive layer 541 and conductive layer 54 2 is provided on a stack consisting of OS layer 521 and OS layer 523, and each is stacked It is in contact with the top surface of the layer and the side surface in the channel length direction of the stack. Also, in the example of Figure 18, the conductive layer Layers 541 and 542 are also in contact with the insulating layer 512. OS layer 523 is in contact with OS layers 521 and 522. , and are formed to cover conductive layers 541 and 542. The lower surface of OS layer 523 is OS It is in contact with the upper surface of layer 522.

[0131] In the OS layer 520, the stacked portion of the OS layers 521-523 is separated by the insulating layer 513. A conductive layer 530 is formed so as to surround the width direction of the panel (see Figure 18C). Therefore, a gate electric field from the vertical direction and a gate electric field from the side direction are also applied to this stacked portion. In the OS transistor 501, the gate electric field is the conductive layer 530 (gate electrode). This refers to the electric field formed by the voltage applied to a layer. Therefore, the gate electric field Therefore, the entire stacked portion of OS layer 521-523 can be electrically surrounded, Channels may form throughout (bulk) 22. Therefore, OS Transis The TA501 can have a high on-current.

[0132] In this specification, a gate electric field can electrically surround a semiconductor in this manner. The structure of the transistor is called a "surrounded channel (s-channel)". This is called a structure. The OS transistor 501 has an s-channel structure. In a NEL structure, a large current can flow between the source and drain of the transistor, and conduction is possible. The drain current (on-current) in this state can be increased.

[0133] By making the OS transistor 501 an s-channel structure, the side surface of the OS layer 522 Since a gate electric field can also be applied, it becomes easier to control the channel formation region. Conductive layer In a structure where 530 extends below OS layer 522 and faces the side of OS layer 521, Furthermore, it has excellent controllability, which is desirable. As a result, the subthreshold of the OS transistor 501 This allows for a reduction in the swing value (also called the S value), thereby suppressing short-channel effects. This is possible. Therefore, it is a structure suitable for miniaturization.

[0134] The OS transistor, like the OS transistor 501, has a three-dimensional device structure. This allows the channel length to be reduced to less than 100 nm. This miniaturizes the OS transistor. This allows for a smaller circuit area. The channel length of the OS transistor should be less than 65 nm. It is preferable that the channel length be small, and more preferably 30 nm or less, or 20 nm or less. Both should be set to 10nm.

[0135] A conductor that functions as the gate of a transistor is used as the gate electrode, and the source of the transistor is used as the source. The functional conductor is the source electrode, and the conductor that functions as the drain of the transistor is the drain. The electrode, the region that functions as the source of the transistor, and the transistor's drain. The region that functions as a gate is called the drain region. In this specification, the gate is referred to as the gate, and the drain is referred to as the drain region. The in-electrode or drain region is referred to as the drain, and the source electrode or source region is referred to as the source. There are cases where this is the case.

[0136] Channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the part of the semiconductor through which current flows when the gate electrode is ON overlaps with the gate electrode, This refers to the distance between the source and drain in the region where the channel is formed. In a single transistor, the channel length is not necessarily the same across all regions. The channel length of a single transistor may not be fixed to a single value. Therefore, In the specification, the channel length is any one of the values ​​in the region where the channel is formed, maximum This can be the value, minimum value, or mean value.

[0137] Channel width refers to, for example, the channel width of a semiconductor (or transistor) when it is in the ON state. In the region where the current flows and the gate electrode overlap, or in the region where the channel is formed This refers to the length of the part where the source and drain face each other. In a stylus, the channel width is not necessarily the same across all regions. That is, one channel The channel width of a transistor may not be fixed to a single value. Therefore, in this specification... The channel width is any one value, maximum value, or minimum value in the region where the channel is formed. Alternatively, use the average value.

[0138] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. There are cases where this occurs. For example, in transistors with a fine and three-dimensional structure, the sides of the semiconductor In some cases, the proportion of the channel region formed may be large. In such cases, it is shown in the top view. The effective channel width in which the channel is actually formed is greater than the apparent channel width. The one becomes larger.

[0139] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0140] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel is the length of the portion in the region where the source and drain face each other. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "channel width." Also, in this specification, when simply referred to as channel width, This may refer to the enclosed channel width or the apparent channel width. Or, this detail In some documents, when simply referred to as "channel width," it may refer to the effective channel width. Oh, channel length, channel width, effective channel width, apparent channel width, enclosure channel Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined.

[0141] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0142] <Circuit board> The substrate 510 is not merely a support material, but also has other devices such as transistors formed on it. A substrate may also be used. In this case, the conductive layer 530 and conductive layer 541 of the OS transistor 501 One of the conductive layers 542 may be electrically connected to the other devices mentioned above.

[0143] <Underlayment insulation layer> The insulating layer 511 serves to prevent the diffusion of impurities from the substrate 510. It is preferable that the insulating layer 51 has the role of supplying oxygen to the OS layer 520. Component 2 is preferably an insulating film containing oxygen, and is an insulating film containing more oxygen than the stoichiometric composition. It is more preferable that this be the case. For example, TDS (Thermal Desorption) In spectroscopy (temperature-increased desorption gas spectroscopy), when the surface temperature of the film is 100°C or higher The amount of oxygen molecules released in the range of above 700°C or above 500°C is 1 .0 × 10 18 [molecules / cm 3 The film is defined as having a thickness of ] or more. The substrate 510 is formed on other devices. If the substrate is treated, the insulating layer 511 is CMP (Chemical Chemical) so that the surface is flat. Planarization is preferably performed using methods such as mechanical polishing. It's nice.

[0144] Insulating layers 511 and 512 are aluminum oxide, aluminum oxide nitride, and magnesium oxide. silicon oxide, silicon oxide nitride, silicon nitride oxide, gallium oxide, germanium oxide M, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafny oxide Insulating materials such as tantalum oxide, silicon nitride, aluminum nitride, or These can be formed using a mixture of materials.

[0145] < Stop gate> The conductive layer 530 is composed of copper (Cu), tungsten (W), molybdenum (Mo), and gold (Au). Aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel Iron (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co) Ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt) Which metals, or alloys thereof, or compounds with these as the main components, can be formed? preferable.

[0146] Furthermore, the conductive layer 530 may be a single-layer structure or a laminated structure of two or more layers. For example, sil A single-layer structure of an aluminum film containing condensate, and a double-layer structure in which a titanium film is laminated on top of an aluminum film. A two-layer structure in which a titanium film is stacked on top of a titanium nitride film, and a tungsten film is stacked on top of a titanium nitride film. A layered two-layer structure, where a tungsten film is laminated on top of a tantalum nitride film or a tungsten nitride film. It has a two-layer structure, with a titanium film and an aluminum film laminated on top of the titanium film, and then a titanium film on top of that. A three-layer structure forming a tan film, a single-layer structure of a Cu-Mn alloy film, and a Cu film on top of a Cu-Mn alloy film. A two-layer structure in which layers are stacked, with a Cu film stacked on top of a Cu-Mn alloy film, and then a Cu-Mn There are three-layer structures, such as those with stacked alloy films. In particular, Cu-Mn alloy films have low electrical resistance, and... Because manganese oxide can be formed at the interface with the oxygen-containing insulating film, preventing the diffusion of Cu. preferable.

[0147] Furthermore, the conductive layer 530 contains indium tin oxide and indium oxide including tungsten oxide. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. Furthermore, transparent conductive materials such as indium tin oxide can also be applied. A laminated structure of a light-transmitting conductive material and the above-mentioned metal element can also be used.

[0148] <Gate Insulation Layer> The insulating layer 513 is formed of an insulating film with a single-layer or multi-layer structure. Aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide N, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Contains one or more of the following: um, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film can be used. Furthermore, the insulating layer 513 may be a laminate of the above materials. Oh, in the insulating layer 513, lanthanum (La), nitrogen, zirconium (Zr), etc. are added as impurities. It may also be included. Furthermore, the insulating layer 511 can be formed in the same way as the insulating layer 513. The insulating layer 511 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Preferably, it contains hafnium oxide and silicon oxide or silicon oxide-nitride.

[0149] Hafnium oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Therefore Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 513 can be increased, The leakage current due to the Nell current can be reduced. In other words, the transient with a small off-current It is possible to achieve this. Furthermore, hafnium oxide having a crystalline structure has an amorphous structure It has a higher dielectric constant compared to hafnium oxide, which has a low off-current. For use as a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of crystal structures include monoclinic and cubic systems. However, one aspect of the present invention is... The term "sama" is not limited to these examples.

[0150] <Source electrode, drain electrode, back electrode> The conductive layer 541 and conductive layer 542 can be manufactured in the same manner as the conductive layer 530. Cu-M The n alloy film has low electrical resistance and, when placed in contact with the oxide semiconductor film, allows the oxide semiconductor to... Manganese oxide can be formed at the interface with the body membrane, and the presence of manganese oxide expands the Cu This prevents scattering. Therefore, Cu-Mn alloy layers are used for conductive layer 541 and conductive layer 542. It is preferable to do so. Also, the conductive layer 531 (Figure 20A), which will be described later, is similar to the conductive layer 530. It can be manufactured.

[0151] <Protective insulating film> The insulating layer 514 blocks oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. It is preferable that it has the function of being able to do so. By providing such an insulating layer 514, the OS layer 52 Prevents the diffusion of oxygen from the outside and the intrusion of hydrogen, water, etc., from the outside into the OS layer 520. This is possible. For example, a nitride insulating film can be used as the insulating layer 514. Examples of nitride-supporting insulating films include silicon nitride, silicon nitride oxide, aluminum nitride, and silicon nitride oxide Aluminum is one example. Furthermore, oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of a nitride insulating film with a locking effect, use blocking effects such as oxygen, hydrogen, and water. An oxide insulating film having the following properties may be provided. An acid having a blocking effect such as oxygen, hydrogen, or water may be provided. Examples of oxide insulating films include aluminum oxide, aluminum oxide nitride, gallium oxide, and nitrile oxide. Gallium oxide, yttrium oxide, yttrium oxide and nitride, hafnium oxide, hafnium oxide and nitride It includes things like nium.

[0152] Aluminum oxide films allow both hydrogen, water, and other impurities, as well as oxygen, to pass through the film. Because it has a high barrier effect, it is preferable to apply it to the insulating layer 514. Therefore, aluminum oxide The aluminum film enhances the electrical properties of the transistor during and after the transistor fabrication process. To prevent the inclusion of impurities such as hydrogen and water, which cause fluctuations in properties, into the OS layer 520, the OS layer 520 The main component material of the semiconductor is oxygen, and it prevents the release of oxygen from the oxide semiconductor and from the insulating layer 512. It is suitable for use as a protective film that prevents the unnecessary release of elements. It is also possible to diffuse the oxygen contained in the aluminum film into the oxide semiconductor.

[0153] <Interlayer insulating film> Furthermore, it is preferable that an insulating layer 515 is formed on the insulating layer 514. Insulating layer 515 This can be formed as a single-layer or multi-layer insulating film. The insulating film may contain magnesium oxide. Nesium, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide, gas Yttrium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, oxide An insulating film containing one or more neodymium, hafnium oxide, and tantalum oxide can be used. ru.

[0154] <Oxide semiconductor layer> Typical semiconductor materials for OS layers 521-523 include In-Ga oxide and In-Z oxide. n oxide, In-M-Zn oxide (where M is Ga, Y, Sn, Zr, La, Ce, or N) There are elements such as d. Element M is, for example, an element with a high bond energy with oxygen, or It is an element whose bonding energy with oxygen is higher than that of indium, or it is an element of oxide semiconductors. It is an element that has the function of increasing the energy gap. Also, OS layers 521-523 The OS layer 521-523 is, for example, Zn- It can be formed from Sn oxide, Ga-Sn oxide, Zn-Mg oxide, etc. Also, O The S layer 522 is preferably formed of In-M-Zn oxide. Also, the OS layer 521, Each of the OS layers 523 can be formed from Ga oxide.

[0155] The OS layer 522 is not limited to an oxide semiconductor containing indium. For example, an oxide that does not contain indium but contains at least one of zinc, gallium, and tin. It can also be a semiconductor (for example, zinc-tin oxide, gallium-tin oxide, etc.).

[0156] The OS layer 522 is preferably formed from an oxide with a large energy gap, for example. The energy gap of 522 is, for example, 2.5 eV to 4.2 eV, preferably 2 The voltage should be between 0.8eV and 3.8eV, and more preferably between 3eV and 3.5eV.

[0157] The OS layer 522 is preferably a CAAC-OS film, as described later. The oxide semiconductor is Zn Since the presence of Zn can sometimes facilitate crystallization, it is preferable that the OS layer 522 contains Zn. .

[0158] When an interface state is formed at the interface between OS layer 522 and OS layer 521, channels also form in the region near the interface. Because a Nell region is formed, the threshold voltage of OS transistor 501 fluctuates. Therefore, the OS layer 521 has at least one of the metal elements that make up the OS layer 522. It is preferable to include it in the element. This results in an interface between OS layer 522 and OS layer 523. Levels become less likely to form, and variations in electrical characteristics such as the threshold voltage of the OS transistor 501 occur. This can be reduced.

[0159] The OS layer 523 contains at least one of the metal elements that make up the OS layer 522 as its constituent elements. It is preferable to do so. As a result, at the interface between OS layer 522 and OS layer 523, interfacial scattering is This makes it less likely to occur, and the movement of the carrier is less likely to be obstructed, so OS transistor 501 The field effect mobility can be increased.

[0160] OS layers 521, 522, and 523 preferably contain at least indium. It is fine. Also, when the OS layer 521 is In-M-Zn oxide, the sum of In and M is 100a When expressed as atomic%, preferably In is less than 50 atomic and M is 50 atomic. Higher than ic%, and more preferably In is less than 25 atomic%, and M is 75 atomic%. It is assumed to be higher than c%. Also, when the OS layer 522 is In-M-Zn oxide, In and M When the sum of these is taken as 100 atomic%, preferably In is higher than 25 atomic%. M is less than 75 atomic%, and more preferably In is higher than 34 atomic%, Assume that M is less than 66 atomic%. Also, when the OS layer 523 is In-M-Zn oxide. When the sum of In and M is taken as 100 atomic%, preferably In is 50 atomic. Less than ic%, M is higher than 50atomic%, and more preferably In is 25atomic%. c% is less, and M is greater than 75 atomic%. Note that OS layer 523 is OS layer 521 The same type of oxide may be used. Alternatively, OS layer 521 and / or OS layer 523 There are cases where it is not necessary for it to contain indium. For example, OS layer 521 or / and The OS layer 523 can be made of gallium oxide.

[0161] Of the OS layers 521-523, it is preferable that OS layer 522 has the highest carrier mobility. This allows for the formation of channels in the OS layer 522, which is separated from the insulating layer 511. can.

[0162] For example, oxides containing In, such as In-M-Zn oxide, can be modified by increasing the In content. Carrier mobility can be increased. In In-M-Zn oxides, this is mainly due to the s orbitals of heavy metals. This contributes to carrier conduction, and by increasing the indium content, more Because the s orbitals overlap, oxides with a high indium content are more suitable for acids with a low indium content. Compared to oxides, it has higher mobility. Therefore, oxide semiconductor films have a high indium content. By using oxides, carrier mobility can be increased.

[0163] When depositing oxide semiconductor films by sputtering, heating of the substrate surface to be deposited is necessary. Alternatively, due to factors such as ambient heating, the composition of the source target and the composition of the film may differ. There are cases where this is the case. For example, when using an In-Ga-Zn oxide target, zinc oxide is Because it sublimes more easily than indium oxide or gallium oxide, the source and In-Ga-Z A deviation in composition from the n oxide is likely to occur. Specifically, the In-Ga-Zn oxide that is deposited. The Zn content will be lower than in the source. Therefore, the change in composition should be taken into consideration beforehand. It is preferable to select a source that meets the following criteria. Note that the amount of deviation in composition between the source and the film is not related to temperature. It also changes depending on factors such as pressure and the gases used for film formation.

[0164] In the case of an In-M-Zn oxide fabricated by sputtering, the In-M- The atomic ratio of the target metal elements used to deposit Zn oxide films, In:M:Zn, is 1:1:1, 3:1:2, or 4:2:4.1 are preferred. For example, In:M:Zn= Atomic ratio of metal elements contained in a semiconductor film deposited using a 4:2:4.1 target. The ratio is approximately In:M:Zn = 4:2:3.

[0165] OS layer 521 and OS layer 523 are In-M-Zn oxide fabricated by sputtering. In this case, the atomic ratio of the metal elements of the target used to deposit In-M-Zn oxide is I The n:M:Zn ratio is preferably 1:3:2 or 1:3:4.

[0166] When depositing oxide semiconductor films using the sputtering method, the power supply required to generate the plasma... The power supply unit can be an RF power supply unit, an AC power supply unit, a DC power supply unit, etc., as appropriate. Tarling gases include noble gases (typically argon), oxygen, and mixtures of noble gases and oxygen. Use as appropriate. Note that in the case of a mixture of noble gases and oxygen, increase the gas ratio of oxygen to the noble gas. It is preferable to do so. Furthermore, the target is appropriately selected according to the composition of the oxide semiconductor to be deposited. You just need to make a choice.

[0167] To obtain an oxide semiconductor that is of high purity intrinsic or substantially high purity intrinsic, in the chamber In addition to high-vacuum evacuation, it is also necessary to purify the sputtering gas. The oxygen gas or argon gas used has a dew point of -40°C or lower, preferably -80°C or lower. Preferably, a gas purified to -100°C or lower, more preferably to -120°C or lower, is used. This prevents moisture and other substances from being incorporated into the oxide semiconductor as much as possible.

[0168] <Energy band structure> Next, the OS layer is composed of the stacking of OS layer 521, OS layer 522, and OS layer 523. The function and effects of 520 are described using the energy band structure diagram shown in Figure 19B. Let me explain. Figure 19A is a magnified view of the channel region of the OS transistor 501. This is a magnified view of part 18B. Figure 19B shows the area indicated by the dotted line z1-z2 in Figure 19A (OS The energy band structure of the channel formation region of transistor 501 is shown below. I will explain using transistor 501 as an example, but the same applies to OS transistors 502-506.

[0169] In Figure 19B, Ec512, Ec521, Ec522, Ec523, and Ec513 are each Then, the conductive band of insulating layer 512, OS layer 521, OS layer 522, OS layer 523, insulating layer 513 This shows the energy at the lower end.

[0170] Here, the difference between the energy of the vacuum level and the energy of the lower end of the conduction band (also called "electron affinity") is true The difference between the energy of the empty level and the energy of the upper end of the valence band (also called the ionization potential) This is the value after subtracting the energy gap. Note that the energy gap is measured using a spectroscopic ellipsometer. Measurement can be performed using the HORIBA JOBIN YVON UT-300. The energy difference between the vacant level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI Corporation) It can be measured using VersaProbe.

[0171] Since insulating layer 512 and insulating layer 513 are insulators, Ec513 and Ec512 are equal to Ec52 1. Closer to the vacuum level than Ec522 and Ec523 (lower electron affinity).

[0172] OS layer 522 is an oxide layer with a higher electron affinity than OS layers 521 and 523. Yes. For example, OS layer 522 has a higher electron affinity than OS layer 521 and OS layer 523. 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, and further Preferably, an oxide with a voltage between 0.15 eV and 0.4 eV is used. The electron affinity is This is the difference between the energy levels of the vacuum and the lower end of the conduction band.

[0173] When a voltage is applied to the gate (conductive layer 530) of the OS transistor 501, the OS layer 521, Of the two OS layers, OS layer 522 and OS layer 523, a channel is formed in OS layer 522, which has a higher electron affinity. It will be done.

[0174] Indium gallium oxide has low electron affinity and high oxygen blocking properties. Therefore, it is preferable that the OS layer 523 contains indium gallium oxide. Gallium atom ratio [ Ga / (In+Ga) is, for example, 70% or more, preferably 80% or more, even more preferably The percentage should be 90% or higher.

[0175] Furthermore, Ec521 is closer to the vacuum level than Ec522. Specifically, Ec521 is E 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0.15eV or more than c522 Above V and below, and below 2eV, 1eV, 0.5eV, or 0.4eV in vacuum levels. Closer is preferable.

[0176] Furthermore, Ec523 is closer to the vacuum level than Ec522. Specifically, Ec523 is E 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0.15eV or more than c522 Above V and below, and below 2eV, 1eV, 0.5eV, or 0.4eV in vacuum levels. Closer is preferable.

[0177] Furthermore, between OS layer 521 and OS layer 522, there is a mixed region of OS layer 521 and OS layer 522. It may exist. Also, between OS layer 523 and OS layer 522, there is a gap between OS layer 523 and OS A mixed region may exist in layer 522. Because the interface state density is low in the mixed region, The laminate of OS layers 521-523 (OS layer 520) emits energy near each interface. The ghee changes continuously (also called a continuous junction), forming a band structure.

[0178] In the OS layer 520 having such an energy band structure, electrons move through the OS layer 522. It will mainly move. Therefore, at the interface between the OS layer 521 and the insulating layer 512, Even if energy levels exist at the interface between the OS layer 523 and the insulating layer 513, these interface energy levels This makes it less likely for the movement of electrons in the OS layer 520 to be hindered, thus OS transitions The on-current of the 501 can be increased.

[0179] Also, as shown in Figure 19B, near the interface between the OS layer 521 and the insulating layer 512, and the OS layer 5 Near the interface between 23 and the insulating layer 513, there are trap levels E caused by impurities and defects. Although t502 may be formed, the presence of OS layer 521 and OS layer 523 means that The OS layer 522 and the trap level Et502 can be kept apart. OS transistor 5 In the channel width direction, the top and side surfaces of the OS layer 522 are in contact with the OS layer 523, The lower surface of the S layer 522 is formed in contact with the OS layer 521 (see Figure 18C). By configuring the OS layer 522 to be covered by OS layer 521 and OS layer 523, the trap level E The impact of t502 can be further reduced.

[0180] However, if the energy difference between Ec521 or Ec523 and Ec522 is small, O Electrons in layer S 522 may exceed this energy difference and reach the trap level. When electrons are trapped in the energy levels, a negative fixed charge is generated at the interface of the insulating film, and the transient The threshold voltage of the terminal shifts in the positive direction. Therefore, Ec521 and Ec523 The energy difference between Ec522 and Ec522 should be 0.1 eV or more, preferably 0.15 eV. As a result, the fluctuation of the threshold voltage of the OS transistor 501 is reduced, and the OS transistor This is preferable because it allows for good electrical characteristics of the 501.

[0181] The on-current of a transistor can be increased as the factors that hinder electron movement are reduced. Yes, it is possible. For example, if there are no factors hindering electron movement, it is estimated that electrons will move efficiently. Electron movement is inhibited, for example, when there are large physical irregularities in the channel region. Alternatively, electron movement can also be inhibited if the defect level density in the channel region is high.

[0182] To increase the on-current of the OS transistor 501, for example, the top surface of the OS layer 522 Or the square of the area of ​​1 μm × 1 μm on the lower surface (the surface to be formed, in this case the OS layer 521) The root mean square (RMS) roughness is less than 1 nm, preferably. Less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. It is sufficient if the average surface roughness (also called Ra) in a 1 μm × 1 μm area is 1 nm. Less than, preferably less than 0.6 nm, more preferably less than 0.5 nm, more preferably 0 It should be less than 0.4 nm. Also, the maximum height difference (PV and Also called.) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, Preferably, it should be less than 7 nm.

[0183] For example, OS layer 522 is oxygen-deficient (V O Also written as: ) If present, oxygen deficiency site Hydrogen can enter and form a donor level. Below, water is used at oxygen-deficient sites. The state in which the element is incorporated is V O It is sometimes written as H. O H scatters electrons, so This is a factor that reduces the on-current of the inverter. Also, hydrogen will enter the oxygen-deficient site. It is more stable when oxygen is present. Therefore, by reducing the oxygen deficiency in the OS layer 522... In some cases, the on-current of the transistor can be increased. For example, in OS layer 522 At a certain depth, or in a certain region of the OS layer 522, secondary ion mass spectrometry ( Measured using SIMS (Secondary Ion Mass Spectrometry). The hydrogen concentration will be 2 × 10⁻⁶ 20 atoms / cm 3The following is preferably 5 × 10 19 at oms / cm 3 More preferably 1 × 10 19 atoms / cm 3 The following are further preferred Or 5 x 10 18 atoms / cm 3 The following applies:

[0184] To reduce oxygen deficiency in the OS layer 522, for example, excess oxygen contained in the insulating layer 512 One method is to move to OS layer 522 via OS layer 521. In this case, the OS layer 521 is preferably an oxygen-permeable layer (a layer that allows oxygen to pass through).

[0185] If the OS transistor 501 has an s-channel structure, the entire OS layer 522 Channels can be formed. The thickness of the OS layer 522 is 10 nm or more. It should be 0 nm or less, or between 10 nm and 30 nm.

[0186] Furthermore, to increase the on-current of the transistor, the OS layer 523 can be made thinner. For example, having a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. The OS layer 523 is made of an insulator adjacent to the OS layer 522. A function that blocks elements other than oxygen (such as hydrogen and silicon) from entering the material. Therefore, it is preferable that the OS layer 523 has a certain thickness. A region with a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. The OS layer 523 should have the following properties. Also, the OS layer 523 is not emitted from the insulating layer 512, etc. To suppress the outward diffusion of oxygen, it is preferable that the material has properties that block oxygen.

[0187] Furthermore, to increase reliability, it is preferable that OS layer 521 be thick and OS layer 523 be thin. For example, 10 nm or more, preferably 20 nm or more, and even more preferably 40 nm or more. More preferably, the OS layer 521 has a region with a thickness of 60 nm or more. By increasing the thickness of 521, channels are formed at the interface between the adjacent insulator and the OS layer 521. The distance to the OS layer 522 can be increased. However, the productivity of semiconductor devices will decrease. Because this may occur, for example, 200nm or less, preferably 120nm or less, even more preferably The OS layer 521 may have a region with a thickness of 80 nm or less.

[0188] To impart stable electrical characteristics to an OS transistor with an oxide semiconductor channel, acid To reduce the impurity concentration in oxide semiconductors and make oxide semiconductors intrinsic or substantially intrinsic. This is effective. Here, "substantially true" means that the carrier density of the oxide semiconductor is 1 × 10⁻⁶. 1 7 / cm 3 It should be less than 1 × 10⁻⁶ 15 / cm 3 Being less than, and even better Mashiku is 1 x 10 13 / cm 3 This refers to being less than or equal to.

[0189] Furthermore, in oxide semiconductors, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component These elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, and carrier density This increases the amount of impurities. Furthermore, silicon contributes to the formation of impurity levels in oxide semiconductors. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, within the layers of OS layer 521, OS layer 522, and OS layer 523, and at their respective interfaces It is preferable to reduce the concentration of impurities in the environment.

[0190] To make an oxide semiconductor intrinsically or substantially intrinsically, SIMS analysis is performed, for example, , at a certain depth in the oxide semiconductor, or in a certain region of the oxide semiconductor, silico The concentration is 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 ate / c m 3 Less than 1 × 10 18 atoms / cm 3 It shall be less than. Also, the chlorohydrogen concentration The degree is, for example, at a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor. And, 2 x 10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 More preferably 5×1 0 18 atoms / cm 3 The following applies. Furthermore, the nitrogen concentration is, for example, in the oxide semiconductor. In terms of depth, or in a region of the oxide semiconductor, 5 × 10 19 ate / c m 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 1 8 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following ru.

[0191] Furthermore, if an oxide semiconductor contains crystals, and if silicon or carbon is present in high concentrations, the oxide semiconductor... This can reduce the crystallinity of conductors. To avoid reducing the crystallinity of oxide semiconductors, For example, at a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor, silicon concentration 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 Atom s / cm 3 Less than 1 × 10 18 atoms / cm 3 There is a portion that is less than It is sufficient if it is done. Also, for example, at a certain depth in an oxide semiconductor, or in an oxide semiconductor In a certain region of the body, the carbon concentration is 1 × 10⁻⁶ 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It is sufficient to have a portion that is less than [a certain value].

[0192] Furthermore, as mentioned above, a transistor using a highly purified oxide semiconductor in the channel formation region The off-current of the transistor is extremely small. For example, if the voltage between the source and drain is 0.1V, 5V Alternatively, if the voltage is set to approximately 10V, the off-current normalized by the transistor's channel width is It becomes possible to reduce the level from several yA / μm to several zA / μm.

[0193] Figure 18 shows an example of a three-layer structure for the OS layer 520, but it is not limited to this. For example, the OS layer 520 can be a two-layer structure without OS layer 521 or OS layer 523. Alternatively, Above or below the OS layer 521, or above or below the OS layer 523, a four-layer structure having any one of the oxide semiconductor layers exemplified as the OS layer 521, OS layer 522 and OS layer 523 can also be formed. Or, between any layers of the OS layer 520, above the OS layer 520, or at any two or more locations below the OS layer 520, one or more of the oxide semiconductor layers exemplified as the OS layers 521-523 are provided to form an n-layer structure (n is an integer of 5 or more).

[0194] <<Configuration Example 2 of OS Transistor>> The OS transistor 502 shown in FIG. 20A is a modified example of the OS transistor 501. The O S transistor 502 also has an s-channel structure, similar to the OS transistor 501. The OS transistor 502 is different from the OS transistor 501 in that the shapes of the conductive layer 541 and the conductive layer 542, and the fact that the conductive layer 531 is provided on the insulating layer 511.

[0195] The conductive layer 531 functions as a back gate electrode. A certain potential may be supplied to the conductive layer 531, or the same potential or the same signal as the conductive layer 530 may be supplied, or different potentials or different signals may be supplied. The conductive layer 541 and the conductive layer 542 each function as a source electrode or a drain electrode, respectively.

[0196] The conductive layer 541 and the conductive layer 542 of the OS transistor 502 are formed from a hard mask used to form the stack of the OS layer 521 and the OS layer 5 22. Therefore, the conductive layer 541 and the conductive layer 542 do not have regions in contact with the side surfaces of the OS layer 521 and the OS layer 522. For example, through the following steps, the OS layer 521, 522, the conductive layer 54 ​​​​​1. 542 can be fabricated. Form two oxide semiconductor films constituting the OS layers 521 and 522. Form a single-layer or laminated conductive film on the oxide semiconductor film. Etch this conductive film to form a hard mask. Using this hard mask, etch the two oxide semiconductor films to form a laminate of the OS layer 521 and the OS layer 522. Next, etch the hard mask to form the conductive layer 541 and the conductive layer 542. The conductive layer 531 can function as the back gate electrode of the OS transistor 502. The OS transistor 501 shown in FIG. 20 and the OS transistors 503 - 506 (FIGS. 18 - 21) described later can also be provided with the conductive layer 531. <<Configuration Examples 3 and 4 of OS Transistor>> … The OS transistor 503 shown in FIG. 20B is a modified example of the OS transistor 501, and the OS transistor 54 shown in FIG. 20C is a modified example of the OS transistor 502. In the OS transistor 503 and the OS transistor 504, the OS layer 523 and the insulating layer 513 are etched using the conductive layer 530 as a mask. Therefore, the ends of the OS layer 523 and the insulating layer 513 will substantially coincide with the ends of the conductive layer 530.

[0197] <<Configuration Examples 5 and 6 of OS Transistor>> The OS transistor 505 shown in FIG. 21A is a modified example of the OS transistor 501, and the OS transistor 506 shown in FIG. 21B is a modified example of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each have the OS layer 523 and the conductive layer …

[0198] <<Configuration Examples 3 and 4 of OS Transistor>> The OS transistor 503 shown in FIG. 20B is a modified example of the OS transistor 501, and the OS transistor 504 shown in FIG. 20C is a modified example of the OS transistor 502. In the OS transistor 503 and the OS transistor 504, the OS layer 523 and the insulating layer 513 are etched using the conductive layer 530 as a mask. Therefore, the ends of the OS layer 523 and the insulating layer 513 will substantially coincide with the ends of the conductive layer 530. <<Configuration Examples 5 and 6 of OS Transistor>> The OS transistor 505 shown in FIG. 21A is a modified example of the OS transistor 501, and the OS transistor 506 shown in FIG. 21B is a modified example of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each have the OS layer 523 and the conductive layer … …

[0199] <<Configuration Examples 5 and 6 of OS Transistor>> The OS transistor 505 shown in FIG. 21A is a modified example of the OS transistor 501, and the OS transistor 506 shown in FIG. 21B is a modified example of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each have the OS layer 523 and the conductive layer … … It has a layer 551 between 541 and the OS layer 523 and the conductive layer 542. .

[0200] Layers 551 and 552 are, for example, transparent conductors, oxide semiconductors, nitride semiconductors, or oxidized nitrides. It can be formed with layers made of a monocrystalline semiconductor. Layers 551 and 552 are n-type oxide semiconductor layers. Alternatively, it can be formed with a conductive layer that has higher resistance than conductive layers 541 and 542. For example, layers 551 and 552 are layers containing indium, tin, and oxygen. Layers containing um and zinc, layers containing indium, tungsten and zinc, tin and phosphate A layer containing lead, a layer containing zinc and gallium, a layer containing zinc and aluminum, zinc and A layer containing fluorine, a layer containing zinc and boron, a layer containing tin and antimony, tin A layer containing fluorine or a layer containing titanium and niobium may be used. These layers consist of one or more of hydrogen, carbon, nitrogen, silicon, germanium, or argon. It's okay to include it.

[0201] Layers 551 and 552 may have the property of transmitting visible light. Alternatively, layer 551, 552 transmits visible light, ultraviolet light, infrared light, or X-rays by reflecting or absorbing them. It is acceptable for it to have the property of preventing transients caused by stray light. In some cases, it is possible to suppress fluctuations in the electrical characteristics of the sta.

[0202] Furthermore, layers 551 and 552 are layers that do not form a Schottky barrier between themselves and the OS layer 522. It is preferable to have this. This improves the on-characteristics of OS transistors 505 and 506. It can be done.

[0203] It is preferable that layers 551 and 552 have higher resistance than conductive layers 541 and 542. Layers 551 and 552 have lower resistance than the channel resistance of OS transistors 505 and 506. It is preferable that the resistivity of layers 551 and 552 be 0.1 Ωcm or more and 100 Ωc. If the resistance is less than or equal to m, between 0.5 Ωcm and 50 Ωcm, or between 1 Ωcm and 10 Ωcm Good. By setting the resistivity of layers 551 and 552 within the above range, the channel and drain and This can alleviate electric field concentration at the boundary. This improves the electrical characteristics of the transistor. This can reduce fluctuations in performance. In addition, it can reduce punch-through caused by the electric field generated from the drain. - Current can be reduced. Therefore, even in transistors with short channel lengths, saturation can be reduced. The sum characteristics can be improved. Note that during operation, the sum of OS transistors 505 and 506 If the circuit configuration does not swap the drain and the flow, then either layer 551 or layer 552 In some cases, it is preferable to provide a drain (for example, on the drain side).

[0204] <<Example of chip device structure 1>> Figure 22 shows the device structure of a chip composed of OS transistors and Si transistors. An example of the structure is shown. Figure 22 is a diagram illustrating the laminated structure of PU200 (Figure 13). Figure 14 is a drawing that more specifically describes the layered structure. Figure 22 shows the PU200 The top was not cut along a specific cutting line.

[0205] The chip is formed on a single-crystal silicon wafer 270. The FET layer 260 contains circuit RC Semiconductor elements such as Si transistors and capacitive elements are provided in the circuit, excluding 50. Figure 22 shows, as representative examples, p-type Si transistor 271 and n-type Si transistor 272. As shown, wiring layers W1-W4 are stacked on the FET layer 260. FET layer 26 1 is stacked.

[0206] The FET layer 261 is the layer where OS transistors are formed, and transistors M1-M3 are formed This has been achieved. Transistor M3 is shown as a representative example. Transistors M1 and M2 are similar. It has the following device structure. Here, the structure of transistors M1-M3 is OS transistor This is the same as in TA504 (Figure 20C). In order to provide a back gate to transistor M3, A conductive layer 280 is formed on the wiring layer W4.

[0207] Wiring layers W5 and W6 are stacked on the FET layer 261, and a capacitive element C11 is stacked on the wiring layer W6. The capacitance element C11 has wiring layers W7 and W8 stacked on it. The capacitance element C11 has a conductive layer 281 , 282, and insulating layer 284 are included. Here, the layer on which the conductive layer 281 is formed is the wiring layer. It is used by stacking the capacitive element C11 on the FET layer 261, It is easy to increase the capacitance of 11. Also, depending on the size of the capacitance of the capacitive element C11 However, it is also possible to provide the capacitive element C11 on the FET layer 261. In this case, the transistor The conductive layer is the same layer as the source and drain electrodes of the M3, and the conductive layer is the same layer as the gate electrode. Two electrodes can be formed using the electrochemical layer. A capacitive element C11 is provided on the FET layer 261. Therefore, the number of processes can be reduced, leading to a reduction in manufacturing costs.

[0208] <<Example of chip device structure 2>> It is possible to stack other FET layers on the FET layer 261 in which OS transistors are formed. Figure 23 shows an example of a chip having such a three-dimensional device structure.

[0209] In the chip shown in Figure 23, the capacitive element C11 is formed on the FET layer 261. Layers W6 and W7 are stacked on top of layer 1. FET layer 262 is stacked on top of wiring layer W7. The FET layer 262 is the layer on which the OS transistor is fabricated. This shows transistor M80. To provide a back gate for transistor M80, wiring layer W7 A conductive layer 283 is formed thereon.

[0210] The FET layer 262 has wiring layers W8 and W9 stacked on it. The capacitance layer 263 is stacked on wiring layer W9. It is done. Wiring layer W in capacitance layer 263. 10 , W 11 These are stacked. The capacitance layer 263 is Multiple capacitive elements C80 are formed. For example, transistor M80 and capacitive element C1 With 1, a single transistor-type single-capacitor memory cell can be constructed. Therefore, FET Memory cell arrays can be stacked on layer 261.

[0211] Furthermore, the OS transistors of FET layer 261 and FET layer 262 are electrically The characteristics can be made different. For example, the second oxide semiconductor layer of an OS transistor Just make them different. The second oxide semiconductor layer is In-Ga, which is deposited by sputtering. -In the case of Zn oxides, you can use targets with different atomic ratios of In:Ga:Zn. For example, transistor M3 uses a target with In:Ga:Zn=1:1:1. The M80 transistor uses a target with In:Ga:Zn=4:2:4.1. The oxide semiconductor layer of transistor M80 has a high In content, therefore, transistor M The mobility of 80 can be increased. On the other hand, the oxide semiconductor layer of transistor M3 is In Because the content of decreases, the mobility of transistor M3 is lower than that of transistor M80. Therefore, the off-current of transistor M3 will be lower than that of transistor M80.

[0212] The insulators used in the chips shown in Figures 22 and 23 are aluminum oxide and aluminum nitride. Aluminum, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, nitriding Silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, One or more elements selected from lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. An insulator containing the following materials can be used. In addition, the insulator may include polyimide resin, polya Resins such as ion resins, acrylic resins, siloxane resins, epoxy resins, and phenolic resins are used. It is also possible that it is present. In this specification, oxidized nitrides are defined as having an oxygen content greater than nitrogen content. This refers to compounds with a high nitrogen content, and nitride oxides are compounds with a higher nitrogen content than oxygen content.

[0213] The insulating layers 291-295 are formed of an insulating material that has a blocking effect against hydrogen, water, etc. It is preferable to include at least one layer that is contained within the oxide semiconductor. Water, hydrogen, etc. are carriers in the oxide semiconductor. Since this is one of the factors that generate A, a blocking layer will be provided for hydrogen, water, etc. This can further improve the reliability of transistor M3. Blockage against hydrogen, water, etc. Insulators that have an insulating effect include, for example, aluminum oxide, aluminum oxide nitride, and aluminum oxide Gallium, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafniu oxide Examples include humic acid, hafnium oxidative nitride, and yttria-stabilized zirconia (YSZ).

[0214] <<Oxide semiconductor structure>> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor These include conductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. From another perspective, oxide semiconductors The semiconductor body is divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. Examples include crystalline oxide semiconductors.

[0215] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle of 60° to 120°. In this context, if the crystal is trigonal or rhombohedral, it is represented as a hexagonal crystal system.

[0216] <caac-os> CAAC-OS, CANC(C-Axis Aligned nanocrystal It can also be called an oxide semiconductor having s). CAAC-OS has multiple c-axis oriented elements. It is one of the oxide semiconductors that has crystalline parts (also called pellets).

[0217] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS is caused by grain boundaries. This means that a decrease in electron mobility is less likely to occur.

[0218] In structural analysis using the out-of-plane method of CAAC-OS, 2θ is near 31°. In addition to the peak, a peak may also appear when 2θ is near 36°. The work indicates that some of the crystals in CAAC-OS do not have c-axis orientation. It is. A more preferable CAAC-OS is used in structural analysis using the out-of-plane method. 2θ shows a peak near 31°, but does not show a peak near 36°.

[0219] For CAAC-OS, the in-plane method is used, where X-rays are incident from a direction approximately perpendicular to the c-axis. Structural analysis reveals a peak near 2θ = 56°. This peak is in InGaZn It is attributed to the (110) plane of the O4 crystal. In the case of CAAC-OS, 2θ is near 56°. The sample is fixed in place and analyzed while rotating it around the normal vector of the sample surface as the axis (φ axis) (φ scanning). Even after performing the procedure, no clear peak appears. In contrast, single-crystal oxidation of InGaZnO4 For a solid semiconductor, if φ scan is performed with 2θ fixed near 56°, the (110) plane is equivalent. Six peaks attributed to the valence crystal planes are observed. Therefore, structural analysis using XRD is performed. From this, it can be confirmed that the orientation of the a-axis and b-axis of CAAC-OS is irregular.

[0220] Furthermore, CAAC-OS is an oxide semiconductor with a low defect level density. Examples include defects caused by impurities and oxygen deficiencies. Therefore, CAA C-OS can also be described as an oxide semiconductor with a low impurity concentration. Furthermore, CAAC-OS is It can also be described as an oxide semiconductor with few oxygen vacancies. The impurities contained in oxide semiconductors are They can act as carrier traps or carrier sources. Also, oxide semiconductors... Oxygen deficiency throughout the body can act as a carrier trap, or it can capture hydrogen, thus preventing the development of carriers. A can be a source of contamination.

[0221] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, silicon and other oxide semiconductors have a stronger bond with oxygen than the metal elements that make up the semiconductor. Elements with a strong resultant force disrupt the atomic arrangement of oxide semiconductors by removing oxygen from them. These factors reduce crystallinity. Also, heavy metals such as iron and nickel, argon, and carbon dioxide can contribute to this. Elements, for example, have a large atomic radius (or molecular radius), which disrupts the atomic arrangement of oxide semiconductors. This can be a factor that reduces crystallinity.

[0222] Oxide semiconductors with a low defect level density (few oxygen vacancies) have a low carrier density. This can be done. Such oxide semiconductors can be made into high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It is called a body. CAAC-OS has a low impurity concentration and a low defect level density. In other words, it is high-purity intrinsic. Alternatively, it tends to become a substantially high-purity intrinsic oxide semiconductor. Therefore, CAAC-OS The transistor used has an electrical characteristic where the threshold voltage is negative (also known as normally-on). .) is rare. Also, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors There are few carrier traps. Therefore, transistors using CAAC-OS have better electrical characteristics. This results in a transistor with low fluctuation and high reliability. CAAC-OS has a low defect level density. Therefore, carriers generated by light irradiation, etc., are less likely to be trapped in defect levels. Therefore, transistors using CAAC-OS are affected by visible light and ultraviolet light irradiation. The variation in atmospheric properties is small.

[0223] Charges trapped in the carrier traps of oxide semiconductors take a long time to release. It can behave as if it were a fixed charge. Therefore, the impurity concentration is high and the defect level Transistors using oxide semiconductors with high ion density may exhibit unstable electrical properties. .

[0224] <Microcrystalline oxide semiconductor> Microcrystalline oxide semiconductors are regions where crystalline parts can be observed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be identified. It is contained in microcrystalline oxide semiconductors. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, with microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a certain nanocrystal is called nc-OS (nanocrystalline It is called Oxide Semiconductor. nc-OS is, for example, a high-resolution T In EM images, grain boundaries may not be clearly visible. Note that nanocrystals are CAAC- It may share the same origin as the pellets in the OS. Therefore, the following will refer to nc-OS. The crystalline portion is sometimes called a pellet.

[0225] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a larger diameter than pellets compared to nc-OS. When structural analysis is performed using this method, the out-of-plane method shows that the crystal planes are visible. No peak is detected. Also, for nc-OS, the probe diameter is larger than the pellet (e.g. For example, when electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or more, A diffraction pattern resembling a halo pattern is observed for nc-OS. Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the pellet size. When this is done, a spot is observed. Also, when nanobeam electron diffraction is performed on nc-OS In some cases, a region of high brightness can be observed in a circular (ring-shaped) pattern. Furthermore, phosphorus Multiple spots may be observed within a circular area.

[0226] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ).

[0227] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than amorphous oxide semiconductors. However, nc-OS There is no regularity in crystal orientation between different pellets. Therefore, nc-OS is CA Compared to AC-OS, the defect level density is higher.

[0228] <Amorphous oxide semiconductor> Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and which do not have crystalline regions. It is a semiconductor. One example is an oxide semiconductor that has an amorphous state, such as quartz. In crystalline semiconductors, the crystalline structure cannot be observed in high-resolution TEM images. Amorphous oxides When structural analysis of semiconductors is performed using an XRD device, the out-of-plane method is used. In the analysis, no peaks indicating crystal planes were detected. Furthermore, for amorphous oxide semiconductors, When nano diffraction is performed, a halo pattern is observed. Furthermore, for amorphous oxide semiconductors, nano When beam electron diffraction is performed, no spots are observed; only a halo pattern is observed.

[0229] Various views have been expressed regarding amorphous structures. For example, some argue that the atomic arrangement has absolutely no order. A structure that does not have a completely amorphous structure It is sometimes called a cture. Also, although it does not have long-range order, it does not have a nearest neighbor atom. A structure that may have order within the range of atoms or up to the second nearest neighbor atoms is called an amorphous structure. It is sometimes called this. Therefore, according to the strictest definition, even a slight order in the atomic arrangement An oxide semiconductor possessing this property cannot be called an amorphous oxide semiconductor. Furthermore, at least, Oxide semiconductors exhibiting distance order cannot be called amorphous oxide semiconductors. Therefore, Because they have crystalline parts, for example, CAAC-OS and nc-OS are amorphous oxide semi-crystalline. It cannot be called a conductor or a complete amorphous oxide semiconductor.

[0230] <Amorphous-like oxide semiconductor> Furthermore, oxide semiconductors may have a structure between nc-OS and amorphous oxide semiconductors. Such an oxide semiconductor having such a structure is called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called.

[0231] a-like OS exhibits porosity (also called voids) in high-resolution TEM images. In some cases, the crystalline region can be clearly identified in high-resolution TEM images. It has regions where the crystalline part cannot be observed and regions where the crystalline part cannot be observed. Because it is porous, it is a-like The OS has an unstable structure. Furthermore, because it is porous, an a-like OS is an nc-OS. And it has a lower density structure compared to CAAC-OS. Specifically, a-like OS The density is between 78.6% and 92.3% of the density of a single crystal of the same composition. -The density of OS and CAAC-OS is 92.3% or higher of the density of a single crystal of the same composition. It will be less than 100%. Oxide semiconductors with a density of less than 78% of that of a single crystal will not be able to be deposited into a film. I am in a physical condition.

[0232] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0233] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, the density equivalent to that of a single crystal at a desired composition can be estimated. This is possible. The density corresponding to a single crystal of the desired composition can be obtained by combining single crystals of different compositions. The proportion can be estimated using a weighted average. Combine as few types of single crystals as possible. It is preferable to estimate the density by combining these factors.

[0234] Oxide semiconductors can take on various structures, each possessing different properties. For example, OS transistors... The semiconductor field of GENGISTA includes amorphous oxide semiconductors, a-like OS, and microcrystalline oxide semiconductors. The laminated film may have two or more of the following: the body and CAAC-OS. [Explanation of symbols]

[0235] 10: Circuit, 11: Scan flip-flop (SFF), 15: Circuit, 20: Selection circuit ,21:Selection circuit (SEL), 30:Circuit, 31:Flip-flop (FF), 31a: Circuit, 32M: latch, 32S: latch, 42: inverter, 43: inverter, 44: Inverter, 45: Buffer (BUF), 50: SFF, 100: Logic circuit, 101: Logic circuit, 102: Logic circuit, 103: Logic circuit, 110: SFF, 112:SFF, 113:SFF, 114:SFF, 115:SFF, 116: SFF, 200: PU, 201: Processor core, 202: Power management unit (PMU), 203: P Power switch (PSW), 204: Clock control circuit, 205: Circuit, 210: Power supply circuit 220: Terminal, 221: Terminal, 222: Terminal, 231: Control device, 232: Program Counter, 233: Pipeline register, 234: Pipeline register, 235: Re ZISTA file, 236: Arithmetic logic unit (ALU), 237: Data bus, 240: Logic circuit, 250:SFF, 260: FET layer, 261: FET layer, 262: FET layer, 263: Capacitance layer, 270: Single Crystalline silicon wafer, 271: p-type Si transistor, 272: n-type Si transistor, 280: conductive layer, 281: conductive layer, 282: conductive layer, 283: conductive layer, 284: insulating layer, 291: insulating layer, 292: insulating layer, 293: insulating layer, 294: insulating layer, 295: insulating layer, 501: OS transistor, 502: OS transistor, 503: OS transistor, 5 04: OS transistor, 505: OS transistor, 506: OS transistor, 51 0: Substrate, 511: Insulating layer, 512: Insulating layer, 513: Insulating layer, 514: Insulating layer, 515 :Insulating layer, 520:OS layer, 521:OS layer, 522:OS layer, 523:OS layer, 530 : conductive layer, 531: conductive layer, 541: conductive layer, 542: conductive layer, 551: layer, 552: layer , 900: Portable game console, 901: Cabinet, 902: Cabinet, 903: Display unit, 904: Display Parts: 905: Microphone, 906: Speaker, 907: Control keys, 908: Stylus 910: Portable information terminal, 911: Housing, 912: Housing, 913: Display unit, 914: Display Section, 915: Connection section, 916: Operation keys, 920: Notebook PC, 921: Enclosure, 922 : Display unit, 923: Keyboard, 924: Pointing device, 930: Electric refrigeration Storage room, 931: enclosure, 932: refrigerator door, 933: freezer door, 940: video camera ,941: Housing, 942: Housing, 943: Display unit, 944: Operation keys, 945: Lens, 946: Connector, 950: Automobile, 951: Vehicle body, 952: Wheel, 953: Dashboard D, 954: Light, 7000: Electronic components, 7001: Leads, 7002: Printed circuit boards, 7003: Circuit section 7004: Circuit board, BK: Terminal, C1: Capacitive element, C11: Capacitive element, C12: Capacitive element, C80: Capacitive element CK: terminal, CK1: terminal, CKB1: terminal, D: terminal, D0: terminal, D1: terminal, D 2: Terminal, D3: Terminal, Dn: Terminal, EN: Terminal, FN: Node, FN11: Node, M 1: Transistor, M2: Transistor, M3: Transistor, M80: Transistor, OBG: terminal, PL: terminal, Q: terminal, QB: terminal, RC1: circuit, RC2: circuit, RC 3: Circuit, RC4: Circuit, RC11: Circuit, RC12: Circuit, RC13: Circuit, RC14 : circuit, RC15: circuit, RC16: circuit, RC50: circuit, RE: terminal, RT: terminal, SD: terminal, SD_IN: terminal, SE: terminal, SW1: switch, SW2: switch, S W3: Switch, T0: Terminal, T1: Terminal, T2: Terminal, VH: Terminal, VL: Terminal, W1 : Wiring layer, W2: Wiring layer, W3: Wiring layer, W4: Wiring layer, W5: Wiring layer, W6: Wiring layer, W7: Wiring layer, W8: Wiring layer, W9: Wiring layer, W 10 :Wiring layer, W 11 :Wiring layer

Claims

1. A semiconductor device having a logic circuit, a holding circuit having a function to hold data output from the logic circuit and a function to output the held data to the logic circuit, The holding circuit comprises a first to third switch and an element for holding data. The output terminal of the logic circuit is always in electrical contact with the first terminal of the second switch. The second terminal of the second switch is always electrically connected to the data-holding element. The second terminal of the second switch is always electrically connected to the first terminal of the third switch. The second terminal of the third switch is always in electrical contact with the input terminal of the logic circuit. The input terminal of the holding circuit is always electrically connected to the first terminal of the first switch. The second terminal of the first switch is always in electrical contact with the input terminal of the logic circuit. The data output from the holding circuit to the logic circuit is data of the same logic as the data output from the logic circuit to the holding circuit. The first layer and the second layer are stacked on top of each other. The first layer contains one of the elements included in the logic circuit, The second layer contains one of the elements included in the holding circuit, It comprises a first period, a second period following the first period, and a third period following the second period. During the first period, the first and second switches are in a conductive state and the third switch is in a non-conductive state. During the second period, the first to third switches are in a non-conductive state. A semiconductor device in which, during the third period, the first and second switches are in a non-conductive state and the third switch is in a conductive state.

2. In claim 1, The logic circuit is a semiconductor device that is a latch, a flip-flop, a shift register, a counter circuit, or a frequency divider circuit.

Images