Semiconductor equipment

Abstract

To provide a semiconductor integrated circuit in which the consumption power can be reduced and the delay of the operation can be reduced.SOLUTION: In each of a plurality of sequential circuits 21_1 to 21_n included in a storage circuit 11, which is a semiconductor integrated circuit, a transistor 31 whose channel formation region is formed of an oxide semiconductor and a capacitative element 32 in which a node with one electrode electrically connected becomes floating when the transistor is turned off are provided. When the channel formation region of the transistor is formed of the oxide semiconductor, the transistor whose off current (leak current) is extremely low can be achieved. Therefore, in a period for which a power supply voltage is not supplied to the storage circuit, the transistor is turned off, so that the potential of the node to which one electrode of the capacitative element is electrically connected in this period can be kept constant or substantially constant.SELECTED DRAWING: Figure 1

Description

[Technical Field] 【0001】 This invention relates to semiconductor integrated circuits. In particular, semiconductor integrated circuits are configured using sequential circuits. It has a memory circuit and controls the supply of power voltage to the memory circuit (power gating). This relates to semiconductor integrated circuits capable of doing so. [Background technology] 【0002】 Semiconductor integrated circuits with logic circuits are expanding in circuit size year by year. What was originally composed of several elements is now a CPU (Central P Processing Unit) and DSP (Digital Signal Processing Unit) Some components, such as essors, are composed of tens of millions of elements. While the power consumption per element has decreased due to miniaturization and lower voltage, the power consumption per element has decreased even more. As the number of components increases, the overall power consumption of the integrated circuit is increasing. Methods to reduce this include clock gating, which partially stops the clock, and clock frequency adjustment. Methods to reduce the number of devices and methods to partially lower the power supply voltage have been developed. 【0003】 Furthermore, power consumption includes the charging that occurs when elements such as transistors switch. This includes not only the operating power caused by discharge, but also the leakage current in the off state of the element. This also includes quiescent power. In integrated circuits with a small number of elements, this quiescent power is almost... It can be mostly ignored, but in integrated circuits with a huge number of elements, it becomes a size that cannot be ignored. In contrast, a method for controlling the supply of power voltage to circuits included in an integrated circuit (power gate) A (ing) is being developed. This will reduce power consumption due to leakage current. It is possible. 【0004】 For example, Patent Document 1 describes a semiconductor integrated circuit capable of performing power gating. It is shown. Specifically, it has a transistor between the logic circuit and the power supply line. By controlling the switching of the transistor, the power supply voltage to the logic circuit is controlled. A controllable semiconductor integrated circuit is disclosed. [Prior art documents] [Patent Documents] 【0005】 [Patent Document 1] Japanese Patent Publication No. 2005-268694 [Overview of the Initiative] [Problems that the invention aims to solve] 【0006】 However, the logic circuit in question is a memory circuit (such as a register) that is constructed using multiple sequential circuits. If it is included, power gating will erase the contents of the memory circuit. In fact, in the logic circuits included in current semiconductor integrated circuits, memory such as registers... It has become common practice to use many circuits, and by performing power gating, the memory contents Data loss has occurred. In this case, when the power supply voltage to the memory circuit is restored... Therefore, calculations need to be performed again. In other words, the same calculations need to be performed twice. Therefore, the power consumption reduction effect obtained by performing power gating is diluted. This will result in the semiconductor integrated circuit being able to resume operation until the calculation is completed. No. Therefore, the operation of semiconductor integrated circuits will be delayed. 【0007】 In view of the above-mentioned problems, one aspect of the present invention reduces power consumption in semiconductor integrated circuits. One of the challenges is to address the delay in operation in a semiconductor integrated circuit. One of the objectives is to suppress it. One aspect of the present invention addresses at least one of the above-mentioned objectives. The challenge is to solve this problem. [Means for solving the problem] 【0008】 At least one of the above problems is that in each of the multiple sequential circuits of the memory circuit , a transistor in which a channel formation region is formed by an oxide semiconductor, and the transistor When the switch is turned off, the node to which one electrode is electrically connected becomes floating. This can be solved by providing a capacitive element. The oxide semiconductor in question is It has a wider band gap than silicon and a lower intrinsic carrier density than silicon. A key feature is that the channel formation region of the transistor is constructed using such oxide semiconductors. This makes it possible to create a transistor with extremely low off-current (leakage current). Therefore, during periods when no power supply voltage is supplied to the memory circuit, the transistor is... By turning it off, one electrode of the capacitive element is electrically connected during that period. It is possible to maintain the potential of the code at a constant or nearly constant level. As a result, for the memory circuit Therefore, when the power supply voltage is restored, there is no need to perform calculations or other operations again. In other words, one aspect of the present invention In the semiconductor integrated circuit of this form, there is no power consumption or operational delay associated with the calculation, etc. This makes it possible to solve the aforementioned problems. 【0009】 In addition, the oxide semiconductor is preferably an i-type (intrinsic) semiconductor or an oxide semiconductor that is extremely close to the i-type, with a reduced impurity concentration of substances such as moisture or hydrogen that can act as electron donors (donors). Specifically, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) for the oxide semiconductor is preferably 5×10 (atoms / cm ^3^) or less, more preferably 5×10 (atoms / cm 19 ) or less, and even more preferably 5×10 3 (atoms / cm ) or less. Also, the carrier density of the oxide semiconductor that can be measured by Hall effect measurement is less than 1×10 18 / cm 3 , preferably less than 1×10 17 (ato ms / cm 3 ^3^), more preferably less than 1×10 (ato 14 ms / cm 3 ^3^). Further, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. 12 / cm 3 , even more preferably less than 1×10 (ato 11 ms / cm 3 ^3^). Here, the analysis of the hydrogen concentration by secondary ion mass spectrometry (SIMS) will be briefly described. In principle, it is known that it is difficult to accurately obtain data near the sample surface or near the laminated interface with a film of a different material in SIMS analysis. Therefore, when analyzing the thickness direction distribution of the hydrogen concentration in the film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme variation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Also, the measurement 【0010】 Here, the analysis of the hydrogen concentration by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy) will be described. SIMS analysis, due to its principle, is known to have difficulty accurately obtaining data near the sample surface or near the laminated interface with a film of different material. Therefore, when analyzing the thickness direction distribution of the hydrogen concentration in the film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme variation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Also, the measurement , due to its principle, has difficulty accurately obtaining data near the sample surface or near the laminated interface with a film of different material. Therefore, when analyzing the thickness direction distribution of the hydrogen concentration in the film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme variation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Also, the measurement is known to be difficult to accurately obtain data near the sample surface or near the laminated interface with a film of different material. Therefore, when analyzing the thickness direction distribution of the hydrogen concentration in the film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme variation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Also, the measurement of the thickness direction distribution of the hydrogen concentration in the film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme variation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Also, the measurement value shows almost no extreme variation and a substantially constant value in the region where the target film exists, and the average value in this region is adopted as the hydrogen concentration When the thickness of the target membrane is small, it is affected by the hydrogen concentration in the adjacent membrane, and is approximately equal. In some cases, it may not be possible to find a region where a specific value can be obtained. In this case, in the region where the film exists... The maximum or minimum hydrogen concentration is adopted as the hydrogen concentration in the membrane. Furthermore, In the region where the film exists, there is a mountain-shaped peak with a maximum value and a valley-shaped peak with a minimum value. If no curve exists, the value of the inflection point is used as the hydrogen concentration. 【0011】 Furthermore, oxide semiconductors are quaternary metal oxides, specifically In-Sn-Ga-Zn-O oxides. Semiconductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors and In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O based oxide semiconductors, Sn-Al-Zn-O based oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides Semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg- O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, and In addition, In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. are used. It is possible to be. In this specification, for example, In-Sn-Ga-Zn-O system Oxide semiconductors include indium (In), tin (Sn), gallium (Ga), and zinc (Zn). This means a metal oxide having [a certain characteristic], and the composition ratio is not particularly specified. Semiconductors may contain silicon. 【0012】 Furthermore, in this specification, an oxide semiconductor is, for example, one with the chemical formula InMO3(ZnO) m ( It can be expressed as m>0), where M is selected from Ga, Al, Mn, and Co. It refers to one or more metallic elements. [Effects of the Invention] 【0013】 A semiconductor integrated circuit according to one aspect of the present invention provides a memory circuit during a period when no power supply voltage is supplied. In this case, in each of the multiple sequential circuits that the memory circuit has, the potential of a specific node It is possible to hold the potential held at the node in the sequential circuit. It is possible to associate it with the data that is held. That is, semiconductor in one aspect of the present invention In integrated circuits, the calculation is performed again when the power supply voltage to the memory circuit is restored. There is no need to perform such tasks. As a result, in one embodiment of the present invention, the semiconductor integrated circuit has low power consumption. It is possible to reduce the amount of noise and operational delay. [Brief explanation of the drawing] 【0014】 [Figure 1] (A) to (C) Diagrams showing examples of semiconductor integrated circuit configurations. [Figure 2] (A) to (H) Diagrams showing an example of a transistor fabrication method. [Figure 3] (A) to (C) Diagrams illustrating the method for measuring the off-current of a transistor. [Figure 4] (A) and (B) are diagrams showing the characteristics of transistors. [Figure 5] A diagram showing the characteristics of a transistor. [Figure 6] A diagram showing the characteristics of a transistor. [Figure 7] A diagram showing the characteristics of a transistor. [Figure 8] A diagram showing the characteristics of a transistor. [Figure 9] A diagram illustrating a specific example of a sequential circuit. [Figure 10] A diagram illustrating an example of sequential circuit operation. [Figure 11] A diagram showing a specific example of a transistor. [Figure 12] (A) to (H) Diagrams showing an example of the specific manufacturing process of a transistor. [Figure 13] (A) to (G) Diagrams showing an example of the specific manufacturing process of a transistor. [Figure 14] (A) to (D) Diagrams showing an example of the specific manufacturing process of a transistor. [Figure 15] A diagram showing a modified transistor. [Figure 16] (A) and (B) diagrams showing modified versions of transistors. [Figure 17] (A) and (B) diagrams showing modified versions of transistors. [Figure 18] (A) and (B) diagrams showing modified versions of transistors. [Figure 19] A diagram showing a modified transistor. [Figure 20] A diagram showing a modified transistor. [Figure 21] (A) to (C) Diagrams showing modified examples of the oxide semiconductor layer fabrication process. [Figure 22] A diagram showing a specific example of a CPU. [Figure 23] (A)-(E) Diagrams illustrating the crystal structure of oxide materials. [Figure 24] (A)-(C) Diagrams illustrating the crystal structure of oxide materials. [Figure 25] (A)-(C) Diagrams illustrating the crystal structure of oxide materials. [Figure 26] This figure illustrates the gate voltage dependence of the mobility obtained through calculation. [Figure 27] (A) to (C) are diagrams illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 28] (A) to (C) are diagrams illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 29] (A) to (C) are diagrams illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 30] (A) and (B) are diagrams illustrating the cross-sectional structure of the transistors used in the calculations. [Figure 31] (A) to (C) Figures showing the characteristics of transistors using oxide semiconductors. [Figure 32] (A), (B) Diagrams showing the characteristics of transistors using oxide semiconductors. [Figure 33] (A), (B) Diagrams showing the characteristics of transistors using oxide semiconductors. [Figure 34] XRD spectrum of an oxide semiconductor. [Figure 35] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 36] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 37] (A), (B) Diagrams showing the characteristics of transistors using oxide semiconductors. [Figure 38] (A), (B) Cross-sectional and plan views of a transistor using an oxide semiconductor. [Figure 39] (A), (B) Cross-sectional and plan views of a transistor using an oxide semiconductor. [Modes for carrying out the invention] 【0015】 The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The present invention is not limited to the following description, and its form may not depart from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, The present invention is not limited to the embodiments described below. 【0016】 <Example of a semiconductor integrated circuit configuration> First, please refer to Figures 1(A) to (C) for an example of the configuration of a semiconductor integrated circuit according to one aspect of the present invention. I will explain by referring to it. 【0017】 Figure 1(A) is a block diagram showing an example of the configuration of a semiconductor integrated circuit. The conductive integrated circuit includes an arithmetic circuit 10 and data obtained from calculations performed by the arithmetic circuit 10. A memory circuit 11 that holds data, and a power gate that controls the supply of power voltage to the memory circuit 11. It has a control circuit 12. 【0018】 Figure 1(B) shows the specific memory circuit 11 and power gate control circuit 12 shown in Figure 1(A). This figure shows an example configuration. The memory circuit 11 shown in Figure 1(B) receives a clock signal (CK) and a reverse signal. The clock signal (CKB), high power supply potential (VDD), and low power supply potential (VSS) are supplied. A sequential circuit 21_1 to 21_n (where n is a natural number greater than or equal to 3) that can operate in the given state and It can operate under conditions where both high power supply potential (VDD) and low power supply potential (VSS) are supplied. It has combinational circuits 22_1 to 22_n. 【0019】 Furthermore, the sequential circuit 21_1 has an input terminal that is electrically connected to the input terminal of the memory circuit 11. The output terminal is electrically connected to the input terminal of combinational circuit 22_1. Also, sequential circuit 2 1_a (where a is a natural number between 2 and n) is an input terminal of combinational circuit 22_a-1. The power terminal is electrically connected, and the output terminal is electrically connected to the input terminal of the combination circuit 22_a. It continues. Also, the combinational circuit 22_n has an output terminal that is connected to the output terminal of the memory circuit 11. It connects to the target. 【0020】 The power gate control circuit 12 shown in Figure 1(B) controls the gate of the power gate transistor 20. A power gating control signal (PG) is output to the terminal, and sequential circuits 21_1 to 21_n For each of these, a set signal (SET), a reset signal (RES), and a first transfer signal ( It is possible to output TS1) and a second transfer signal (TS2). Transistor 20 has drains in sequential circuits 21_1~21_n and combinational circuits 2 Electrically connect the wiring that supplies the low power supply potential (VSS) to each of 2_1 to 22_n. The source is electrically connected to a low power supply potential (VSS) source. Therefore, The switching of the power gate transistor 20 causes the sequential circuits 21_1 to 21_n to be affected. The supply of low power supply potential (VSS) to each of the combination circuits 22_1 to 22_n It is possible to control it. Also, the first transfer signal (TS1) is sequential circuit 21_1~2 The data held in 1_n is described later, and the channel formation region is formed by an oxide semiconductor. The transistors that make up the node are turned off, resulting in a floating state, and the data is transferred to the node. The second transfer signal (TS2) is a signal for transferring the data from the node. This is a signal for that purpose. 【0021】 Note that in Figure 1(B), sequential circuits 21_1 to 21_n and combinational circuit 22_ Regarding the configuration for controlling the supply of low power supply potential (VSS) for each of 1 to 22_n As shown, the configuration controls the supply of a high power supply potential (VDD) or a low power supply potential (VSS) and It is also possible to configure the system to control the supply of a high power potential (VDD). Specifically, sequentially Each of the pre-circuits 21_1~21_n and combinational circuits 22_1~22_n, and a high power supply The configuration involves placing a power gate transistor between the wiring that supplies the electric potential (VDD) and the power gate transistor. It is also possible. 【0022】 Figure 1(C) shows the sequential circuit 21_x (where x is a natural number between 1 and n, inclusive) shown in Figure 1(B). This is a diagram showing an example configuration of (1). The sequential circuit 21_x shown in Figure 1(C) has input terminals It is electrically connected to the input terminal of the sequential circuit 21_x, and its output terminal is connected to the output terminal of the sequential circuit 21_x. A flip-flop 30 is electrically connected to the child, and the gate receives the first transfer signal (TS1). The power supply is electrically connected to the wiring, with one of the source and drain being within the flip-flop 30. It is electrically connected to the first node, which is a node of the system, and the source and the other drain are flipped. A transistor 31 is electrically connected to the second node, which is a node in the flop 30, One electrode supplies electricity to the second node and the other to the source and drain of transistor 31. They are connected, and the other electrode is electrically connected to a wire that supplies a fixed potential (Vcom). It has a capacitive element 32. The transistor 31 has an oxide semiconductor channel formation region. It is a transistor composed of [the following components]. Also, the fixed potential (Vcom) is the power gaiter. Any potential that always shows a constant value, regardless of whether or not a voltage check is performed, is acceptable. For example, a fixed electric current The voltage (Vcom) can be set to either a high power supply potential (VDD) or a low power supply potential (VSS). This is possible. In this case, it is not necessary to generate a new potential as a fixed potential (Vcom). This is preferable because it does not have [the following characteristics]. Furthermore, the low power supply potential (VSS) is applied as the fixed potential (Vcom). In this case, the low power supply potential supplied as a fixed potential (Vcom) to the sequential circuit 21_x ( VSS applies power gating to the logic gates contained in flip-flop 30. It is necessary to control the supply so that it is available even during the period in which it is performed. Specifically, sequential circuit 21_x Low power supply potential (VSS) and flip-flop are supplied as a fixed potential (Vcom). A separate supply path is provided for the low power supply potential (VSS) supplied to the logic gates included in the 30. You could say something like "establish it." 【0023】 In addition, here, one of the source and drain of transistor 31 (the first node) is High power is supplied via the transistors that make up the logic gates included in the flip-flop 30. Electrically connected to wiring that supplies power (VDD) or wiring that supplies low power potential (VSS) It is possible to do this, and the source and drain of transistor 31 and the other side of capacitive element 3 One of the electrodes (the second node) of the two is unable to be electrically connected to these wires. Let's assume that there is a logic game that includes at least 30 flip-flops. Electrically connected to the source or drain of any one of the multiple transistors that make up the array. The latter is designed to supply electricity to all of the sources and drains of the multiple transistors. Not directly connected and electrically connected to the gate of at least one of the plurality of transistors The circuit should be designed to connect. That is, in the sequential circuit 21_x shown in Figure 1(C) Therefore, when transistor 31 is turned off, the source and The other electrode of the drain and one electrode of the capacitive element 32 are electrically connected to the node (second node) It is possible to put the (code) into a floating state. 【0024】 In other words, in the sequential circuit 21_x shown in Figure 1(C), the first transfer signal (TS1) By supplying a high level of potential, the data held in the flip-flop 30 The source and drain of transistor 31 and one electrode of capacitive element 32 are electrically charged. The data is transferred to a directly connected node (the second node), and the data is retained at that node. It is possible to do so. 【0025】 In this example, each of the sequential circuits 21_1 to 21_n is equipped with a transistor 31 and a capacitor. The configuration in which element 32 is provided has been shown, but all of the sequential circuits 21_1 to 21_n are the same It does not need to have a configuration. That is, m sequential circuits 21_1~21_n The transistor 31 and the capacitive element 32 are provided only in the circuit (where m is a natural number between 1 and n). It is also possible to have a configuration in which transistor 31 and capacitive element 32 For sequential circuits that do not have this feature, the first transfer signal (TS1) and the second transfer signal It should be noted that (TS2) does not need to be supplied. 【0026】 <Off-current of a transistor whose channel formation region is formed by an oxide semiconductor> Here, the off-current of a transistor in which the channel formation region is formed by an oxide semiconductor. The results of the (leakage current) measurement are shown below. 【0027】 First, the method for fabricating the transistor used in the above measurement will be explained with reference to Figure 2. 【0028】 First, a silicon nitride layer with a thickness of 100 nm and an acid layer with a thickness of 150 nm are placed on the glass substrate 50. A base layer 51 consisting of a stack of silicon nitride layers was formed by the CVD method (see Figure 2(A)). ). 【0029】 Next, a tungsten layer with a thickness of 100 nm is applied to the base layer 51 by sputtering. It was formed. Furthermore, the tungsten layer was selectively etched using photolithography. A gate layer 52 was formed by ching (see Figure 2(B)). 【0030】 Next, a silicon oxidizride layer with a thickness of 100 nm is applied to the base layer 51 and the gate layer 52. A gate insulating layer 53 was formed by the CVD method (see Figure 2(C)). 【0031】 Next, an oxide semiconductor layer with a thickness of 25 nm is applied to the gate insulating layer 53 by sputtering. The oxide semiconductor layer was formed using In2O3:Ga2O3:ZnO= A 1:1:2 [mol] metal oxide target was used. Furthermore, the shape of the oxide semiconductor layer was also considered. The setup involves a substrate temperature of 200°C, a chamber pressure of 0.6 Pa, a DC power supply of 5 kW, and oxygen and The conditions were an argon-mixed atmosphere (oxygen flow rate 50 sccm, argon flow rate 50 sccm). This is done in [location]. Furthermore, the oxide semiconductor layer is selected using photolithography. An oxide semiconductor layer 54 was formed by etching (see Figure 2(D)). 【0032】 Next, in a mixed atmosphere of nitrogen and oxygen (80% nitrogen, 20% oxygen), at 450°C for 1 hour. Heat treatment was performed. 【0033】 Next, the gate insulating layer 53 was selectively etched using photolithography. (Not shown in the diagram). The etching process involves the gate layer 52 and the conductive layer that is formed later. This is a process for forming contact holes. 【0034】 Next, a titanium layer with a thickness of 100 nm is placed on the gate insulating layer 53 and the oxide semiconductor layer 54. A 200nm thick aluminum layer and a 100nm thick titanium layer are laminated by sputtering. Formed by the method. Furthermore, the layer was selectively etched using photolithography. By doing so, the source layer 55a and the drain layer 55b were formed (see Figure 2(E)). 【0035】 Next, the material was heat-treated at 300°C for 1 hour under a nitrogen atmosphere. 【0036】 Next, gate insulating layer 53, oxide semiconductor layer 54, source layer 55a, and drain layer 5 A protective insulating layer 56 consisting of a silicon oxide layer with a thickness of 300 nm was formed on 5b. Furthermore, The protective insulating layer 56 was selectively etched using photolithography (see Figure 2(F)). (See image). Note that the etching process involves the gate layer, source layer, and drain layer, and the later formed This is a process for forming contact holes with the conductive layer. 【0037】 Next, an acrylic layer with a thickness of 1.5 μm is applied onto the protective insulating layer 56, and the acrylic layer is selected A planarized insulating layer 57 was formed by selective exposure (see Figure 2(G)). Furthermore, By heat treatment at 250°C for 1 hour under a nitrogen atmosphere, a planar insulating layer made of acrylic is produced. Layer 57 was baked solid. 【0038】 Next, a titanium layer with a thickness of 200 nm is formed on the planarized insulating layer 57 by sputtering. Achieved. Furthermore, the titanium layer was selectively etched using photolithography. This connects to a conductive layer (not shown) connected to the gate layer 52, and a conductive layer connected to the source layer 55a. A conductive layer 58b connected to 58a and the drain layer 55b was formed (see Figure 2(H)). 【0039】 Next, the material was heat-treated at 250°C for 1 hour under a nitrogen atmosphere. 【0040】 The transistor used in the above measurement was fabricated through the above process. 【0041】 Furthermore, the method for calculating the off-current value using the characteristic evaluation circuit used in the above measurements is described below. I will explain it to them. 【0042】 Current measurement using a characteristic evaluation circuit will be explained using Figure 3. Figure 3 is a characteristic evaluation circuit This is a diagram to explain the circuit. 【0043】 First, the circuit configuration of the characteristic evaluation circuit will be explained using Figure 3(A). This is a circuit diagram showing the circuit configuration of the characteristic evaluation circuit. 【0044】 The characteristic evaluation circuit shown in Figure 3(A) includes multiple measurement systems 801. 1 is connected in parallel to each other. In this configuration, eight measurement systems 801 are connected in parallel. Therefore, by using multiple measurement systems 801, multiple measurements can be performed simultaneously. . 【0045】 The measurement system 801 consists of transistor 811, transistor 812, and capacitive element 813. It includes transistor 814 and transistor 815. 【0046】 Transistors 811, 812, 814, and 8 15 is an N-channel field-effect transistor. 【0047】 A voltage V1 is input to either the source or drain of transistor 811, and the transistor A voltage Vext_a is input to the gate of transistor 811. Transistor 811 is charged This is an injection transistor. 【0048】 One of the sources and drains of transistor 812 is connected to the source and drain of transistor 811. The other side of the drain is connected, and the voltage is applied to the other side of the source and drain of transistor 812. V2 is input, and the voltage Vext_b is input to the gate of transistor 812. The 812 transistor is used for evaluating leakage current. Current refers to leakage current, including the transistor's off-current. 【0049】 One electrode of the capacitive element 813 is in contact with the other of the source and drain of the transistor 811. The voltage V2 is then applied to the other electrode of the capacitive element 813. The voltage V2 is 0V. 【0050】 A voltage V3 is input to either the source or drain of transistor 814, and the transistor The gate of transistor 814 is connected to the source and the other drain of transistor 811. Furthermore, the gate of transistor 814 and the other of the source and drain of transistor 811 , one of the source and drain electrodes of transistor 812, and one electrode of capacitive element 813 The connection point is also called node A. Note that in this case, voltage V3 is 5V. 【0051】 One of the sources and drains of transistor 815 is connected to the source and drain of transistor 814. The other side of the drain is connected, and the voltage is applied to the other side of the source and drain of transistor 815. V4 is input, and the voltage Vext_c is input to the gate of transistor 815. Oh, here the voltage Vext_c is 0.5V. 【0052】 Furthermore, the measurement system 801 connects the source and drain of transistor 814, and the other side of the transistor The voltage at the connection point between the source and drain of the ZISTA 815 is taken as the output voltage Vout. Output. 【0053】 Here, transistor 811 is formed by the fabrication method described using Figure 2. A transistor with a channel length L = 10 μm and a channel width W = 10 μm is used. 【0054】 Furthermore, the fabrication of transistors 814 and 815 is explained using Figure 2. Transitions with channel length L=3μm and channel width W=100μm are formed by the method. Use a sta. 【0055】 Furthermore, at least transistor 812 has a gate layer 52 and a socket as shown in Figure 3(B). The drain layer 55a, gate layer 52, and drain layer 55b do not overlap, and there is an offset of 1 μm width. It has an offset region. By providing this offset region, the parasitic capacity can be reduced. Furthermore, the transistor 812 has six different channel lengths L and channel widths W. We use a sample transistor (also called an SMP) (see Table 1). 【0056】 [Table 1] 【0057】 As shown in Figure 3(A), a transistor for charge injection and a transistor for leakage current evaluation By providing separate transistors, the transistor used for evaluating leakage current during charge injection can be used. It can be kept in the off state at all times. 【0058】 Furthermore, separate transistors are provided for charge injection and leakage current evaluation. By doing so, each transistor can be made to an appropriate size. Also, The channel width W of the transistor used for current evaluation, and the channel width W of the transistor used for charge injection. By making it larger than this, the characteristics of the leakage current evaluation transistor other than leakage current can be evaluated. The leakage current component of the valence circuit can be made relatively smaller. As a result, leakage current evaluation It is possible to measure the leakage current of the transistor with high precision. At the same time, during charge injection... Therefore, since it is not necessary to turn on the leakage current evaluation transistor, channel formation There is no influence from voltage fluctuations at node A caused by some of the region's charge flowing into node A. 【0059】 Next, regarding the leakage current measurement method for the characteristic evaluation circuit shown in Figure 3(A), Figure 3(C) is used. Let me explain. Figure 3(C) shows the leakage current measurement method using the characteristic evaluation circuit shown in Figure 3(A). This is a timing chart used to explain the law. 【0060】 The leakage current measurement method using the characteristic evaluation circuit shown in Figure 3(A) is based on the writing period and retention period. It can be divided into periods. The actions taken during each period are described below. 【0061】 During the writing period, transistor 812 will be in the OFF state, with voltage Vext_b. Input the voltage VL (-3V). Also, input the write voltage Vw as voltage V1. After that, the voltage Vext_a is set such that transistor 811 remains ON for a certain period of time. A voltage VH (5V) is input. This causes charge to accumulate at node A, and the voltage at node A changes. This will be a value equivalent to the writing voltage Vw. Then, as voltage Vext_a, the transistor Input a voltage VL such that the TA811 turns off. Then, set the voltage V1 to voltage V Enter SS(0V). 【0062】 Furthermore, during the retention period, the change in the amount of charge held by node A causes the electrical activity of node A to increase. The change in voltage is measured. From the change in voltage, the source and drain of transistor 812 are determined. The value of the current flowing between them can be calculated. Therefore, the charge accumulation at node A and the current flowing between them can be calculated. It is possible to measure the change in voltage of channel A. 【0063】 At this time, the accumulation of charge at node A and the change in voltage at node A are measured (accumulation and measurement motion The process (also called production) is repeated. First, the first accumulation and measurement operation is repeated 15 times. In the accumulation and measurement operation of step 1, a voltage of 5V is input as the write voltage Vw during the write period. Then, a 1-hour holding period is performed. Next, the second accumulation and measurement operation is repeated twice. In the second storage and measurement operation, a voltage of 3.5V is applied as the write voltage Vw during the write period. The data is entered and retained for a 50-hour period. Next, the third accumulation and measurement operation is performed once. In the third storage and measurement operation, a voltage of 4.5V is set as the write voltage Vw during the write period. Input data and hold it for 10 hours. Repeat the accumulation and measurement process. This allows us to confirm that the measured current value is the value under steady-state conditions. Then, the current I flowing through node A A Of these, transient current (decreases over time from the start of measurement) It is possible to remove the current component that is slightly fading. As a result, leakage current can be measured with higher accuracy. It is possible. 【0064】 Generally, the voltage V at node A A It can be expressed as a function of the output voltage Vout as shown in equation (1). It can be done. 【0065】 【number】 【0066】 Also, the charge Q at node A. A The voltage V at node AA Capacity C connected to node A A , Using a constant (const), it can be expressed as in equation (2). Here, it is connected to node A. Capacity C A This is the sum of the capacitance of the capacitive element 813 and the capacitance components other than the capacitive element 813. 【0067】 【number】 【0068】 Current I at node A A This is the charge flowing into node A (or the charge flowing out of node A). Since it is the time derivative of, the current I at node A A This can be expressed as shown in equation (3). 【0069】 【number】 【0070】 Here, Δt is assumed to be approximately 54,000 seconds. In this way, it is connected to node A. Capacity C A Then, from the output voltage Vout, the leakage current at node A, I, is calculated. A To seek Therefore, it is possible to determine the leakage current of the characteristic evaluation circuit. 【0071】 Next, the measurement results of the output voltage obtained by the measurement method using the above characteristic evaluation circuit and the results of said measurement The calculated leakage current value of the characteristic evaluation circuit will be explained using Figure 4. 【0072】 Figure 4(A) shows the above measurement of transistors in SMP4, SMP5, and SMP6. This shows the relationship between the elapsed time (Time) related to the first accumulation and measurement operation and the output voltage (Vout). Figure 4(B) shows the elapsed time Time related to the above measurement and the current I calculated by the measurement. A This shows the relationship. The output voltage Vout fluctuates from the start of measurement, and when it reaches a steady state... It appears that more than 10 hours are needed for this. 【0073】 Furthermore, Figure 5 shows the SMP1 to SMP6 values ​​estimated from the values ​​obtained from the above measurements. The relationship between the voltage and leakage current at node A is shown. In Figure 5, for example, in SMP4, When the voltage of line A is 3.0V, the leakage current is 28yA / μm. Since the off-current of transistor 812 is also included, the off-current of transistor 812 is also 28yA. It can be considered to be less than or equal to / μm. 【0074】 Furthermore, Figures 6 to 8 show the estimations based on the above measurements at 85°C, 125°C, and 150°C. The relationship between the voltage and leakage current at node A in SMP1 to SMP6 is shown in Figure 6. As shown in Figure 8, even at 150°C, the leakage current is less than 100 Hz / μm. It can be seen that it is below. 【0075】 As described above, a transistor is used in which a channel formation region is formed by an oxide semiconductor. In the characteristic evaluation circuit, the leakage current is sufficiently low, so the off-current of the transistor It can be seen that it is sufficiently small. Also, the off-current of the transistor is when the temperature rises. Even so, it is clear that it is still quite low. 【0076】 <Regarding the semiconductor integrated circuits disclosed herein> The semiconductor integrated circuit disclosed herein includes a memory circuit during a period when no power supply voltage is supplied to it. Even in between, in each of the multiple sequential circuits that the memory circuit has, a specific node ( The source and drain of transistor 31 shown in Figure 1(C), and one of the capacitive elements 32. It is possible to maintain the potential of the node to which the electrodes are electrically connected. The potential held at the node is to correspond to the data held in the sequential circuit. It is possible. That is, in the semiconductor integrated circuits disclosed herein, the memory circuit When the power supply voltage is restored, there is no need to perform calculations again. The semiconductor integrated circuits disclosed in the specification aim to reduce power consumption and operational delay. This is possible. 【0077】 <Specific example> Specific examples of the semiconductor integrated circuits mentioned above will be explained with reference to Figures 9 to 19. 【0078】 <Sequential circuit 21_x> Figure 9 shows a specific example of the sequential circuit 21_x shown in Figure 1(C). The introductory circuit 21_x consists of transistor 31, capacitive element 32, and NAND gate 210a~2 It has 10f, AND gates 211a and 211b, and switches 212a to 212d. The connection relationships are self-evident when referring to Figure 9, so the sequential circuit shown in Figure 9 is shown. A detailed explanation of the connection relationship of 1_x is omitted. Also, the source and slave of transistor 31 Node N is the node electrically connected to the other electrode of n and one electrode of the capacitive element 32. The data retention operation at node N is described below. 【0079】 Figure 10 shows the storage of data at node N of the sequential circuit 21_x shown in Figure 9. This figure shows an example of the actions taken when the action is performed. Note that in the example of actions shown in Figure 10, the duration T1 and T3 are periods when the power gating signal (PG) shows a high potential (power supply Period T2 is the period in which the power gating signal (PG) shows a low potential. This is a period of power outage. 【0080】 During period T1, the data held by the sequential circuit 21_x prior to clock gating In order to determine the Data, a clock signal (CK) is supplied to the sequential circuit 21_x. The power supply is stopped. Then, a high-level potential is supplied as the first transfer signal (TS1). This transfers the data held by the sequential circuit 21_x to node N. 【0081】 During period T2, the supply of power voltage to each logic gate of the sequential circuit 21_x It is stopped. Therefore, the data of the sequential circuit 21_x becomes an undefined state (Z). On the other hand, The data stored in node N will not be lost. 【0082】 During period T3, a high-level potential is supplied as the second transfer signal (TS2). This restores the data of the sequential circuit 21_x. Next, the clock signal (CK) By resuming power supply, the operation of the semiconductor integrated circuit having the sequential circuit 21_x can be resumed early. It is possible. 【0083】 <Transistor> The semiconductor integrated circuit described above is composed of a large number of transistors. The number of transistors is determined from among the various types of transistors, and each transistor is required. It is possible to select as appropriate depending on the characteristics, etc. For example, in the semiconductor integrated circuit mentioned above... The logic contained in sequential circuits 21_1~21_n and combinational circuits 22_1~22_n The transistors that make up the gate are required to operate at high speed. Therefore, the transistor Examples include single-crystal silicon, polycrystalline silicon, or gallium arsenide (GaAs). It is preferable to use transistors in which the channel formation region is formed by compound semiconductors. Furthermore, the power gate transistor 20 is required to have a low off-current (leakage current). Therefore, the transistor in question uses the aforementioned oxide semiconductor to form the channel. It is preferable to use a transistor in which the formation region is formed. 【0084】 In light of the above points, an example of a transistor found in a semiconductor integrated circuit will be described. Specifically, transistors and An example of a semiconductor integrated circuit having transistors formed using a silicon oxide semiconductor. show. 【0085】 Figure 11 shows an example of a transistor found in a semiconductor integrated circuit. The transistor 160 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and a pair of impurity regions 114a, 11 provided so as to sandwich the channel-forming region 116 4b and a pair of high-concentration impurity regions 120a and 120b (these together are simply called impurity regions) (Also called) and a gate insulating layer 108 provided on the channel forming region 116, and gate insulating A gate layer 110 provided on the edge layer 108 and a socket electrically connected to the impurity region 114a It has a drain layer 130a and a drain layer 130b that is electrically connected to the impurity region 114b. ru. 【0086】 Furthermore, a sidewall insulating layer 118 is provided on the side surface of the gate layer 110. In the region of the substrate 100 containing semiconductor material that does not overlap with the sidewall insulating layer 118, There are two pairs of high-concentration impurity regions 120a and 120b, and the pair of high-concentration impurity regions 120a, A pair of metallic compound regions 124a and 124b exist on 120b. Also, the substrate 100 An element isolation insulating layer 106 is provided above, surrounding the transistor 160. Interlayer insulating layers 126 and 128 are provided to cover the ZISTA 160. The source layer 130a and drain layer 130b are interlayer insulating layer 126 and interlayer insulating layer 128 Through the opening formed therein, one of the pair of metal compound regions 124a, 124b is electrically connected They are connected. In other words, the source layer 130a has a high concentration via the metal compound region 124a. The impurity region 120a and impurity region 114a are electrically connected, and the drain layer 130b This is via the metal compound region 124b to the high-concentration impurity region 120b and the impurity region 114 b is electrically connected. 【0087】 The transistor 164 shown in Figure 11 has a gate layer 136 provided on the interlayer insulating layer 128. d, a gate insulating layer 138 provided on the gate layer 136d, and on the gate insulating layer 138 An oxide semiconductor layer 140 is provided, and an oxide semiconductor is provided on the oxide semiconductor layer 140. It has a source layer 142a electrically connected to layer 140 and a drain layer 142b. . 【0088】 Here, the gate layer 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided in such a way. Also, similar to the gate layer 136d, transistor 160 is The electrode layer 136a in contact with the source layer 130a and the electrode layer in contact with the drain layer 130b 136b is formed. 【0089】 Furthermore, on top of the transistor 164, a portion of the oxide semiconductor layer 140 is in contact with the transistor. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source layer 142a and An opening is provided that reaches the drain layer 142b, and through this opening, the source layer 1 An electrode layer 150d is formed in contact with 42a, and an electrode layer 150e is formed in contact with the drain layer 142b. In addition, similar to electrode layer 150d and electrode layer 150e, gate insulating layer 138, protective insulating layer Through openings provided in the edge layer 144 and the interlayer insulating layer 146, the electrodes in contact with the electrode layer 136a An electrode layer 150b is formed in contact with layer 150a and electrode layer 136b. 【0090】 Here, the oxide semiconductor layer 140 is purified to a high degree by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5 × 10⁻⁶. 19 (atoms / cm 3 ) or less. Note that the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10 18 (atoms / cm 3 It is preferable that it be less than or equal to 5 × 10 17 (atoms / cm 3 ) is below It is more desirable that... Secondary Ion Mass Spectroscop (SIMS) This was measured at y). 【0091】 Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152 Electrode layers 154a, 154b, and 154d are provided so that they can be inserted. Oh, electrode layer 154a is in contact with electrode layer 150a, and electrode layer 154b is in contact with electrode layer 150b It is in contact with electrode layer 150d, and electrode layer 154d is in contact with electrode layer 150e. 【0092】 As shown in Figure 11, the drain layer 130b of transistor 160 is in the upper region Through the provided electrode layers 136b, 150b, 154b, and 150d It is electrically connected to the source layer 142a of transistor 164. 【0093】 <Example of manufacturing process> Next, an example of a method for fabricating transistors 160 and 164 will be described. The following section will begin by explaining the method for fabricating the P-type transistor 160, with reference to Figure 12. Next, the method for fabricating transistor 164 will be explained with reference to Figures 13 and 14. do. 【0094】 First, prepare a substrate 100 containing semiconductor material (see Figure 12(A)). The substrate 100 may be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a multi-crystalline semiconductor substrate. Suitable materials include crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, or SOI substrates. It can be used. Here, as the substrate 100 containing semiconductor material, a single crystal silicon group An example of using a board is shown below. Generally, "SOI substrates" are... This refers to a substrate having a silicon semiconductor layer on its surface, but in this specification, etc., it refers to an insulating This also includes substrates having a semiconductor layer made of a material other than silicon on its surface. In other words, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. In addition, the SOI substrate includes a structure in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate. It shall also include such a configuration. 【0095】 On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see Fig. 12(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. Note that, before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, gallium, etc. can be used. Next, etching is performed using the above protective layer 102 as a mask, and a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region) is removed. Thereby, a separated semiconductor region 104 is formed (see Fig. 12(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and etching solution can be appropriately selected according to the etched material. Next, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in the region overlapping the semiconductor region 104 is selectively removed to form an element isolation insulating layer 106 (see Fig. 12(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. Before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, gallium, etc. can be used. Next, etching is performed using the above protective layer 102 as a mask, and a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region) is removed. Thereby, a separated semiconductor region 104 is formed (see Fig. 12(B)). For this etching, dry etching is preferably used, but wet etching may also be used. 【0096】 The etching gas and etching solution can be appropriately selected according to the etched material. Next, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in the region overlapping the semiconductor region 104 is selectively removed to form an element isolation insulating layer 106 (see Fig. 12(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and etching solution can be appropriately selected according to the etched material. 【0097】 Next, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in the region overlapping the semiconductor region 104 is selectively removed to form an element isolation insulating layer 106 (see Fig. 12(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. By selectively removing the insulating layer in the region overlapping the semiconductor region 104, an element isolation insulating layer 106 is formed (see Fig. 12(B)). This is done. As a method for removing the insulating layer, there are polishing processes such as CMP (Chemical Mechanical l Polishing) and etching processes, and any of them can be used. After the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106 the protective layer 102 is removed. 【0098】 Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed thereon. 【0099】 The insulating layer will serve as the subsequent gate insulating layer, and it is preferably a single-layer structure or a laminated structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide nium, tantalum oxide, etc., obtained by using the CVD method, sputtering method, etc. Alternatively, the surface of the semiconductor region 104 can be oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment to form the above-mentioned insulating layer. The high-density plasma treatment can be performed, for example, using a mixed gas of a noble gas such as He, Ar, Kr, Xe, etc., and oxygen, nitrogen oxide, ammonia, nitrogen, etc. Also, the thickness of the insulating layer is not particularly limited, but can be, for example, 1 nm or more and 100 n m or less. The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Also, a layer containing the conductive material can be formed using a semiconductor material such as polycrystalline silicon containing the conductive material. The formation method is not particularly limited, and various film formation methods such as evaporation method, CVD method, sputtering method, spin coating method, etc. can be used. Here, an example of the case where the layer containing the conductive material is formed using a metal material is 【0100】 described. The layer containing the conductive material can be formed using a semiconductor material such as polycrystalline silicon containing the conductive material. The formation method is not particularly limited, and various film formation methods such as evaporation method, ​​​​​​It shall be shown. 【0101】 Subsequently, the layers containing the insulating layer and conductive material are selectively etched to form the gate insulating layer 10 8. Form the gate layer 110 (see Figure 12(C)). 【0102】 Next, an insulating layer 112 is formed to cover the gate layer 110 (see Figure 12(C)). Then, Boron (B), phosphorus (P), arsenic (As), etc. are added to the semiconductor region 104 to create a shallow junction depth. This forms a pair of impurity regions 114a and 114b (see Figure 12(C)). The formation of impurity regions 114a and 114b results in the gate insulating layer 108 of the semiconductor region 104. A channel-forming region 116 is formed in the lower part (see Figure 12(C)). Here, the added The concentration of impurities can be set as appropriate, but when transistors are miniaturized to a high degree... It is desirable to increase its concentration. Also, here, after forming the insulating layer 112 The process employs to form a pair of impurity regions 114a and 114b, but the pair of impurity regions The process may also involve forming regions 114a and 114b, followed by forming the insulating layer 112. 【0103】 Next, the sidewall insulating layer 118 is formed (see Figure 12(D)). The insulating layer 118 is formed after the insulating layer is formed so as to cover the insulating layer 112, and anisotropy is applied to the insulating layer. By applying a high-performance etching process, it can be formed in a self-aligned manner. During this process, the insulating layer 112 is partially etched, and the upper surface of the gate layer 110 and a pair of impurities are removed. It is best to expose the upper surfaces of material regions 114a and 114b. 【0104】 Next, the gate layer 110, a pair of impurity regions 114a, 114b, and the sidewall insulating layer. An insulating layer is formed so as to cover 118 and the like. Then, boron (B), phosphorus (P), arsenic (As), etc. are added to a part of the pair of impurity regions 114a and 114 b to form a pair of high-concentration impurity regions 120a and 120b (see Fig. 12(E)). Thereafter, the insulating layer is removed, and a metal layer 122 is formed so as to cover the gate layer 110, the sidewall insulating layer 118, the pair of high-concentration impurity regions 120 a, 120b, etc. (see Fig. 12(E)). The metal layer 12 2 can be formed using various film-forming methods such as vacuum evaporation, sputtering, spin coating, etc. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. As such a metal material, for example, titanium, tantalum, tungsten, nickel, cobalt, platinum, etc. are available. 【0105】 Next, heat treatment is performed to react the metal layer 122 and the semiconductor material. As a result, a pair of metal compound regions 124a and 124 in contact with the pair of high-concentration impurity regions 120a and 120b are formed (see Fig. 12(F)). When polycrystalline silicon or the like is used as the gate layer 110, a metal compound region is also formed at the portion of the gate layer 110 that contacts the metal layer 122. 【0106】 As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method that can achieve heat treatment in a very short time. The above metal compound region is formed by the reaction of the metal material and the semiconductor material. ​​​​​​​This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the element's characteristics. After forming the compound regions 124a and 124b, the metal layer 122 is removed. 【0107】 Next, an interlayer insulating layer 126 is formed to cover each of the components formed by the above process. Layer 128 is formed (see Figure 12(G)). The interlayer insulating layer 126 and interlayer insulating layer 128 are acid Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, acid It can be formed using materials containing inorganic insulating materials such as tantalum oxide. It is also possible to form it using organic insulating materials such as acrylic. It has a two-layer structure consisting of an interlayer insulating layer 126 and an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is as follows Not limited. After the formation of the interlayer insulating layer 128, its surface may be treated with CMP or etching. It is desirable to flatten it out by doing so. 【0108】 Subsequently, openings extending to a pair of metal compound regions 124a and 124b are made in the interlayer insulating layer. An opening is formed, and a source layer 130a and a drain layer 130b are formed in the opening (Figure 12( See H). The source layer 130a and the drain layer 130b are, for example, P in the region including the opening. After forming a conductive layer using methods such as VD or CVD, etching or CMP is performed. This can be formed by removing a portion of the conductive layer using the method described above. 【0109】 Furthermore, when forming the source layer 130a and the drain layer 130b, their surfaces are flat. It is desirable to process it in such a way. For example, a titanium film or titanium nitride film in the region including the opening. If a tungsten film is formed to embed the opening after a thin layer has been formed, CMP removes unwanted tungsten, titanium, titanium nitride, etc. The flatness of the surface can be improved. In this way, the source layer 130a and drain By planarizing the surface including layer 130b, good electrodes and wiring can be obtained in subsequent processes. This makes it possible to form insulating layers, semiconductor layers, and the like. 【0110】 In this case, the source layer 130 is in contact with the pair of metal compound regions 124a and 124b. Although only a and drain layer 130b are shown, in this process they function as wiring. Electrode layers and the like can be formed together. Source layer 130a and drain layer 130b There are no particular limitations on the materials that can be used; various conductive materials can be used. It can. For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, Conductive materials such as copper, neodymium, and scandium can be used. 【0111】 As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material. Furthermore, electrodes, wiring, insulating layers, etc., may be formed after the above process. Wiring structure By adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, We can provide highly integrated circuits. 【0112】 Next, a transistor 164 is fabricated on the interlayer insulating layer 128 using Figures 13 and 14. The process will be explained below. Figures 13 and 14 show various electrical components on the interlayer insulating layer 128. This shows the manufacturing process for polar layers and transistor 164, so transistor 164 Transistor 160 and other components located at the bottom have been omitted. 【0113】 First, an insulating layer 13 is placed on the interlayer insulating layer 128, source layer 130a, and drain layer 130b. Form layer 2 (see Figure 13(A)). The insulating layer 132 is shaped using methods such as PVD or CVD. It can be done. Also, silicon oxide, silicon nitride, silicon nitride, HA5 Formed using materials containing inorganic insulating materials such as nium, aluminum oxide, and tantalum oxide. It is possible. 【0114】 Next, the insulating layer 132 extends to the source layer 130a and the drain layer 130b. An opening is formed. At this time, an opening is also formed in the region where the gate layer 136d will be formed later. Then, a conductive layer 134 is formed so as to be embedded in the above-mentioned opening (see Figure 13(B)). The above-mentioned opening can be formed by methods such as etching using a mask. The etch can be formed by methods such as exposure using a photomask. For etching, either wet etching or dry etching can be used, but for fine processing... From an engineering standpoint, dry etching is preferable. The formation of the conductive layer 134 is This can be done using film deposition methods such as PVD or CVD. Used for forming the conductive layer 134. Materials that can be used include molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium, as well as their alloys and compounds Examples include nitrides. 【0115】 More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, C After forming a thin titanium nitride film using the VD method, a tungsten film was then embedded in the opening. A method for forming it can be applied. Here, the titanium film formed by the PVD method is The oxide film at the interface is reduced, and the lower electrode layer (here, source layer 130a, drain layer 130b) It has the function of reducing contact resistance with (etc.). Furthermore, the titanium nitride film that is formed afterwards It has a barrier function that suppresses the diffusion of conductive materials. Also, titanium and titanium nitride, etc. After forming a barrier film, a copper film may be formed by a plating method. 【0116】 After forming the conductive layer 134, the conductive layer is further processed using methods such as etching and CMP. By removing a portion of 134 and exposing the insulating layer 132, electrode layer 136a, electrode layer 136b, A gate layer 136d is formed (see Figure 13(C)). Note that a portion of the conductive layer 134 is removed. When forming the electrode layer 136a, electrode layer 136b, and gate layer 136d, the surface is flat. It is desirable to process it so that it becomes flat. In this way, insulating layer 132, electrode layer 136a, By planarizing the surfaces of the electrode layer 136b and the gate layer 136d, in subsequent processes, This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and so on. 【0117】 Next, covering the insulating layer 132, electrode layer 136a, electrode layer 136b, and gate layer 136d A gate insulating layer 138 is formed on top of this (see Figure 13(D)). The gate insulating layer 138 is CV It can be formed using methods such as D method or sputtering method. In addition, the gate insulating layer 138 silicon dioxide, silicon nitride, silicon oxide nitride, silicon dioxide nitride, aluminum oxide, hafniac oxide It is preferable to form it to contain tantalum oxide, gallium oxide, etc. The insulating layer 138 may be a single-layer structure or a multi-layer structure. For example, the raw material gas For example, by plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A simple gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is particularly While not limited, it can be, for example, between 10 nm and 500 nm. (Laminated structure) For example, a first gate insulating layer with a film thickness of 50 nm to 200 nm and the first gate It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the insulating layer. be. 【0118】 Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as G to form island-shaped oxide semiconductor layers 140. (See Figure 13(E)). 【0119】 The oxide semiconductor used shall contain at least indium (In) or zinc (Zn). It is preferable to include these elements. It is particularly preferable to include In and Zn. Furthermore, using the oxide semiconductor As a stabilizer to reduce variations in the electrical characteristics of transistors, In addition, it is preferable to have gallium (Ga). Also, tin (S) as a stabilizer is preferable. It is preferable to have n). Also, it is preferable to have hafnium (Hf) as a stabilizer. It is preferable that the stabilizer be made of aluminum (Al). It's nice. 【0120】 Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europieu Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Ho Lumium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more types of lutetium (Lu). 【0121】 For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and binary metal acids. The oxides are In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxides (also written as IGZO) and In-Al-Zn are oxides of the same material. In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides Oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn acids In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides Materials, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, I n-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al -Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides It can be used. 【0122】 For example, in-Ga-Zn oxides are those whose main components are In, Ga, and Zn. It means an oxide containing In, and the ratio of In, Ga, and Zn is not specified. Also, In and Other metal elements besides Ga and Zn may be present. 【0123】 In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0, and m is not an integer) Materials represented by ) may also be used. Note that M is selected from Ga, Fe, Mn, and Co. It represents one or more metallic elements. Also, as an oxide semiconductor, In3SnO 5(ZnO) n Materials expressed as (n>0 and n is an integer) may also be used. 【0124】 For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn system with an atomic ratio of Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used. Alternatively, In:Sn:Zn= 1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3: (1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use In-Sn-Zn oxides with a specific atomic ratio or oxides with a similar composition. 【0125】 However, this is not limited to these, and includes the required semiconductor characteristics (mobility, threshold, variability, etc.). A suitable composition should be used depending on the requirements. Furthermore, in order to obtain the desired semiconductor properties, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density It is preferable to set the degree and other parameters appropriately. 【0126】 For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, However, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It can be raised. 【0127】 For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn = a:b:c(a+b The composition of an oxide with +c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+ The composition of the oxide C=1) is considered to be in the vicinity of a, b, and c, (a-A) 2 +(b-B) 2 +(c―C) 2 ≤r 2 This means that the following condition is met, and r can be set to, for example, 0.05. The same applies to other oxides. . 【0128】 Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or multicrystalline. It can be crystalline. Also, a structure that includes crystalline parts within an amorphous material is also acceptable. "S" is also acceptable. 【0129】 Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface. This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily. It allows for high mobility. 【0130】 Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, as shown in the table. By improving the flatness of the surface, mobility exceeding that of amorphous oxide semiconductors can be obtained. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably It is preferable to form it on a surface with a nm or smaller. 【0131】 Note that Ra is the centerline average roughness defined in JIS B0601 applied to the surface. This is a three-dimensional extension that allows for the calculation of "averaging the absolute value of the deviation from the reference plane to the specified plane." It can be expressed as "the value obtained" and is defined by the following formula. 【0132】 【number】 【0133】 In the above, S0 is the measurement surface (coordinates (x1,y1)(x1,y2)(x2,y 1) Refers to the area of ​​the rectangle enclosed by the four points represented by (x², y²), Z0 refers to the average height of the measurement surface. Ra is an atomic force microscope (AFM) It can be evaluated using a microscope. 【0134】 Here, an In-Ga-Zn-O-based metal oxide target is used as the oxide semiconductor layer. Therefore, an amorphous oxide semiconductor layer will be formed by sputtering. 【0135】 For example, a target for fabricating the oxide semiconductor layer 140 by sputtering is Alternatively, a metal oxide target, primarily composed of zinc oxide, can be used. Metal oxide target containing In, Ga, and Zn (composition ratio: In2O3:Ga 2O3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[ato [m ratio]) etc. can also be used. In addition, metal oxides containing In, Ga, and Zn - As a result, In:Ga:Zn = 1:1:1 [atom ratio], or In:Ga:Z A target with a composition ratio of n=1:1:2 [atom ratio] may also be used. The filling rate of the target material is 90% or more and 100% or less, preferably 95% or more (for example, 99%). It is 0.9%. By using a metal oxide target with a high packing density, a dense oxide can be formed. A semiconductor layer is formed. 【0136】 Furthermore, when using an In-Zn-O based material as the oxide semiconductor layer 140, the ter The composition ratio of Ghetto is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (when converted to mole ratio) In2O3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 ( Converted to a molar ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In Zn = 15:1 ~ 1.5:1 (converted to mole ratio: In2O3:ZnO = 15:2 ~) Let's assume a ratio of 3:4. For example, metal oxides used in the formation of In-Zn-O based oxide semiconductors Gett states that when the atomic ratio is In:Zn:O=X:Y:Z, Z > 1.5X + Y. 【0137】 Furthermore, In-Sn-Zn oxides can be called ITZOs, and the target used is The composition ratios are In:Sn:Zn in atomic ratios of 1:2:2, 2:1:3, 1:1:1, and This uses an oxide target with a ratio such as 20:45:35. 【0138】 The formation atmosphere for oxide semiconductor layers includes a noble gas atmosphere (typically argon), an oxygen atmosphere, Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferable. In terms of composition, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present in amounts of several ppm (desirable). It is preferable to use a high-purity gas that has been reduced to a level of approximately a few ppb. 【0139】 During the formation of the oxide semiconductor layer, the substrate is held in a processing chamber that is kept under reduced pressure, and the substrate The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming an oxide semiconductor layer while heating, the impurity concentration contained in the oxide semiconductor layer is reduced. This can reduce the amount of sputtering damage. Sputtered gas, from which hydrogen and water have been removed while removing residual moisture from the room, is introduced, and metal oxidation is performed. To form an oxide semiconductor layer using an object as a target. To remove residual moisture in the processing chamber. It is preferable to use an adsorption-type vacuum pump. For example, a cryopump or an ion pump. A titanium sublimation pump can be used. In addition, as an exhaust means, A cryopump may be used to add a cold trap to the pump. The deposition chamber is, for example, a compound containing hydrogen atoms, such as water (H2O) (more preferably) Since compounds containing carbon atoms are exhausted, oxide semiconductors formed in the deposition chamber are affected. The concentration of impurities in the layer can be reduced. 【0140】 Formation conditions include, for example, a distance of 100 mm between the substrate and the target, and a pressure of 0. 6 Pa, DC power of 0.5 kW, atmosphere is oxygen (oxygen flow rate ratio 100%). The following conditions can be applied. Note that if you use a pulsed DC power supply, This is preferable because it reduces distortion and results in a uniform film thickness distribution. The thickness of the oxide semiconductor layer is 2 nm. The wavelength should be 200 nm or less, preferably 5 nm to 30 nm. The appropriate thickness varies depending on the semiconductor material, so the thickness should be selected appropriately according to the material being used. Yes. 【0141】 Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced. Reverse sputtering is performed to generate plasma, and the material is deposited on the surface of the gate insulating layer 138. It is preferable to remove dust. Here, reverse sputtering is, in normal sputtering, Instead of colliding ions with a sputtering target, we're doing the opposite: colliding ions with the processing surface. This refers to a method of modifying a surface by causing ions to collide with it. This involves applying a high-frequency voltage to the processing surface under an argon atmosphere, thereby generating plasma near the substrate. There are methods for generating it, among others. Note that nitrogen, helium, oxygen, etc. can be used instead of an argon atmosphere. You may use it. 【0142】 For etching the above oxide semiconductor layer, dry etching and wet etching are both possible. You may use this. Of course, you can also use both in combination. To enable etching, etching conditions (etching gas and etching solution, Set the etching time, temperature, etc. as appropriate. 【0143】 Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases). For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), tetrachloride Examples include carbon (CCl4, etc.). Also, fluorine-containing gases (fluorinated gases, for example, fluorine-containing gases). Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethyl phosphate (e.g., CHF3), hydrogen bromide (HBr), oxygen (O2), and helium in these gases ( Gases to which noble gases such as helium (He) or argon (Ar) have been added may also be used. 【0144】 As for dry etching methods, parallel plate type RIE (Reactive Ion Etc The hing method, or ICP (Inductively Coupled Plasma): A conductively coupled plasma etching method can be used. It is possible to etch the material into the desired shape. As such, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The amount of power used, the electrode temperature on the substrate, etc., should be set as appropriate. 【0145】 The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid. These can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's okay to be there. 【0146】 Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably between 400°C and below the strain point of the substrate. The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. The oxide semiconductor layer 140 is subjected to a heat treatment at 450°C for 1 hour under ambient air conditions. This prevents re-introduction of water or hydrogen without contact with the material. 【0147】 Furthermore, heat treatment equipment is not limited to electric furnaces; it also includes heat conduction from a heated medium such as gas, and This may be a device that heats the object to be processed by thermal radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is: Inert gases such as argon or nitrogen, which do not react with the material being treated during heat treatment, are used. A gaseous substance is used. 【0148】 For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is placed in the inert gas, heated for several minutes, and then the board is removed from the inert gas during the GRTA process. It is also possible to do so. Using GRTA treatment makes high-temperature heat treatment possible in a short time. Because this is a heat treatment, it can be applied even under temperature conditions that exceed the strain point of the substrate. 【0149】 The first heat treatment mainly uses nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to perform this in an atmosphere that is free from water, hydrogen, etc. If so, the purity of the nitrogen, or noble gas such as helium, neon, or argon, introduced into the heat treatment device , 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, Furthermore, the impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less. 【0150】 Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. It may undergo crystallization and become microcrystalline or polycrystalline. For example, if the crystallization rate is 90% or higher, or 8 In some cases, a microcrystalline oxide semiconductor layer with 0% or more crystalline material may be formed. Also, the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it can become an amorphous oxide semiconductor layer that does not contain crystalline components. In some cases, it may be the case. 【0151】 Furthermore, microcrystals (particle size 1 nm) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer contains a mixture of elements up to 20 nm (typically between 2 nm and 4 nm). In some cases, this may be the case. 【0152】 Furthermore, by arranging microcrystals within an amorphous material, the electrical properties of the oxide semiconductor layer can be changed. It is also possible to use an In-Ga-Zn-O metal oxide target. When forming an oxide semiconductor layer, an electrically anisotropic In2Ga2ZnO7 crystal is used. By forming oriented microcrystalline regions, the electrical properties of the oxide semiconductor layer are altered. It is possible. 【0153】 More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the elements in a specific direction, the conductivity in a direction parallel to the surface of the oxide semiconductor layer is directed. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. These microcrystalline regions suppress the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. To have the ability. 【0154】 The oxide semiconductor layer having the above-mentioned microcrystalline portion is an oxide semiconductor layer obtained by GRTA treatment. It can be formed by surface heating. Also, the Zn content is insulated from In or Ga. By using a sputtering target smaller than the required volume, it is possible to form the material more favorably. . 【0155】 Here, the c-axis orientation is triangular or hexagonal when viewed from the direction of the ab-plane, surface, or interface. It has a angular atomic arrangement, and along the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are arranged in a specific way. They are arranged in layers, and in the ab plane, the orientation of the a axis or b axis is different (rotating around the c axis). (Also known as CAAC: C Axis Aligned Crystal) This section describes oxides that include this component. 【0156】 CAAC-containing oxides, in a broad sense, are non-single crystals, and from a direction perpendicular to their ab-plane... Observe, it has an atomic arrangement of triangles, hexagons, equilateral triangles, or regular hexagons, and is perpendicular to the c-axis direction. When viewed from a certain direction, it contains a phase in which metal atoms are arranged in layers, or in which metal atoms and oxygen atoms are arranged in layers. It refers to an oxide. 【0157】 CAAC is not a single crystal, but it is not formed solely from amorphous material. Also, C AAC contains crystalline parts (crystalline portions), but the boundary between one crystalline portion and another crystalline portion is Sometimes it's not possible to clearly distinguish between the two. 【0158】 If CAAC contains oxygen, some of the oxygen may be replaced with nitrogen. The c-axis of each individual crystal portion constituting C is in a constant direction (for example, the substrate surface supporting CAAC, They may be aligned in a direction perpendicular to the surface of the CAAC, etc. Alternatively, the individual components of the CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of each crystal portion is in a certain direction (for example, the substrate surface supporting CAAC, CAA It may be oriented perpendicular to the surface of C, etc. 【0159】 CAAC can be a conductor, a semiconductor, or an insulator, depending on its composition. And depending on its composition, it can be transparent or opaque to visible light. They might do that. 【0160】 An example of such CAAC is one that is formed in a film-like manner and perpendicular to the film surface or the supporting substrate surface. When observed from a certain direction, a triangular or hexagonal atomic arrangement can be observed, and the cross-section of the film is also observed. Then, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) was observed. We can also list crystals. 【0161】 An example of the crystal structure contained in CAAC will be explained in detail using Figures 23 to 25. Unless otherwise specified, Figures 23 to 25 define the upward direction as the c-axis direction, and the direction perpendicular to the c-axis direction. Let the intersecting surfaces be called surface ab. Note that when we simply refer to the upper half and the lower half, we are using surface ab as the boundary. This refers to the upper half and the lower half. 【0162】 Figure 23(A) shows one 6-coordinate In atom and six 4-coordinate oxygen atoms adjacent to the In atom (hereinafter The structure shows a 4-coordinate O(O) and a nearby oxygen atom. Here, for each metal atom, there is a nearby oxygen atom. A structure showing only atoms is called a small group. The structure in Figure 23(A) takes the form of an octahedron, For simplicity, it is shown as a planar structure. Note that the upper and lower halves of Figure 23(A) are respectively There are 3 oxygen atoms in each of the 4-coordinate groups. The small group shown in Figure 23(A) has a charge of 0. 【0163】 Figure 23(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the Ga atom (hereinafter The structure shows a 3-coordinate oxygen atom and two 4-coordinate oxygen atoms adjacent to Ga. The 3-coordinate oxygen atom is Both are located on the ab plane. There is one in the upper half and one in the lower half of Figure 23(B). There is a 4-coordinate oxygen atom. Also, since in can take on a 5-coordinate structure, it can take on the structure shown in Figure 23(B). The small group shown in Figure 23(B) has a charge of 0. 【0164】 Figure 23(C) shows a molecule with one 4-coordinate Zn and four 4-coordinate O atoms adjacent to the Zn. The structure is shown. The upper half of Figure 23(C) has one 4-coordinate oxygen atom, and the lower half has three 4-coordinate oxygen atoms. There is an O in position 1. Alternatively, there are 3 4-coordinate O in the upper half of Figure 23(C) and 1 in the lower half. There may also be O atoms with 4 coordination. The small group shown in Figure 23(C) has a charge of 0. 【0165】 Figure 23(D) shows a structure with one 6-coordinate Sn element and six 4-coordinate O elements adjacent to the Sn element. The structure is shown. The upper half of Figure 23(D) has three 4-coordinate oxygen atoms, and the lower half has three 4-coordinate oxygen atoms. There is an O at position 1. The small group shown in Figure 23(D) has a charge of +1. 【0166】 Figure 23(E) shows a small group containing two Zn molecules. The upper half of Figure 23(E) shows one Zn molecule. There is a 4-coordinate oxygen atom, and the lower half has one 4-coordinate oxygen atom. Small group shown in Figure 23(E) The charge of P becomes -1. 【0167】 Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups This is called a large group (also called a unit cell). 【0168】 Here, we will explain the rules by which these subgroups combine. These rules are shown in Figure 23(A). The three oxygen atoms in the upper half of the 6-coordinate In each have three adjacent oxygen atoms in the lower half The three O atoms each have three adjacent In atoms in the upward direction. One of the upper half of the 5-coordinate Ga O has one adjacent Ga in the downward direction, and the lower half of O has one adjacent Ga in the upward direction. The 4-coordinate Zn has one oxygen atom in the upper half that is adjacent to one Zn atom below it, and the 3 oxygen atoms in the lower half O has three neighboring Zn atoms in the upward direction. In this way, the metal atom has four coordination in the upward direction. The number of oxygen atoms is equal to the number of nearby metal atoms below that oxygen atom, and similarly, the number of metal atoms below that oxygen atom is equal. The number of 4-coordinate oxygen atoms is equal to the number of adjacent metal atoms above each oxygen atom. The sum of the number of nearby metal atoms below and the number of nearby metal atoms above is 4. This refers to the number of 4-coordinate oxygen atoms above a metal atom and the number of 4-coordinate oxygen atoms below another metal atom. When the sum of the number of oxygen atoms is 4, two small groups containing metal atoms can bond together. For example, a 6-coordinate metal atom (In or Sn) can bond via a 4-coordinate oxygen atom in the lower half. In that case, since there are three 4-coordinate oxygen atoms, a 5-coordinate metal atom (Ga or In) or 4 It will bond with one of the coordinating metal atoms (Zn). 【0169】 Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine in such a way that the total charge of the layered structure becomes 0. They form a middle group. 【0170】 Figure 24(A) shows a model diagram of the intermediate group that constitutes the layered structure of the In-Sn-Zn-O system. Figure 24(B) shows the large group, which is composed of three medium groups. (C) shows the atomic arrangement when the layer structure of Figure 24(B) is observed from the c-axis direction. 【0171】 In Figure 24(A), for simplicity, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, the upper half and lower half of Sn each contain three 4-coordinate oxygen atoms. It is shown as frame 3. Similarly, in Figure 24(A), the upper and lower halves of In Each of these has one 4-coordinate oxygen atoms, which are shown as 1 in the circle. Similarly, Figure 2 In 4(A), the lower half has one 4-coordinate oxygen atom, and the upper half has three 4-coordinate oxygen atoms. A Zn molecule has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half. This indicates n. 【0172】 In Figure 24(A), the middle group that constitutes the layered structure of the In-Sn-Zn-O system is the upper Starting from there, there are three 4-coordinate oxygen atoms in the upper half and three 4-coordinate oxygen atoms in the lower half of the Sn atom, and one 4-coordinate oxygen atom in each half. It is bonded to In in the upper and lower halves, and that In has three 4-coordinate oxygen atoms in the upper half. It is bonded to Zn, and through one 4-coordinate oxygen atom in the lower half of the Zn, three 4-coordinate oxygen atoms are bonded to the upper half. In is bonded to the In in the lower half, and that In has one 4-coordinate O in the upper half of the Zn It binds to a small group consisting of two atoms, via one 4-coordinate oxygen atom in the lower half of this small group. This configuration consists of 4-coordinate oxygen atoms bonded to Sn atoms in the upper and lower halves, with three oxygen atoms bonded to each other. Multiple groups combine to form a larger group. 【0173】 Here, in the case of 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0, respectively. It can be considered as 667, -0.5. For example, In (6-coordinate or 5-coordinate), Zn ( The charges of 4-coordinate (Sn) and 5-coordinate (Sn) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Thus, it forms a layered structure containing Sn. To achieve this, a charge of -1 is needed to cancel out the charge of +1. A structure that takes on a charge of -1 is shown in the figure. As shown in 23(E), a small group containing two Zn atoms is an example. If there is one small group containing Zn and another small group containing 2 Zn, the charges cancel each other out. Therefore, the total charge of the layered structure can be set to 0. 【0174】 Specifically, the large groups shown in Figure 24(B) are repeated, resulting in In-Sn-Z An nO-based crystal (In2SnZn3O8) can be obtained. The layered structure of the n-Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number) It can be represented by the following empirical formula: 【0175】 In addition, there are other oxides of quaternary metals, such as In-Sn-Ga-Zn oxides, In-Ga-Zn oxides (also written as IGZO), which are oxides of ternary metals, -Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn- Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In- Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-S m-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb -Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er- Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Z n-based oxides, and oxides of binary metals such as In-Zn oxides, Sn-Zn oxides, and A l-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, The same applies when using In-Ga-based oxides, etc. 【0176】 For example, Figure 25(A) shows the intermediate group that constitutes the layered structure of the In-Ga-Zn-O system. A diagram is shown. 【0177】 In Figure 25(A), the middle group constituting the layered structure of the In-Ga-Zn-O system is the upper In order from there, the ion has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with Zn in the middle, and via the three 4-coordinate oxygen atoms in the lower half of that Zn, the 4-coordinate oxygen atoms are connected. Each atom bonds with the Ga atoms in the upper and lower halves, and one of the four-coordinate O atoms in the lower half of that Ga atom... Through this, the structure consists of three 4-coordinate oxygen atoms bonded to the in atoms in the upper and lower halves, respectively. These smaller groups combine to form larger groups. 【0178】 Figure 25(B) shows the large group, which is composed of three subgroups. Note that Figure 25(C) This shows the atomic arrangement when the layer structure in Figure 25(B) is observed from the c-axis direction. 【0179】 Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since they are +3, +2, and +3 respectively, they are small groups containing any of In, Zn, and Ga. The charge becomes 0. Therefore, if these are combinations of small groups, then the medium group The total charge is always 0. 【0180】 Furthermore, the intermediate groups constituting the layered structure of the In-Ga-Zn-O system are shown in Figure 25(A). Not limited to the same intermediate group, but combining intermediate groups with different arrangements of In, Ga, and Zn. Large groups could also be targeted. 【0181】 The first heat treatment of the oxide semiconductor layer 140 involves processing the island-shaped oxide semiconductor layer 140. It can also be performed on the oxide semiconductor layer before the first heat treatment. In that case, after the first heat treatment, a heating device The substrate is removed from the machine, and then the photolithography process is performed. 【0182】 Furthermore, is the above heat treatment effective in dehydrating and dehydrogenating the oxide semiconductor layer 140? These processes can also be called dehydration or dehydrogenation. The chemical treatment involves forming an oxide semiconductor layer, and then forming a source layer and a drain layer on the oxide semiconductor layer 140. After laminating the layers, or after forming a protective insulating layer on the source layer and drain layer, etc. This can be done in the ming. Furthermore, such dehydration and dehydrogenation treatments are performed. You can do it multiple times, not just once. 【0183】 Next, the source layer 142a and the drain layer 142 are brought into contact with the oxide semiconductor layer 140. b is formed (see Figure 13(F)). The source layer 142a and drain layer 142b oxidize. After forming a conductive layer to cover the semiconductor layer 140, the conductive layer is selectively etched. It can be formed by doing so. 【0184】 The conductive layer is produced by methods such as sputtering, PVD, and plasma CVD. It can be formed using the CVD method. Furthermore, aluminum can be used as the material for the conductive layer. Elements selected from chromium, copper, tantalum, titanium, molybdenum, and tungsten, as mentioned above. Alloys containing the following elements can be used. Manganese, magnesium, zirconium Materials selected from one or more of the following may be used: thorium, beryllium, and thorium. In addition, aluminum is combined with titanium, tantalum, tungsten, molybdenum, chromium, and neodymium. Materials may be used that consist of one or more elements selected from mu and scandium. The conductive layer may be a single layer or a laminated structure of two or more layers. For example, A single-layer structure of aluminum film containing ricon, and a double-layer structure with a titanium film laminated on top of the aluminum film. Examples of structures include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are stacked. 【0185】 Furthermore, during etching of the conductive layer, care must be taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. Therefore, in this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (concave) are formed. It may also become an oxide semiconductor layer having a portion. 【0186】 Furthermore, between the oxide semiconductor layer 140 and the source layer 142a, or between the oxide semiconductor layer 140 and the An oxide conductive layer may be formed between the rain layer 142b. Oxide conductive layer and source layer 1 The metal layers for forming 42a and the drain layer 142b are to be formed continuously. (Post-deposition is possible.) The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced. This allows for high-speed operation of transistors. 【0187】 Furthermore, in order to reduce the number of masks used and the number of processes, the transmitted light will have multiple intensities. A resist mask is formed using a multi-gradation mask, which is an optical mask, and this is used for etching. The process may be carried out. The resist mask formed using a multi-gradation mask has multiple thicknesses. This results in a stepped shape, and the shape can be further deformed by ashing. It can be used in multiple etching processes to process different patterns. The multi-level mask allows for registrations corresponding to at least two different patterns. A mask can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding mask can be formed. Since the photography process can also be reduced, the process can be simplified. 【0188】 Furthermore, after the above-mentioned process, plasma treatment using gases such as N2O, N2, or Ar is performed. It is preferable to perform the following. The surface of the exposed oxide semiconductor layer by the plasma treatment Water and other substances adhering to it are removed. Additionally, plasma treatment is performed using a mixed gas of oxygen and argon. You may do so. 【0189】 Next, a protective insulating layer 1 that contacts a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Forms 44 (see Figure 13(G)). 【0190】 The protective insulating layer 144 is made by sputtering or other methods to remove impurities such as water and hydrogen from the protective insulating layer 144. It can be formed using appropriate methods to prevent the inclusion of certain substances. Furthermore, its thickness is at least The thickness should be 1 nm or greater. Materials that can be used for the protective insulating layer 144 include silicon dioxide and nitrogen dioxide. Examples include silicon dioxide, silicon oxide nitride, and silicon dioxide nitride. Furthermore, their structure can also be expressed as a single-layer structure. It's good, and it's also good as a laminated structure. The substrate temperature when forming the protective insulating layer 144 is above room temperature. The temperature should preferably be 300°C or lower, and the atmosphere should be a noble gas atmosphere (typically argon) and acid. A plain atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen, is preferable. ru. 【0191】 If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer 140, Hydrogen extracts oxygen from the oxide semiconductor layer 140, and so on, and the oxide semiconductor layer 14 The back channel side of 0 may become less resistant, potentially leading to the formation of parasitic channels. Therefore, in the formation method, hydrogen should be used to ensure that the protective insulating layer 144 contains as little hydrogen as possible. It is important not to use it. 【0192】 Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is because the oxide semiconductor layer 140 and the protective insulating layer 144 contain hydrogen, hydroxyl groups, or water. This is to prevent it from happening. 【0193】 To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, by using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbo pump with a cold trap added is preferable. It may be present. The deposition chamber, which is evacuated using a cryopump, may contain, for example, hydrogen atoms or water (H Because compounds containing hydrogen atoms, such as 2O, are removed, the protective insulation formed in the deposition chamber is The concentration of impurities in the marginal layer 144 can be reduced. 【0194】 The sputtering gas used when forming the protective insulating layer 144 includes hydrogen, water, hydroxyl groups, and This process removes impurities such as hydrides to a level of several ppm (preferably several ppb). It is preferable to use a high-purity gas. 【0195】 Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the process at temperatures between 0°C and 400°C, for example, between 250°C and 350°C. Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the transistors. 【0196】 Furthermore, heat treatment is performed in air at a temperature between 100°C and 200°C for a period of 1 hour to 30 hours. This is also acceptable. This heat treatment may be carried out by heating while maintaining a constant heating temperature, or from room temperature to 100°C. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment is performed under reduced pressure. This procedure may be performed instead of the second heat treatment, or before or after the second heat treatment. 【0197】 Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 14(A)). The intervening insulating layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as fluorine. After formation, the surface is planarized by methods such as CMP or etching. desirable. 【0198】 Next, electrodes are applied to the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. An opening that extends to layer 136a, electrode layer 136b, source layer 142a, and drain layer 142b. A conductive layer 148 is formed and embedded in the opening (see Figure 14(B)). The opening can be formed by methods such as etching using a mask. The mask is It can be formed by methods such as exposure using a photomask. Etching and Either wet etching or dry etching can be used, but the appearance of microfabrication From this perspective, dry etching is preferable. The conductive layer 148 is formed by PVD This can be done using film deposition methods such as the CVD method. It is used for forming the conductive layer 148. Materials that can be used include molybdenum, titanium, chromium, tantalum, tungsten, and aluminum. Conductive materials such as nium, copper, neodymium, scandium, and their alloys and compounds (for example) Examples include nitrides. 【0199】 Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then CVD is applied. After forming a thin titanium nitride film using the method, a tungsten film is formed to fill the opening. A method can be applied. Here, the titanium film formed by the PVD method is at the interface. The oxide film is reduced, and the lower electrode (here, electrode layer 136a, electrode layer 136b, source layer 1) It has the function of reducing contact resistance with 42a and the drain layer 142b). Furthermore, afterwards The formed titanium nitride film has a barrier function that suppresses the diffusion of conductive materials. Even if a copper film is formed by a plating method after forming a barrier film with tungsten or titanium nitride, good. 【0200】 After forming the conductive layer 148, the conductive layer 14 is formed using methods such as etching and CMP. Remove a portion of 8 to expose the interlayer insulating layer 146, and then electrode layer 150a, electrode layer 150b, Electrode layer 150d and electrode layer 150e are formed (see Figure 14(C)). Note that the above conductive layer 1 Remove a portion of 48 to obtain electrode layer 150a, electrode layer 150b, electrode layer 150d, electrode layer 150 When forming layer e, it is desirable to process the surface so that it becomes flat. The insulating layer 146, electrode layer 150a, electrode layer 150b, electrode layer 150d, and electrode layer 150e By planarizing the surface, good electrodes, wiring, insulating layers, and semiconductor layers can be created in subsequent processes. It becomes possible to form things like this. 【0201】 Furthermore, an insulating layer 152 is formed, and an electrode layer 150a and an electrode layer 150b are added to the insulating layer 152. An opening is formed that extends to electrode layer 150d and electrode layer 150e, and the opening is to be embedded After forming the conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP, and then an insulating layer is formed. The margin layer 152 is exposed to form electrode layers 154a, 154b, and 154d. (See Figure 14(D)). This process is the same as when forming the electrode layer 150a, etc. Details will be omitted. 【0202】 Figures 15 to 18 show modified examples of transistor 164. 【0203】 Figure 15 shows a gate layer 136d below an oxide semiconductor layer 140, and a source layer 142a The drain layer 142b is in contact with the lower surface of the oxide semiconductor layer 140. This indicates the 'njista 164'. 【0204】 A major difference between the configuration shown in Figure 15 and the configuration shown in Figure 11 is the source layer 142a and the do The connection point between the rain layer 142b and the oxide semiconductor layer 140 can be seen in Figure 1. In the configuration shown in 1, the source layer 142a and the dot are located on the upper surface of the oxide semiconductor layer 140. In contrast to contact with the rain layer 142b, in the configuration shown in Figure 15, the oxide semiconductor layer 140 On the lower surface, it is in contact with the source layer 142a and the drain layer 142b. Due to differences in contact, the arrangement of other electrode layers, insulating layers, etc., differs. The details of each component are the same as in Figure 11. 【0205】 Specifically, the transistor 164 shown in Figure 15 is provided on the interlayer insulating layer 128. The gate layer 136d, the gate insulating layer 138 provided on the gate layer 136d, and the gate insulating A source layer 142a and a drain layer 142b are provided on layer 138, and the source layer 142 It also has an oxide semiconductor layer 140 in contact with the upper surface of a and the drain layer 142b. On top of the transistor 164, a protective insulating layer 144 is placed so as to cover the oxide semiconductor layer 140. A system is in place. 【0206】 Figure 16 shows a transistor 16 having a gate layer 136d on an oxide semiconductor layer 140. Figure 4 shows that the source layer 142a and the drain layer 142b are oxidized. This figure shows an example of a configuration in which the lower surface of the material semiconductor layer 140 is in contact with the oxide semiconductor layer 140. Yes, Figure 16(B) shows that the source layer 142a and the drain layer 142b are oxide semiconductor layers 1 This figure shows an example of a configuration in which the oxide semiconductor layer 140 is in contact with the upper surface of 40. 【0207】 The main difference between the configuration shown in Figure 11 or Figure 15 and the configuration shown in Figure 16 is the oxide semiconductor layer 1 The point is that there is a gate layer 136d on top of 40. Also, the configuration shown in Figure 16(A) and Figure 16 The main difference in the configuration shown in (B) is that the source layer 142a and the drain layer 142b are oxidized The point is whether the contact occurs on the lower or upper surface of the semiconductor layer 140. And, due to these differences, the arrangement of other electrode layers, insulating layers, etc. may differ. This is the case. Details of each component are the same as those shown in Figure 11, etc. 【0208】 Specifically, the transistor 164 shown in Figure 16(A) is provided on the interlayer insulating layer 128. Source layer 142a and drain layer 142b, and source layer 142a and drain layer 14 An oxide semiconductor layer 140 in contact with the upper surface of 2b, and provided on the oxide semiconductor layer 140 The region where the gate insulating layer 138 and the oxide semiconductor layer 140 on the gate insulating layer 138 overlap. It has a gate layer 136d. 【0209】 Furthermore, the transistor 164 shown in Figure 16(B) is provided on the interlayer insulating layer 128. A saw is provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. The drain layer 142a and the drain layer 142b, and the oxide semiconductor layer 140, the source layer 142a, and The gate insulating layer 138 provided on the drain layer 142b, and the acid on the gate insulating layer 138 It has a gate layer 136d provided in a region that overlaps with the ionized semiconductor layer 140. 【0210】 In addition, the configuration shown in Figure 16 omits some components compared to the configuration shown in Figure 11, etc. This may occur (for example, electrode layer 150a or electrode layer 154a). In this case, the manufacturing process This also has the secondary effect of simplifying the process. Of course, even in the configuration shown in Figure 11, It goes without saying that non-essential components can be omitted. 【0211】 Figure 17 shows the case where the device size is relatively large, and below the oxide semiconductor layer 140 A transistor 164 having a gate layer 136d is shown. In this case, the flatness of the surface and The requirements for coverage are relatively lenient, so wiring and electrodes can be placed in the insulating layer. It is not necessary to form it in an embedded manner. For example, patterning can be done after the conductive layer has been formed. This makes it possible to form gate layers such as 136d. 【0212】 The main difference between the configuration shown in Figure 17(A) and the configuration shown in Figure 17(B) is the source layer 142 a and drain layer 142b are either on the lower surface or the upper surface of the oxide semiconductor layer 140. The point is whether or not they come into contact. And due to these differences, other electrode layers The arrangement of insulating layers and other components differs. Details of each component can be seen in Figure 11, etc. It is similar to that. 【0213】 Specifically, the transistor 164 shown in Figure 17(A) is provided on the interlayer insulating layer 128. A gate layer 136d, a gate insulating layer 138 provided on the gate layer 136d, and A source layer 142a and a drain layer 142b are provided on the insulating layer 138, and the source layer The structure includes an oxide semiconductor layer 140 in contact with the upper surface of 142a and the drain layer 142b. . 【0214】 Furthermore, the transistor 164 shown in Figure 17(B) is provided on the interlayer insulating layer 128. The gate layer 136d, the gate insulating layer 138 provided on the gate layer 136d, and the gate insulating An oxide semiconductor layer 140 is provided in the region overlapping with the gate layer 136d on layer 138, and acid Source layer 142a and drain provided in contact with the upper surface of the ionized semiconductor layer 140 It has layer 142b. 【0215】 Furthermore, in the configuration shown in Figure 17, the number of components is reduced compared to the configuration shown in Figure 11, etc. It may be omitted. In this case, too, the effect of simplifying the manufacturing process can be achieved. 【0216】 Figure 18 shows the case where the device size is relatively large, with the oxide semiconductor layer 140 on top of A transistor 164 having a gate layer 136d is shown. In this case as well, the surface is flat. The requirements for insulation and coverage are relatively lenient, so wiring and electrodes are insulated. It is not necessary to form it by embedding it inside. For example, patterning can be done after the conductive layer has been formed. This makes it possible to form gate layers such as 136d. 【0217】 The main difference between the configuration shown in Figure 18(A) and the configuration shown in Figure 18(B) is the source layer 142 a and drain layer 142b are either on the lower surface or the upper surface of the oxide semiconductor layer 140. The point is whether or not they come into contact. And due to these differences, other electrode layers The arrangement of insulating layers and other components differs. Details of each component can be seen in Figure 11, etc. It is similar to that. 【0218】 Specifically, the transistor 164 shown in Figure 18(A) is provided on the interlayer insulating layer 128. Source layer 142a and drain layer 142b, and source layer 142a and drain layer 14 The oxide semiconductor layer 140 in contact with the upper surface of 2b, the source layer 142a, and the drain layer 142 b, and a gate insulating layer 138 provided on the oxide semiconductor layer 140, and gate insulating layer 13 8 has a gate layer 136d provided in a region that overlaps with the oxide semiconductor layer 140 on the above. . 【0219】 Furthermore, the transistor 164 shown in Figure 18(B) is provided on the interlayer insulating layer 128. A saw is provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. The source layer 142a and the drain layer 142b, and the source layer 142a, the drain layer 142b, A gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate insulating layer 138 provided on the gate insulating layer 138 It has a gate layer 136d, and the gate layer 136d is a gate insulating layer 13 It is provided in the region that overlaps with the oxide semiconductor layer 140 via 8. 【0220】 Furthermore, in the configuration shown in Figure 18, the number of components is reduced compared to the configuration shown in Figure 11, etc. It may be omitted. In this case, too, the effect of simplifying the manufacturing process can be achieved. 【0221】 Furthermore, the oxide semiconductor layer 140, source layer 142a, and drain layer 142b shown in Figure 11. Between them, an oxide conductive layer that functions as a source region and a drain region is used as a buffer layer. It may be provided. Figures 19 and 20 show a transistor 164 in Figure 11 with an oxide conductive layer provided. This is a diagram showing a lunger. 【0222】 The transistor 164 in Figures 19 and 20 consists of an oxide semiconductor layer 140 and a source layer 142a. Between the drain layer 142b and the oxide conductive layer, which functions as a source region and a drain region. 162a and 162b are formed. The difference between transistor 164 in Figures 19 and 20 is that The difference lies in the shape of the oxide conductive layers 162a and 162b, which vary depending on the manufacturing process. 【0223】 In transistor 164 of Figure 19, an oxide semiconductor layer and an oxide conductive layer are stacked, and acid The laminate of the oxide semiconductor layer and the oxide conductive layer is processed using the same photolithography process. This forms island-shaped oxide semiconductor layers 140 and oxide conductive layers. Oxide semiconductor layer and oxide After forming a source layer 142a and a drain layer 142b on the conductive layer, the source layer 142a and drain layer 142b are formed. Using the rain layer 142b as a mask, the island-shaped oxide conductive layer is etched, and the source region and Then, oxide conductive layers 162a and 162b, which will serve as drain regions, are formed. 【0224】 In the transistor 164 of Figure 20, an oxide conductive layer is formed on the oxide semiconductor layer 140. A metal conductive layer is formed on top of it, and the oxide conductive layer and the metal conductive layer are subjected to the same photolithography. Processed by the process, oxide conductive layers 162a and 1 become the source region and drain region. 62b, source layer 142a, and drain layer 142b are formed. 【0225】 Furthermore, during the etching process to shape the oxide conductive layer, the oxide semiconductor layer becomes excessive To prevent excessive etching, the etching conditions (type of etching material, concentration, etching) Adjust the time (and other details) as appropriate. 【0226】 The methods for depositing the oxide conductive layers 162a and 162b include sputtering and vacuum deposition (electron Methods such as beam deposition, arc discharge ion plating, and spraying are used. Examples of materials for the conductive oxide layer include zinc oxide, aluminum zinc oxide, and aluminum zinc oxynitride. Zinc gallium oxide, indium tin oxide, etc., can be applied. Silicon dioxide may be added to it. 【0227】 The oxide conductive layer is used as the source region and drain region, and the oxide semiconductor layer 140 and the source layer By providing it between 142a and the drain layer 142b, the source region and drain region are reduced This allows for reduced resistance, enabling transistor 164 to operate at high speed. 【0228】 Furthermore, by adopting this configuration, the voltage rating of transistor 164 can be improved. It is possible. 【0229】 Note that in Figures 19 and 20, the oxide semiconductor layer 140 of the transistor 164 shown in Figure 11 Regarding the configuration in which an oxide conductive layer is provided between the source layer 142a and the drain layer 142b... As shown in Figures 15, 16, 17, and 18, the oxide semiconductor layer 1 of transistor 164 40 and a configuration in which an oxide conductive layer is provided between the source layer 142a and the drain layer 142b. It is also possible to do so. 【0230】 In this example, transistor 164 is stacked on top of transistor 160. As explained above, the configuration of transistors 160 and 164 is limited to this. It is not that. For example, transistors 160 and 164 are formed on the same plane. Furthermore, transistors 160 and 164 can be superimposed. You can do that. 【0231】 <Variations in the Oxide Semiconductor Layer Fabrication Process> Figure 21 shows the process for fabricating an oxide semiconductor layer, which is different from the transistor fabrication process described above. I will use it to explain. 【0232】 The oxide semiconductor layer is formed by placing a first crystalline oxide semiconductor layer on a first crystalline oxide semiconductor layer It has a second crystalline oxide semiconductor layer that is thicker than the first one. 【0233】 An insulating layer 437 is formed on the insulating layer 400. Here, as the insulating layer 437, PECV Oxide insulation with a film thickness of 50 nm to 600 nm using the D method or sputtering method. A layer is formed. For example, the oxide insulating layer may be a silicon oxide layer, a gallium oxide layer, and an acid Aluminum oxide layer, silicon oxide nitride layer, aluminum oxide nitride layer, or silicon oxide nitride layer A single layer selected from the recon layer or a stack of these layers can be used. 【0234】 Next, a first oxide semiconductor layer with a thickness of 1 nm to 10 nm is formed on the insulating layer 437. The first oxide semiconductor layer is formed using the sputtering method, and the sputtering method The substrate temperature during film deposition shall be between 200°C and 400°C. 【0235】 Here, metal oxide targets (In-Ga-Zn-O type metal oxide targets (I Using n2O3:Ga2O3:ZnO (molar ratio = 1:1:2), the substrate and target were... Distance between the two points: 170mm, board temperature: 250℃, pressure: 0.4Pa, DC power supply: 0 0.5kW, under oxygen only, argon only, or argon and oxygen atmosphere, first film thickness of 5nm A thin oxide semiconductor layer is formed. 【0236】 Next, the chamber atmosphere in which the substrate is placed is changed to nitrogen or dry air, and the first heating treatment is performed. The process is carried out. The temperature of the first heat treatment shall be between 400°C and 750°C. First heat treatment This forms the first crystalline oxide semiconductor layer 450a (see Figure 21(A)). 【0237】 Depending on the substrate temperature during film formation and the temperature of the first heat treatment, the film formation and the first heat treatment Therefore, crystallization occurs from the film surface, crystal growth occurs from the film surface toward the interior, and c-axis orientation occurs. Crystals are obtained. Due to the first heat treatment, zinc and oxygen accumulate in large quantities on the film surface, and the upper surface A graphene-type two-dimensional crystal, composed of zinc and oxygen with hexagonal faces, forms a single layer on the outermost surface. Multiple layers are formed, which grow in the film thickness direction and overlap to form a laminate. The temperature of the heat treatment is increased. Crystal growth then progresses from the surface to the interior, and then from the interior to the bottom. 【0238】 The first heat treatment removes oxygen from the insulating layer 437, which is an oxide insulating layer, and the first crystalline acid Diffusion occurs at or near the interface with the ionized semiconductor layer 450a (within ±5 nm of the interface). This reduces oxygen vacancies in the first crystalline oxide semiconductor layer. Therefore, as an underlying insulating layer The insulating layer 437 used is in the film (bulk) and the first crystalline oxide semiconductor layer 450a At least one of the interfaces of the insulating layer 437 contains an amount of oxygen exceeding the stoichiometric ratio. It is preferable. 【0239】 Next, a second oxide semiconductor layer thicker than 10 nm is placed on the first crystalline oxide semiconductor layer 450a. A conductive layer is formed. The second oxide semiconductor layer is formed using the sputtering method, and the film is deposited. The substrate temperature at that time shall be between 200°C and 400°C. The substrate temperature during film formation shall be 20 By setting the temperature to between 0°C and 400°C, the first crystalline oxide semiconductor layer is in contact with the surface. The oxide semiconductor layer being deposited undergoes alignment of precursors, thereby creating what is known as order. ru. 【0240】 Here, metal oxide targets (In-Ga-Zn-O type metal oxide targets (I Using n2O3:Ga2O3:ZnO (molar ratio = 1:1:2), the substrate and target were... Distance between the boards: 170mm, board temperature: 400℃, pressure: 0.4Pa, DC power supply: 0 0.5kW, oxygen only, argon only, or argon and oxygen atmosphere, film thickness 25nm A second oxide semiconductor layer is formed. 【0241】 Next, the atmosphere in the chamber where the substrate is placed is changed to nitrogen or dry air, and the second heating treatment is performed. Perform the following. The temperature for the second heat treatment shall be between 400°C and 750°C. Second heat treatment This forms a second crystalline oxide semiconductor layer 450b (see Figure 21(B)). The heat treatment is performed under a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen. This aims to increase the density of the second crystalline oxide semiconductor layer and reduce the number of defects. According to the principle, the first crystalline oxide semiconductor layer 450a acts as a nucleus, and the film thickness direction, i.e., from the bottom to the inside, is formed. Crystal growth progresses in the region, forming a second crystalline oxide semiconductor layer 450b. 【0242】 Furthermore, the process from the formation of the insulating layer 437 to the second heat treatment is carried out continuously without exposure to the atmosphere. It is preferable to carry this out precisely. The steps from the formation of the insulating layer 437 to the second heat treatment involve hydrogen and And under an atmosphere that contains almost no moisture (inert atmosphere, reduced pressure atmosphere, dry air atmosphere, etc.) It is preferable to carry this out at a dew point of -40°C or lower, preferably -5°C, for example, for moisture. Maintain a dry nitrogen atmosphere at 0°C or below. 【0243】 Next, the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b An oxide semiconductor layer consisting of an oxide semiconductor stack is processed to form an oxide semiconductor layer 4 consisting of an island-shaped oxide semiconductor stack. Forms 53 (see Figure 21(C)). In the figure, the first crystalline oxide semiconductor layer 450a and The interface of the second crystalline oxide semiconductor layer 450b is shown by a dotted line, and the oxide semiconductor stacking is explained. However, there is no clear interface; the diagram is merely there to make it easier to understand. It is showing. 【0244】 The process of processing oxide semiconductor stacks involves first forming a mask of the desired shape on the oxide semiconductor stack, This can be done by etching the oxide semiconductor stack. The mask described above is They can be formed using methods such as photolithography. Alternatively, inkjet The mask may be formed using methods such as the T method. 【0245】 Furthermore, etching of oxide semiconductor layers can be done using either dry etching or wet etching. That's also fine. Of course, you can also use them in combination. 【0246】 Furthermore, the first crystalline oxide semiconductor layer and the second crystalline acid obtained by the above manufacturing method One of the characteristics of the ion semiconductor layer is that it has a c-axis orientation. However, the first conclusion The crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer do not have a single-crystal structure, but an amorphous structure. It is not a structure, but a crystal with c-axis orientation (C Axis Aligned Crystal). It contains an oxide containing stal (also called CAAC). The body layer and the second crystalline oxide semiconductor layer have grain boundaries in some parts. 【0247】 The first and second crystalline oxide semiconductor layers are made of an oxide material having at least Zn. Yes, there are quaternary metal oxides such as In-Al-Ga-Zn-O and In-Sn-G a-Zn-O type materials, and ternary metal oxides such as In-Ga-Zn-O type materials, In -Al-Zn-O type materials, In-Sn-Zn-O type materials, Sn-Ga-Zn-O type Materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials, and binary metallic acids In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials These include Zn-Mg-O based materials and Zn-O based materials. Also, In-Si-Ga- Zn-O-based materials, In-Ga-B-Zn-O-based materials, In-B-Zn-O-based materials Materials may be used. Furthermore, SiO2 may be added to the above materials. Here, for example, I n-Ga-Zn-O materials are composed of indium (In), gallium (Ga), and zinc (Zn This means an oxide having ), and the composition ratio is not particularly specified. Also, In and Ga and It may contain elements other than Zn. 【0248】 Furthermore, a two-layer structure is formed in which a second crystalline oxide semiconductor layer is formed on a first crystalline oxide semiconductor layer. Not limited to the construction, a third crystalline oxide semiconductor layer is formed after the formation of a second crystalline oxide semiconductor layer. The process of film formation and heat treatment is repeated to create a laminated structure of three or more layers. That's good too. 【0249】 A first crystalline oxide semiconductor layer such as oxide semiconductor layer 453 and a second crystalline oxide semiconductor layer By using stacked layers in transistors, stable electrical characteristics and reliability are achieved. High transistors can be achieved. 【0250】 <cpu> A specific example of a CPU having the semiconductor integrated circuit described above will be explained with reference to Figure 22. . 【0251】 Figure 22 is a block diagram showing the specific configuration of the CPU. The CPU shown in Figure 22 is based Arithmetic logic unit (ALU) 90 on board 900 1, ALU Controller902, Instruction Decoder9 03, Interrupt Controller904, Timing Control ller905, Register906, Register Controller9 07. Bus interface (Bus I / F) 908, rewritable ROM 909, It mainly has a ROM interface (ROM I / F) 920. ROM909 and The ROM I / F920 may be placed on a separate chip. Of course, the CPU shown in Figure 22 is... This is merely one simplified example of a configuration; actual CPUs have a wide variety of configurations depending on their application. It has the ability. 【0252】 Instructions input to the CPU via the Bus I / F908 are, The data is input to Decoder903, decoded, and then sent to ALU Controller9 02, Interrupt Controller904, Register Cont. The input is sent to roller907 and Timing Controller905. 【0253】 ALU Controller902, Interrupt Controller9 04, Register Controller907, Timing Control The ler905 performs various controls based on the decoded instructions. Specifically, ALU C The controlr902 generates signals to control the operation of the ALU901. Furthermore, the Interrupt Controller 904 intercepts the CPU program execution during Interrupt requests from external input / output devices and peripheral circuits can be identified based on their priority and mask status. Disconnect and process. Register Controller 907 is Register Generate an address for 906, and depending on the CPU state, read Register906 or Write a message. 【0254】 Furthermore, the Timing Controller 905 is ALU901, ALU Con troller902, Instruction Decoder903, Interr upt Controller904, Register Controller907 It generates a signal that controls the timing of the operation. For example, Timing Control The ER905 generates an internal clock signal CLK2 based on the reference clock signal CLK1. It is equipped with an internal clock generation unit that supplies the clock signal CLK2 to the various circuits mentioned above. 【0255】 In the CPU shown in Figure 22, the Register906 is equipped with the memory circuit 11 shown in Figure 1. It is being done. Also, the Register Controller 907 is as shown in Figure 1. A power gate control circuit 12 is provided. In the CPU shown in Figure 22, Regi The ster Controller 907, following instructions from the ALU 901, registers Select the holding operation in ter906. That is, Register906 has In the memory circuit 11, data is retained by sequential circuits 21_1 to 21_n, Whether to retain data at a node electrically connected to one electrode of the quantitative element 32. Select. If data retention by sequential circuits 21_1~21_n is selected, Reg Power voltage is supplied to the memory circuit 11 within ister906. If data retention is selected at the node electrically connected to the electrode, Re The power supply voltage to the memory circuit 11 within gister906 can be stopped. 【0256】 In this way, when the CPU operation is temporarily stopped and the power supply voltage is cut off, It is possible to retain data and reduce power consumption. Specifically For example, when a personal computer user inputs information to an input device such as a keyboard. The CPU can be stopped even while input is stopped, thereby reducing power consumption. It is possible. 【0257】 Although a CPU was used as an example in this explanation, the semiconductor integrated circuit of the present invention is not limited to a CPU. DSP, custom LSI, FPGA (Field Programmable G It can also be applied to LSIs such as ATE Arrays. [Examples] 【0258】 The field-effect mobility of insulated-gate transistors, as actually measured, is not limited to oxide semiconductors. For various reasons, their mobility will be lower than it should be. Factors that reduce mobility include In some cases, defects exist within the semiconductor or at the interface between the semiconductor and the insulating film, but the Levinson model Using this method, we can theoretically derive the field-effect mobility assuming there are no defects inside the semiconductor. I can do it. 【0259】 Let μ0 be the intrinsic mobility of the semiconductor, and μ be the measured field-effect mobility. Assuming that potential barriers (grain boundaries, etc.) exist, 【0260】 【number】 【0261】 This can be expressed as follows: Here, E is the height of the potential barrier, k is the Boltzmann constant, and T This is absolute temperature. Also, assuming that the potential barrier originates from a defect, Levin In the son model, 【0262】 【number】 【0263】 This is expressed as follows: where e is the elementary charge and N is the average defect density per unit area in the channel. ε is the dielectric constant of the semiconductor, n is the number of carriers contained in the channel per unit area, C ox teeth Capacity per unit area, V g is the gate voltage, and t is the channel thickness. Note that the thickness is 30 For semiconductor layers smaller than a nanometer, the channel thickness can be considered the same as the thickness of the semiconductor layer. i. Drain current I in the linear region d teeth, 【0264】 【number】 【0265】 Here, L is the channel length and W is the channel width, and in this case, L=W=10μ m. Also, V d is the drain voltage. Subtract V from both sides of the above equation. g Divide by, and then take the logarithm of both sides. If you take it, 【0266】 【number】 【0267】 Therefore, the right-hand side of equation 8 is V g This is a function of . As can be seen from this formula, the vertical axis is ln(I d / V g ), horizontal axis is 1 / V g From the slope of the straight line on the graph obtained by plotting the measured values ​​as follows: The defect density N can be determined. That is, the I of the transistor d ―V g Based on the characteristics, the defect density can be evaluated. It can be valued. Oxide semiconductors include indium (In), tin (Sn), and zinc (Zn). For a ratio of In:Sn:Zn=1:1:1, the defect density N is 1 × 10⁻¹⁰. 12 / cm 2 degree It is a degree. 【0268】 Based on the defect density and other factors obtained in this way, we can conclude from equations 5 and 6 that μ0 = 120 cm². 2 / V s is derived. The mobility measured in defective In-Sn-Zn oxide is 40 cm². 2 / It is approximately Vs. However, there are no defects in the semiconductor interior or at the interface between the semiconductor and the insulating film. The mobility μ0 of a semiconductor is 120 cm. 2 It can be expected that the result will be / Vs. 【0269】 However, even if there are no defects inside the semiconductor, scattering at the interface between the channel and the gate insulating layer can cause problems. The transport characteristics of the transistor are affected by this. That is, when the distance x from the gate insulating layer interface is... The mobility μ1 in the location is 【0270】 【number】 【0271】 It is expressed as follows: Here, D is the electric field in the gate direction, and B and l are constants. B and l are real This can be determined from the measurement results, and from the above measurement results, B = 4.75 × 10 7 cm / s, l = 10 nm (depth of interface scattering). D increases (i.e., gate electric current) As the pressure increases, the second term of equation 9 increases, and therefore the mobility μ1 decreases. 【0272】 Transistor movement using an ideal oxide semiconductor channel with no defects inside the semiconductor. The results of the calculation of the degree μ2 are shown in Figure 26. Note that the calculation was performed using Synopsys device simulator. Using Sentaurus Device, a bandgear for oxide semiconductors. The cap, electron affinity, relative permittivity, and thickness were set to 2.8 electron volts and 4.7 electron volts, respectively. The values ​​were set to 15 nm and 15 nm. These values ​​were measured for thin films formed by the sputtering method. This is what was obtained. 【0273】 Furthermore, the work functions of the gate layer, source, and drain were set to 5.5 electron volts and 4. The voltages were set to 6 electron volts and 4.6 electron volts. The gate insulating layer thickness was 100 nm. The power factor was set to 4.1. The channel length and channel width were both 10 μm, and the drain voltage was V d The voltage is 0.1V. 【0274】 As shown in Figure 26, with a gate voltage of slightly over 1V, the mobility is 100cm. 2 / Vs or higher peak However, if the gate voltage increases further, interfacial scattering increases and mobility decreases. Furthermore, in order to reduce interfacial scattering, the semiconductor layer surface must be made atomically flat (A A tomic layer flatness is desirable. 【0275】 When a miniature transistor is fabricated using an oxide semiconductor with such mobility, The results of the characteristic calculations are shown in Figures 27 to 29. Note that the cross-section of the transistor used in the calculations is shown. The structure is shown in Figure 30. The transistor shown in Figure 30 has an oxide semiconductor layer with n + It exhibits the following conductivity type. It has semiconductor region 503a and semiconductor region 503c. The resistivity of the conductor region 503c is 2 × 10⁻⁶. -3 Let it be Ωcm. 【0276】 The transistor shown in Figure 30(A) is embedded in the base insulating layer 501 and the base insulating layer 501 Formed on top of an embedded insulator 502 made of aluminum oxide that is formed to be embedded The transistor consists of semiconductor region 503a, semiconductor region 503c, and the area sandwiched between them. It has an intrinsic semiconductor region 503b which forms a Nell formation region and a gate layer 505. The width of 05 is set to 33 nm. 【0277】 Between the gate layer 505 and the semiconductor region 503b, there is a gate insulating layer 504, and also, Side wall insulators 506a and 506b are located on both sides of the gate layer 505, and the gate layer 50 The upper part of 5 has an insulator 507 to prevent short circuits between the gate layer 505 and other wiring. The width of the side wall insulator shall be 5 nm. Also, semiconductor region 503a and semiconductor region 503 It has a source layer 508a and a drain layer 508b in contact with c. The channel width in the sta is set to 40 nm. 【0278】 The transistor shown in Figure 30(B) consists of an underlay insulating layer 501 and aluminum oxide. A semiconductor region 503a, a semiconductor region 503c, and are formed on the embedded insulator 502. The intrinsic semiconductor region 503b sandwiched between them, the 33nm wide gate layer 505 and gate insulation Layer 504 and side wall insulator 506a and side wall insulator 506b and insulator 507 and source layer 50 It is the same as the transistor shown in Figure 30(A) in that it has 8a and drain layer 508b. ru. 【0279】 The difference between the transistor shown in Figure 30(A) and the transistor shown in Figure 30(B) is the side wall. This is the conductivity type of the semiconductor region beneath the insulator 506a and the side wall insulator 506b. Figure 30(A In the transistor shown, the semiconductor under the side wall insulators 506a and 506b The region is n + Semiconductor regions 503a and 503c exhibit the conductivity type shown in Figure In the transistor shown in 30(B), the intrinsic semiconductor region is 503b. That is, Figure 3 In the semiconductor layer shown in 0(B), semiconductor region 503a (semiconductor region 503c) and gate Layer 505 has a region where it does not overlap with Loff. This region is called the offset region. The width Loff is called the offset length. As is clear from the diagram, the offset length is the side wall It is the same width as the insulator 506a (side wall insulator 506b). 【0280】 Other parameters used in the calculations are as described above. The calculations were performed using a Synopsys device. The chair simulation software, Sentaurus Device, was used. Figure 27 shows The drain current (I) of the transistor with the structure shown in Figure 30(A) d (Solid line) and movement Gate voltage (V) at degree (μ, dotted line) g (The potential difference between the gate and source) is shown as a dependence of the drain. current I d The drain voltage (potential difference between drain and source) is set to +1V, and the mobility μ is the drain. This calculation assumes an input voltage of +0.1V. 【0281】 Figure 27(A) shows the gate insulating layer thickness as 15 nm, and Figure 27(B) shows 10 The values ​​are in nm, and Figure 27(C) is set to 5 nm. The gate insulating layer is thin. The drain current I in the off state is particularly important. d (Off-current) decreases significantly. Meanwhile, movement Peak value of degree μ and drain current I in the ON state d There is no significant change in the (on-current). It was shown that the drain current exceeds 10 μA at a gate voltage of around 1 V. 【0282】 Figure 28 shows a transistor with the structure shown in Figure 30(B), where the offset length Loff is 5 The drain current I of nm d Gate voltage V (solid line) and mobility μ (dotted line) g Depends It shows existence. Drain current I d The drain voltage is set to +1V, and the mobility μ is the drain voltage. This calculation was performed assuming a voltage of +0.1V. Figure 28(A) shows a gate insulating layer thickness of 15nm. Figure 28(B) shows the result at 10 nm, and Figure 28(C) shows the result at 5 nm. That is what happened. 【0283】 Furthermore, Figure 29 shows a transistor with the structure shown in Figure 30(B), with an offset length of Lof The drain current I of f set to 15 nm d (Solid line) and the gate voltage of mobility μ (dotted line) It exhibits pressure dependence. Drain current I d The drain voltage is set to +1V, and the mobility μ is the drain voltage. This calculation was performed assuming a voltage of +0.1V. Figure 29(A) shows the gate insulation layer thickness as 15 The values ​​are in nm, Figure 29(B) is 10 nm, and Figure 29(C) is 5 nm. This is represented as m. 【0284】 In both cases, the thinner the gate insulating layer, the more significantly the off-current decreases, while the mobility μ is There are no noticeable changes in the step value or on-current. 【0285】 Note that the peak of mobility μ is at 80 cm in Figure 27. 2 It is approximately / Vs, but in Figure 28 it is 6 0cm 2 Approximately / Vs, 40cm in Figure 29 2 / Vs and an increase in offset length Loff The more you do it, the lower it becomes. The off-current also shows a similar trend. On the other hand, the on-current also decreases with the offset length. It decreases with increasing Loff, but this decrease is much more gradual than the decrease in off-current. Furthermore, it was shown that in all cases, the drain current exceeds 10 μA at a gate voltage of around 1 V. It was done. 【0286】 A transistor whose channel formation region is an oxide semiconductor mainly composed of In, Sn, and Zn. This refers to the process of heating the substrate to form the oxide semiconductor film, or the oxide semiconductor film Good properties can be obtained by heat treatment after forming the material. Note that the main component is combined with This refers to elements present in a composition ratio of 5 atomic percent or more. 【0287】 After depositing an oxide semiconductor film mainly composed of In, Sn, and Zn, the substrate is intentionally heated. This makes it possible to improve the field-effect mobility of the transistor. This allows the threshold voltage of the device to be shifted positively, enabling it to be normally turned off. 【0288】 For example, Figures 31(A) to 31(C) show a channel with In, Sn, and Zn as the main components. An oxide semiconductor film with a length L of 3 μm and a channel width W of 10 μm, and a channel with a thickness of 100 nm. This describes the characteristics of a transistor using an insulating layer. d The voltage was set to 10V. 【0289】 Figure 31(A) shows the process of sputtering In, Sn, and Zn onto a substrate without intentionally heating it. This is the transistor characteristic when an oxide semiconductor film is formed using the given method. At this time, the field effect transfer... The range of motion was 18.8 cm. 2 / Vsec is obtained. On the other hand, the substrate is intentionally heated and In, Forming an oxide semiconductor film mainly composed of Sn and Zn improves the field-effect mobility. This becomes possible. Figure 31(B) shows the substrate heated to 200°C and composed mainly of In, Sn, and Zn. This shows the transistor characteristics when an oxide semiconductor film is formed, with a field-effect mobility of 32. 2cm 2 / Vsec is obtained. 【0290】 The field-effect mobility is determined by the heat generated after forming an oxide semiconductor film mainly composed of In, Sn, and Zn. Further processing can enhance the results. Figure 31(C) shows In, Sn, Z An oxide semiconductor film mainly composed of n was deposited by sputtering at 200°C, and then heated at 650°C. The transistor characteristics after processing are shown. At this time, the field-effect mobility is 34.5 cm⁻¹. 2 / Vsec has been obtained. 【0291】 By intentionally heating the substrate, moisture during sputtering deposition is absorbed into the oxide semiconductor film. It is expected to reduce the amount of material that gets trapped inside. Also, by performing heat treatment after film formation, Hydrogen, hydroxyl groups, or water can be released and removed from oxide semiconductor films, as described above. This can improve the field effect mobility. Such improvement in field effect mobility is possible. In addition to removing impurities through hydration and dehydrogenation, the increased density shortens the interatomic distance. It is also presumed that crystallization occurs by removing impurities from oxide semiconductors to increase their purity. This can be achieved. In this way, the highly purified non-single-crystal oxide semiconductor is, ideally, 1 00cm 2 It is estimated that it will also be possible to achieve field effect mobility exceeding / Vsec. . 【0292】 Oxygen ions are implanted into an oxide semiconductor mainly composed of In, Sn, and Zn, and then heat-treated. By releasing hydrogen, hydroxyl groups, or water contained in the oxide semiconductor, simultaneously with the heat treatment or The oxide semiconductor may be crystallized by subsequent heat treatment. By performing a crystallization process, non-single-crystal oxide semiconductors with good crystallinity can be obtained. 【0293】 The effect of intentionally heating the substrate to form a film and / or heat-treating it after film formation is that This not only improves field effect mobility but also contributes to the normal-off operation of transistors. It is formed without intentionally heating the substrate, and is an oxide mainly composed of In, Sn, and Zn. In a transistor using a semiconductor film as the channel formation region, the threshold voltage is shifted to the negative. There is a tendency for this to happen. However, using an oxide semiconductor film formed by intentionally heating the substrate In this case, the negative shift of the threshold voltage is eliminated. In other words, the threshold voltage is The 'njista' is moving towards becoming normally off, and this trend is shown in Figure 31(A) and Figure 31( This can also be confirmed by the comparison in B). 【0294】 Furthermore, the threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. This is possible, and by setting the composition ratio to In:Sn:Zn=2:1:3, the transistor Normalization can be expected. Also, the target composition ratio is In:Sn:Z By setting n=2:1:3, a highly crystalline oxide semiconductor film can be obtained. 【0295】 The intentional substrate heating temperature or heat treatment temperature should be 150°C or higher, preferably 200°C or higher. More preferably, the temperature is 400°C or higher, and by forming the film or heat treating at a higher temperature, the translucency is achieved. This makes it possible to disable the normal operation of the ZISTA. 【0296】 Furthermore, by intentionally heating the substrate during film deposition and / or performing heat treatment after film deposition, gate bars can be formed. It can increase stability against stress. For example, 2 MV / cm, 150 Under the conditions of application at °C for 1 hour, the drift should be less than ±1.5V, preferably 1.0V. You can obtain a value less than V. 【0297】 In fact, sample 1, which has not undergone heat treatment after oxide semiconductor film deposition, and sample 1, which has undergone heat treatment at 650°C... A BT test was performed on the transistor of sample 2, which had undergone the same procedure. 【0298】 First, set the substrate temperature to 25°C, V ds Let the voltage be 10V, and the voltage of the transistor g -I d Measurement of characteristics The determination was made. ds This indicates the drain voltage (the potential difference between the drain and the source). Next, The substrate temperature was set to 150 °C, and V ds was set to 0.1 V. Next, V was applied with 20 V so that the electric field strength applied to the gate insulating layer became 2 MV / cm, and it was held for 1 hour as it was. Next g V was set to 0 V. Next, the substrate temperature was set to 25 °C, V g was set to 10 V, and the V ds -I characteristics of the transistor g -I d measurement was performed. This is called the plus BT test. 【0299】 Similarly, first, the substrate temperature was set to 25 °C, V ds was set to 10 V, and the V g -I d characteristics of the transistor were measured. Next, the substrate temperature was set to 150 °C, V ds was set to 0.1 V. Next V g was applied with -20 V so that the electric field strength applied to the gate insulating layer became -2 MV / cm and it was held for 1 hour as it was. Next, V g was set to 0 V. Next, the substrate temperature was set to 25 °C, V ds was set to 10 V, and the V g -I d measurement of the transistor was performed. This is called the minus BT test. call. 【0300】 The results of the plus BT test of sample 1 are shown in Fig. 32(A), and the results of the minus BT test are shown in Fig. 32( B). Also, the results of the plus BT test of sample 2 are shown in Fig. 33(A), and the results of the minus BT test are shown in Fig. 33(B). 【0301】 The variations in the threshold voltage due to the plus BT test and the minus BT test of sample 1 were 1.80 V and -0.42 V, respectively . Also, for the plus BT test and the minus BT test of sample 2 The variations in the threshold voltage due to the BT test were 0.79 V and 0.76 V, respectively. For both Sample 1 and Sample 2, the variation in the threshold voltage before and after the BT test was small, indicating high reliability. 【0302】 The heat treatment can be performed in an oxygen atmosphere, or first in a nitrogen or inert gas atmosphere, or under reduced pressure and then in an atmosphere containing oxygen. By first performing dehydration and dehydrogenation and then adding oxygen to the oxide semiconductor, the effect of the heat treatment can be enhanced further. Also, to add oxygen later, a method of accelerating oxygen ions by an electric field and injecting them into the oxide semiconductor film can be applied. Defects due to oxygen deficiency are likely to occur in the oxide semiconductor and at the interface between the oxide semiconductor and the film in contact therewith. However, by making the oxide semiconductor contain an excessive amount of oxygen by such heat treatment, it becomes possible to compensate for the constantly generated oxygen deficiency with the excessive oxygen. The excessive oxygen mainly exists between the lattices, and the oxygen concentration can be made to be 1×10 / cm 【0303】 Defects due to oxygen deficiency are likely to occur in the oxide semiconductor and at the interface between the oxide semiconductor and the film in contact therewith. However, by making the oxide semiconductor contain an excessive amount of oxygen by such heat treatment, it becomes possible to compensate for the constantly generated oxygen deficiency with the excessive oxygen. The excessive oxygen mainly exists between the lattices, and the oxygen concentration can be made to be 1×10 / cm or more and 2×1 16 / cm 3 or less. By doing so, it can be made to be contained in the oxide semiconductor without giving strain or the like to the crystal. 0 20 / cm 3 or less. By doing so, it can be made to be contained in the oxide semiconductor without giving strain or the like to the crystal. This can be achieved. 【0304】 Also, by making at least a part of the oxide semiconductor contain crystals by heat treatment, a more stable oxide semiconductor film can be obtained. For example, an oxide semiconductor film formed by sputtering without intentionally heating the substrate using a target with a composition ratio of In:Sn:Zn = 1:1:1 has a halo pattern in X-ray diffraction (XRD: X-Ray Diffraction). 1: 1:1 has a halo pattern in X-ray diffraction (XRD: X-Ray Diffraction). Tan is observed. This deposited oxide semiconductor film is then heat-treated to crystallize it. It is possible to perform heat treatment at any temperature, but for example, by performing heat treatment at 650°C, X Clear diffraction peaks can be observed through linear diffraction. 【0305】 In fact, XRD analysis was performed on the In-Sn-Zn-O film. The XRD analysis was conducted using a Bruke XRD scanner. Using the AXS D8 ADVANCE X-ray diffractometer, the Out-of-Plane method was used. It was measured using [this method]. 【0306】 Sample A and Sample B were prepared as samples for XRD analysis. Below are the results for Sample A and The method for preparing sample B will be explained. 【0307】 An In-Sn-Zn-O film with a thickness of 100 nm is deposited on a dehydrogenated quartz substrate. Ta. 【0308】 The In-Sn-Zn-O film was formed using a sputtering apparatus in an oxygen atmosphere with a power of 100W. The film was deposited as (DC). The target was In:Sn:Zn=1:1:1 [atomic ratio] An In-Sn-Zn-O target was used. The substrate heating temperature during film deposition was 200°C. The sample prepared in this manner was designated as Sample A. 【0309】 Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment involves first heating in a nitrogen atmosphere for 1 hour, and then, without lowering the temperature, heating in an oxygen atmosphere. The sample was then subjected to a further heat treatment for one hour. The sample prepared in this manner was designated as Sample B. 【0310】 Figure 34 shows the XRD spectra of sample A and sample B. In sample A, crystalline pea is observed. Although no 'k' was observed, in sample B, 2θ was near 35deg and 37deg~38d For example, peaks originating from crystals were observed. 【0311】 Thus, oxide semiconductors mainly composed of In, Sn, and Zn can be intentionally formed on the substrate during film deposition. The characteristics of transistors can be improved by heating and / or heat treatment after film formation. It is possible. 【0312】 This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. It has the effect of preventing them from being included or removing them from the film. In other words, oxides By removing hydrogen, which acts as a donor impurity in semiconductors, higher purity can be achieved. Therefore, it is possible to normally turn off the transistor, and the oxide semiconductor can be made highly pure. By doing so, the off-current can be reduced to 1 aA / μm or less. Here, the above off-current value The unit indicates the current value per 1 μm of channel width. 【0313】 Figure 35 shows the relationship between the transistor's off-current and the reciprocal of the substrate temperature (absolute temperature) during measurement. Here, for simplicity, we will use the reciprocal of the substrate temperature at the time of measurement multiplied by 1000 (1000 The horizontal axis is / T). Specifically, as shown in Figure 35, when the substrate temperature is 125°C... It contains 1 aA / μm (1 × 10⁻¹⁰ -18 (A / μm) or less, 100 zA / μm at 85℃ (1×10 -19 If the A / μm level is less than or equal to 1 zA / μm (1 × 10⁻¹⁰) at room temperature (27°C), then 1 zA / μm (1 × 10⁻¹⁰) is the minimum level. - 21 It can be reduced to less than A / μm. Preferably, it is 0.1 aA / μm at 125°C. m(1×10 -19 (A / μm) or less, at 85°C, 10 zA / μm (1 × 10⁻⁶ A / μm). -20 (A / μm) or less, at room temperature 0.1 zA / μm (1 × 10⁻¹⁰ -22 A / μm) or less It is possible. 【0314】 However, to prevent hydrogen and moisture from entering the film during the deposition of oxide semiconductor films, outside the deposition room... This aims to sufficiently suppress leakage from the area and degassing from the inner wall of the deposition chamber, thereby achieving high purity of sputtering gas. It is preferable that the sputtering gas has a dew point of -70°C so that no moisture is contained in the film. It is preferable to use the following gases. In addition, hydrogen and water are present in the target itself. It is preferable to use a highly purified target that is free of impurities. Oxide semiconductors, mainly composed of In, Sn, and Zn, can have moisture removed from the film through heat treatment. However, compared to oxide semiconductors mainly composed of In, Ga, and Zn, the moisture release temperature Because of the high moisture content, it is preferable to form a film that does not contain moisture from the beginning. 【0315】 Furthermore, a transient was observed using sample B, which underwent heat treatment at 650°C after oxide semiconductor film deposition. In this study, the relationship between substrate temperature and electrical characteristics was evaluated. 【0316】 The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lo v is 0 μm and dW is 0 μm. Note that V ds The voltage was set to 10V. The board temperature was -4 The experiment was conducted at 0°C, -25°C, 25°C, 75°C, 125°C, and 150°C. Here, the transition In a st, the overlapping width between the gate layer and the pair of electrodes is called Lov, and in an oxide semiconductor film... The overhang of the opposing pair of electrodes is called dW. 【0317】 Figure 36 shows I d (Solid line) and field effect mobility (dotted line) V g It shows dependency. Also, the figure Figure 37(A) shows the relationship between substrate temperature and threshold voltage, and Figure 37(B) shows the relationship between substrate temperature and field effect transfer. This shows the relationship in degrees. 【0318】 Figure 37(A) shows that the threshold voltage decreases as the substrate temperature increases. The temperature range was -40°C to 150°C, with a voltage of 1.09V to -0.23V. 【0319】 Furthermore, Figure 37(B) shows that the field-effect mobility decreases as the substrate temperature increases. The temperature range is -40°C to 150°C and the length is 36 cm. 2 / Vs~32cm 2 / Vs Therefore, it can be seen that the variation in electrical characteristics is small within the temperature range mentioned above. 【0320】 The above-mentioned oxide semiconductor, mainly composed of In, Sn, and Zn, is used as the channel formation region. According to the transistor, the off-current is kept below 1 aA / μm while the field-effect mobility is 30 cm 2 / Vsec or greater, preferably 40cm 2 / Vsec or more, more preferably 60cm 2 It can be set to / Vsec or higher, and the on-current value required by the LSI can be met. This is a FET with L / W = 33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V. At this time, an on-current of 12 μA or more can be supplied. Also, the operation of the transistor is required Sufficient electrical characteristics can be ensured even in a wide temperature range. If transistors formed from oxide semiconductors are mixed into integrated circuits made from Si semiconductors, Even when implemented, it is possible to realize integrated circuits with new functions without sacrificing operating speed. can. [Examples] 【0321】 In this embodiment, an example of a transistor using an In-Sn-Zn-O film as the oxide semiconductor film is presented. This will be explained using Figure 38. 【0322】 Figure 38 shows a coplanar top-gate, top-contact transistor. These are top and cross-sectional views. Figure 38(A) shows a top view of the transistor. Also, Figure 38 (B) shows the cross-section AB corresponding to the dashed line AB in Figure 38(A). 【0323】 The transistor shown in Figure 38(B) consists of a substrate 600 and an insulating substrate provided on the substrate 600. The edge film 602, the protective insulating film 604 provided around the base insulating film 602, and the base insulating film 6 02 and the high-resistance region 606a and low-resistance region 606 provided on the protective insulating film 604 an oxide semiconductor film 606 having b, and a gate insulating layer provided on the oxide semiconductor film 606. 608 and a gate that is superimposed on the oxide semiconductor film 606 via the gate insulating layer 608 A gate layer 610, a side wall insulating film 612 provided in contact with the side surface of the gate layer 610, and at least A pair of electrodes 614 are provided in contact with the low-resistance region 606b, and at least an oxide semiconductor An interlayer insulating film 616 is provided covering the film 606, the gate layer 610, and the pair of electrodes 614. And, through an opening provided in the interlayer insulating film 616, one of at least one pair of electrodes 614 It has wiring 618 connected to it. 【0324】 Although not shown in the diagram, a protective film is provided covering the interlayer insulating film 616 and the wiring 618. It is acceptable to have it. By providing the protective film, the surface conduction caused by the interlayer insulating film 616 This reduces the minute leakage current that occurs, thereby reducing the transistor's off-current. It is possible. [Examples] 【0325】 In this example, a different In-Sn-Zn-O film was used as the oxide semiconductor film. Here is another example of a 'njista'. 【0326】 Figure 39 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this embodiment. Figure 39(A) is a top view of the transistor. Figure 39(B) is a single point view of Figure 39(A). This is a cross-sectional view corresponding to the dashed line AB. 【0327】 The transistor shown in Figure 39(B) consists of a substrate 700 and an insulating substrate provided on the substrate 700. A border film 702, an oxide semiconductor film 706 provided on the underlying insulating film 702, and an oxide semiconductor A pair of electrodes 714 in contact with the film 706, and on the oxide semiconductor film 706 and the pair of electrodes 714 A gate insulating layer 708 is provided therein, and an oxide semiconductor film 706 is connected via the gate insulating layer 708. The gate layer 710 is provided superimposed on the gate insulating layer 708 and the gate layer 710. An interlayer insulating film 716 is provided, and a pair of openings are provided in the interlayer insulating film 716. A wiring 718 that connects to the electrode 714, and an interlayer insulating film 716 and wiring 718 are provided covering each other. It has a protective film 720 applied to it. 【0328】 As the substrate 700, a glass substrate is used, and as the underlay insulating film 702, a silicon oxide film is used. As the semiconductor film 706, an In-Sn-Zn-O film is used, and as the pair of electrodes 714, tungsten As the stainless steel film, the gate insulating layer 708 is a silicon oxide film, and as the gate layer 710 is a silicon oxide film. The laminated structure of the tantalum oxide film and the tungsten film is constructed using silica oxide nitride as the interlayer insulating film 716. The laminated structure of the condenser film and the polyimide film is used for the wiring 718, which consists of a titanium film, an aluminum film, The titanium film is formed in this order in a laminated structure, and the protective film 720 is a polyimide film, They used them. 【0329】 In the transistor with the structure shown in Figure 39(A), the gate layer 710 and a pair of electrodes are present. The width of the overlap with 714 is called Lov. Similarly, a pair of electrons on the oxide semiconductor film 706 The overhang of the Extreme 714 is called dW. [Explanation of Symbols] 【0330】 10 Arithmetic circuit 11 Memory circuit 12 Power gate control circuit 20 Power Gate Transistors 21_1~21_n Sequential circuit 21_x sequential circuit 22_1~22_n Combinatorial Circuits 30 flip-flops 31 transistors 32 Capacitive elements 50 circuit boards 51 Base layer 52 Gate Layers 53 Gate Insulation Layer 54 Oxide semiconductor layer 55a Source layer 55b Drain layer 56 Protective insulating layer 57 Planarized insulating layer 58a conductive layer 58b Conductive layer 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108 Gate Insulation Layer 110 Gate Layers 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel formation region 118 Sidewall insulation layer 120a High concentration impurity region 120b High concentration impurity region 122 Metal layer 124a Metal compound area 124b Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source layer 130b Drain layer 132 Insulating layer 134 Conductive layer 136a Electrode layer 136b Electrode layer 136d Gate Layer 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source layer 142b Drain layer 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode layer 150b electrode layer 150d electrode layer 150e electrode layer 152 Insulating layer 154a Electrode layer 154b Electrode layer 154d electrode layer 160 transistors 162a Oxide conductive layer 162b Oxide conductive layer 164 transistors 210a NAND gate 210b NAND gate 210c NAND gate 210d NAND gate 210e NAND gate 210f NAND gate 211a AND gate 211b AND gate 212a switch 212b switch 212c switch 212d switch 400 Insulating layer 437 Insulating layer 450a Crystalline oxide semiconductor layer 450b Crystalline oxide semiconductor layer 453 Oxide semiconductor layer 501 Underlayment Insulation Layer 502 Embedded Insulation 503a Semiconductor Domain 503b Semiconductor area 503c Semiconductor Domain 504 Gate Insulation Layer 505 Gate Layer 506a Sidewall insulation 506b Sidewall insulation 507 Insulators 508a Source layer 508b Drain layer 600 circuit boards 602 Underlying insulating film 604 Protective insulating film 606 Oxide Semiconductor Film 606a High resistance area 606b Low resistance area 608 Gate Insulation Layer 610 Gate Layer 612 Sidewall insulating film 614 Electrode 616 Interlayer insulating film 618 Interlayer insulating film 700 circuit boards 702 Underlying insulating film 706 Oxide Semiconductor Film 708 Gate Insulation Layer 710 Gate Layer 714 Electrode 716 Interlayer insulating film 718 Wiring 720 Protective film 801 Measurement System 811 Transistors 812 transistors 813 Capacitive element 814 Transistors 815 Transistors 900 circuit boards 901 ALU 902 ALU Controller 903 Instruction Decoder 904 Interrupt Controller 905 Timing Controller 906 Register 907 Register Controller 908 Bus I / F 909 ROM 920 ROM I / F< / cpu>

Claims

[Claim 1] The device comprises a first transistor having silicon in its channel formation region, and a second transistor having oxide semiconductor in its channel formation region. A semiconductor device in which one of the source or drain of the first transistor is always in electrical contact with the one of the source or drain of the second transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating film having a region positioned above the first conductive film and a region facing the side surface of the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate electrode of the second transistor, A third conductive film having a region positioned above the first insulating film, A second insulating film having a region positioned above the second conductive film and a region positioned above the third conductive film, A semiconductor film having a region positioned above the second insulating film and having a channel formation region for the second transistor, A third insulating film having a region positioned above the semiconductor film, A fourth conductive film having a region positioned above the third insulating film, A fifth conductive film having a region positioned above the third insulating film and being in constant electrical contact with the third conductive film, The second conductive film has a region in contact with the upper surface of the first insulating film, The third conductive film has a region in contact with the upper surface of the first insulating film, The fourth conductive film is always in electrical contact with either the source or the drain of the first transistor, and is always in electrical contact with either the source or the drain of the second transistor. When the third conductive film is electrically connected to the fourth conductive film at least through the channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film. Semiconductor equipment. [Claim 2] The device comprises a first transistor having silicon in its channel formation region, and a second transistor having oxide semiconductor in its channel formation region. A semiconductor device in which one of the source or drain of the first transistor is always in electrical contact with the one of the source or drain of the second transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating film having a region positioned above the first conductive film and a region facing the side surface of the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate electrode of the second transistor, A third conductive film having a region positioned above the first insulating film, A second insulating film having a region positioned above the second conductive film and a region positioned above the third conductive film, A semiconductor film having a region positioned above the second insulating film and having a channel formation region for the second transistor, A third insulating film having a region positioned above the semiconductor film, A fourth conductive film having a region positioned above the third insulating film, A fifth conductive film having a region positioned above the third insulating film and being in constant electrical contact with the third conductive film, The third conductive film has an overlap with the fifth conductive film, The second conductive film has a region in contact with the upper surface of the first insulating film, The third conductive film has a region in contact with the upper surface of the first insulating film, The fourth conductive film is always in electrical contact with either the source or the drain of the first transistor, and is always in electrical contact with either the source or the drain of the second transistor. When the third conductive film is electrically connected to the fourth conductive film at least through the channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film. Semiconductor equipment. [Claim 3] The device comprises a first transistor having silicon in its channel formation region, and a second transistor having oxide semiconductor in its channel formation region. A semiconductor device in which one of the source or drain of the first transistor is always in electrical contact with the one of the source or drain of the second transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating film having a region positioned above the first conductive film and a region facing the side surface of the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate electrode of the second transistor, A third conductive film having a region positioned above the first insulating film, A second insulating film having a region positioned above the second conductive film and a region positioned above the third conductive film, A semiconductor film having a region positioned above the second insulating film and having a channel formation region for the second transistor, A third insulating film having a region positioned above the semiconductor film, A fourth conductive film having a region positioned above the third insulating film, A fifth conductive film having a region positioned above the third insulating film and being in constant electrical contact with the third conductive film, The third conductive film has an overlap with the fifth conductive film, The second conductive film has a region in contact with the upper surface of the first insulating film, The third conductive film has a region in contact with the upper surface of the first insulating film, The fourth conductive film has a region in contact with the upper surface of the third insulating film, The fifth conductive film has a region in contact with the upper surface of the third insulating film, The fourth conductive film is always in electrical contact with either the source or the drain of the first transistor, and is always in electrical contact with either the source or the drain of the second transistor. When the third conductive film is electrically connected to the fourth conductive film at least through the channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film. Semiconductor equipment. [Claim 4] The device comprises a first transistor having silicon in its channel formation region, and a second transistor having oxide semiconductor in its channel formation region. A semiconductor device in which one of the source or drain of the first transistor is always in electrical contact with the one of the source or drain of the second transistor, A first conductive film having a region positioned above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A first insulating film having a region positioned above the first conductive film and a region facing the side surface of the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate electrode of the second transistor, A third conductive film having a region positioned above the first insulating film, A second insulating film having a region positioned above the second conductive film and a region positioned above the third conductive film, A semiconductor film having a region positioned above the second insulating film and having a channel formation region for the second transistor, A third insulating film having a region positioned above the semiconductor film, A fourth conductive film having a region positioned above the third insulating film, A fifth conductive film having a region positioned above the third insulating film and being in constant electrical contact with the third conductive film, The second conductive film has a region in contact with the upper surface of the first insulating film, The third conductive film has a region in contact with the upper surface of the first insulating film, The fourth conductive film has a region in contact with the upper surface of the third insulating film, The fifth conductive film has a region in contact with the upper surface of the third insulating film, The fourth conductive film is always in electrical contact with either the source or the drain of the first transistor, and is always in electrical contact with either the source or the drain of the second transistor. When the third conductive film is electrically connected to the fourth conductive film at least through the channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film. Semiconductor equipment. [Claim 5] In any one of claims 1 to 4, The channel formation region of the first transistor is located on a silicon semiconductor film on an insulating surface. Semiconductor equipment.

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