Display device and driving method thereof

Abstract

To solve various technical problems in a display panel.SOLUTION: An embodiment provides a display device including a display panel in which a plurality of pixels are disposed, a data driver configured to provide a data voltage to the plurality of pixels through a plurality of data lines, and a driving circuit connected between the data driver and the plurality of data lines and configured to: A multiplexer including a plurality of switching elements controlled by a plurality of MUX control signals, wherein each of the plurality of pixels includes a first sub-pixel displaying a first image and a second sub-pixel displaying a second image different from the first image and displaying the same color as the first sub-pixel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device and a driving method thereof. [Background technology]

[0002] With the development of the information society, various types of display devices have been developed, including liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs).

[0003] General display devices do not have a limited viewing angle. However, for reasons of privacy and information protection, there has been a recent demand for limiting the viewing angle of display devices. For example, in the case of a display device used as an information medium inside a vehicle, it is necessary to provide high-quality images to passengers in the front seat, but to limit the viewing angle for the driver for driving safety reasons. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a display device capable of displaying independent images in a plurality of regions on a display panel, and a driving method thereof.

[0005] The embodiments provide a display device capable of displaying privacy images and sharing images in multiple regions on a display panel, and a driving method thereof.

[0006] The embodiment provides a display device and a driving method thereof in which a plurality of sub-pixels are arranged in one pixel region and controlled so that each sub-pixel displays an independent image.

[0007] The embodiments provide a display device including a data driver and a multiplexer that outputs either a privacy image or a share image to a sub-pixel in response to a MUX control signal, and a driving method thereof.

[0008] The embodiments provide a display device and a driving method thereof that effectively control the viewing angle of a displayed image. [Means for solving the problem]

[0009] A display device according to one embodiment may include a display panel on which a plurality of pixels are arranged, a data driver that provides data voltages to the plurality of pixels via a plurality of data lines, and a multiplexer that is connected between the data driver and the plurality of data lines and is composed of a plurality of switching elements controlled by a plurality of MUX control signals.

[0010] Each of the plurality of pixels may include a first sub-pixel that displays a first image, and a second sub-pixel that displays the same color as the first sub-pixel and displays a second image that is different from the first image.

[0011] The data driver may include an output buffer that outputs the data voltage to an output channel, and the multiplexer may include a first switching element that is turned on by a first MUX control signal to connect the output channel to the first sub-pixel, and a second switching element that is turned on by a second MUX control signal to connect the output channel to the second sub-pixel.

[0012] The output buffer may output a first data voltage corresponding to the first image in synchronization with the first MUX control signal while the pixel is driven in a first mode, and may output a second data voltage corresponding to the second image in synchronization with the second MUX control signal while the pixel is driven in a second mode.

[0013] The output buffer may output a dummy data voltage in synchronization with the second MUX control signal while the pixel is driven in the first mode, and may output the dummy data voltage in synchronization with the first MUX control signal while the pixel is driven in the second mode.

[0014] The data driver may include a first output buffer configured to output a first data voltage corresponding to the first image to a first output channel, and a second output buffer configured to output a second data voltage corresponding to the second image to a second output channel, wherein the first output channel is connected to the first sub-pixel, and the second output channel is connected to the second sub-pixel.

[0015] The first output buffer may output a first data voltage corresponding to the first image to the first sub-pixel while the pixel is driven in a first mode, and the second output buffer may output a second data voltage corresponding to the second image to the second sub-pixel while the pixel is driven in a second mode.

[0016] The first output buffer may output a dummy data voltage to the first sub-pixel while the pixel is driven in the first mode, and may output the dummy data voltage to the second sub-pixel while the pixel is driven in the second mode.

[0017] The multiplexer may include a first switching element that is turned on by a first MUX control signal to connect the first output channel to the first sub-pixel, and a second switching element that is turned on by the first MUX control signal to connect the second output channel to the second sub-pixel.

[0018] The display panel may include a first unit pixel and a second unit pixel, each of which includes two or more pixels.

[0019] The multiplexer may include a first switching element that is turned on by a first MUX control signal to connect the first output channel to the first sub-pixel of the first unit pixel, a second switching element that is turned on by the first MUX control signal to connect the second output channel to the second sub-pixel of the first unit pixel, a third switching element that is turned on by a second MUX control signal to connect the first output channel to the second sub-pixel of the second unit pixel, and a fourth switching element that is turned on by the second MUX control signal to connect the second output channel to the second sub-pixel of the second unit pixel.

[0020] The display panel may include a first region in which the first image is displayed through the first sub-pixels of the plurality of pixels, and a second region in which the second image is displayed through the second sub-pixels of the plurality of pixels, and the first region and the second region may be variable while the display panel is being driven.

[0021] The second sub-pixel may output a dummy image in the first region, and the first sub-pixel may output the dummy image in the second region.

[0022] The first sub-pixel and the second sub-pixel may have the same pixel structure and may have a mirrored shape along the pixel column direction.

[0023] The display device may further include a lens member disposed on the display panel and including a plurality of lenses, wherein the lens member includes a first lens disposed on a first light-emitting region of the first sub-pixel and a second lens disposed on a second light-emitting region of the second sub-pixel and having a shape different from that of the first lens.

[0024] The first lens may control and emit light emitted from the first light-emitting region at a first viewing angle, and the second lens may control and emit light emitted from the second light-emitting region at a second viewing angle wider than the first viewing angle.

[0025] A driving method of a display device according to one embodiment may include the steps of: the data driver outputting a first data voltage corresponding to the first image to the first sub-pixel; and the data driver outputting a second data voltage corresponding to the second image to the second sub-pixel.

[0026] The step of outputting the first data voltage may include the steps of: the multiplexer connecting a first output channel to the first sub-pixel in response to a first MUX control signal during a first period of one horizontal period; the data driver outputting the first data voltage in synchronization with the first MUX control signal during the first period; the multiplexer connecting the first output channel to the second sub-pixel in response to a second MUX control signal during a second period of the one horizontal period; and the data driver outputting a dummy data voltage in synchronization with the second MUX control signal during the second period.

[0027] The step of outputting the second data voltage may include the steps of: the multiplexer connecting a first output channel to the first sub-pixel in response to a first MUX control signal during a first period of one horizontal period; and the data driver outputting the dummy data voltage in synchronization with the first MUX control signal during the first period; and the multiplexer connecting the first output channel to the second sub-pixel in response to a second MUX control signal during a second period of the one horizontal period; and the data driver outputting the second data voltage in synchronization with the second MUX control signal during the second period.

[0028] The step of outputting the first data voltage may include the steps of: the multiplexer connecting a first output channel to the first sub-pixel of the first unit pixel in response to a first MUX control signal during a first period of one horizontal period; and the data driver outputting the first data voltage to the first output channel in synchronization with the first MUX control signal during the first period; and the step of outputting the second data voltage may include the steps of: the multiplexer connecting the second output channel to the second sub-pixel of the first unit pixel in response to the first MUX control signal during the first period; and the data driver outputting the second data voltage to the second output channel in synchronization with the first MUX control signal during the first period.

[0029] The step of outputting the first data voltage may include the steps of: the multiplexer connecting a first output channel to the first sub-pixel of the second unit pixel in response to a second MUX control signal during a second period of the one horizontal period; and the data driver outputting the first data voltage to the first output channel in synchronization with the second MUX control signal during the second period; and the step of outputting the second data voltage may include the steps of: the multiplexer connecting the second output channel to the second sub-pixel of the second unit pixel in response to the second MUX control signal during the second period; and the data driver outputting the second data voltage to the second output channel in synchronization with the second MUX control signal during the second period.

[0030] The step of outputting the first data voltage may include the data driver outputting the first data voltage to the first sub-pixel through a first output channel during a first horizontal period, and the step of outputting the second data voltage may include the data driver outputting the second data voltage to the second sub-pixel through a second output channel during the first horizontal period. [Effects of the Invention]

[0031] The display device and the driving method thereof according to the embodiment can freely and easily change the size and shape of the area in which the privacy image and the share of image are displayed.

[0032] The display device and the driving method thereof according to the embodiment can alleviate the problems of output delay and image quality degradation caused by image switching by allocating the output buffer of the data driver to either the privacy image or the share image.

[0033] The display device and the driving method thereof according to the embodiment may efficiently implement a privacy mode and a share mode in various usage environments. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a block diagram showing a configuration of a display device according to an embodiment. [Figure 2] 1A and 1B are diagrams illustrating a method for driving a display device according to an embodiment. [Figure 3] FIG. 2 is a diagram showing a configuration of a pixel according to an embodiment. [Figure 4] FIG. 2 is a block diagram illustrating a configuration of a data driver according to an embodiment. [Figure 5] FIG. 3 is a diagram illustrating a connection relationship between pixels and a data driver according to the first embodiment. [Figure 6] 6 is a waveform diagram of control and drive signals applied to the display device of FIG. 5. [Figure 7] FIG. 10 is a diagram illustrating a connection relationship between pixels and a data driver according to a second embodiment. [Figure 8] 8 is a waveform diagram of control and drive signals applied to the display device of FIG. 7. [Figure 9] FIG. 11 is a diagram illustrating a connection relationship between pixels and a data driver according to a third embodiment. [Figure 10] 10 is a waveform diagram of control and drive signals applied to the display device of FIG. 9. [Figure 11] FIG. 2 is a circuit diagram of a pixel according to an embodiment. [Figure 12]FIG. 12 is a plan view showing the layout of the pixel shown in FIG. [Figure 13] 12 is a diagram illustrating a method for driving the pixel shown in FIG. [Figure 14] FIG. 2 is a plan view of a unit pixel according to an embodiment. [Figure 15] FIG. 15 is a diagram schematically illustrating a first lens shown in FIG. [Figure 16] FIG. 16 is a diagram showing a light profile with respect to the viewing angle of the first lens shown in FIG. [Figure 17] FIG. 15 is a diagram schematically illustrating a second lens shown in FIG. [Figure 18] FIG. 18 is a diagram showing a light profile with respect to the viewing angle of the second lens shown in FIG. [Figure 19] 2 is a schematic cross-sectional view of a display area of ​​a display panel according to an embodiment. FIG. [Figure 20] FIG. 2 is a schematic cross-sectional view of a non-display area of ​​a display panel according to an embodiment. [Figure 21] 1 shows an example of an arrangement of a display device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0035] Hereinafter, embodiments will be described with reference to the drawings. In this specification, when a component (or region, layer, portion, etc.) is referred to as being "on," "connected," or "coupled" to another component, this means that it may be directly connected / coupled to the other component, or that a third component may be disposed therebetween.

[0036] The same reference numerals refer to the same elements. In the drawings, thickness, ratio, and dimensions of elements are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all one or more combinations that can define the related configuration.

[0037] Terms such as "first," "second," and the like may be used to describe various components, but the components are not limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be designated a "second component," and similarly, a second component may be designated a "first component," without departing from the scope of the present embodiment. A singular term includes a plural term unless the context dictates otherwise.

[0038] Terms such as "under," "below," "on," and "above" are used to describe the relative relationships of features shown in the drawings. These terms are relative concepts and are described with reference to the directions shown in the drawings.

[0039] It should be understood that the use of terms such as "comprise" or "have" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but does not preclude the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0040] FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment.

[0041] Referring to FIG. 1, a display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a multiplexer 31, a power supply 40, and a display panel 50.

[0042] The timing control unit 10 can receive a video signal RGB and a control signal CS from an external host system or the like. The video signal RGB may include multiple grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0043] The timing control unit 10 processes the video signal RGB and the control signal CS to conform to the operating conditions of the display panel 60, and can generate and output video data DATA, gate drive control signal CONT1, light emission drive control signal CONT2, data drive control signal CONT3, and power supply control signal CONT4.

[0044] The gate driver 20 may include a scan driver circuit 20A that generates scan signals based on the gate driver control signal CONT1 input from the timing controller 10. The scan driver circuit 20A may provide the generated scan signals to the pixels PX via multiple scan lines GL. In one embodiment, one pixel PX may be configured to receive multiple scan signals having different waveforms. In such an embodiment, the scan driver circuit 20A may provide the multiple scan signals to the pixels PX via corresponding scan lines GL.

[0045] The gate driver 20 may further include a light emitting drive circuit 20B that generates a light emitting control signal based on the light emitting drive control signal CONT2. The light emitting drive circuit 20B may provide the generated light emitting control signal to the pixel PX via the light emitting line EL.

[0046] The gate driver 20 may be configured in the form of a gate-in-panel mounted on the display panel 50. The gate driver 20 may be disposed on one side of the display panel 50, or may be disposed on both sides (e.g., the left and right sides) of the display panel 50 as shown. Depending on the driving method, panel design method, etc., the gate driver 20 may be disposed on both sides (e.g., the left and right sides) of the display panel 50 as shown, or may be connected to two or more of the four sides of the display panel 50.

[0047] The data driver 30 may generate data voltages based on the image data DATA and the data drive control signal CONT3 output from the timing controller 10. The data driver 30 may provide the generated data voltages to the pixels PX through a plurality of data lines DL.

[0048] In one embodiment, the display device 1 may include a multiplexer 31 connected between the data driver 30 and the pixel PX to drive the data lines DL in a time-division manner. The multiplexer 31 connects each output channel of the data driver 30 to two or more data lines DL. The multiplexer 31 also distributes the data voltages output from the output channels of the data driver 30 to the data lines DL in a time-division manner, thereby reducing the number of output channels of the data driver 30.

[0049] In one embodiment, the multiplexer 31 may include a plurality of switching elements connected between the output channels of the data driver 30 and the data lines DL. For example, the multiplexer 31 may be a 1:n multiplexer in which one output channel is connected to i data lines DL (i is an integer greater than 1) via one switching element.

[0050] The power supply unit 40 generates a high potential driving voltage VDD and a low potential driving voltage VSS to be provided to the display panel 50 based on the power supply control signal CONT4. The power supply unit 40 can provide the generated driving voltages VDD and VSS to the pixels PX via corresponding power lines PL1 and PL2. The power supply unit 40 can also generate a reference voltage Vref required to drive the pixels PX and provide it to the pixels PX via a corresponding voltage line VrefL.

[0051] A plurality of pixels PX (also called sub-pixels) are arranged on the display panel 50. The pixels PX may be arranged in a matrix on the display panel 50, for example. The pixels PX arranged in one pixel row are connected to the same scan line GL and emission line EL, and the pixels PX arranged in one pixel column are connected to the same data line DL. In response to an emission control signal applied via the emission line EL, the pixels PX can emit light at a brightness corresponding to the scan signal and data voltage supplied via the scan line GL and data line DL.

[0052] In one embodiment, each pixel PX can display any of the colors red, green, and blue. In another embodiment, each pixel PX can display any of the colors cyan, magenta, and yellow. In various embodiments, each pixel PX can also display any of the colors red, green, blue, and white.

[0053] FIG. 2 is a diagram showing a method for driving a display device according to an embodiment.

[0054] 2, the display panel 50 may include a display area AA where an image is displayed, and a non-display area NA surrounding the display area AA. The display area AA may have a substantially rectangular shape as shown, but is not limited thereto, and may be formed into a shape such as a polygon, a circle, an ellipse, or a polygon with at least one curved corner, depending on the type of display device 1 (FIG. 1). The non-display area NA is disposed to surround the display area AA, and may follow the shape of the display area AA, or may be formed into an independent shape.

[0055] The display area AA may be divided into a first area A1 and a second area A2. The first area A1 is an area for displaying a first image, and may be driven to display, for example, a privacy image that is visible only to a specific viewer. Here, the viewer may be, for example, the driver. In this case, the first area A1 may include, but is not limited to, an area disposed adjacent to the driver's seat.

[0056] The second area A2 is an area that displays a second image different from the first image, and may be driven to display a shared image that is visible to other viewers or all viewers, for example. Here, the other viewers may be passengers, and in this case, the second area A2 may include, but is not limited to, an area disposed adjacent to the passenger seat.

[0057] The display panel 50 may be controlled so that the first region A1 operates in a first mode and the second region A2 operates in a second mode. For example, the first region A1 may operate in the first mode having a narrower viewing angle than the second region A2, and the second region A2 may operate in the second mode having a wider viewing angle than the first region A1.

[0058] In other words, the first area A1 may operate in a first mode, i.e., privacy mode, in which the viewing angle is limited so that the image is visible only to a specific viewer (e.g., the driver), and the second area A2 may operate in a second mode, i.e., share mode, in which the viewing angle is expanded so that the image is visible to other viewers or all viewers.

[0059] The size and shape of the first region A1 and the second region A2 are not limited. In particular, in one embodiment, the size and shape of the first region A1 and the second region A2 can be changed during operation of the display panel 50. In the illustrated embodiment, the first region A1 may have a smaller area than the second region A2. However, the embodiment is not limited thereto.

[0060] FIG. 3 is a diagram showing a configuration of a pixel according to an embodiment.

[0061] 3, a pixel PX according to an embodiment includes a plurality of sub-pixels SP1 and SP2. For example, the pixel PX may include a first sub-pixel SP1 and a second sub-pixel SP2.

[0062] Each of the sub-pixels SP1 and SP2 may include a light-emitting element LD and a control circuit CC for controlling the amount of drive current applied to the light-emitting element LD. The control circuit CC may include at least one transistor and a capacitor.

[0063] The control circuits CC of the subpixels SP1 and SP2 constituting one pixel PX may be configured with the same or different circuits. For example, the control circuits CC of the subpixels SP1 and SP2 may have the same circuit structure and be arranged in a mirrored configuration. However, this is not limiting.

[0064] The light emitting element LD may be various light emitting elements such as an LED, an OLED, a QLED, a QNED, a mini LED, a micro LED, a nano LED, etc. Hereinafter, an embodiment will be described taking the case where the light emitting element LD is an OLED as an example, but is not limited thereto.

[0065] The light-emitting element LD can display any of the colors red, green, and blue. In another embodiment, the light-emitting element LD can display any of the colors cyan, magenta, and yellow. In still another embodiment, the light-emitting element LD can display any of the colors red, green, blue, and white.

[0066] The light-emitting elements LD of the sub-pixels SP1 and SP2 constituting one pixel PX can display the same color. For example, the light-emitting elements LD of the sub-pixels SP1 and SP2 included in the red pixel PX can display red, the light-emitting elements LD of the sub-pixels SP1 and SP2 included in the green pixel PX can display green, and the light-emitting elements LD of the sub-pixels SP1 and SP2 included in the blue pixel PX can display blue.

[0067] Three pixels PX respectively displaying red, green, and blue may constitute one unit pixel. However, this embodiment is not limited to this. As described above, if a pixel PX displays cyan, magenta, and yellow, three pixels PX displaying cyan, magenta, and yellow may constitute one unit pixel. Alternatively, if a pixel PX displays red, green, blue, and white, four pixels PX displaying red, green, blue, and white may constitute one unit pixel. Alternatively, one unit pixel may include two or more pixels PX displaying the same color.

[0068] In various embodiments, the sub-pixels SP1 and SP2 included in one pixel PX may be driven to display different images, for example, the first sub-pixel SP1 may display the first image described with reference to FIG. 2, and the second sub-pixel SP2 may display the second image described with reference to FIG.

[0069] When the pixel PX is driven in a first mode in the first region, the first subpixel SP1 may be driven to display a first image, and when the pixel PX is driven in a second mode in the second region, the second subpixel SP2 may be driven to display a second image.

[0070] On the other hand, when the pixel PX is driven in the first mode in the first region, the second sub-pixel SP2 may be driven to display a predetermined dummy image. The dummy image may be, for example, but is not limited to, a black image. Conversely, when the pixel PX is driven in the second mode in the second region, the first sub-pixel SP1 may be driven to display a predetermined dummy image.

[0071] As described above, the first and second regions may have different shapes and sizes. That is, the pixel PX may operate in a first mode during a first period and in a second mode during a second period while the display device 1 (FIG. 1) is driven. In this embodiment, the first sub-pixel SP1 may receive a data voltage corresponding to a first image and output the first image during the first period, and the second sub-pixel SP2 may receive a data voltage corresponding to a second image during the second period and output the second image during the second period.

[0072] Hereinafter, a specific embodiment for applying data voltages corresponding to the first and second images to the first and second sub-pixels SP1 and SP2, respectively, will be described.

[0073] FIG. 4 is a block diagram showing a configuration of a data driver according to an embodiment.

[0074] Referring to FIG. 4, the data driver 30 may include a register unit 31a, a latch unit 32, a digital-to-analog converter (DAC) 33, and an output buffer .

[0075] The register unit 31a generates a sampling signal using the data drive control signal CONT2 received from the timing control unit 10 (FIG. 1), and provides the generated sampling signal to the latch unit 32.

[0076] The latch unit 32 latches the video data DATA received from the timing control unit 10, and outputs the video data DATA to the digital-to-analog conversion unit 33 in response to the sampling signal received from the register unit 31a.

[0077] The digital-to-analog converter 33 converts the image data DATA received from the latch 32 into a gamma compensation voltage to generate a data voltage.

[0078] The output buffer 34 outputs the data voltage output from the digital-to-analog converter 33 to the data line DL via the output channel CH in response to a source output enable signal SOE received from the timing controller 10.

[0079] In one embodiment, the data driver 30 may further include a power management circuit 35. The power control circuit 35 may generate a bias current Ibias based on a power control signal PWRC received from the timing controller 10 and apply the bias current Ibias to the output buffer 34. The power control circuit 35 may vary the magnitude of the bias current Ibias depending on the mode indicated by the power control signal PWRC, thereby controlling the magnitude of the data voltage output from the data driver 30 and managing the power consumption of the data driver 30.

[0080] FIG. 5 is a diagram showing the connection relationship between the pixels and the data driver according to the first embodiment.

[0081] 5, the data driver 30 may include a plurality of output channels CH1, CH2, and CH3 respectively connected to a plurality of output buffers 341, 342, and 343. Each of the output channels CH1, CH2, and CH3 may output a data voltage applied from the connected output buffer 341, 342, or 343.

[0082] Each of the output channels CH1, CH2, CH3 may be connected to a respective pixel PX1, PX2, PX3 via a multiplexer 31. For example, the first output channel CH1 may be connected to the first pixel PX1, the second output channel CH2 may be connected to the second pixel PX2, and the third output channel CH3 may be connected to the third pixel PX3.

[0083] The multiplexer 31 includes a plurality of switching elements M1, M2, M3, M4, M5, and M6. Each of the switching elements M1, M2, M3, M4, M5, and M6 may be connected to one of the output channels CH1, CH2, and CH3 of the data driver 30.

[0084] In this case, two or more switching elements M1, M2, M3, M4, M5, M6 may be connected to one output channel CH1, CH2, CH3. For example, the first and second switching elements M1, M2 may be connected to the first output channel CH1, the third and fourth switching elements M3, M4 may be connected to the second output channel CH2, and the fifth and sixth switching elements M5, M6 may be connected to the third output channel CH3.

[0085] The switching elements M1, M2, M3, M4, M5, and M6 may be controlled to be turned on and off via MUX control signals MUX1 and MUX2 provided from the timing control unit 10 (FIG. 1), etc. Specifically, the first switching element M1, the third switching element M3, and the fifth switching element M5 may be controlled by the first MUX control signal MUX1, and the second switching element M2, the fourth switching element M4, and the sixth switching element M6 may be controlled by the second MUX control signal MUX2. Here, because the switching elements M1, M2, M3, M4, M5, and M6 are controlled by two MUX control signals MUX1 and MUX2, the multiplexer 31 may be referred to as a 2-MUX structure.

[0086] The display panel 50 includes a plurality of pixels PX1, PX2, and PX3 arranged in a matrix. Figure 5 representatively shows pixels PX1, PX2, and PX3 that display a first color, a second color, and a third color, respectively. Here, the first color may be red, the second color may be green, and the third color may be blue. However, the embodiment is not limited to this. The first to third pixels PX1, PX2, and PX3 that display the first to third colors can form one unit pixel PXU.

[0087] Each of the pixels PX1, PX2, and PX3 includes first and second sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32. The sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 of each of the pixels PX1, PX2, and PX3 are driven to display a first image or a second image, as described with reference to FIG.

[0088] The sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 are connected to corresponding data lines DL1, DL2, DL3, DL4, DL5, and DL6 and scan lines GL1 and GL2. The input ends of the data lines DL1, DL2, DL3, DL4, DL5, and DL6 are connected to switching elements M1, M2, M3, M4, M5, and M6 of the multiplexer 31, respectively.

[0089] In this case, subpixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting one pixel PX1, PX2, or PX3 may be connected to one output channel CH1, CH2, or CH3 via switching elements M1, M2, M3, M4, M5, and M6. For example, subpixels SP11 and SP12 constituting a first pixel PX1 may be connected to a first output channel CH1 via first and second switching elements M1 and M2, subpixels SP21 and SP22 constituting a second pixel PX2 may be connected to a second output channel CH2 via third and fourth switching elements M3 and M4, and subpixels SP31 and SP32 constituting a third pixel PX3 may be connected to a third output channel CH3 via fifth and sixth switching elements M5 and M6.

[0090] When the switching elements M1, M2, M3, M4, M5, and M6 are turned on by the MUX control signals MUX1 and MUX2, data voltages may be applied to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to the corresponding switching elements M1, M2, M3, M4, M5, and M6. Specifically, when the first MUX control signal MUX1 turns on the first, third, and fifth switching elements M1, M3, and M5, data voltages may be applied to the first sub-pixels SP11, SP21, and SP31 of the pixels PX1, PX2, and PX3 connected to the first, third, and fifth data lines DL1, DL3, and DL5. In addition, when the second, fourth, and sixth switching elements M2, M4, and M6 are turned on by the second MUX control signal MUX2, data voltages may be applied to the second sub-pixels SP12, SP22, and SP32 of each pixel PX1, PX2, and PX3 connected to the second, fourth, and sixth data lines DL2, DL4, and DL6.

[0091] In one embodiment, the switching elements M1, M2, M3, M4, M5, and M6 may be configured as transistors. In the illustrated embodiment, the switching elements M1, M2, M3, M4, M5, and M6 are PMOS transistors. In such an embodiment, the turn-on levels of the MUX control signals MUX1 and MUX2 are low. However, this embodiment is not limited thereto. That is, in other embodiments, the switching elements M1, M2, M3, M4, M5, and M6 may be PMOS transistors. In such an embodiment, the turn-on levels of the MUX control signals MUX1 and MUX2 may be low.

[0092] In one embodiment, the output buffers 341, 342, and 343 may output a data voltage corresponding to a first image in synchronization with the first MUX control signal MUX1 having a turn-on level, and output a data voltage corresponding to a second image in synchronization with the second MUX control signal MUX2 having a turn-on level. Thus, while the first MUX control signal MUX1 is applied, the data voltage corresponding to the first image may be applied to the first sub-pixels SP11, SP21, and SP31, and while while the second MUX control signal MUX2 is applied, the data voltage corresponding to the second image may be applied to the second sub-pixels SP12, SP22, and SP32. Thus, the first sub-pixels SP11, SP21, and SP31 may emit light with a brightness corresponding to the first image, and the second sub-pixels SP12, SP22, and SP32 may emit light with a brightness corresponding to the second image.

[0093] When there is no first image to be displayed in the first sub-pixels SP11, SP21, and SP31 in a given frame (for example, when the pixels PX1, PX2, and PX3 are driven in the second mode in that frame), the output buffers 341, 342, and 343 may be controlled to output a predetermined dummy data voltage in synchronization with the first MUX control signal MUX1 in that frame. Conversely, when there is no second image to be displayed in the second sub-pixels SP12, SP22, and SP32 in a given frame (for example, when the pixels PX1, PX2, and PX3 are driven in the first mode in that frame), the output buffers 341, 342, and 343 may be controlled to output a predetermined dummy data voltage in synchronization with the second MUX control signal MUX2 in that frame.

[0094] In the above embodiment, the output channels CH1, CH2, and CH3 of the data driver 30 are connected to the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 in a 1:n, i.e., 1:2, relationship. That is, one output channel CH1, CH2, or CH3 is connected to the first subpixels SP11, SP21, and SP31 and the second subpixels SP12, SP22, and SP32 constituting one pixel PX1, PX2, and PX3 in a 1:n relationship via the multiplexer 31.

[0095] Figure 6 is a waveform diagram of control and drive signals applied to the display device of Figure 5. Figure 6 shows an example in which, during one frame shown, pixels PX1, PX2, and PX3 in a first pixel row are driven in a first mode, and pixels PX1, PX2, and PX3 in a second pixel row are driven in a second mode.

[0096] 5 and 6, gate signals of a turn-on level are sequentially applied to scan lines GL1 and GL2 during one frame. At this time, each gate signal may be applied at the turn-on level for one horizontal period 1H. Pixels PX1, PX2, and PX3 in the pixel row to which the gate signals of the turn-on level are applied may receive data voltages via data lines DL1, DL2, DL3, DL4, DL5, and DL6.

[0097] Each of the output buffers 341, 342, and 343 can time-divide one horizontal period 1H and sequentially output data voltages for the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 that make up one pixel PX1, PX2, and PX3. For example, each of the output buffers 341, 342, and 343 may output data voltages for the first subpixels SP11, SP21, and SP31 during a first period t1 of one horizontal period 1H, and output data voltages for the second subpixels SP12, SP22, and SP32 during a second period t2.

[0098] The timing control unit 10 (FIG. 1) provides MUX control signals MUX1 and MUX2 so that the switching elements M1, M2, M3, M4, M5, and M6 of the multiplexer 31 are sequentially turned on during one horizontal period 1H.

[0099] The pixels PX1, PX2, and PX3 in the first pixel column may be driven in the first mode. During a first period t1 of a first horizontal period, a first MUX control signal MUX1 is applied to the multiplexer 31 at a turn-on level. This turns on the first, third, and fifth switching elements M1, M3, and M5, and the first image data voltage Vdata1 output from the output buffers 341, 342, and 343 may be applied to the first sub-pixels SP11, SP21, and SP31, respectively.

[0100] During the second period t2, the second MUX control signal MUX2 is applied at a turn-on level to the multiplexer 31. As a result, the second, fourth, and sixth switching elements M2, M4, and M6 are turned on, and the dummy data voltages VdataD output from the output buffers 341, 342, and 343 may be applied to the second sub-pixels SP12, SP22, and SP32, respectively.

[0101] The pixels PX1, PX2, and PX3 in the second pixel column may be driven in the second mode. During the first period t1 of the second horizontal period, the first MUX control signal MUX1 is applied to the multiplexer 31 at a turn-on level. This turns on the first, third, and fifth switching elements M1, M3, and M5, and the dummy data voltage VdataD output from the output buffers 341, 342, and 343 may be applied to the first sub-pixels SP11, SP21, and SP31, respectively.

[0102] During the second period t2, the second MUX control signal MUX2 is applied at a turn-on level to the multiplexer 31. As a result, the second, fourth, and sixth switching elements M2, M4, and M6 are turned on, and the data voltage Vdata2 of the second image output from the output buffers 341, 342, and 343 may be applied to the second sub-pixels SP12, SP22, and SP32, respectively.

[0103] In this manner, the size and shape of the first area A1 (FIG. 2) where the first image is displayed and the second area A2 (FIG. 2) where the second image is displayed on the display panel 50 can be freely changed by selectively applying the first mode or the second mode image data to the pixel row.

[0104] FIG. 7 is a diagram showing the connection relationship between the pixels and the data driver according to the second embodiment.

[0105] 7, the data driver 30 may include a plurality of output channels CH1, CH2, CH3, CH4, CH5, and CH6 respectively connected to a plurality of output buffers 341, 342, 343, 344, 345, and 346. Each of the output channels CH1, CH2, CH3, CH4, CH5, and CH6 may output a data voltage applied from the connected output buffer 341, 342, 343, 344, 345, and 346.

[0106] The output channels CH1, CH2, CH3, CH4, CH5, and CH6 may be connected to the pixels PX1, PX2, and PX3 of the unit pixels PXU1 and PXU2, respectively, via the multiplexer 31. For example, the first output channel CH1 and the fourth output channel CH4 may be connected to the first pixel PX1 of the unit pixels PXU1 and PXU2, the second output channel CH2 and the fifth output channel CH5 may be connected to the second pixel PX2 of the unit pixels PXU1 and PXU2, and the third output channel CH3 and the sixth output channel CH4 may be connected to the third pixel PX3 of the unit pixels PXU1 and PXU2.

[0107] The multiplexer 31 includes a plurality of switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12. Each of the switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12 may be connected to one of the output channels CH1, CH2, CH3, CH4, CH5, and CH6 of the data driver 30.

[0108] In this case, two or more switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12 may be connected to one output channel CH1, CH2, CH3, CH4, CH5, CH6. For example, the first and seventh switching elements M1 and M7 may be connected to the first output channel CH1, the third and ninth switching elements M3 and M9 may be connected to the second output channel CH2, the fifth and eleventh switching elements M5 and M11 may be connected to the third output channel CH3, the second and eighth switching elements M2 and M8 may be connected to the fourth output channel CH4, the fourth and tenth switching elements M4 and M10 may be connected to the fifth output channel CH5, and the sixth and twelfth switching elements M6 and M12 may be connected to the sixth output channel CH6.

[0109] The switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12 may be controlled to be turned on and off via MUX control signals MUX1 and MUX2 provided from the timing control unit 10 (FIG. 1), etc. Specifically, the first to sixth switching elements M1, M2, M3, M4, M5, and M6 may be controlled by a first MUX control signal MUX1, and the seventh to twelfth switching elements M7, M8, M9, M10, M11, and M12 may be controlled by a second MUX control signal MUX2.

[0110] The display panel 50 includes a plurality of unit pixels PXU1 and PXU2 arranged in a matrix. Each of the unit pixels PXU1 and PXU2 includes a plurality of pixels PX1, PX2, and PX3.

[0111] Each of the pixels PX1, PX2, and PX3 constituting one unit pixel PXU1 and PXU2 includes first and second sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32. The sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 of each of the pixels PX1, PX2, and PX3 are driven to display a first image or a second image, as described with reference to FIG.

[0112] The subpixels SP11, SP12, SP21, SP22, SP31, and SP32 are connected to corresponding data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, and DL12 and scan lines GL. The input ends of the data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, and DL12 are connected to switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12 of the multiplexer 31, respectively.

[0113] In this case, subpixels SP11, SP12, SP21, SP22, SP31, and SP32 included in the plurality of unit pixels PXU1 and PXU2 may be connected to one output channel CH1, CH2, CH3, CH4, CH5, and CH6 via switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12, respectively. For example, the first subpixel SP11 constituting the first pixel PX1 of the unit pixels PXU1 and PXU2 may be connected to the first output channel CH1 via the first and seventh switching elements M1 and M7, respectively, and the second subpixel SP12 may be connected to the fourth output channel CH4 via the second and eighth switching elements M2 and M8, respectively. The first sub-pixel SP21 constituting the second pixel PX2 of each unit pixel PXU1, PXU2 may be connected to the second output channel CH2 via the third and ninth switching elements M3, M9, respectively, and the second sub-pixel SP22 may be connected to the fifth output channel CH5 via the fourth and tenth switching elements M4, M10, respectively. The first sub-pixel SP31 constituting the third pixel PX3 of each unit pixel PXU1, PXU2 may be connected to the third output channel CH3 via the fifth and eleventh switching elements M5, M11, respectively, and the second sub-pixel SP32 may be connected to the sixth output channel CH6 via the sixth and twelfth switching elements M6, M12, respectively.

[0114] When switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12 are turned on by the MUX control signals MUX1 and MUX2, data voltages may be applied to data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, and DL12 connected to the corresponding switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12. Specifically, when first to sixth switching elements M1, M2, M3, M4, M5, and M6 are turned on by the first MUX control signal MUX1, data voltages may be applied to pixels PX1, PX2, and PX3 of the first unit pixel PXU1 connected to the first to sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6. In addition, when the seventh to twelfth switching elements M7, M8, M9, M10, M11, and M12 are turned on by the second MUX control signal MUX2, data voltages may be applied to the pixels PX1, PX2, and PX3 of the second unit pixel PXU2 connected to the seventh to twelfth data lines DL7, DL8, DL9, DL10, DL11, and DL12.

[0115] In one embodiment, some of the output buffers 341, 342, 343, 344, 345, and 346 may output data voltages corresponding to a first image in synchronization with the MUX control signals MUX1 and MUX2 at a turn-on level, and other of the output buffers 341, 342, 343, 344, 345, and 346 may output data voltages corresponding to a second image in synchronization with the MUX control signals MUX1 and MUX2 at a turn-on level. For example, the first group of output buffers, i.e., the first to third output buffers 341, 342, and 343, may output data voltages corresponding to the first image in synchronization with the MUX control signals MUX1 and MUX2, and the second group of output buffers, i.e., the fourth to sixth output buffers 344, 345, and 346, may output data voltages corresponding to the second image in synchronization with the MUX control signals MUX1 and MUX2.

[0116] When there is no first image to be displayed in the first sub-pixels SP11, SP21, and SP31 in a given frame (for example, when the pixels PX1, PX2, and PX3 are driven in the second mode in that frame), the first to third output buffers 341, 342, and 343 may be controlled to output predetermined dummy data voltages in synchronization with the MUX control signals MUX1 and MUX2 in that frame. Conversely, when there is no second image to be displayed in the second sub-pixels SP12, SP22, and SP32 in a given frame (for example, when the pixels PX1, PX2, and PX3 are driven in the first mode in that frame), the fourth to sixth output buffers 344, 345, and 346 may be controlled to output predetermined dummy data voltages in synchronization with the MUX control signals MUX1 and MUX2 in that frame.

[0117] Compared to the embodiment of Figure 5, in the embodiment of Figure 7, each output buffer 341, 342, 343, 344, 345, and 346 is configured to output only a data voltage corresponding to one image (first image or second image) depending on the mode. In this embodiment, the gray scale change between data voltages output during consecutive horizontal periods is smaller than in the embodiment of Figure 5. Therefore, the transition delay between output data voltages is minimized, preventing image quality degradation.

[0118] In the above embodiment, the output channels CH1, CH2, CH3, CH4, CH5, and CH6 of the data driver 30 are connected in a 1:1 relationship to the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting one unit pixel PXU1 (PXU2). That is, one output channel CH1, CH2, CH3, CH4, CH5, and CH6 is connected in a 1:1 relationship to the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting one unit pixel PXU1 (PXU2), and is connected in a 1:n relationship to a plurality of unit pixels PXU1 (PXU2) via the multiplexer 31.

[0119] Figure 8 is a waveform diagram of control and driving signals applied to the display device of Figure 7. Figure 8 shows an example in which, during one frame shown, the first pixel unit PXU1 of the first pixel row is driven in the first mode, the second pixel unit PXU2 is driven in the second mode, and the first pixel unit PXU1 of the second pixel row is driven in the second mode, and the second pixel unit PXU2 is driven in the first mode.

[0120] 7 and 8, gate signals of a turn-on level are sequentially applied to scan lines GL1 and GL2 during one frame. At this time, each gate signal may be applied at the turn-on level for one horizontal period 1H. Pixels PX1, PX2, and PX3 in the pixel row to which the gate signals of the turn-on level are applied may receive data voltages via data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, and DL12.

[0121] The output buffers 341, 342, 343, 344, 345, and 346 may time-divide one horizontal period 1H and sequentially output data voltages for the pixel units PXU1 and PXU2. For example, during a first period t1 of one horizontal period 1H, the first group output buffers 341, 342, and 343 may output data voltages for the first sub-pixels SP11, SP21, and SP31 of the first pixel unit PXU1, and the second group output buffers 344, 345, and 346 may output data voltages for the second sub-pixels SP12, SP22, and SP32 of the first pixel unit PXU1. Also, during the second period t2 of one horizontal period 1H, the first group output buffers 341, 342, 343 may output data voltages for the first sub-pixels SP11, SP21, SP31 of the second pixel unit PXU2, and the second group output buffers 344, 345, 346 may output data voltages for the second sub-pixels SP12, SP22, SP32 of the second pixel unit PXU2.

[0122] The timing control unit 10 (FIG. 1) provides MUX control signals MUX1 and MUX2 so that the switching elements M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12 of the multiplexer 31 are sequentially turned on during one horizontal period 1H.

[0123] In one embodiment, the pixels PX1, PX2, and PX3 of the first pixel unit PXU1 in the first pixel column may be driven in the first mode, and the pixels PX1, PX2, and PX3 of the second pixel unit PXU2 may be driven in the second mode. During a first period t1 of a first horizontal period, a first MUX control signal MUX1 is applied to the multiplexer 31 at a turn-on level. This turns on the first to sixth switching elements M1, M2, M3, M4, M5, and M6, so that the data voltages Vdata1 of the first image output from the first group output buffers 341, 342, and 343 are applied to the first sub-pixels SP11, SP21, and SP31 of the first pixel unit PXU1, respectively, and the dummy data voltages VdataD output from the second group output buffers 344, 345, and 346 are applied to the first sub-pixels SP11, SP21, and SP31 of the first pixel unit PXU1, respectively.

[0124] During the second period t2, the second MUX control signal MUX2 is applied at a turn-on level to the multiplexer 31. As a result, the seventh to twelfth switching elements M7, M8, M9, M10, M11, and M12 are turned on, so that the dummy data voltages VdataD output from the first group output buffers 341, 342, and 343 are applied to the first sub-pixels SP11, SP21, and SP31 of the second pixel unit PXU2, respectively, and the data voltages Vdata2 of the second image output from the second group output buffers 344, 345, and 346 are applied to the second sub-pixels SP12, SP22, and SP32 of the second pixel unit PXU2, respectively.

[0125] In one embodiment, the pixels PX1, PX2, and PX3 of the first pixel unit PXU1 in the second pixel column may be driven in the second mode, and the pixels PX1, PX2, and PX3 of the second pixel unit PXU2 may be driven in the first mode. During the first period t1 of the second horizontal period, the first MUX control signal MUX1 is applied to the multiplexer 31 at a turn-on level. This turns on the first to sixth switching elements M1, M2, M3, M4, M5, and M6, so that the dummy data voltages VdataD output from the first group output buffers 341, 342, and 343 may be applied to the first sub-pixels SP11, SP21, and SP31 of the second pixel unit PXU2, respectively, and the data voltage Vdata2 of the second image output from the second group output buffers 344, 345, and 346 may be applied to the second sub-pixels SP12, SP22, and SP32 of the second pixel unit PXU2, respectively.

[0126] During the second period t2, the second MUX control signal MUX2 is applied at a turn-on level to the multiplexer 31. As a result, the seventh to twelfth switching elements M7, M8, M9, M10, M11, and M12 are turned on, so that the data voltages Vdata1 of the first image output from the first group output buffers 341, 342, and 343 are applied to the first sub-pixels SP11, SP21, and SP31 of the second pixel unit PXU2, respectively, and the dummy data voltages VdataD output from the second group output buffers 344, 345, and 346 are applied to the second sub-pixels SP12, SP22, and SP32 of the second pixel unit PXU2, respectively.

[0127] In this manner, first mode or second mode image data is selectively applied to each unit pixel PXU1, PXU2 arranged in the pixel row and pixel column directions, so that the size and shape of the first area A1 (Figure 2) where the first image is displayed on the display panel 50 and the second area A2 (Figure 2) where the second image is displayed can be freely changed.

[0128] FIG. 9 is a diagram illustrating a connection relationship between pixels and a data driver according to the third embodiment.

[0129] 9, the data driver 30 may include a plurality of output channels CH1, CH2, CH3, CH4, CH5, and CH6 respectively connected to a plurality of output buffers 341, 342, 343, 344, 345, and 346. Each of the output channels CH1, CH2, CH3, CH4, CH5, and CH6 may output a data voltage applied from the connected output buffer 341, 342, 343, 344, 345, and 346.

[0130] The output channels CH1, CH2, CH3, CH4, CH5, and CH6 may be connected to the pixels PX1, PX2, and PX3, respectively. For example, the first output channel CH1 may be connected to the first subpixel SP11 of the first pixel PX1, the second output channel CH2 may be connected to the second subpixel SP12 of the first pixel PX1, the third output channel CH3 may be connected to the first subpixel SP21 of the second pixel PX2, the fourth output channel CH4 may be connected to the second subpixel SP22 of the second pixel PX2, the third output channel CH3 may be connected to the first subpixel SP31 of the third pixel PX3, and the sixth output channel CH6 may be connected to the second subpixel SP32 of the third pixel PX3.

[0131] The display panel 50 includes a plurality of pixels PX1, PX2, and PX3 arranged in a matrix. Each of the pixels PX1, PX2, and PX3 includes first and second sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32. The sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 of each of the pixels PX1, PX2, and PX3 are driven to display a first image or a second image, as described with reference to FIG. 3 .

[0132] The sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 are connected to corresponding data lines DL1, DL2, DL3, DL4, DL5, and DL6 and scan lines GL. The input ends of the data lines DL1, DL2, DL3, DL4, DL5, and DL6 are connected to output channels CH1, CH2, CH3, CH4, CH5, and CH6, respectively.

[0133] In one embodiment, some of the output buffers 341, 342, 343, 344, 345, and 346 may output data voltages corresponding to a first image, and other of the output buffers 341, 342, 343, 344, 345, and 346 may output data voltages corresponding to a second image. For example, the first group of output buffers, i.e., the first to third output buffers 341, 342, and 343, may output data voltages corresponding to the first image, and the second group of output buffers, i.e., the fourth to sixth output buffers 344, 345, and 346, may output data voltages corresponding to the second image.

[0134] When there is no first video signal to be displayed in the first sub-pixels SP11, SP21, and SP31 in a given frame (for example, when the pixels PX1, PX2, and PX3 are driven in the second mode in that frame), the first to third output buffers 341, 342, and 343 may be controlled to output predetermined dummy data voltages in that frame. Conversely, when there is no second video signal to be displayed in the second sub-pixels SP12, SP22, and SP32 in a given frame (for example, when the pixels PX1, PX2, and PX3 are driven in the first mode in that frame), the fourth to sixth output buffers 344, 345, and 346 may be controlled to output predetermined dummy data voltages in that frame.

[0135] In the above embodiment, the output channels CH1, CH2, CH3, CH4, CH5, and CH6 of the data driver 30 have a 1:1 connection relationship with the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting one unit pixel PXU1 and PXU2. That is, one output channel CH1, CH2, CH3, CH4, CH5, and CH6 is connected 1:1 to the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting one unit pixel PXU1 and PXU2.

[0136] Figure 10 is a waveform diagram of control and drive signals applied to the display device of Figure 9. Figure 10 shows an example in which, during one frame shown, pixels PX1, PX2, and PX3 in the first pixel row are driven in the first mode, and pixels PX1, PX2, and PX3 in the second pixel row are driven in the second mode.

[0137] 9 and 10, gate signals of a turn-on level are sequentially applied to scan lines GL1 and GL2 during one frame. At this time, each gate signal may be applied at a turn-on level for one horizontal period 1H. Pixels PX1, PX2, and PX3 in the pixel row to which the gate signals of the turn-on level are applied may receive data voltages via data lines DL1, DL2, DL3, DL4, DL5, and DL6.

[0138] The pixels PX1, PX2, and PX3 in the first pixel column may be driven in the first mode. The output buffers 341, 342, 343, 344, 345, and 346 may output data voltages to the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting each pixel PX1, PX2, and PX3 during the first horizontal period 1H. For example, during the horizontal period 1H, the first group output buffers 341, 342, and 343 may output the first data voltage Vdata1 to the first subpixels SP11, SP21, and SP31, and the second group output buffers 344, 345, and 346 may output the dummy data voltage VdataD to the second subpixels SP12, SP22, and SP32.

[0139] The pixels PX1, PX2, and PX3 in the second pixel column may be driven in the second mode. The output buffers 341, 342, 343, 344, 345, and 346 may output data voltages for the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting each pixel PX1, PX2, and PX3 during the second horizontal period 1H. For example, during the horizontal period 1H, the first group output buffers 341, 342, and 343 may output a dummy data voltage VdataD to the first subpixels SP11, SP21, and SP31, and the second group output buffers 344, 345, and 346 may output a data voltage Vdata1 of the second image to the second subpixels SP12, SP22, and SP32.

[0140] In this manner, the size and shape of the first area A1 (FIG. 2) where the first image is displayed and the second area A2 (FIG. 2) where the second image is displayed on the display panel 50 can be freely changed by selectively applying the first mode or the second mode image data to the pixel row.

[0141] Fig. 11 is a circuit diagram of a pixel according to one embodiment, and Fig. 12 is a plan view showing the layout of the pixel shown in Fig. 11.

[0142] 11 and 12, the display panel 50 may include first scan lines SC1, second scan lines SC2, and light emitting lines EL extending in a row direction, and may also include high driving voltage lines PL1, low driving voltage lines PL2, data lines DL, and reference voltage lines VrefL extending in a column direction substantially perpendicular to the row direction. Sub-pixels SP1 and SP2 may be formed in areas where the first scan lines SC1, second scan lines SC2, and light emitting lines EL intersect with the high driving voltage lines PL1 and data lines DL.

[0143] Two subpixels SP1 and SP2 adjacent in the row direction may constitute one pixel PX. The subpixels SP1 and SP2 constituting one pixel PX may be configured with the same or different circuits. When the subpixels SP1 and SP2 constituting one pixel PX are configured with the same circuit, the subpixels SP1 and SP2 may have a layout that is mirrored to each other with respect to the column direction. Specifically, the two adjacent subpixels SP1 and SP2 constituting one pixel PX may have a layout that is mirrored to each other with respect to the high-potential drive voltage line PL1. However, this embodiment is not limited to this.

[0144] The first scan line SC1, the second scan line SC2, and the light-emitting line EL extend in the row direction across the subpixels SP1 and SP2. The high-potential driving voltage line PL1, the low-potential driving voltage line PL2, the data line DL, and the reference voltage line VrefL extend in the column direction between two adjacent subpixels SP1 and SP2. For example, the high-potential driving voltage line PL1 may extend in the column direction between two adjacent subpixels SP1 and SP2, and the data line DL may extend in the column direction on one side of each subpixel SP1 and SP2 and between two adjacent pixels PX. The reference voltage line VrefL and the low-potential driving voltage line PL2 may extend in the column direction on one side of at least some of the subpixels SP1 and SP2 of the multiple pixels PX.

[0145] In one embodiment, two or more adjacent subpixels SP1 and SP2 may share at least one of the high-potential drive voltage line PL1, the low-potential drive voltage line PL2, the data line DL, and the reference voltage line VrefL. For example, two subpixels SP1 and SP2 included in one pixel PX may share one high-potential drive voltage line PL1. Furthermore, for example, two or more pixels PX may share the low-potential drive voltage line PL2 and / or the reference voltage line VrefL. In this case, a connection line CL extending in the row direction may be formed via the subpixels SP1 and SP2 to connect the reference voltage line VrefL extending in the column direction to each of the subpixels SP1 and SP2. However, this embodiment is not limited to this.

[0146] The configuration of the subpixels SP1 and SP2 will be described below based on the first subpixel SP1.

[0147] The first sub-pixel SP1 according to an embodiment may include a drive transistor DT, a light-emitting element LD connected to the drive transistor DT, and a control circuit for controlling the amount of drive current applied to the light-emitting element LD via the drive transistor DT. For example, the control circuit may include first to fifth transistors T1 to T5 and a capacitor Cst. In this embodiment, one pixel PX has a 12T2C structure.

[0148] The first electrode of the driving transistor DT is configured to receive a high potential driving voltage VDD (connected to the high potential driving voltage line PL1), and the second electrode is connected to the second node N2. The gate electrode of the driving transistor DT is connected to the second node N2. The driving transistor DT is turned on by the voltage applied to the first node N1, and can control the amount of driving current flowing through the light emitting element LD.

[0149] In one embodiment, the driving transistor DT may be composed of two auxiliary driving transistors DT1 and DT2 connected in series as shown. In this case, the first auxiliary driving transistor DT1 may be connected between the high-potential driving voltage VDD and the second auxiliary driving transistor DT2, and the second auxiliary driving transistor DT2 may be connected between the first auxiliary driving transistor DT1 and the first node N1. The gate electrodes of the first auxiliary driving transistor DT1 and the second auxiliary driving transistor DT2 are connected to the first node N1. However, the embodiment is not limited to this.

[0150] A first electrode of the first transistor T1 is connected to the data line DL, and a second electrode is indirectly connected to the gate electrode of the drive transistor DT via a third node N3. A gate electrode of the first transistor T1 is connected to a first scan line GL1 to receive a first scan signal SC1. The first transistor T1 is turned on by the first scan signal SC1 applied to the first scan line GL1 to transfer a data voltage Vdata applied to the data line DL to the third node N3. Such a first transistor T1 may be referred to as a switching transistor.

[0151] When the pixel PX is driven in the first mode in a given frame, the first transistor T1 of the first sub-pixel SP1 may be applied with the data voltage Vdata of the first image (FIG. 2) applied to the data line DL, and when the pixel PX is driven in the second mode in a given frame, the first transistor T1 may be applied with a dummy data voltage to the data line DL.

[0152] The first electrode of the second transistor T2 is connected to the gate electrode of the driving transistor DT via the first node N1, and the second electrode is connected to the second electrode of the driving transistor DT via the second node N2. The gate electrode of the second transistor T2 is connected to the second scan line GL2 to receive the second scan signal SC2. The second transistor T2 is turned on by the second scan signal SC2 applied to the second scan line GL2 to connect the gate electrode of the driving transistor DT to the second electrode.

[0153] The third transistor T3 has a first electrode configured to receive a reference voltage Vref (connected to a reference voltage line VrefL) and a second electrode connected to a third node N3. The gate electrode of the third transistor T3 is connected to the light emitting line EL to receive the light emitting signal EM. The third transistor T3 is turned on by the light emitting signal EM applied to the light emitting line EL, and can apply the reference voltage Vref to the third node N3. Such a third transistor T3 can be called an initialization transistor.

[0154] The first electrode of the fourth transistor T4 is connected to the driving transistor DT via the second node N2, and the second electrode is connected to the light-emitting element LD via the fourth node N4. The gate electrode of the fourth transistor T4 is connected to the emission line EL to receive the light-emitting signal EM. The fourth transistor T4 is turned on by the light-emitting signal EM applied to the emission line EL to connect the driving transistor DT and the light-emitting element LD. When the fourth transistor T4 is turned on, a current path is formed between the high-potential driving voltage VDD and the low-potential driving voltage VSS, allowing a driving current to flow through the light-emitting element LD, causing the light-emitting element LD to emit light. This fourth transistor T4 can be called an emission transistor.

[0155] The third transistor T3 of the fifth transistor T5 has a first electrode configured to receive the reference voltage Vref (connected to the reference voltage line VrefL), and a second electrode connected to the anode electrode of the light-emitting element LD via a fourth node N4. The gate electrode of the fifth transistor T5 is connected to the second scan line GL2 to receive the second scan signal SC2. The second transistor T2 is turned on by the second scan signal SC2 applied to the second scan line GL2 to transmit the reference voltage Vref to the anode electrode of the light-emitting element LD. This fifth transistor T5 may be referred to as an anode initialization transistor.

[0156] The capacitor Cst is connected between the first node N1 and the third node N3 and can store a voltage corresponding to the voltage difference between the first node N1 and the third node N3.

[0157] The light emitting device LD may have an anode electrode connected to the fourth node N4 and a cathode electrode connected to the low potential driving voltage VSS. When the driving transistor DT and the fourth transistor T4 are turned on, a current path is formed between the high potential driving voltage VDD and the low potential driving voltage VSS, allowing a driving current to flow through the light emitting device LD. The light emitting device LD may emit light with a brightness corresponding to the amount of the applied driving current.

[0158] In the embodiment shown in FIG. 7, the pixel PX may be configured with an LTPS (Low Temperature Poly-Silicon) thin-film transistor. The LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin-film transistor has an active layer formed of polysilicon. Such an LTPS thin-film transistor may be configured as a P-type thin-film transistor. The LTPS thin-film transistor has high electron mobility and therefore high-speed driving characteristics.

[0159] In another embodiment, the pixel PX may be configured with an oxide semiconductor thin film transistor, or may be a hybrid type including an LTPS thin film transistor and an oxide thin film transistor. The oxide semiconductor thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor thin film transistor has an active layer formed of an oxide semiconductor. Here, the oxide semiconductor may be configured as an amorphous or crystalline oxide semiconductor. The oxide semiconductor thin film transistor may be configured as an N-type transistor. The oxide semiconductor thin film transistor can be processed at a low temperature and has lower charge mobility than the LTPS thin film transistor. Such an oxide semiconductor thin film transistor has excellent off-current characteristics.

[0160] A more specific stacking configuration of the pixel will be described in detail below with reference to FIG.

[0161] FIG. 13 is a diagram illustrating a method of driving the pixel shown in FIG.

[0162] Referring to both FIG. 13 and FIG. 11, one frame may include an initialization period t1, a sampling and programming period t2, and a light-emitting period t3.

[0163] During the initialization period t1, the second scan signal SC2 and the light emitting signal EM at a turn-on level (for example, a low level) are applied, and the second to fifth transistors T2, T3, T4, and T5 are turned on.

[0164] As a result, the reference voltage Vref is applied to the third node N3 through the turned-on third transistor T3, and the third node N3 may be initialized to the reference voltage Vref.

[0165] Furthermore, the reference voltage Vref is applied to the fourth node N4, the second node N2, and the first node N1 through the turned-on fifth transistor T5, the fourth transistor T4, and the second transistor T2, and the fourth node N4, the second node N2, and the first node N1 may be initialized to the reference voltage Vref. At this time, the reference voltage Vref is set lower than the threshold voltage of the light emitting element LD, and the light emitting element LD may not emit light.

[0166] During the initialization period t1, the high-potential driving voltage line PL1, the driving transistor DT, the fourth transistor T4, the fifth switching transistor T5, and the reference voltage line VrefL are substantially connected to form a current path, and the first node N1 and the third node N3 are also connected to the current path via the first switching transistor T1 and the second switching transistor T2, respectively. Therefore, the first node N1 and the third node N3 converge to any voltage between the high-potential driving voltage VDD and the reference voltage Vref, and there is no voltage difference between the two electrodes of the capacitor Cst.

[0167] During the sampling and programming period t2, the light-emitting signal EM may be switched to a turn-off level (e.g., a high level) to turn off the third transistor T3 and the fourth transistor T4, and during the sampling period t2, the first scan signal SC1 may be switched to a turn-on level to turn on the first transistor T1.

[0168] As a result, the data voltage Vdata can be applied to the first electrode of the storage capacitor Cst, i.e., the third node N3, through the turned-on first transistor T1. Also, since the second transistor T2 is turned on, the gate electrode and the second electrode of the driving transistor DT are short-circuited, so that the driving transistor DT is diode-connected.

[0169] During the sampling and programming period t2, the drive transistor DT is turned on, causing current to flow between the source and drain of the drive transistor DT (i.e., between the first and second electrodes of the drive transistor DT). At this time, since the drive transistor DT is in a diode-connected state, the voltage of the gate electrode of the drive transistor DT, i.e., the voltage of the first node N1, gradually increases. At this time, the voltage of the first node N1 increases until it reaches a voltage (VDD-Vth) corresponding to the difference between the high potential voltage VDD and the threshold voltage Vth of the drive transistor DT.

[0170] The capacitor Cst stores a voltage (VDD-Vth-Vdata) that corresponds to the voltage difference between the first node N1 and the third node N3.

[0171] Meanwhile, during the sampling and programming period t2, the anode electrode of the light emitting device LD can maintain the state of the reference voltage Vref through the fifth transistor T5 in the turned-on state.

[0172] During the light-emitting period t3, the first scan signal SC1 and the second scan signal SC2 may be switched to a turn-off level, and the light-emitting signal EM may be switched to a turn-on level, thereby turning on the third and fourth transistors T3 and T4.

[0173] As a result, the reference voltage Vref is applied to the third node N3 through the turned-on third transistor T3. As a result, the voltage of the third node N3 changes from the voltage in the previous period, i.e., the data voltage Vdata, to the reference voltage Vref. The voltage of the first node N1 also changes (VDD-Vth-Vdata+Vref) through the storage capacitor Cst in response to the voltage change of the third node N3.

[0174] Also, a current path is formed from the high potential driving voltage VDD to the light emitting element LD via the driving transistor DT through the turned-on fourth transistor T4, so that a driving current corresponding to the voltage programmed in the driving transistor DT is provided to the light emitting element LD, causing the light emitting element LD to emit light at a corresponding brightness.

[0175] Here, a high potential driving voltage VDD is applied to the first electrode, which is the source electrode of the driving transistor DT, and the first node N1, which is the gate electrode, has a changed voltage (VDD-Vth-Vdata+Vref), so the source-gate voltage Vsg of the driving transistor DT is VDD-(VDD-Vth-Vdata+Vref)=(Vdata+Vth-Vref). That is, the voltage programmed to the driving transistor DT is a voltage obtained by compensating the data voltage Vdata by the threshold voltage Vth, and therefore, degradation of the driving transistor DT can be compensated for.

[0176] FIG. 14 is a plan view of a unit pixel according to an embodiment.

[0177] FIG. 14 shows a top plan view of a unit pixel PXU in which three pixels PX1, PX2, and PX3 are arranged, and each of the pixels PX1, PX2, and PX3 includes two sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32.

[0178] Each of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 includes a light-emitting element LD (FIG. 11). Accordingly, each of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 includes an anode electrode ANO constituting the light-emitting element LD. The anode electrodes ANO of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 may have the same or different shapes and sizes. As shown in the figure, the anode electrodes ANO may have various shapes, such as a polygonal, circular, or elliptical shape, as well as shapes that are at least partially bent.

[0179] Each of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 has a light-emitting area EA defined by its corresponding light-emitting element LD. The light-emitting area EA can be defined as an area where the anode electrode ANO is exposed from above without being covered by an upper insulating layer (e.g., a bank, which will be described later). The sizes and shapes of the light-emitting areas EA of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 may be the same or different. In one embodiment, the light-emitting areas EA of the first subpixels SP11, SP21, and SP31 may be substantially circular, and the light-emitting areas of the second subpixels SP12, SP22, and SP32 may be substantially rectangular, but are not limited thereto.

[0180] The number of light-emitting regions EA provided in each of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32 may be one or more, and may be the same or different for each of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32. In one embodiment, one light-emitting region EA may be formed in a portion of the first subpixels SP11, SP21, and SP31, and multiple light-emitting regions EA may be formed in the remaining portion. In one embodiment, one light-emitting region EA may be formed in each of the second subpixels SP12, SP22, and SP32. However, the number of light-emitting regions EA is not limited to this.

[0181] In one embodiment, the first, second, and third pixels PX1, PX2, and PX3 may be red, green, and blue pixels, respectively, so that the light-emitting elements LD of the sub-pixels SP11 and SP12 of the first pixel PX1 emit red light, the light-emitting elements LD of the sub-pixels SP21 and SP22 of the second pixel PX2 emit green light, and the light-emitting elements LD of the sub-pixels SP31 and SP32 of the third pixel PX3 emit blue light.

[0182] A lens member including a plurality of lenses 501, 502 is disposed over each of the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32. The lens member may include a first lens 501 and a second lens 502 that provide different viewing angles. For example, the first lens 501 may be disposed over the light-emitting areas EA of the first sub-pixels SP11, SP21, and SP31, and the second lens 502 may be disposed over the light-emitting areas EA of the second sub-pixels SP12, SP22, and SP32.

[0183] The size and shape of the first lens 501 or the second lens 502 disposed on each light-emitting area EA may be different to provide different viewing angles. For example, the first lens 501 may be a hemispherical lens having a flat bottom surface and a spherical top surface opposite the bottom surface. For example, the second lens 502 may be a semi-cylindrical lens having a flat bottom surface and a cylindrical top surface opposite the bottom surface. However, the embodiment is not limited thereto.

[0184] The viewing angle of the display panel 50 may be controlled through the first lens 501 and the second lens 502 having different shapes. Specifically, the viewing angle limiting directions of the first lens 501 and the second lens 502 are different, and a narrow viewing angle and a wide viewing angle can be realized by selectively driving the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32.

[0185] A method for realizing a narrow viewing angle and a wide viewing angle using the lenses 501 and 502 will be described in detail below with reference to FIGS.

[0186] The number of first lenses 501 or second lenses 502 arranged over each of the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 may be the same or different depending on the number of light-emitting areas EA.

[0187] In one embodiment, one or more first lenses 501 or second lenses 502 may be arranged over each of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32. For example, one first lens 501 or one second lens 502 may be arranged over some of the subpixels SP11, SP12, SP21, SP22, SP31, and SP32, and two or more first lenses 501 or two or more second lenses 502 may be arranged over other subpixels. In the illustrated embodiment, one or more first lenses 501 are arranged over each of the first subpixels SP11, SP21, and SP31, and one second lens 502 is arranged over each of the second subpixels SP12, SP22, and SP32. However, this embodiment is not limited to this.

[0188] Fig. 15 is a diagram schematically showing the first lens shown in Fig. 14. Fig. 16 is a diagram showing a light profile with respect to the viewing angle of the first lens shown in Fig. 15. Fig. 17 is a diagram schematically showing the second lens shown in Fig. 14. Fig. 18 is a diagram showing a light profile with respect to the viewing angle of the second lens shown in Fig. 17.

[0189] 15, the first lens 501 is a hemispherical lens having a semicircular cross section in the X and Y directions. Therefore, the first lens 501 limits the viewing angle in the X and Y directions.

[0190] 17, second lens 502 is a semi-cylindrical lens that has a rectangular cross section in the X direction and a semi-circular cross section in the Y direction. Therefore, second lens 502 limits the viewing angle in the Y direction, but does not limit the viewing angle in the length direction of first lens 501, i.e., the X direction.

[0191] 16, the light-emitting regions EA11, EA21, and EA31 (FIG. 14) of the first sub-pixels SP11, SP21, and SP31 (FIG. 14) provided with the hemispherical first lenses 501 have narrow viewing angles of approximately 30 degrees or less in all directions. On the other hand, as shown in FIG. 18, the light-emitting regions EA12, EA22, and EA32 (FIG. 14) of the second sub-pixels SP12, SP22, and SP32 (FIG. 14) provided with the semi-cylindrical second lenses 502 have wide viewing angles of approximately 60 degrees or more in all directions.

[0192] Therefore, a vertical narrow field of view mode and a horizontal narrow field of view mode (i.e., privacy mode) can be realized for the first image displayed in the first sub-pixels SP11, SP21, and SP31, and a vertical narrow field of view mode and a horizontal wide field of view mode (i.e., share mode) can be realized for the second image displayed in the second sub-pixels SP12, SP22, and SP32.

[0193] In this way, the display panel 50 (FIG. 1) always has a narrow viewing angle in the vertical direction, so when applied to a vehicle, it can prevent images from being reflected by the vehicle windshield and obstructing the driving field of view.

[0194] In addition, the display panel 50 can display a first image having a narrow viewing angle in the left-right direction in the first region A1 (Figure 2) driven in the first mode, and a second image having a wide viewing angle in the left-right direction in the second region A2 (Figure 2) driven in the second mode.

[0195] Fig. 19 is a schematic cross-sectional view of a display region of a display panel according to one embodiment. Fig. 19 shows cross sections of two adjacent sub-pixels SP. In particular, Fig. 19 shows a cross section of a first sub-pixel that displays a first image.

[0196] 19, the display panel 50 may include a substrate 101, a thin film transistor 120, a light emitting element LD, an encapsulating unit 170, and a touch unit 180. However, the embodiments of the present specification are not limited thereto.

[0197] The substrate 101 may have a space thereon in which various configurations can be arranged. The substrate 101 may correspond to the planar shape of the display panel 50 in FIG. 1. In other words, the substrate 101 may be substantially rectangular or circular, but is not limited thereto. The substrate 101 may have various shapes, such as a polygonal or elliptical shape. In one embodiment, the substrate 101 may include at least one notch portion. The substrate 101 may substantially similarly include the display area AA (FIG. 2) and the non-display area NA (FIG. 2) of the display panel 50.

[0198] The substrate 101 may include one or more plastic materials such as polyimide or glass materials. For example, the substrate 101 may be a multi-substrate including a first substrate 101a, a second substrate 101b, and a third substrate 101c, but the embodiments herein are not limited thereto. For example, the substrate 101 may be a single substrate consisting of one layer.

[0199] The substrate 101 may be a rigid substrate or a flexible substrate.

[0200] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may minimize or delay the diffusion of moisture or oxygen into the substrate 101. The buffer layer 102 may be formed by alternately stacking at least one layer of silicon nitride (SiNx) and silicon oxide (SiOx), but is not limited to this.

[0201] Although FIG. 19 shows that the buffer layer 102 is formed of a multi-layer film consisting of three layers, the number of layers constituting the buffer layer 102 is not limited to this, and the buffer layer 102 may be formed of a single film.

[0202] A light-shielding layer 126 may be disposed on the buffer layer 102. The light-shielding layer 126 can prevent light from passing through the semiconductor layer 123 of the thin film transistor 120. For example, the semiconductor layer 123 may be disposed to overlap the light-shielding layer 126. The light-shielding layer 126 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited to these.

[0203] A first insulating layer 103 may be disposed on the light-shielding layer 126. The first insulating layer 103 can prevent a short circuit between the thin film transistor 120 and the light-shielding layer 126. The first insulating layer 103 may be made of the same material as the buffer layer 102, but the embodiment of the present specification is not limited thereto. For example, the first insulating layer 103 may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0204] A thin film transistor 120 may be disposed on the first insulating layer 103. The thin film transistor 120 may include a source electrode 121, a gate electrode 122, a semiconductor layer 123, and a drain electrode .

[0205] The semiconductor layer 123 may be disposed on the first insulating layer 103. The semiconductor layer 123 may include a source region, a drain region, and a channel region between the source and drain regions.

[0206] The semiconductor layer 123 may include, but is not limited to, a metal oxide semiconductor such as IGZO (Indium-Gallium-Zinc Oxide), or a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon. A polycrystalline semiconductor layer has higher mobility than an amorphous semiconductor layer and an oxide semiconductor layer, and therefore has low power consumption and excellent reliability. Therefore, the driving transistor DT (FIG. 13) may be formed of, but is not limited to, a polycrystalline semiconductor layer.

[0207] A second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be made of the same material as the first insulating layer 103, but the embodiment of the present specification is not limited thereto. The second insulating layer 104 may prevent a short circuit between the semiconductor layer 123 and other components of the first thin film transistor 120.

[0208] A gate electrode 122 may be disposed on the second insulating layer 104. The gate electrode 122 may be disposed on the second insulating layer 104 so as to overlap a channel region of the semiconductor layer 123. The gate electrode 122 may be composed of a single layer or multiple layers including, but not limited to, molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or a compound thereof. The gate electrode 122 may be disposed together with the scan line GL (FIG. 13), although embodiments herein are not limited thereto.

[0209] A third insulating layer 105 and a fourth insulating layer 106 may be disposed on the gate electrode 122. The third insulating layer 105 and the fourth insulating layer 106 may be made of the same material as the first insulating layer 103 or the second insulating layer 104, although embodiments herein are not limited thereto.

[0210] A source electrode 121 and a drain electrode 124 may be disposed on the fourth insulating layer 106. The source electrode 121 and the drain electrode 124 may be electrically connected to the semiconductor layer 123 through contact holes. The source electrode 121 and the drain electrode 124 may be formed of a metal material. For example, the source electrode 121 and the drain electrode 124 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but the embodiment of the present specification is not limited thereto.

[0211] A storage electrode 140 may be disposed spaced apart from the first thin film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0212] The first storage electrode 141 is disposed on the third insulating layer 105. The first storage electrode 141 may be formed of a metal material. For example, the first storage electrode 141 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but the embodiment of the present specification is not limited thereto. The first storage electrode 141 may be covered by the fourth insulating layer 106.

[0213] The second storage electrode 142 may be disposed on the fourth insulating layer 106 so as to overlap at least one region of the first storage electrode 141. The second storage electrode 142 may be made of, but is not limited to, the same material as the source electrode 121 and the drain electrode 124. Alternatively, the second storage electrode 142 may be made of, but is not limited to, the same material as the first storage electrode 141.

[0214] A capacitance may be formed using the fourth insulating layer 106 between the first storage electrode 141 and the second storage electrode 142 as a dielectric.

[0215] The thin film transistor 120 may be a drive transistor DT (FIG. 11), and the display panel 50 may further include a transistor (not shown).

[0216] A first protective layer 111 may be disposed on the source electrode 121 and the drain electrode 124 .

[0217] The first protective layer 111 can planarize the top of the first thin film transistor 120 and protect the first thin film transistor 120. The first protective layer 111 may be made of an organic material. For example, the first protective layer 111 may be made of an organic material including, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0218] A second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but is not limited to this.

[0219] A connection electrode 145 may be disposed between the first protective layer 111 and the second protective layer 112. The connection electrode 145 can electrically connect the thin film transistor 120 and the light emitting element LD. The connection electrode 145 may be made of, but is not limited to, the same material as the source electrode 121 and the drain electrode 124. The connection electrode 145 may be in contact with the drain electrode 124 through a contact hole formed in the first protective layer 111, thereby electrically connecting them. The connection electrode 145 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited to these.

[0220] The connection electrode 145 may be disposed together with the high potential driving voltage line PL1 and the data line DL. For example, the high potential driving voltage line PL1 and the data line DL may be formed in the same layer and made of the same material as the connection electrode 145, but is not limited to this. The connection electrode 145 may also be formed in the same layer as the low potential driving voltage line PL2 and the reference voltage line VrefL (not shown).

[0221] The light emitting element LD may be disposed on the second protective layer 112. The light emitting element LD may include an anode electrode 151, an organic layer 152, and a cathode electrode 153.

[0222] An anode electrode 151 may be disposed on the second protective layer 112. The anode electrode 151 may be electrically connected to the first thin film transistor 120 through contact holes formed in the first protective layer 111 and the second protective layer 112. The anode electrode 151 may be a reflective electrode that reflects light, but the embodiment of the present specification is not limited thereto. The anode electrode 151 may include a metal material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), or an APC alloy, and may be formed as a single layer or multiple layers, but is not limited thereto.

[0223] The bank 154 may be formed to cover the edge of the anode electrode 151 and expose at least one region on top. The bank 154 is formed to define the opening (or light-emitting region) of the sub-pixel SP. That is, the exposed region of the anode electrode 151 that is not covered by the bank 154 can define the light-emitting region of the sub-pixel SP.

[0224] The bank 154 may be made of a material containing a black pigment or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer, but the embodiments of the present specification are not limited thereto. When the bank 154 is made of a material containing a black pigment or a black dye, it may be a black bank. When the bank 154 is made of a material containing a black pigment or a black dye, it can block external light or light reflected from the outside, thereby further improving the brightness of the display device.

[0225] Spacers 155 may be further disposed on the banks 154. The spacers 155 may be made of the same material as the banks 154, but the embodiment of the present specification is not limited thereto. The spacers 155 may prevent sagging of the mask during the masking process, thereby suppressing or preventing defects such as dents and scratches on the display panel 50.

[0226] The organic layer 152 may be disposed on the exposed area of ​​the anode electrode 151 that is not covered by the bank 154. In other words, the organic layer 152 may be disposed on the anode electrode 151 that is exposed by the bank 154. In other embodiments, the organic layer 152 may be formed on the entire surface of the substrate.

[0227] The organic layer 152 may include one or more light-emitting structures (or light-emitting elements or devices) in which a hole transport layer and an electron transport layer are stacked on the anode electrode 151, in this order or in reverse order. For example, the hole transport layer may include a hole transport layer, a hole injection layer, an electron blocking layer, or a P-type charge generation layer, but the embodiments herein are not limited thereto. For example, the electron transport layer may include an electron transport layer, an electron injection layer, a hole blocking layer, or an N-type charge generation layer, but the embodiments herein are not limited thereto.

[0228] The organic layer 152 may be, but is not limited to, an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, or a micro mini light-emitting diode. For example, the organic layer 152 of the display panel 50 according to an embodiment of the present disclosure may include an organic light-emitting layer. The organic layer 152 may include, but is not limited to, a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The organic layer 152 may further include, but is not limited to, a white light-emitting layer.

[0229] A cathode electrode 153 may be disposed on the organic layer 152. The cathode electrode 153 may be a transparent electrode that transmits light, but the embodiment of the present specification is not limited thereto. For example, the cathode electrode 153 may include, but is not limited to, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a metal that transmits visible light.

[0230] A capping layer 156 may be further disposed on the cathode electrode 153. The capping layer 156 may minimize damage to the cathode electrode 153 of the light emitting device LD and the organic layer 152 below the cathode electrode 153 from an external light source. The capping layer 156 may be formed of an organic or inorganic film.

[0231] The capping layer 156 may be formed using a material such as LiF as an inorganic film, or may further include an organic film, but the embodiment of the present specification is not limited thereto. For example, the capping layer 156 may be formed of a laminated structure of an organic film and an inorganic film, and the thickness of the organic film may be different from the thickness of the inorganic film. In this case, the thickness of the organic film may be greater than the thickness of the inorganic film. In another example, the capping layer 156 may be formed of two or more layers by laminating materials with different refractive indices. This may improve the light efficiency of the display panel 50.

[0232] An encapsulating unit 170 may be disposed on the bank 154 or the light-emitting element LD. The encapsulating unit 170 may include one or more insulating layers. For example, the encapsulating unit 170 may include a first inorganic encapsulating layer 171, an organic encapsulating layer 172 on the first inorganic encapsulating layer 171, and a second inorganic encapsulating layer 173 on the organic encapsulating layer 172. The encapsulating unit 170 may include one or more inorganic material layers and one or more organic material layers. For example, the first inorganic encapsulating layer 171 and the second inorganic encapsulating layer 173 may include an inorganic material, and the organic encapsulating layer 172 may include an organic material, but is not limited to this.

[0233] Even if the first inorganic sealing layer 171 and the second inorganic sealing layer 173 are disposed to extend to the edge of the non-display area NA, the organic sealing layer 172 can terminate inside the dam portion DMP (FIG. 20). In other words, the organic sealing layer 172 may be disposed within the area surrounded by the dam portion DMP without exceeding the dam portion DMP.

[0234] A touch unit 180 may be disposed on the encapsulation unit 170. The touch unit 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulation layer 183, a black matrix BM, a second touch insulation layer 184, a second touch electrode 185, and a third touch insulation layer 186.

[0235] A touch buffer layer 181 may be disposed on the encapsulation part 170. For example, the touch buffer layer 181 may be disposed on the second inorganic encapsulation layer 173. The touch buffer layer 181 may be made of the same material as the buffer layer 102, but is not limited to this.

[0236] A first touch electrode 182 may be disposed on the touch buffer layer 181.

[0237] A first touch insulating layer 183 may be disposed on the first touch electrode 182. The first touch insulating layer 183 may be formed of, but is not limited to, silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0238] A black matrix BM may be disposed on the first touch insulating layer 183. The black matrix BM may include a material capable of absorbing light. The black matrix BM may include, but is not limited to, a black pigment or dye. The black matrix BM may prevent light leakage defects that may occur between the sub-pixels SP.

[0239] A second touch insulating layer 184 may be disposed on the black matrix BM. The second touch insulating layer 184 may include an organic insulating material. For example, the second touch insulating layer 184 may be made of, but is not limited to, photo acryl, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA).

[0240] The first touch electrode 182 and the second touch electrode 185 may include a metal material, such as, but not limited to, titanium (Ti), nickel (Ni), aluminum (Al), or an alloy thereof, or may be made up of three layers such as titanium (Ti) / aluminum (Al) / titanium (Ti).

[0241] One of the first touch electrode 182 and the second touch electrode 185 may have a touch sensing function, and the other may have a touch driving function, but is not limited thereto.

[0242] A third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may include the same material as the first touch insulating layer 183, but is not limited thereto.

[0243] A microlens ML may be disposed on the third touch insulating layer 186. The microlens ML may have a hemispherical or semi-cylindrical shape, but is not limited thereto. The shape of the microlens ML may vary depending on the size and shape of the light emitting area EA.

[0244] By arranging the microlenses ML, it is possible to ensure a wide viewing angle characteristic, improve brightness, and prevent light leakage by blocking leaked light and reflected light.

[0245] The center of the microlens ML may be aligned with the center of the corresponding light-emitting area EA. However, this embodiment is not limited to this. In other embodiments, the center of the microlens ML may be offset from the light-emitting area EA. In such embodiments, an optical element may be further disposed to direct the light emitted from the light-emitting element LD toward the microlens ML. Alternatively, the light emitted from the light-emitting element LD may be directed toward the microlens ML by tilting a portion of the light-emitting element LD.

[0246] In the illustrated embodiment, the microlens ML is a hemispherical first lens 501 (FIG. 14) disposed on the first sub-pixel SP. However, the microlens ML is not limited to this, and the microlens ML may be a semi-cylindrical second lens 502 (FIG. 14) disposed on the second sub-pixel SP.

[0247] A lens protection film 190 may be disposed on the microlenses ML. The lens protection film 190 may include, but is not limited to, an organic insulating material. The lens protection film 190 can protect the microlenses ML by covering the microlenses ML.

[0248] The refractive index of the lens protection film 190 may be smaller than the refractive index of the microlens ML. This makes it possible to prevent light that has passed through the microlens ML from being reflected in the direction of the substrate 101 due to the difference in refractive index between the microlens ML and the lens protection film 190.

[0249] Fig. 20 is a schematic cross-sectional view of a non-display area of ​​a display panel according to one embodiment. In explaining Fig. 20, the same content as that explained in the cross-sectional structure of the display area AA in Fig. 19 will be explained briefly or omitted.

[0250] Referring to Figure 20, in the non-display area NA, the display panel 50 may include, arranged in order, a substrate 101, a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, a bank 154, a sealing portion 170, a touch buffer layer 181, a first touch insulating layer 183, and a third touch insulating layer 186.

[0251] In the non-display area NA, the display panel 50 may further include a gate control transistor G120, a low potential voltage line VSSL, a dam portion DMP, and a crack prevention pattern CSP.

[0252] The gate control transistor G120 has substantially the same configuration as the transistor 120 of the sub-pixel SP, and may be formed together with the transistor 120 of the sub-pixel SP by the same process, but is not limited to this.

[0253] The gate-controlled transistor G120 may include a control source electrode G121, a control gate electrode G122, a control semiconductor layer G123, and a control drain electrode G124.

[0254] The low potential voltage line VSSL may be disposed on the fourth insulating layer 106. The low potential voltage line VSSL may be disposed in the same layer as the source electrode 121 and the drain electrode 124, may include the same material, and may be formed together with the source electrode 121 and the drain electrode 124 using one mask by the same process, but is not limited thereto.

[0255] The dam unit DMP may include a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 may overlap the low potential voltage line VSSL. The first dam DM1 may be disposed outside the second dam DM2, but is not limited to this.

[0256] The first dam DM1 may have a multi-layer structure, and each layer of the first dam DM1 may include the same material as the second protective layer 112, the banks 154, and the spacers 155, and may be formed together using one mask by the same process, but is not limited to this.

[0257] The second dam DM2 may have a multi-layer structure, and each layer of the second dam DM2 may contain the same material as the second protective layer 112 and the bank 154, and may be formed together using one mask by the same process, but is not limited to this.

[0258] The crack leaving pattern CSP may be disposed on the outermost side of the non-display area NA. The crack leaving pattern CSP can be defined by recessing at least one of the inorganic films disposed on the substrate 101.

[0259] For example, the crack leaving pattern CSP can be defined by forming a depression (recess) in the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic sealing layer 171, the second inorganic sealing layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186, but is not limited to this.

[0260] At least a portion of the inorganic film disposed on the substrate 101 may extend to the edge of the non-display area NA. In other words, at least a portion of the inorganic film disposed on the substrate 101 may extend to the edge of the substrate 101.

[0261] The buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic sealing layer 171, the second inorganic sealing layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may extend to the edges of the non-display area NA.

[0262] In other words, in the non-display area NA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic sealing layer 171, the second inorganic sealing layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may extend to the edge of the substrate 101.

[0263] In the non-display area NA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic sealing layer 171, the second inorganic sealing layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can cover substantially the entire area of ​​the substrate 101.

[0264] The respective ends (or sides) of the substrate 101, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic sealing layer 171, the second inorganic sealing layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may be aligned with each other, but this is not limited to this.

[0265] Fig. 21 shows an example of an arrangement of a display device according to an embodiment. Specifically, Fig. 21 shows a more specific example of an arrangement of the display device 1 in a vehicle.

[0266] 21, the display device 1 may be arranged in at least a part of a dashboard of a vehicle. The dashboard of a vehicle includes a configuration arranged in front of the front seats of the vehicle (e.g., driver's seat, passenger seat). For example, the dashboard of the vehicle may include an input configuration for operating various functions inside the vehicle (e.g., air conditioning, audio system, navigation system).

[0267] In one embodiment, the display device 1 is disposed on the dashboard of the vehicle and can operate as an input unit for operating at least some of the various functions of the vehicle. The display device 1 can provide various information related to the vehicle, such as vehicle operation information (e.g., current vehicle speed, remaining fuel, mileage) and vehicle part information (e.g., damage level of vehicle tires).

[0268] As shown in the figure, the display device 1 may be disposed across the driver's seat and the passenger seat, which are disposed in the front seats of the vehicle. The user of the display device 1 may include the driver of the vehicle and the passenger sitting in the passenger seat. In other words, both the driver and the passenger of the vehicle can use the display device 1.

[0269] In one embodiment, the display device 1 may be divided into a plurality of regions. For example, the display device 1 may be divided into a first region A1 and a second region A2. The first region and the second region may be divisions of the display region of the display device 1 where content is displayed. That is, the first region A1 may display a first image, and the second region A2 may display a second image. In one embodiment, the first region A1 may be disposed adjacent to the driver, and the second region A2 may be disposed adjacent to the passenger seat, but is not limited to this.

[0270] The display device 1 shown in Fig. 21 can correspond to at least a part of the display panel 50 (Fig. 2) included in the display device 1. For example, the display device 1 shown in Fig. 21 may show at least a part of the display area AA (Fig. 2) and the non-display area NA (Fig. 2) of the display panel 50. The components of the display device 1 other than those shown in Fig. 21 may be mounted inside the vehicle.

[0271] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the technical configuration of the present invention described above can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. The scope of the present invention is defined by the claims that follow rather than the above detailed description. Furthermore, any modifications or variations derived from the meaning and scope of the claims and their equivalents should be construed as being within the scope of the present invention. [Explanation of symbols]

[0272] 1:Display device 10: Timing control section 20: Gate driver 30: Data driver 31: Multiplexer 34: Output buffer 40:Power supply section 50: Display panel MUX: MUX control signal

Claims

1. a display panel on which a plurality of pixels are arranged; a data driver for providing data voltages to the pixels via a plurality of data lines; a multiplexer connected between the data driver and the plurality of data lines, the multiplexer including a plurality of switching elements controlled by a plurality of MUX control signals; Each of the plurality of pixels is a first sub-pixel for displaying a first image; a second sub-pixel that displays the same color as the first sub-pixel and that displays a second image that is different from the first image.

2. The data driver an output buffer for outputting the data voltage to an output channel; The multiplexer a first switching element that is turned on by a first MUX control signal to connect the output channel to the first sub-pixel; a second switching element that is turned on by a second MUX control signal to connect the output channel to the second sub-pixel;

3. The output buffer outputting a first data voltage corresponding to the first image in synchronization with the first MUX control signal while the pixel is driven in a first mode; The display device of claim 2 , wherein the pixel outputs a second data voltage corresponding to the second image in synchronization with the second MUX control signal while the pixel is driven in the second mode.

4. The output buffer outputting a dummy data voltage in synchronization with the second MUX control signal while the pixel is driven in the first mode; The display device according to claim 3 , wherein the pixel outputs the dummy data voltage in synchronization with the first MUX control signal while the pixel is driven in the second mode.

5. The data driver a first output buffer for outputting a first data voltage corresponding to the first image to a first output channel; a second output buffer configured to output a second data voltage corresponding to the second image to a second output channel; the first output channel is connected to the first sub-pixel; The display device of claim 1 , wherein the second output channel is connected to the second sub-pixel.

6. The first output buffer While the pixel is driven in a first mode, a first data voltage corresponding to the first image is output to the first sub-pixel; The second output buffer The display device of claim 5 , wherein a second data voltage corresponding to the second image is output to the second sub-pixel while the pixel is driven in a second mode.

7. The first output buffer outputting a dummy data voltage to the first sub-pixel while the pixel is driven in the first mode; The display device of claim 6 , wherein the dummy data voltage is output to the second sub-pixel while the pixel is driven in the second mode.

8. The multiplexer a first switching element that is turned on by a first MUX control signal to connect the first output channel to the first sub-pixel; a second switching element that is turned on by the first MUX control signal to connect the second output channel to the second sub-pixel;

9. The display panel includes: a first unit pixel and a second unit pixel each including two or more pixels; The multiplexer a first switching element that is turned on by a first MUX control signal to connect the first output channel to the first sub-pixel of the first unit pixel; a second switching element that is turned on by the first MUX control signal to connect the second output channel to the second sub-pixel of the first unit pixel; a third switching element that is turned on by a second MUX control signal to connect the first output channel to the second sub-pixel of the second unit pixel; The display device of claim 5 , further comprising: a fourth switching element that is turned on by the second MUX control signal to connect the second output channel to the second sub-pixel of the second unit pixel.

10. The display panel includes: a first region in which the first image is displayed via the first sub-pixels of the plurality of pixels; a second region in which the second image is displayed through the second sub-pixels of the plurality of pixels, The first region and the second region are The display device according to claim 1 , wherein the voltage is variable while the display panel is being driven.

11. the second sub-pixel in the first region outputs a dummy image; The display device of claim 10 , wherein the first sub-pixel in the second region outputs the dummy image.

12. the first sub-pixel and the second sub-pixel have the same pixel structure; 10. The display device of claim 1, having a mirrored configuration along the pixel column direction.

13. a lens member disposed on the display panel and including a plurality of lenses; The lens member is a first lens disposed on the first light-emitting region of the first sub-pixel; The display device according to claim 1 , further comprising: a second lens disposed on the second light-emitting region of the second sub-pixel and having a shape different from that of the first lens.

14. the first lens controls the light emitted from the first light-emitting region to a first viewing angle, and emits the light; The display device according to claim 13 , wherein the second lens controls the light emitted from the second light-emitting region to be emitted at a second viewing angle wider than the first viewing angle.

15. a display panel on which a plurality of pixels are arranged; a data driver for supplying data voltages to a plurality of data lines connected to the plurality of pixels via a plurality of output channels; a multiplexer connected between the data driver and the plurality of data lines, the multiplexer including a plurality of switching elements controlled by a plurality of MUX control signals; Each of the plurality of pixels is a first sub-pixel for displaying a first image; a second sub-pixel that displays the same color as the first sub-pixel and that displays a second image different from the first image, the data driver outputs a first data voltage corresponding to the first image to the first sub-pixel; the data driver outputting a second data voltage corresponding to the second image to the second sub-pixel.

16. The step of outputting the first data voltage includes: during a first period of a horizontal period, the multiplexer responding to a first MUX control signal to connect a first output channel to the first sub-pixel; the data driver outputs the first data voltage in synchronization with the first MUX control signal during the first period; during a second period of the one horizontal period, the multiplexer responding to a second MUX control signal to connect the first output channel to the second sub-pixel; The method of claim 15 , further comprising: during the second period, the data driver outputs a dummy data voltage in synchronization with the second MUX control signal.

17. The step of outputting the second data voltage includes: during a first period of a horizontal period, the multiplexer responding to a first MUX control signal to connect a first output channel to the first sub-pixel; the data driver outputs a dummy data voltage in synchronization with the first MUX control signal during the first period; during a second period of the one horizontal period, the multiplexer responding to a second MUX control signal to connect the first output channel to the second sub-pixel; The method of claim 15 , further comprising: during the second period, the data driver outputs the second data voltage in synchronization with the second MUX control signal.

18. The display panel includes: a first unit pixel and a second unit pixel each including two or more pixels; The step of outputting the first data voltage includes: During a first period of one horizontal period, the multiplexer connects a first output channel to the first sub-pixel of the first unit pixel in response to a first MUX control signal; during the first period, the data driver outputs the first data voltage to the first output channel in synchronization with the first MUX control signal; The step of outputting the second data voltage includes: During the first period, the multiplexer connects a second output channel to the second sub-pixel of the first unit pixel in response to the first MUX control signal; The method of claim 15 , further comprising: during the first period, the data driver outputs the second data voltage to the second output channel in synchronization with the first MUX control signal.

19. The step of outputting the first data voltage includes: during a second period of the one horizontal period, the multiplexer responding to a second MUX control signal to connect the first output channel to the first sub-pixel of the second unit pixel; during the second period, the data driver outputs the first data voltage to the first output channel in synchronization with the second MUX control signal; The step of outputting the second data voltage includes: During the second period, the multiplexer connects the second output channel to the second sub-pixel of the second unit pixel in response to the second MUX control signal; The method of claim 18 , further comprising: during the second period, the data driver outputs the second data voltage to the second output channel in synchronization with the second MUX control signal.

20. The step of outputting the first data voltage includes: the data driver outputs the first data voltage to the first sub-pixel through a first output channel during a first horizontal period; The step of outputting the second data voltage includes: The method of claim 15 , further comprising: the data driver outputting the second data voltage to the second sub-pixel through a second output channel during the first horizontal period.

Images