Semiconductor device

Abstract

To provide a semiconductor device having a novel structure.SOLUTION: The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. One memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrically connecting to a driver circuit. The wiring is in contact with the first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor, and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and is a semiconductor element ( circuits including transistors, diodes, photodiodes, etc., and devices that have such circuits. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, integrated circuits A chip with an integrated circuit or an electronic component that houses a chip in a package is a type of semiconductor device. In addition, storage devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. The body may be a semiconductor device or may have a semiconductor device. [Background technology]

[0003] Metal oxides are attracting attention as semiconductors that can be used in transistors. In-Ga-Zn oxide, also known as "Ixo," is a representative multi-component metal oxide. In research on IGZO, it was found that the IGZO is neither single crystal nor amorphous, but CAAC (c- axis aligned crystalline structure, and nc (nanocr A crystalline structure was found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in the channel formation region (hereinafter referred to as an oxide semiconductor transistor) These transistors are sometimes called "OS transistors" or "OS transistors." It has been reported that OS transistors are used (for example, Non-Patent Documents 1 and 2). Various semiconductor devices have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process for OS transistors is the same as the CMOS process used for conventional Si transistors. The OS transistor can be stacked on the Si transistor. For example, in Patent Document 1, a layer of a memory cell array having an OS transistor is formed by using a Si transistor. The document discloses a structure in which multiple layers are stacked on a substrate on which a resistor is provided. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2012 / 0063208 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. Therefore, it is possible to provide a semiconductor device or the like having a novel configuration, which can reduce manufacturing costs. Another object of one embodiment of the present invention is to provide a semiconductor device that functions as a memory device utilizing extremely small off-state current. To provide a semiconductor device having a novel configuration that is excellent in reducing power consumption in a semiconductor device. Another object of one embodiment of the present invention is to provide a memory device utilizing an extremely small off-state current. A semiconductor device having a novel configuration that can reduce the size of a functional semiconductor device. Another object of the present invention is to provide a semiconductor device or the like. In a semiconductor device that functions as a memory device, the fluctuation in the electrical characteristics of a transistor is small. An object of the present invention is to provide a semiconductor device or the like having a highly reliable and novel structure.

[0009] The description of a plurality of problems does not preclude the existence of each other. It is not necessary to solve all of the problems listed. Also, problems other than those listed may be solved by the present invention. This becomes self-evident, and such a problem can also be an object of one embodiment of the present invention. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor memory device including a first element layer having a first memory cell and a second element layer having a second memory cell. a silicon substrate having a second device layer, a third device layer having switching circuits, and a drive circuit; and the first element layer is provided between the silicon substrate and the second element layer, and the third element The silicon layer is disposed between the silicon substrate and the first device layer, and the first memory cell includes a first transistor. The first memory cell has a second transistor and a first capacitor, and the second memory cell has a second transistor and a second capacitor. a capacitor, and the switching circuit includes a first memory cell or a second memory cell, and a drive circuit a third transistor having a function of controlling the conduction state between the first transistor and the second transistor; and one of the source and drain of the second transistor, The wiring for electrically connecting to one of the source and drain of the third transistor is The other of the source and drain of the third transistor is electrically connected to the drive circuit. The wiring is connected to the first semiconductor layer of the first transistor and the second transistor. and a second semiconductor layer that is in contact with the second semiconductor layer and is perpendicular or substantially perpendicular to the surface of the silicon substrate. The semiconductor device is provided in the above-mentioned direction.

[0011] In one embodiment of the present invention, the first semiconductor layer and the second semiconductor layer each have a channel forming Semiconductor devices having metal oxide regions are preferred.

[0012] In one aspect of the present invention, the first capacitor is provided below the first semiconductor layer, and the second capacitor is provided below the first semiconductor layer. The semiconductor device is preferably one in which the capacitor is provided below the second semiconductor layer.

[0013] In one aspect of the present invention, the first capacitor is provided on the first semiconductor layer, and the second capacitor is provided on the first semiconductor layer. The semiconductor device is preferably one in which the capacitor is provided above the second semiconductor layer.

[0014] In one embodiment of the present invention, one electrode of the first capacitor is provided in the same layer as the first semiconductor layer. one electrode of the second capacitor is provided in the same layer as the second semiconductor layer, Positioning is preferred.

[0015] One aspect of the present invention is a semiconductor memory device including a first element layer having a first memory cell and a second element layer having a second memory cell. a silicon substrate having a second device layer, a third device layer having a first control circuit, and a drive circuit; and the first element layer is provided between the silicon substrate and the second element layer. the third element layer is provided between the silicon substrate and the first element layer, The first memory cell has a first transistor and a first capacitor, and the second memory cell The first control circuit includes a second transistor and a second capacitor. a third transistor for amplifying a signal read from the memory cell; one of the source or drain of the first transistor and the source or drain of the second transistor one of the first wirings is electrically connected to the gate of the third transistor, and one of the source and drain of the third transistor is electrically connected to the drive circuit. The first wiring is electrically connected to a second wiring for making the first transistor a first semiconductor layer of the second transistor and a second semiconductor layer of the second transistor; The second wiring is provided in a direction perpendicular or approximately perpendicular to the surface of the silicon substrate. The semiconductor device is provided in a direction parallel to or approximately parallel to the first wiring. .

[0016] In one embodiment of the present invention, the first control circuit includes a fourth transistor, One of the source or drain of the first transistor is connected to the source or drain of the third transistor. the other of the source or drain of the fourth transistor is electrically connected to one of the inputs. The semiconductor device is preferably electrically connected to the second wiring.

[0017] In one embodiment of the present invention, the first control circuit includes a fifth transistor and a sixth transistor. the source or drain of the fifth transistor is connected to the third transistor the other of the source or drain of the fifth transistor is electrically connected to the gate of the fifth transistor is electrically connected to the second wiring and is a source or drain of the sixth transistor. one of which is electrically connected to the other of the source or drain of the third transistor, The other of the source and the drain of the sixth transistor is electrically connected to the ground line. , semiconductor devices are preferred.

[0018] In one embodiment of the present invention, the first semiconductor layer and the second semiconductor layer each have a channel A semiconductor device having a metal oxide in the formation region is preferred.

[0019] In one embodiment of the present invention, the metal oxide is a semiconductor containing In, Ga, and Zn. Body devices are preferred.

[0020] In one aspect of the present invention, the first capacitor is provided below the first semiconductor layer. Preferably, the second capacitor is provided below the second semiconductor layer. .

[0021] In one aspect of the present invention, the first capacitor is provided in an upper layer of the first semiconductor layer. Preferably, the second capacitor is provided above the second semiconductor layer. .

[0022] In one embodiment of the present invention, one electrode of the first capacitor is the same as the first semiconductor layer. one electrode of the second capacitor is provided in the same layer as the second semiconductor layer; The semiconductor device is preferably a semiconductor device that can

[0023] One embodiment of the present invention is a semiconductor memory device including a first element layer having a first memory cell and a second element layer having a second memory cell. and a second element layer that includes the first element layer and the second element layer, the first element layer and the second element layer being stacked. The first memory cell has a first transistor and a first capacitor. The second memory cell includes a second transistor, a third transistor, a second capacitor, and one of the source and drain of the first transistor is connected to the first capacitor. One of the source and drain electrodes of the second transistor is electrically connected to the , electrically connected to the gate of the third transistor and one electrode of the second capacitor. This is a semiconductor device.

[0024] In one embodiment of the present invention, a substrate is provided, and the second element layer is a layer including the substrate and the first element. A semiconductor device is preferably provided between the substrate and the substrate layer.

[0025] In one embodiment of the present invention, the first transistor has a first semiconductor layer, and the second transistor The transistor has a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are each A semiconductor device having a metal oxide in a channel formation region is preferred.

[0026] In one embodiment of the present invention, the metal oxide is a semiconductor containing In, Ga, and Zn. Body devices are preferred.

[0027] Other aspects of the present invention will be described in the following embodiments and and as described in the drawings. [Effects of the Invention]

[0028] One embodiment of the present invention can provide a semiconductor device or the like with a novel structure. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current, It is possible to provide a semiconductor device or the like having a novel configuration, which can reduce costs. Another embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. It is possible to provide a semiconductor device or the like having a novel configuration that is excellent in low power consumption. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. It is possible to provide a semiconductor device or the like having a novel configuration that can reduce the size of the device. Another embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. A semiconductor with a novel structure in which the fluctuation in the electrical characteristics of the transistor is small and the reliability is excellent It is possible to provide a device, etc.

[0029] The description of a plurality of effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Problems, effects, and novel features other than those described above can be easily understood from the description and drawings of this specification. It will become clear as time goes by. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1A is a block diagram and FIG. 1B is a schematic diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 3] 3A and 3B are schematic diagrams showing a configuration example of a semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 5] FIG. 5 is a timing chart showing an example of the configuration of the semiconductor device. [Figure 6] FIG. 6A is a block diagram and FIG. 6B is a schematic diagram showing an example of the configuration of a semiconductor device. [Figure 7] FIG. 7 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 10] 10A and 10B are schematic diagrams showing a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a block diagram and a schematic diagram showing a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a block diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a block diagram showing a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 15] FIG. 15 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 17]FIG. 17 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 18] 18A and 18B are circuit diagrams showing an example of the configuration of a semiconductor device. [Figure 19] 19A and 19B are circuit diagrams showing an example of the configuration of a semiconductor device. [Figure 20] FIG. 20 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 21] FIG. 21 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 22] FIG. 22 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 23] FIG. 23 is a timing chart showing an example of the configuration of a semiconductor device. [Figure 24] FIG. 24 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 25] FIG. 25 is a block diagram (A) and a schematic diagram (B) showing a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 27] 27A and 27B are schematic diagrams showing a configuration example of a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a timing chart showing an example of the configuration of a semiconductor device. [Figure 30] FIG. 30 is a schematic diagram illustrating a configuration example of a semiconductor device. [Figure 31] FIG. 31 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 32] FIG. 32 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 33] FIG. 33 is a schematic diagram illustrating a configuration example of a semiconductor device. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 35]FIG. 35 is a schematic cross-sectional view (A) and a schematic cross-sectional view (B) showing a configuration example of a semiconductor device. [Figure 36] 36A, 36B, and 36C are schematic cross-sectional views showing a configuration example of a semiconductor device. [Figure 37] FIG. 37 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 39] FIG. 39 shows an example of the configuration of a semiconductor device, in which (A) is a top view, (B) is a schematic cross-sectional view, and (C) is a schematic cross-sectional view. [Figure 40] 40A to 40D are top views showing configuration examples of a semiconductor device. [Figure 41] FIG. 41 shows (A) a diagram explaining the classification of IGZO crystal structures, (B) a diagram explaining the XRD spectrum of a CAAC-IGZO film, and (C) a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 42] FIG. 42 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 43] FIG. 43 is a conceptual diagram showing a configuration example of a semiconductor device. [Figure 44] FIG. 44 is a graph (A) and a graph (B) showing a configuration example of a semiconductor device. [Figure 45] FIG. 45 is a schematic diagram (A) and a schematic diagram (B) illustrating an example of an electronic component. [Figure 46] FIG. 46 is a diagram illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0031] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified as follows. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0032] In this specification, the ordinal numbers "first," "second," and "third" refer to the constituent elements. The numbers are added to avoid confusion and do not limit the number of components. The order of the components is not limited. The element referred to as "first" in one embodiment may be used in other embodiments or in the claims. In addition, for example, the second component may be the component referred to as "second" in the specification. A component referred to as "first" in one embodiment may be used in other embodiments, or It may be omitted in the claims.

[0033] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In some cases, elements formed at the same time may be given the same reference numerals, and repeated explanations thereof will be omitted. This may occur.

[0034] In this specification, for example, the power supply potential VDD is abbreviated as potential VDD, VDD, etc. This may be due to the presence of other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.). The same applies to (etc.).

[0035] Also, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, The code is followed by an identifying code such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0036] (Embodiment 1) 1A to 1C illustrate examples of a configuration of a semiconductor device according to one embodiment of the present invention and a method for operating the semiconductor device. 1 to 5.

[0037] Semiconductor devices are devices that utilize the characteristics of semiconductors, and are made up of semiconductor elements (transistors, In this embodiment, the present invention is a circuit including a photodiode, a photodiode, or the like, and a device having the circuit. The semiconductor device to be described functions as a memory device using a transistor with extremely low off-state current. It can function as a semiconductor device.

[0038] FIG. 1A is a block diagram of a semiconductor device described in this embodiment mode. The semiconductor device 10 includes a peripheral circuit 20 and a memory cell array 30 .

[0039] The peripheral circuit 20 includes a row driver 21 and a column driver 22. The column driver 21 and the column driver 22 may be simply referred to as a drive circuit or a driver.

[0040] The row driver 21 outputs a signal to the word line WL to drive the memory cell array 30. Specifically, the row driver 21 is a circuit that outputs a signal to the word line WL (FIG. 1(A)). ) shows WL_1 and WL_N. N is a natural number greater than or equal to 2) The row driver 21 may also be called a word line side driver circuit. The decoder circuit 21 is a decoder circuit for selecting a word line WL according to a specified address. The word line WL may also be simply called a wiring.

[0041] The column driver 22 supplies a signal to the bit line BL to drive the memory cell array 30. Specifically, the column driver 22 is a circuit that outputs a signal to the bit line BL (see FIG. 1 In (A), it has the function of transmitting data signals to BL_1 and BL_2. The column driver 22 is sometimes called a bit line side drive circuit. A decoder for selecting a bit line according to a specified address is provided. The bit line BL may be simply called a wiring. The bit lines BL may be shown as thick lines or thick dotted lines to improve visibility.

[0042] The data signal applied to the bit line BL is a signal to be written to the memory cell, or The data signal corresponds to a data 1 or a data 0. The data signal will be described as a binary signal having a high or low potential. The high level potential is VDD, the low level potential is VSS, Alternatively, it may be the ground potential (GND). In addition to the data signal, there is also a precharge potential for reading data. It can be set to VDD / 2.

[0043] The memory cell array 30 includes a plurality of, for example, N layers (N is a natural number of 2 or more) of element layers 34_1 The element layer 34_1 includes one or more memory cells 31_1 to 34_N. The recell 31_1 includes a transistor 32_1 and a capacitor 33_1. The memory cell 31_N includes one or more memory cells 31_N. The capacitors are sometimes called capacitance elements. The element layer is a layer in which elements such as capacitors and transistors are provided, and is a conductive layer. It is a layer made up of materials such as metals, semiconductors, and insulators.

[0044] The transistors 32_1 to 32_N are connected to the word lines WL_1 to WL_N. Transistor 3 functions as a switch that is controlled to be on or off according to the input signal. 2_1 to 32_N, one of the source or drain is connected to one of the bit lines BL. It is connected to one (BL_1 in the figure).

[0045] The transistors 32_1 to 32_N each have an oxide semiconductor in a channel formation region. It is preferable that the optical fiber of the present invention is composed of an OS transistor (hereinafter referred to as OS transistor). In one embodiment, a memory cell including an OS transistor is used. The leakage current (hereinafter referred to as "off current") that flows between the source and drain when the device is turned off is extremely low. By using the capacitor 33_1, a charge corresponding to a desired voltage is stored in the other of the source and drain. That is, the data can be stored in the memory cells 31_1 to 31_N. This allows data to be retained for a long time once it has been written. This reduces the frequency of flashing and reduces power consumption.

[0046] In addition, in the memory cells 31_1 to 31_N using OS transistors, charge or Since data can be rewritten and read by discharging the It is possible to write and read data a limited number of times. The rechargeable cells 31_1 to 31_N are atomic memories such as magnetic memories or resistance change type memories. Since no structural changes are required at the write level, it has excellent rewrite durability. The memory cells 31_1 to 31_N using the above-mentioned method can be repeatedly rewritten like a flash memory. Even when the device is operated, no instability due to an increase in electron trap centers is observed.

[0047] The memory cells 31_1 to 31_N using OS transistors have a channel forming region On a silicon substrate with a silicon-containing transistor (hereinafter referred to as Si transistor) Since the OS transistor can be freely arranged, it can be easily integrated. can be manufactured using the same manufacturing equipment as Si transistors, making it a low-cost option. It can be made in a few minutes.

[0048] In addition to the gate electrode, source electrode, and drain electrode, the OS transistor also has a buffer When a gate electrode is included, the OS transistor can be a four-terminal semiconductor element. A current flows between the source and drain depending on the voltage applied to the gate electrode or back gate electrode. The input and output of the signals to be transmitted can be configured as an electric circuit network that can be controlled independently. Circuit design can be done with the same thinking as in I. In addition, OS transistors can be used in high-temperature environments. Specifically, it has better electrical properties than Si transistors at temperatures above 125°C. Even at high temperatures below 50°C, the ratio of on-current to off-current is large, resulting in good switching performance. A switching operation can be performed.

[0049] The memory cell shown in FIG. 1A is a DOSRAM memory using an OS transistor. (Dynamic Oxide Semiconductor Random Acce. It can be called a ss Memory. It consists of one transistor and one capacitor. This allows for higher memory density. By doing so, the data retention period can be extended. The structure is such that an insulator is sandwiched between conductors that serve as electrodes. For the material, in addition to metal, a semiconductor layer that has been given conductivity can be used. However, the capacitors 33_1 to 33_N are located above or below the transistors 32_1 to 32_N. In addition, the semiconductors constituting the transistors 32_1 to 32_N are arranged in overlapping positions below the A part of the body layer or electrode is used as one electrode of the capacitors 33_1 to 33_N. It is possible.

[0050] In each of the structures described with reference to FIG. 1A, element layers 34_1 to 34_2 according to one embodiment of the present invention are To explain _N, the schematic diagram shown in FIG. 1(B) will be used. The schematic diagram shown in Fig. 1(A) is arranged along the x-axis, y-axis, and z-axis to explain the arrangement of each component described in Fig. 1(A). For ease of understanding, the x-axis direction is defined as the depth direction in the specification. The direction of travel, the y-axis direction, and the z-axis direction are sometimes called the horizontal direction and the vertical direction, respectively.

[0051] As shown in FIG. 1B, the element layers 34_1 to 34_N are stacked in N layers. The element layers 34_1 to 34_N having the memory cells 31_1 to 31_N are respectively It has an area overlapping with the column driver 22 provided on the silicon substrate 11. As shown in the figure, the element layer 34_1 is provided between the silicon substrate 11 and the element layer 34_N. It can also be said that...

[0052] The transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the element layer 34_N are The transistor of the memory cell 31_N having the bit line BL is arranged in the vertical direction. The bit lines BL are connected to the column drivers 11 provided on the silicon substrate 11. 22.

[0053] The bit line BL_1 is connected to the semiconductor layer of the transistor and the memory cell 31_1. The bit line 31_N is provided in contact with the semiconductor layer of the transistor of the bit line 31_N. BL_1 is a source or drain of a semiconductor layer of a transistor included in the memory cell 31_1. The region functioning as a gate and the semiconductor layer of the transistor included in the memory cell 31_N are The bit line BL_ is provided in contact with the region that functions as the source or drain. 1 is a source or drain of a semiconductor layer of a transistor included in the memory cell 31_1. a conductor provided in contact with a region that functions as a transistor, and a transistor included in the memory cell 31_N. a conductor provided in contact with a region that functions as a source or a drain of the semiconductor layer of the transistor; That is, the bit line BL is provided in contact with the transistor of the memory cell 31_1. and one of the source or drain of the transistor included in the memory cell 31_N. This is a wiring for electrically connecting one of the drains and the column driver 22 in the vertical direction. It can be said that.

[0054] The bit lines BL are arranged in a direction perpendicular to the surface of the silicon substrate 11 on which the column drivers 22 are provided. It can be said that the conductors are provided extending in the vertical direction or in the substantially vertical direction. In this way, the bit line BL is connected to the transistor and the memory cell 31_1. 31_N and on the surface (xy plane) of the silicon substrate. The direction of the light source is perpendicular or approximately perpendicular (z direction) to the light source. This refers to a state in which the object is arranged at an angle of 85 degrees or more and 95 degrees or less.

[0055] The row driver 21 provided on the silicon substrate 11 and the element layers 34_1 to 34_3 The word lines WL extending in the depth direction of the element layers 34_1 to 34_N are 4_N, a region where the memory cells 31_1 to 31_N are not provided, for example, an element layer The connection may be made through openings in the outer peripheries of the element layers 34_1 to 34_N. A row driver 21 provided on the silicon substrate 11 and a word line W provided on each element layer The connection to L is made via wiring provided in the upper layer of the element layers 34_1 to 34_N. It is also possible.

[0056] According to one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used, so the refresh frequency of data stored in memory cells is low. Therefore, the semiconductor device can be reduced in power consumption. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable manner. In addition, one embodiment of the present invention is a memory. The transistors that make up the recells are arranged vertically instead of horizontally, improving memory density. Furthermore, the OS transistor can be used in high-temperature environments. Even under high temperatures, the fluctuations in electrical characteristics are smaller than those of Si transistors, making it suitable for stacking and integration. The change in the electrical characteristics of the transistor is small when the Furthermore, one embodiment of the present invention is a semiconductor device. By providing the bit lines in the vertical direction, the bipolar transistors between the memory cell array and the column drivers can be This allows the length of the bit line to be shortened, which significantly reduces the parasitic capacitance of the bit line. Even if the data signal held in the memory cell is multi-valued, the potential can be read out.

[0057] 2, the vertical direction ( A schematic diagram of a cross section of a plane parallel to the z-axis direction is shown.

[0058] As shown in FIG. 2, the semiconductor device 10 includes memory cells 31_1, 31_2, 31_3, 31_4, 31_5, 31_6, 31_7, 31_8, 31_9, 31_10, 31_11, 31_12, 31_13, 31_14, 31_15, 31_16, 31_17, 1 to 31_N and the column driver 22 provided on the silicon substrate 11 at the shortest distance. The connection can be made via a bit line BL provided in a certain vertical direction. Although the number of bit lines BL increases compared to the configuration in which the bit lines BL are arranged in the plane direction, The number of memory cells 31_1 to 31_N connected to the bit lines can be reduced. Therefore, the parasitic capacitance of the bit line BL can be reduced. Even if the capacitance of the capacitors 33_1 to 33_N included in the capacitor _N is reduced, the capacitance of the capacitor 33_1 to 33_N included in the capacitor _N is reduced due to the movement of charges. The potential of the bit line BL can be changed.

[0059] The capacitances of the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N are Therefore, the capacitors 33_1 to 33_N can be connected to the transistors 32_ The capacitors 33_1 to 33_N can be provided in the same layer as the transistors 33_1 to 33_N. By providing the transistors 32_1 to 32_N in the same layer, each element layer 34 Therefore, the semiconductor device 10 can be made smaller. This can be done.

[0060] The capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N are The transistors 32_1 to 32_N may be provided in the same layer as the transistors 32_1 to 32_N, but other configurations are also possible. For example, in the schematic diagram shown in FIG. 3A, the memory cells included in the element layers 34_1 to 34_N are The capacitor 33A of the transistor 31 is provided vertically above the transistor 32. This configuration allows for a larger capacity, so the readout This improves the reliability of the data and the data retention time. In this configuration, a capacitor 33A is provided above the transistor 32, one electrode of which is connected to a fixed potential. Since the electrodes can be arranged, the influence of external noise can be suppressed.

[0061] The schematic diagram shown in FIG. 3B shows the memory cells 31 included in the element layers 34_1 to 34_N. The capacitor 33B is disposed vertically below the transistor 32. This configuration allows for a larger capacity, so the data being read In addition, the configuration of Figure 3(B) can improve the reliability of data and the data retention time. One electrode of the transistor 32 is connected to a fixed potential between the transistor 32 and the column driver 22. Since the electrodes of the capacitor 33B can be arranged, the noise of the column driver 22 can be reduced. The influence on the memory cells 31 can be suppressed.

[0062] FIG. 4 shows a memory cell array having element layers 34_1 to 34_N as described in FIG. 1(A). A circuit configuration example of the column driver 22 connected to the memory cell. 1A and 1B are circuit diagrams for explaining a configuration example.

[0063] FIG. 4 illustrates element layers 34_1 to 34_N as the memory cell array 30. 4, a memory cell 31_N_A is illustrated as a memory cell connected to the bit line BL_A. The memory cell 31_N_A is a transistor whose gate is connected to the word line WL_A. 4, the bit line BL_B is connected to the transistor 32A and the capacitor 33. The memory cell 31_N_B is shown as an example of the memory cell. , a transistor 32B whose gate is connected to the word line WL_B, and a capacitor 33. The capacitor 33 in each element layer is connected to a wiring to which a fixed potential, for example, a ground potential, is applied. Connected to VL.

[0064] 4, the column driver 22 includes a pre-channel MOS transistor on the silicon substrate side. Charge circuit 22_1, sense amplifier 22_2, selection switch 22_3, write / read The circuit 29 is shown. The precharge circuit 22_1 and the sense amplifier 22_2 are The transistors used are Si transistors. The selection switch 22_3 is also a Si transistor. A transistor can be used.

[0065] The precharge circuit 22_1 is composed of n-channel transistors 24_1 to 24_3. The precharge circuit 22_1 receives the precharge signal applied to the precharge line PCL. Depending on the bit line signal, the bit lines BL_A and BL_B are set to a potential between VDD and VSS. This is a circuit for precharging to the intermediate potential VPC, which corresponds to VDD / 2.

[0066] The sense amplifier 22_2 is a p-channel type Transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 The wiring VHH or VLL has the function of supplying VDD or VSS. The transistors 25_1 to 25_4 are transistors that form an inverter loop. The sense amplifier 22_2 sets the word lines WL_A and WL_B to a high level. The bit lines BL_A and BL_B are changed by selecting the memory cells 31_N_A and 31_N_B. The potential of the bit line BL_B is set to the high power supply potential VDD or the low power supply potential VSS. The potentials of the line BL_A and the bit line BL_B are transmitted to the outside via the write / read circuit 29. The bit line BL_A and the bit line BL_B correspond to a bit line pair. do.

[0067] FIG. 5 shows a timing chart for explaining the operation of the circuit diagram shown in FIG. In the timing chart shown in FIG. 5, period T1 is the initialization operation, and period T2 is the write operation. The period T1 is the period during which the operation is performed, the period T2 is the period during which the operation is not performed, and the period T3 is the period during which the operation is performed when the In the description of FIG. 5, the switches 23_A and 23_B of the selection switch 22_3 are Although the explanation of B is omitted, it is turned on appropriately during the write operation and the read operation. It is selected to be.

[0068] In FIG. 5, arrows between waveforms are provided to facilitate understanding of the operation. Among the signal lines, the high level (H level) of the wiring PCL is VDD. The high level of WL is V Although HM (>VDD) is used, it can also be set to VDD.

[0069] During the period T1, the wiring VPC, wiring VHH, and wiring VLL are set to VDD / 2. The bit line BL_A is precharged to VDD / 2. This is performed by the precharge circuit 22_1. This allows the bit line BL_A (or bit line BL_B) to be precharged and the potential to be smoothed. The process is carried out.

[0070] In the period T2, when a write access occurs, the bit line BL_A (or the bit line BL This changes the wiring PCL from H level to L level. This is done by setting the word line WL_A to H level. After WL_A is selected, VHH is set to VDD and VLL is set to GND. Thus, data DA1 is written to the bit line BL_A. Then, the precharge operation of the bit line BL_A (or bit line BL_B) is started. These are precharged to VDD / 2.

[0071] During the period T3, the line PCL is at the H level and the word line WL_A is at the L level. PC, VHH and VLL are VDD / 2. The bit line pair and the local bit line pair are It is precharged to VDD / 2. By setting VHH and VLL to VDD / 2, The leakage current of the sense amplifier 22_2 can be reduced.

[0072] In the period T4, when a read access occurs, the bit line BL_A (or the bit line BL _B) from the precharge state to the floating state. Next, the word line WL_A is set to the H level. This turns on the transistor 32A. The data DA1 is written to the bit line BL_A. After the word line WL_A is set to the H level, VHH is set to VDD and VLL is set to GND, the sense amplifier 22_2 is made to function as a differential amplifier circuit, and the bit line BL_A The data DA1 on the bit line BL_A is amplified by the write / read circuit 2. Read by 9.

[0073] In the semiconductor device according to one embodiment of the present invention, a transistor provided in each element layer has an off-state current The OS transistor has extremely low resistance. Therefore, the same number of layers can be stacked on a silicon substrate. This allows the manufacturing process to be the same as that of the conventional method, thereby reducing the manufacturing cost. In one aspect of the invention, the transistors constituting the memory cells are arranged vertically rather than in a planar direction. This allows for an improvement in memory density and a reduction in the size of the device.

[0074] (Embodiment 2) Structural examples of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 6 to 10. For the components having the same reference numerals as those in the first embodiment, the description of the first embodiment is cited and will be explained below. The explanation may be omitted.

[0075] FIG. 6A shows a block diagram of a semiconductor device 10A.

[0076] The peripheral circuit 20 includes a row driver 21, a column driver 22, and a switching circuit. The switching circuit may be simply called a driving circuit. The path is a transistor having a function of controlling the conduction state between the memory cell and the column driver. It has a distaster.

[0077] The element layer 26 in which the switching circuit is provided selectively connects the column driver 22 to the bit line BL. The switching circuit has a function of connecting to the selection signal output from the column driver 22. In response to this, a predetermined bit line is connected to a driving circuit such as a sense amplifier of the column driver 22. The switching circuit functions as a multiplexer. A circuit having a function of outputting a signal to the bit line BL for driving the memory cell array 30 is.

[0078] In the semiconductor device of FIG. 6A, the element layer 26 in which the switching circuit is provided is In this case, the number of bit lines BL connected to the column driver 22 is reduced, and the data writing This can shorten the loading time and improve the reading accuracy.

[0079] The transistors constituting the switching circuit are preferably OS transistors. The element layer 26 having a switching circuit using OS transistors uses Si transistors. Since it can be freely placed on the circuit, it can be easily integrated. S transistors can be fabricated using the same manufacturing equipment as Si transistors. Therefore, it can be produced at low cost.

[0080] In each of the structures described with reference to FIG. 6A, the element layers 34_1 to 34_2 according to one embodiment of the present invention are 6B shows the element layer 26 having the switching circuit. The schematic diagram shown in FIG. 6(B) shows the respective components explained in FIG. 6(A). To explain the arrangement, the diagram corresponds to a perspective view in which the x-axis, y-axis, and z-axis directions are defined.

[0081] As shown in FIG. 6B, in the semiconductor device 10A, the transistors constituting the switching circuit The element layer 26 in which the transistor is provided is a V layer (V is a natural number equal to or greater than 1), and the element layers 34_1 to 34_2 are The layer 34_N has N layers, and the total number of layers (N+V) of OS transistors is a silicon substrate. The element layers 34_1 to 34_N are stacked on the substrate 11. 31_1 to 31_N, and an element layer in which transistors constituting the switching circuit are provided. 26 have an area overlapping with the column driver 22 provided on the silicon substrate 11. As shown in FIG. 6B, the element layer 26 is formed by bonding the silicon substrate 11 and the element layer 34_1. As shown in FIG. 6B, the element layer 34_1 is formed of silicon. It can also be said that the insulating film 34 is provided between the substrate 11 and the element layer 34_N.

[0082] The transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the element layer 34_N are The transistor of the memory cell 31_N having the bit line BL is arranged in the vertical direction. The bit line BL is connected via a transistor that constitutes a switching circuit. The element layer 26 is connected to a column driver provided on the silicon substrate 11. The hub 22 is connected to the hub 22.

[0083] The bit line BL_1 is set in contact with the semiconductor layer of the transistor included in the memory cell 31_1. Alternatively, the bit line BL_1 is connected to the half of the transistor of the memory cell 31_1. The bit line is provided in contact with the area of ​​the conductor layer that functions as the source or drain. The line BL_1 is connected to the source or drain of the semiconductor layer of the transistor included in the memory cell 31_1. The bit line is provided in contact with a conductor provided in contact with a region that functions as an in-line. BL is a signal line connecting one of the source and drain of the transistor included in the memory cell 31_1 and the memory One of the source or drain of the transistor included in the resonator 31_N and the element layer 26 It can be said that this is wiring that provides electrical connection in the vertical direction.

[0084] According to one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used, so the refresh frequency of data stored in memory cells is low. Therefore, the semiconductor device can be reduced in power consumption. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable manner. In addition, one embodiment of the present invention is a memory. The transistors that make up the recells are arranged vertically instead of horizontally, improving memory density. Furthermore, the OS transistor can be used in high-temperature environments. Even under high temperatures, the fluctuations in electrical characteristics are smaller than those of Si transistors, making it suitable for stacking and integration. The change in the electrical characteristics of the transistor is small when the The semiconductor device may be a semiconductor device.

[0085] Additionally, one aspect of the present invention includes an element layer having a switching circuit. It is possible to reduce the number of bit lines BL connected to the sense amplifiers of the column drivers. Therefore, the load on the bit line BL can be reduced. In the direction, the number of bit lines BL connected to the column driver is reduced, and data writing is This reduces the time required for writing data and improves the accuracy of reading data. Therefore, it is possible to avoid the occurrence of electrical discharge, and a semiconductor device with low power consumption can be obtained. Since it is possible to place memory cells directly above circuits such as sense amplifiers, It is possible to achieve miniaturization. In addition, even if the capacitance of the capacitor of the memory cell is reduced, it will still function. Furthermore, one embodiment of the present invention is a semiconductor memory device that is provided extending from a memory cell array. By providing the bit lines in the vertical direction, the bit lines between the memory cell array and the column driver This allows the length of the line to be shortened, which significantly reduces the parasitic capacitance of the bit line, allowing for a memory Even if the data signal held in the cell is multi-valued, the potential can be read out.

[0086] 7, the vertical direction of the semiconductor device 10A described with reference to FIGS. 6(A) and 6(B) is A schematic diagram of a cross section of a plane parallel to the (z-axis) direction is shown.

[0087] As shown in FIG. 7, the semiconductor device 10A includes memory cells 31 provided in each element layer. _1 to 31_N, the element layer 26, and the column driver 22 provided on the silicon substrate 11 and are connected via a bit line BL provided in the vertical direction, which is the shortest distance. Although the number of element layers 26 having the switching circuits 27 increases, the number of column drivers The number of bit lines BL connected to the sense amplifier 22 can be reduced. Therefore, the load on the bit line BL can be reduced.

[0088] As shown in FIG. 7, the switching circuit 27 has transistors 28_1 to 28_2. n (n is a natural number of 2 or more) corresponds to the selection signal MUX output from the column driver 22. The potential of the bit line BL selected by the signal BL_OUT is output to the column driver 22. The semiconductor device 10A shown in FIG. 7 can be represented as a unit 30_1. can be done.

[0089] FIG. 8 shows the memory cell array 30 including element layers 34_1 to 34_N as well as transistors. The circuit diagram is shown in FIG. 8, which includes the device layer 26 having the capacitors 28_a and 28_b. On the element layer 26 having the transistors 28_a and 28_b, element layers 34_1 to 34_2 are provided. _N are provided in the vertical direction, and bit lines BL_A and BL_B are provided in the vertical direction. The element layer having the switching circuit that constitutes part of the circuit is the same as the element layers 34_1 to 34_N. The bit lines BL_A and BL_B are connected to the transistors 2 8_a, 28_b.

[0090] 8, the column driver 22 includes a pre-channel FET on the silicon substrate side. A charge circuit 22_1, a sense amplifier 22_2, a switch circuit 22_3, and a write / read The precharge circuit 22_1 and the sense amplifier 22_2 are shown. The transistors used for the selection switch 22_3 are Si transistors. The source of the transistors 28_a and 28_b or The other drain is connected to a transistor that constitutes a precharge circuit 22_1 and a sense amplifier 22_2. In FIG. 8, the switch circuit 22_3 has a 3_A, the element layers 34_1 to 34_N connected to the wiring, and the element layer 26 In addition to the block shown, the wiring connected to the switch circuit 23_B included in the switch circuit 22_3 is The device layers 34_1 to 34_N connected to the lines and the block representing the device layer 26 are shown. are.

[0091] In the element layer 26 having the switching circuit, the bit line BL_A or BL_B is selected, One of a pair of wires connected to the precharge circuit 22_1 and the sense amplifier 22_2, and switch 23_A. Also, element layer 26 having another pair of switching circuits However, when the bit line BL is selected, the precharge circuit 22_1 and the sense amplifier 22_2 The other of the pair of wires connected to the selected bit is connected to the switch 23_B. The precharge voltage is applied to the memory cell by selecting the word line of the memory cell connected to the precharge voltage as high level. The potential of the bit line changes, and the precharge circuit 22_1 and the The potential of the pair of wirings connected to the sense amplifier 22_2 is either the high power supply potential VDD or the low power supply potential This potential is VSS via the switch circuit 22_3 and the write / read circuit 29. and output it to the outside.

[0092] As shown in FIG. 8, the semiconductor device 10A has an increased number of element layers 26 each having a switching circuit. However, one of the plurality of bit lines BL is selected and connected to the column driver 22. Therefore, a small number of bit lines BL can be connected to the sense amplifier 22_2. This allows a configuration in which the load on the bit line BL can be reduced.

[0093] The unit 30_1 in the semiconductor device 10A shown in FIG. 7 is stacked in the vertical direction. 9 shows a configuration in which the unit 30_1 described in FIG. 7 is arranged in M ​​stages ( The semiconductor device 10A has a stacked structure of units 30_1 to 30_M (M is 2 or more). 9 corresponds to a schematic diagram of a cross section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device. That is, the configuration of the semiconductor device 10A shown in FIG. 9 is such that the stack of element layers shown in FIG. 7 is M× It has a (N+V) layer configuration.

[0094] As shown in FIG. 9, the semiconductor device 10A includes units 30_1 to 30_M. The switching circuits 27_1 to 27_M are provided respectively. M outputs the signal BL_OUT when the selection signal MUX is input. One of the multiple wirings from which T is output is a switch circuit that can be switched by a selection signal SEL. The line 98 is selected and connected to the column driver 22 via a wiring GBL different from the bit line BL. The switch circuit 98 is connected to the OS that configures the switching circuits 27_1 to 27_M. A transistor can be used.

[0095] By adopting this configuration, the element layers 34_1 to 34_M of the units 30_1 to 30_M are Therefore, the number of stacked units 30_1 to 30_M and 34_N can be reduced. The length of each bit line BL can be shortened, and the load on the bit line BL can be reduced. In the drawings, the wiring GBL is shown as a thick line or a thick dot to improve visibility. The wiring GBL may be referred to as a global bit line.

[0096] The wiring GBL shown in FIG. 9 is provided after the element layer having the OS transistor is fabricated. For example, as shown in the schematic cross-sectional view of FIG. 10(A), An element layer having a transistor is fabricated, and an opening is provided on the periphery of the sealing layer 70A surrounding each element layer. Alternatively, the wiring GBL can be provided in the opening as shown in FIG. As shown in the schematic cross-sectional view, an element layer having an OS transistor is fabricated, and each element layer is collectively An opening can be provided on the outer periphery of the sealing layer 70B that surrounds the wiring GBL. The details of each element layer including the wiring GBL will be described in the third embodiment.

[0097] In the semiconductor device according to one embodiment of the present invention, a transistor provided in each element layer has an off-state current The OS transistor has extremely low resistance. Therefore, the same number of layers can be stacked on a silicon substrate. This allows the manufacturing process to be the same as that of the conventional method, thereby reducing the manufacturing cost. In one aspect of the invention, the transistors constituting the memory cells are arranged vertically rather than in a planar direction. This allows for an improvement in memory density and a reduction in the size of the device.

[0098] In addition, one aspect of the present invention includes an element layer having a switching circuit. In the vertical direction, the number of bit lines BL connected to the column driver is reduced, and the data This reduces the write time and improves the read accuracy. Therefore, it is possible to avoid charging and discharging the semiconductor device, and it is possible to provide a semiconductor device with low power consumption. can.

[0099] (Embodiment 3) Structural examples of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 11 to 24. The description of the first embodiment will be cited for the components denoted by the same reference numerals as in the first embodiment. The explanation may be omitted.

[0100] FIG. 11A shows a block diagram of the semiconductor device 10B.

[0101] The peripheral circuit 20 includes a row driver 21, a column driver 22, and a control circuit. The control circuit includes a sense amplifier configured with OS transistors. It has a circuit that functions as a

[0102] The element layer 40 in which the control circuit is provided is configured as a sense amplifier made up of OS transistors. The sense amplifier, which is made up of OS transistors, is a circuit that functions as a In addition to writing or reading a data signal to or from the memory cells 31_1 to 31_N, It functions as a switching circuit for selecting the units 50_1 to 50_M. 0, the column driver 22 drives a sense amplifier configured with OS transistors. The control signals WE, RE, and MUX are given to the sense amplifier. The memory cell has a transistor for controlling the reading or writing of a data signal. Therefore, it is sometimes called a control circuit.

[0103] In the semiconductor device of FIG. 11A, the control circuit can function as an amplifier. By using this configuration, the slight potential difference of the bit line BL is amplified during reading, and S It is possible to drive a sense amplifier using an i-transistor.

[0104] Furthermore, the transistors constituting the control circuit are preferably OS transistors. The element layer 40 having a control circuit using S transistors is a circuit using Si transistors. It can be freely placed on top of other devices, making integration easy. Since silicon transistors can be manufactured using the same manufacturing equipment as silicon transistors, It can be produced at low cost.

[0105] In each of the structures described in FIG. 11A, element layers 34_1 to 34_3 according to one embodiment of the present invention are 11(B) to explain the element layer 40 having the control circuit. The schematic diagram shown in FIG. 11(B) shows the respective components explained in FIG. 11(A). In order to explain the arrangement of the components, the diagram corresponds to a perspective view in which the x-axis, y-axis, and z-axis directions are defined.

[0106] As shown in FIG. 11B, in the semiconductor device 10B, the transistors constituting the control circuit The element layer 40 in which the resistor is provided is a V layer (V is a natural number equal to or greater than 1), and the element layers 34_1 to 34_3 are The layer 34_N has N layers, and the layer having a total of (N+V) layers of OS transistors is a silicon substrate. The element layers 34_1 to 34_N are stacked on the memory cell 3 1_1 to 31_N, and the element layer 40 in which the transistors constituting the control circuit are provided. , each having an area overlapping with a column driver 22 provided on the silicon substrate 11. As shown in FIG. 11(B), the element layer 40 is disposed between the silicon substrate 11 and the element layer 34_1. As shown in FIG. 11B, the element layer 34_1 is made of silicon. It can also be said that it is provided between the substrate 11 and the element layer 34_N.

[0107] The transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the element layer 34_N are The transistor of the memory cell 31_N having the bit line BL is arranged in the vertical direction. The bit line BL is connected to the transistors constituting the control circuit. The element layer 40 is connected to the wiring GBL ( The pixel electrodes 21 are connected to a column driver 22 provided on the silicon substrate 11 via a power supply (not shown). In the drawings, the wiring GBL is shown by a thick line or a thick dotted line to improve visibility. This may occur.

[0108] The bit line BL_1 is set in contact with the semiconductor layer of the transistor included in the memory cell 31_1. Alternatively, the bit line BL_1 is connected to the half of the transistor of the memory cell 31_1. The bit line is provided in contact with the area of ​​the conductor layer that functions as the source or drain. The line BL_1 is connected to the source or drain of the semiconductor layer of the transistor included in the memory cell 31_1. The bit line is provided in contact with a conductor provided in contact with a region that functions as an in-line. BL is a connection between one of the source and drain of the transistor included in the memory cell 31_1 and the One of the source or drain of the transistor included in the memory cell 31_N, and the element layer 40 , can be said to be wiring that electrically connects them in the vertical direction.

[0109] The semiconductor device 10B has one type of memory cell, but it may have two or more types of memory cells. 12A is a block diagram showing a configuration example of a semiconductor device 10C. The semiconductor device 10C is a modified example of the semiconductor device 10B. In addition to the memory cell 31, a memory cell 51 having a different configuration from the memory cell 31 is provided. The semiconductor device 10C is different from the semiconductor device 10B in that it is composed of one or more memory cells 51. The device layer 54 includes a

[0110] In the semiconductor device 10C, the element layer 54 is an element layer 34_i (i is an integer between 1 and N-1). The element layer 54 may be provided between the first and second layers (number of layers) and the element layer 34_i+1. When the semiconductor device 10C has two or more element layers 54, for example, the first The element layer 34 may be provided between the first element layer 54 and the second element layer, or may be provided It doesn't have to be.

[0111] In the semiconductor device 10C, the row driver 21 is connected to the memory cell 51 via the word line WL2. The row driver 21 of the semiconductor device 10C is electrically connected to the word line WL In addition, it has a function of outputting a signal to drive the memory cell array 30 to the word line WL2. Specifically, the row driver 21 supplies not only the word line WL but also the word line WL2 with a word line. The word line WL1 has a function of transmitting a word signal. The word line WL is provided separately from the row driver which has the function of transmitting the word signal to the word line WL. The word line WL2 may also be simply called a wiring.

[0112] FIG. 12B is a circuit diagram showing a configuration example of the memory cell 51. The memory cell 51 is The transistor 55 , the transistor 56 , and the capacitor 57 are included.

[0113] Either the source or the drain of the transistor 55 is electrically connected to the gate of the transistor 56. The gate of the transistor 56 is electrically connected to one electrode of the capacitor 57. The other of the source and drain of transistor 55 and One of the source and drain of the transistor 56 is electrically connected to the wiring BL. The other of the source and drain of the capacitor 56 is electrically connected to the wiring SL. The other electrode of the transistor 57 is electrically connected to the wiring CAL. 5, the gate of the transistor 56, and one of the capacitor elements 57. The node to which the electrode of is electrically connected is defined as node N.

[0114] The wiring CAL serves as a wiring for applying a predetermined potential to the other electrode of the capacitance element 57. When data is read from the memory cell 51, the potential of the wiring CAL is set to the potential of the memory cell When writing data to the memory cell 51 and while the data is being stored in the memory cell 51, This makes the potential of the CAL different from that of the memory cell 51. The apparent threshold voltage of the transistor 56 is set when writing data to the memory cell 51, and The apparent threshold voltage of transistor 56 while data is being stored in memory cell 51 can be made different from.

[0115] When the memory cell 51 has the configuration shown in FIG. 12(B), data is written to the memory cell 51. When writing data to the memory cell 51 or while the data is being held in the memory cell 51, Regardless of the data stored in the memory cell, no current flows between the wiring SL and the wiring BL. When reading data from the memory cell 51, the data stored in the memory cell 51 is transferred between the wiring SL and the wiring BL. A current corresponding to the input data flows.

[0116] Transistor 55 is preferably an OS transistor. The transistor has an extremely low off-state current. The charge corresponding to the charge can be held for a long time at the node N. This allows data to be retained for a long time once it has been written. This can reduce the frequency of flashes, thereby reducing the power consumption of the semiconductor device of one embodiment of the present invention.

[0117] In addition, the memory cells 51 using OS transistors can be freely arranged on a silicon substrate, etc. Since the memory cell 51 can be easily integrated, Therefore, it is preferable that the transistor 56 be an OS transistor.

[0118] The transistor 55 preferably has a back gate electrode. By controlling the applied potential, the threshold voltage of the transistor 55 can be controlled. This increases the on-current of the transistor 55 and decreases the off-current thereof, for example. When the transistor 56 is an OS transistor, the transistor It is also preferable to provide a back gate electrode at 56.

[0119] The memory cell 51 having the configuration shown in FIG. 12B is a NO type memory cell using an OS transistor as a memory. SRAM(Nonvolatile Oxide Semiconductor RAM) NOSRAM has the advantage of being able to perform non-destructive readout. On the other hand, the DOSRAM that can be applied to the memory cell 31 has a retained data. When reading data, a destructive read is performed.

[0120] The operation of the semiconductor device 10C will be described. The data written to the memory cell 30 is stored in the memory cell 31. Among the data, data that is frequently read is written from memory cell 31 to memory cell 51. As mentioned above, the memory cell 51, which is an NOSRAM, is designed to perform non-destructive readout. Therefore, the frequency of data refresh can be reduced. Therefore, the power consumption of such a semiconductor device can be reduced.

[0121] The potential of the node N is determined not only by the data written in the memory cell 51 but also by the data stored in the wiring CA Therefore, after writing data to the memory cell 51, the potential of the wiring C By adjusting the potential of AL, the data held in the memory cell 51 can be corrected. For example, when correcting data stored in the memory cell 51, The potential of the wiring CAL when reading data from the memory cell 51 is corrected by When the data is read from the memory cell 51, the potential of the wiring CAL is set to be different from that of the wiring CAL. Therefore, for example, when the data written in the memory cell is image data, The semiconductor device 10C can perform image processing. For example, it can be an image engine.

[0122] In the semiconductor device 10C, it is preferable that i is N / 2 or a value close to that. This allows, for example, the wiring distance from the memory cell 51 to the memory cell 31_1, This allows the wiring distance from the memory cell 51 to the memory cell 31_N to be shortened. Thus, data is transferred from the memory cell 51 to, for example, the memory cell 31_1 or the memory cell 31_N. This can suppress the decrease in data potential due to the wiring resistance of the wiring BL when writing data. Cut.

[0123] FIG. 13 is a block diagram showing a configuration example of the semiconductor device 10D, which is a variation of the semiconductor device 10C. The semiconductor device 10D has a structure in which the element layer 34_1 is formed before the element layer 34_1, i.e., the element layer 34_1 and the The semiconductor device 10C differs from the semiconductor device 10C in that an element layer 54 is provided between the element layer 40 and the semiconductor device 10C. .

[0124] The semiconductor device 10D has an element layer 40 in which a sense amplifier and the like are provided, and an element layer 54. This reduces the increase in the wiring resistance of the memory cell 51. This makes it possible to eliminate the difficulty in operation caused by the above-mentioned problem, and to control the operation of the memory cell 51. After the element layer 34_N, that is, for example, the element layer 54 is formed on the element layer 34_N. may be provided.

[0125] FIG. 14 is a diagram illustrating the arrangement of the components of the semiconductor device 10C shown in FIG. 12(A) along the x-axis. 15 is a perspective view of the semiconductor device 1 shown in FIG. 1 is a perspective view in which the x-axis, y-axis, and z-axis directions are defined to explain the arrangement of each component of the 0D.

[0126] The semiconductor device 10C having the configuration shown in FIG. 14 and the semiconductor device 10D having the configuration shown in FIG. In this case, the element layer 40 in which the transistors constituting the control circuit are provided is the V layer, and the element layer 34 There are N layers of element layers 34_1 to 34_N and one layer of element layer 54, for a total of (N+V+1) layers of OS layers. A layer having a transistor is stacked on the silicon substrate 11. The memory cell 51 has an area overlapping with the column driver 22 provided on the silicon substrate 11. The element layer 54 may be provided in two or more layers. For example, the element layer 54 may be an H layer (H is 1 or more). In the case where the semiconductor device 10C is provided with the element layer 54 as an H layer, 10C provides a layer having OS transistors with a total of (N+V+H) layers.

[0127] FIG. 16 is a diagram illustrating an example of the configuration of the semiconductor device 10E, showing a diagonal view in which the x-axis, y-axis, and z-axis directions are defined. In the semiconductor device 10E, the element layer 34_i may include a DOSRAM. A device layer 40 having a sense amplifier may be provided between the device layer 34_i+1 and the device layer 34_i+2. In addition, between the element layer 34_i and the element layer 40, and between the element layer 40 and the element layer 34_i+1 There may be provided device layers 541, each of which may have NOSRAM. , the device layer 40 and the device layer 54 can be provided between the two device layers 34. In the semiconductor device 10E, only one element layer 54 may be provided, or three or more element layers may be provided.

[0128] According to one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used, so the refresh frequency of data stored in memory cells is low. Therefore, the semiconductor device can be reduced in power consumption. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable manner. In addition, one embodiment of the present invention is a memory. The transistors that make up the recells are arranged vertically instead of horizontally, improving memory density. Furthermore, the OS transistor can be used in high-temperature environments. Even under high temperatures, the fluctuations in electrical characteristics are smaller than those of Si transistors, making it suitable for stacking and integration. The change in the electrical characteristics of the transistor is small when the The semiconductor device may be a semiconductor device.

[0129] In addition, one aspect of the present invention includes an element layer having a control circuit. The control circuit includes an amplifier and By using this configuration, the bit line BL can be It is possible to amplify a small potential difference and drive a sense amplifier using a Si transistor. Circuits such as sense amplifiers using Si transistors can be miniaturized, which contributes to the miniaturization of semiconductor devices. In addition, the memory cell can operate even if the capacitance of the capacitor is reduced. Furthermore, one aspect of the present invention is to provide a semiconductor memory device that extends from a memory cell array. By providing the bit lines in the vertical direction, the bit lines between the memory cell array and the column driver This allows the length of the bit line to be shortened, which significantly reduces the parasitic capacitance of the bit line, Even if the data signal held in the memory cell is multi-valued, the potential can be read out. In this way, the data stored in the memory cell can be read out as a current, making it possible to Therefore, data can be easily read even if the

[0130] In FIG. 17, the vertical direction of the semiconductor device 10B described with reference to FIGS. 11(A) and 11(B) is A schematic diagram of a cross section of a plane parallel to the perpendicular direction (z-axis direction) is shown.

[0131] As shown in FIG. 17, the semiconductor device 10B has memory cells 3 provided in each element layer. 1_1 to 31_N, an element layer 40, and a column driver 2 provided on a silicon substrate 11. 2 are connected via the bit line BL and the wiring GBL which are provided in the vertical direction, which is the shortest distance. The element layer 40 having the transistors that constitute the control circuit can be configured to be connected to the Although the number of wirings increases, the number of wirings connected to the column driver 22 in the vertical direction can be reduced. The load on the bit line BL can be reduced, which shortens the write time and It is possible to make the data easier to read.

[0132] As shown in FIG. 17, the transistors 41 to 44 included in the element layer 40 are columns. The driver 22 controls the control signals WE and RE and the selection signal MUX. Each transistor is connected to a bit line GBL in response to a control signal and a selection signal. The potential of the line BL can be output to the column driver 22. The unit 10B can be represented as a unit 50_1.

[0133] Next, the OS transistors in the element layer 40 function as sense amplifiers. For specific circuit configuration examples, please refer to Figures 18(A), (B) and 19(A), (B). This will be explained in light of the above.

[0134] FIG. 18(A) shows a unit 50 corresponding to the unit 50_1 shown in FIG. In the unit 50 shown in FIG. 19(A), the device layer 40A includes transistors 41 to 44. The transistors 41 to 44 can each be configured as an OS transistor. It is illustrated as an n-channel transistor.

[0135] During the period when a data signal is read from the memory cell, the transistor 41 A transistor that configures a source follower to amplify the wiring GBL to a potential corresponding to the potential of L. The transistor 42 is a source / drain transistor in response to a selection signal MUX input to the gate. A transistor that acts as a switch that controls the on or off state between the source and drain. The transistor 43 is turned on in response to a write control signal WE input to the gate. It is a transistor that functions as a switch that controls the on / off between the source and drain. The transistor 44 has a source and a drain that are connected in response to a read control signal RE input to the gate. The transistor functions as a switch that controls the on / off between the drain and the transistor. The source side of the transistor 44 is given a fixed ground potential GND. .

[0136] The configuration of the element layer 40A shown in FIG. 18(A) is the same as that shown in FIG. 18(B) and FIG. 19(A), The element layer 40B in FIG. 18B includes a transistor 43 The connection of one of the source or drain of the transistor 41 is made from the wiring GBL to the source or drain of the transistor 42. The element layer 40C in FIG. 19(A) is a transistor. The column driver 22 performs the function of the transistor 42, so that the configuration is equivalent to omitting the transistor 42. The element layer 40D in FIG. 19B corresponds to a configuration in which the transistor 44 is omitted.

[0137] FIG. 20 is a schematic diagram showing a configuration in which the units 50_1 described in FIG. 17 are stacked. 7, the semiconductor device 10B shown in FIG. 20 has memory cells provided in each element layer. The semiconductor device 10B shown in FIG. The vertical direction, which is the shortest distance between the modules 31_1 to 31_N and the element layers 40_1 to 40_M, is The element layer 40 is connected to the column driver via a bit line BL provided in the The configuration is such that the signal is connected to the driver 22.

[0138] Note that the units 50_1 to 50_M in the M stages in the semiconductor device 10B shown in FIG. As shown in FIG. 18, the semiconductor The device 10B includes units 50_1 to 50_M each made of an OS transistor. The device layers 40_1 to 40_M each include a circuit that functions as a sense amplifier. That is, the configuration of the semiconductor device 10B shown in FIG. 20 is the same as that of the stacked element layers shown in FIG. The structure consists of a total of M × (N + V) layers.

[0139] FIG. 21 is a schematic diagram of a configuration in which the semiconductor device 10D shown in FIG. 14 is applied as the unit 50. Each of the units 50_1 to 50_M includes an element layer 40 and an element The element layer 54 and the element layers 34_1 to 34_N are stacked in the vertical direction. The unit 50 may be the semiconductor device 10C or the semiconductor device 10E.

[0140] According to one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used, so the refresh frequency of data stored in memory cells is low. Therefore, the semiconductor device can be reduced in power consumption. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable manner. In addition, one embodiment of the present invention is a memory. The transistors that make up the recells are arranged vertically instead of horizontally, improving memory density. Furthermore, the OS transistor can be used in high-temperature environments. Even under high temperatures, the fluctuations in electrical characteristics are smaller than those of Si transistors, making it suitable for stacking and integration. The change in the electrical characteristics of the transistor is small when the The semiconductor device may be a semiconductor device.

[0141] Additionally, one aspect of the present invention includes an element layer having a control circuit. The line BL is connected to the gate of the transistor 41, so that the transistor 41 functions as an amplifier. By using this configuration, a slight voltage drop of the bit line BL during reading can be prevented. The potential difference can be amplified to drive a sense amplifier using Si transistors. This allows for the miniaturization of circuits such as sense amplifiers that use transistors, which contributes to the miniaturization of semiconductor devices. Furthermore, it is possible to operate the memory cell even if the capacitance of the capacitor is reduced. This becomes possible.

[0142] FIG. 22 shows the element layer 34_1 described in FIG. 17 which functions as the memory cell array 30. In addition to the transistors 41_a, 41_b, 42_a, 42_b, 42_c, 42_d, 42_e, 42_f, 42_i, 42_m ... 2 shows the device layer 40 having the following layers: 43_a, 43_b, 44_a, and 44_b. 2, the transistors 41_a, 41_b, 42_a, 42_b, 43_a, and 43_b are On the element layer 40 having the element layers 44_b, 44_a, and 44_b, element layers 34_1 to 34_N are provided. The bit lines BL_A and BL_B are arranged in the vertical direction. The element layer having the switching circuit constituting the element layer 34_1 to 34_N is laminated in the same manner as the element layers 34_1 to 34_N. The bit lines BL_A and BL_B are connected to the transistors 41_a, 41_b, and 41_c. It is connected to the gate of 1_b.

[0143] In addition, in FIG. 22, the transistors 42_a, 42_b, and 43_a included in the element layer 40 , 43_b are connected to the wirings GBL_A and GBL_B. BL_B is provided in the vertical direction like the bit lines BL_A and BL_B, and The driver 22 is connected to the transistor 42 in the element layer 40. The gates of _a, 42_b, 43_a, 43_b, 44_a, and 44_b are connected to the control signal WE ,RE,MUX is given.

[0144] 22 shows a circuit of the column driver 22, which is a pre-selected circuit on the silicon substrate side. A charge circuit 22_A, a precharge circuit 22_B, a sense amplifier 22_C, a switch circuit The circuit 22_D, the switch circuit 22_E, and the write / read circuit 29 are shown. The charge circuit 22_A, the precharge circuit 22_B, and the sense amplifier 22_C are configured The transistors used are Si transistors. The switches 23_A to 23_D constituting the 22_E can also be made of Si transistors. The source or drain of the transistors 42_a, 42_b, 43_a, and 43_b One includes a precharge circuit 22_A, a precharge circuit 22_B, and a sense amplifier 22_C. , and are connected to the transistors that form the switch circuit 22_D.

[0145] The precharge circuit 22_A is composed of n-channel transistors 24_1 to 24_3. The precharge circuit 22_A receives the precharge signal supplied to the precharge line PCL1. Depending on the image signal, the bit lines BL_A and BL_B are set to a voltage between VDD and VSS. This is a circuit for precharging to the intermediate potential VPC, which corresponds to the voltage VDD / 2.

[0146] The precharge circuit 22_B is composed of n-channel transistors 24_4 to 24_6. The precharge circuit 22_B receives the precharge signal from the precharge line PCL2. Depending on the message signal, the wires GBL_A and GBL_B are set to the potential V between VDD and VSS. This is a circuit for precharging to the intermediate potential VPC, which corresponds to DD / 2.

[0147] The sense amplifier 22_C is a p-channel type Transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 The wiring VHH or VLL has the function of supplying VDD or VSS. The transistors 25_1 to 25_4 are transistors that form an inverter loop. The sense amplifier 22_C sets the word lines WL_A and WL_B to a high level. The bit line BL_A changes when the memory cells 31_N_A and 31_N_B are selected. The potentials of the wiring GBL_A and the wiring GBL_B are increased according to the potential of the bit line BL_B. The power supply potential is VDD or the low power supply potential VSS. The potential is applied to the switch circuit 22_D and the switch circuit 22_E, and the write / read circuit The bit lines BL_A and BL_B can be output to the outside via the line 25. , and the wiring GBL_A and the wiring GBL_B correspond to a bit line pair. The read circuit 25 controls the writing of the data signal in response to the signal EN_data.

[0148] The switch circuit 22_D is connected to the sense amplifier 22_C and the wiring GBL_A and the wiring GBL_ The switch circuit 22_D is a circuit for controlling the conduction state between the terminals A and B. The switch 23_A and the switch 23_B are turned on or off by controlling the signal CSEL1. When 23_B is an n-channel transistor, when the switching signal CSEL1 is at a high level, When the level is low, switches 23_A and 23_B are on. When the level is low, switches 23_A and 23_B are on. The switch circuit 22_E is connected to the write / read circuit 29 and the sense amplifier 3_B. 22_C and the bit line pair connected to amplifier 22_C. The switch circuit 22_D is turned on or off under the control of a switching signal CSEL1. Switches 23_C and 23_D are the same as switches 23_A and 23_B. Similarly, it can be switched on or off by controlling CSEL2.

[0149] FIG. 23 shows a timing chart for explaining the operation of the circuit diagram shown in FIG. In the timing chart shown in Figure 23, period T11 is the write operation, period T1 The period T2 is the precharge operation of the bit line BL, the period T13 is the precharge operation of the wiring GBL, The period T14 is the charge sharing operation, the period T15 is the readout standby operation, and the period T16 corresponds to a period that describes a read operation.

[0150] In the period T11, a data signal is applied to the gate of a transistor of a memory cell to be written. The connected word line is set to a high level. At this time, the control signal WE and the signal EN_d ata is set to high level, and the data signal is sent to the memory cell via the wiring GBL and the bit line BL. Write to the rule.

[0151] During the period T12, the control signal WE is set to a high level in order to precharge the bit line BL. In this state, the precharge line PCL1 is set to high level. During a period T12, the power supply voltage is supplied to the sense amplifier 22_C. The wiring VHH or VLL that supplies the power is set to VDD / 2 to reduce the power consumption due to through current. It is preferable to suppress it.

[0152] During the period T13, the precharge line PCL2 is set to high level in order to precharge the wiring GBL. The wiring GBL is precharged to the precharge potential. Therefore, by setting both the VHH and VLL lines to VDD, the GBL line with a large load can be precharged in a short time.

[0153] The period T14 is for balancing the charges precharged on the bit line BL and the wiring GBL. For charge sharing, the control signal WL and the control signal MUX are set to high level. The bit line BL and the wiring GBL are at the same potential. During the period T14, the sense amplifier The wiring VHH or VLL that supplies the power supply voltage to 22_C is set to VDD / 2. It is preferable to suppress the power consumption due to the current flow.

[0154] During the period T15, the control signal RE is set to a high level. This is the period during which a current flows through the transistor 41 and the potential of the wiring GBL fluctuates according to the amount of the current. When the switching signal CSEL1 is set to low level, the fluctuation of the potential of the wiring GBL is detected by the sense amplifier. The wiring VHH or VLL is not affected by the period T14. It seems that

[0155] In the period T16, the switching signal CSEL1 is set to a high level, and the potential of the wiring GBL changes. is written to the memory cell by amplifying it with a bit line pair connected to the sense amplifier 22_C. The data signal is read out.

[0156] The configuration of the semiconductor device 10B shown in FIG. 17 is the same as that of the circuit of the element layer 40B shown in FIG. 18(B). When adopting this configuration, the circuit diagram can be rewritten as shown in FIG. Now, let us extract the transistors 42 of the element layers 40_1 to 40_M of each unit. , the switching circuit 49 configured by the transistor 42 is shown. 0_1 to 40_M are the element layers 40_1 to 40_M selected by the switching circuit 49. Select one of the memory cells 31_1 to 31_M selected by one of the Data signals can be written or read using the memory cells.

[0157] In the semiconductor device according to one embodiment of the present invention, a transistor provided in each element layer has an off-state current The OS transistor has extremely low resistance. Therefore, the same structure can be repeatedly formed in the vertical direction. This allows the device to be manufactured using a manufacturing process, thereby reducing manufacturing costs. In one embodiment, the transistors constituting the memory cell are arranged vertically rather than in a planar direction. This allows for an improvement in memory density and a reduction in the size of the device.

[0158] Additionally, one aspect of the present invention includes an element layer having a control circuit. The line BL is connected to the gate of the transistor 41, so that the transistor 41 functions as an amplifier. By using this configuration, a slight voltage drop of the bit line BL during reading can be prevented. The potential difference can be amplified to drive a sense amplifier using Si transistors. This allows for the miniaturization of circuits such as sense amplifiers that use transistors, which contributes to the miniaturization of semiconductor devices. Furthermore, it is possible to operate the memory cell even if the capacitance of the capacitor is reduced. This becomes possible.

[0159] (Fourth embodiment) 1A to 1C illustrate examples of a configuration of a semiconductor device according to one embodiment of the present invention and a method for operating the semiconductor device. 25 to 29. The components having the same reference numerals as those in the first embodiment are The explanation of the first embodiment will be used and may be omitted.

[0160] FIG. 25A is a block diagram of a semiconductor device described in this embodiment mode. The semiconductor device 10F shown includes a peripheral circuit 20 and a memory cell array 30.

[0161] The memory cell array 30 has a single or multiple element layers 34. The memory cells 31_1 to 31_N (N is a natural number of 2 or more) are as follows. The memory cell 31_1 includes a transistor 32_1 and a capacitor 33_1. N includes a transistor 32_N and a capacitor 33_N. The element layer is sometimes called a capacitor. It is a layer that is made of materials such as conductors, semiconductors, and insulators.

[0162] In each of the structures described in FIG. 25A, the element layer 34 according to one embodiment of the present invention will be described. For clarity, the schematic diagram shown in FIG. 25(B) will be used for explanation. In the figure, the x-axis, y-axis, and z-axis directions are defined in order to explain the arrangement of each component described in FIG. 25(A). This corresponds to the perspective view shown.

[0163] As shown in FIG. 25B, the element layer 34 having the memory cells 31_1 to 31_N is , has an area overlapping with a column driver 22 provided on the silicon substrate 11 .

[0164] The transistor of the memory cell 31_1 included in the element layer 34 is formed by vertically extending bits. The element layer 34 is connected to the column driver 22 via the bit line BL_1. The transistors 31_N are connected to the column drivers via the bit lines BL_N arranged in the vertical direction. 22. The bit lines BL_1 and BL_N and the other bit lines B L is connected to a column driver 22 provided on the silicon substrate 11.

[0165] According to one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used, so the refresh frequency of data stored in memory cells is low. Therefore, the semiconductor device can be reduced in power consumption. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable manner. In addition, one embodiment of the present invention is a memory. The transistors that make up the recells are arranged vertically instead of horizontally, improving memory density. Furthermore, the OS transistor can be used in high-temperature environments. Even under high temperatures, the fluctuations in electrical characteristics are smaller than those of Si transistors, making it suitable for stacking and integration. The change in the electrical characteristics of the transistor is small when the Furthermore, one embodiment of the present invention is a semiconductor device. By providing the bit lines in the vertical direction, the bipolar transistors between the memory cell array and the column drivers can be This allows the length of the bit line to be shortened, which significantly reduces the parasitic capacitance of the bit line. Even if the data signal held in the memory cell is multi-valued, the potential can be read out.

[0166] 26, the vertical direction of the semiconductor device 10F described with reference to FIGS. 25(A) and 25(B) is A schematic diagram of a cross section of a plane parallel to the perpendicular direction (z-axis direction) is shown.

[0167] As shown in FIG. 26, the semiconductor device 10F includes a memory cell 31 provided in an element layer 34. _1 to 31_N and the column driver 22 provided on the silicon substrate 11 at the shortest distance The connection can be made via the bit lines BL provided in the vertical direction. Although the number of bit lines increases compared to the configuration in which bit lines are arranged in the plane direction, Since the number of memory cells connected to the bit line can be reduced, the parasitic capacitance of the bit line can be reduced. Therefore, even if the capacitance of the capacitor in the memory cell is reduced, the charge The potential of the bit line can be changed in accordance with the movement.

[0168] The capacitances of the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N are Therefore, the capacitors 33_1 to 33_N can be connected to the transistors 32_ The capacitors 33_1 to 33_N can be provided in the same layer as the transistors 33_1 to 33_N. By providing the transistors 32_1 to 32_N in the same layer, each element layer 34 Therefore, the semiconductor device 10F can be made smaller. It is possible.

[0169] The capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N are The transistors 32_1 to 32_N may be provided in the same layer as the transistors 32_1 to 32_N, but other configurations are also possible. For example, in the schematic diagram shown in FIG. 27A, the memory cells included in the element layers 34_1 to 34_N are The capacitor 33A of the transistor 31 is disposed vertically above the transistor 32. This configuration allows for a larger capacity, This improves the reliability of the data stored and the data retention time. In this configuration, a capacitor 33 having one electrode connected to a fixed potential is provided above the transistor 32. Since the electrode A can be placed, the influence of external noise can be suppressed. .

[0170] 27B shows the memory cells 3 included in the element layers 34_1 to 34_N. The capacitor 33B is disposed vertically below the transistor 32. By adopting this configuration, the capacity can be increased, The reliability of data and the data retention time can be improved. In this configuration, one electrode is connected to a fixed potential between the transistor 32 and the column driver 22. Therefore, the electrode of the capacitor 33B can be arranged so that the noise of the column driver 22 can be reduced. The influence of noise on the memory cell 31 can be suppressed.

[0171] FIG. 28 shows the circuit of the memory cell array 30 having the element layer 34 described in FIG. 25(A). and a specific circuit configuration example of the column driver 22 connected to the memory cell. FIG. 1 is a circuit diagram illustrating the above.

[0172] FIG. 28 illustrates the element layer 34 as the memory cell array 30. The memory cell 31_N_A is connected to the output line BL_A. The resistor 31_N_A is connected to a transistor 32A whose gate is connected to the word line WL_A. 28 also shows the memory cell connected to the bit line BL_B. The memory cell 31_N_B has a gate The transistor 32B and capacitor 33 connected to the wire WL_B are shown. The capacitor 33 in the child layer is connected to a wiring VL to which a fixed potential, for example, a ground potential, is applied. will be done.

[0173] 28 shows a circuit of the column driver 22, which is a pre-transistor on the silicon substrate side. Charge circuit 22_1, sense amplifier 22_2, switch circuit 22_3, write / read The precharge circuit 22_1 and the sense amplifier 22_2 are configured as The transistors used for the selection switch 22_3 are Si transistors. A transistor can be used.

[0174] FIG. 29 shows a timing chart for explaining the operation of the circuit diagram shown in FIG. In the timing chart shown in Figure 29, period T1 is the initialization operation, and period T2 is the write operation. The period T1 is the write operation, the period T2 is the non-access operation, and the period T3 is the read operation. Corresponds to the interval.

[0175] In the semiconductor device according to one embodiment of the present invention, a transistor provided in each element layer has an off-state current The OS transistor has extremely low resistance. Therefore, the same number of layers can be stacked on a silicon substrate. This allows the manufacturing process to be the same as that of the conventional method, thereby reducing the manufacturing cost. In one aspect of the invention, the transistors constituting the memory cells are arranged vertically rather than in a planar direction. This allows for an improvement in memory density and a reduction in the size of the device.

[0176] (Embodiment 5) In this embodiment, a circuit modification applicable to the semiconductor device 10 described in the first embodiment is An example of this will be described with reference to FIG.

[0177] In the memory cells included in the above-described element layers 34_1 to 34_N, transistors The transistors are top-gate or bottom-gate structures without a back gate electrode. However, the structure of the transistor 32 is not limited to this. As shown in FIG. 1, the transistor of the memory cell 31 is connected to the back gate electrode line BGL. The transistor 32 may have a back gate electrode. The electrical characteristics of the transistor 32, such as the threshold voltage, can be easily controlled externally. do.

[0178] (Sixth embodiment) In this embodiment, a circuit applicable to the semiconductor device 10A described in the second embodiment is The modified example will be described with reference to FIG.

[0179] The transistors constituting the switching circuits of the element layer 26 described above have back gate electrodes. Although the transistors are shown as having either a top-gate or bottom-gate structure, The structure of the transistor is not limited to this. For example, as shown in FIG. The transistors constituting the transistors have back gate electrodes connected to the back gate electrode line BGL. The transistor 28 may have the configuration shown in FIG. Electrical properties such as threshold voltage can be easily controlled externally.

[0180] (Embodiment 7) In this embodiment, a circuit applicable to the semiconductor device 10B described in the third embodiment is The modified example will be described with reference to FIG.

[0181] In the memory cells included in the above-described element layers 34_1 to 34_N, transistors The transistors are top-gate or bottom-gate structures without a back gate electrode. However, the structure of the transistor 32 is not limited to this. As shown in FIG. 1, the transistor of the memory cell 31 is connected to the back gate electrode line BGL. The transistor 32 may have a back gate electrode. The electrical characteristics of the transistor 32, such as the threshold voltage, can be easily controlled externally. do.

[0182] (Embodiment 8) In this embodiment, a modified example of a circuit applicable to the semiconductor device described in the fourth embodiment is This will be described with reference to FIG.

[0183] In the memory cell included in the element layer 34 described above, the transistor has a back gate voltage Although the figure shows a top-gate or bottom-gate transistor without a pole, The structure of the transistor 32 is not limited to this. For example, as shown in FIG. The transistor 31 has a back gate electrode connected to the back gate electrode line BGL. By using the configuration of FIG. 33, the transistor 32 This makes it easier to externally control electrical characteristics such as the threshold voltage of the semiconductor.

[0184] (Embodiment 9) An example of a semiconductor device that functions as a memory device according to one embodiment of the present invention will be described below. Reveal.

[0185] FIG. 34 shows a semiconductor device in which a memory unit is formed on an element layer 411 having a circuit formed on a semiconductor substrate 311. The memory unit 470 (memory unit 470_1 to memory unit 470_m:m) is two or more 34 is a diagram illustrating an example of a semiconductor device in which an element layer 411 is stacked. A plurality of memory units 470 are stacked on the element layer 411. The transistor layers 413 (transistor layers 413_1 to 413_2) are connected to the transistor layer 470. memory device layers 415 ( Memory device layers 415_1 to 415_n (n is a natural number of 2 or more) In each memory unit 470, the transistor layer 413 In the example shown, the memory device layer 415 is provided on the upper surface of the semiconductor substrate 410, but this is not limited to this. The transistor layer 413 may be provided on multiple memory device layers 415. A memory device layer 415 may be provided above and below the transistor layer 413 .

[0186] The element layer 411 includes a transistor 300 provided on a semiconductor substrate 311. It can function as a circuit for the device (sometimes called a peripheral circuit). , column driver, row driver, column decoder, row decoder, sense amplifier, Charge circuit, amplifier circuit, word line driver circuit, output circuit, control logic circuit Examples include:

[0187] The transistor layer 413 includes a transistor 200T, which controls each memory unit 470. The memory device layer 415 can function as a circuit for controlling the memory device 4. The memory device 420 shown in this embodiment has a transistor 200M and a capacitor 200M. It has a capacitance element 292.

[0188] The value of m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more. It is preferably 50 or less, and more preferably 2 or more and 10 or less. There is no limitation, but it is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and The product of m and n is 4 or more and 256 or less, preferably 4 or more and 12 or less. It is 8 or less, and more preferably 4 or more and 64 or less.

[0189] FIG. 34 also shows a transistor 200T included in the memory unit and a transistor A cross-sectional view of the 200M channel length direction is shown.

[0190] As shown in FIG. 34, a transistor 300 is provided on a semiconductor substrate 311. On the memory unit 470, a transistor layer 413 and a memory device A layer 415 is provided, and the transistors included in the transistor layer 413 in one memory unit 470 are The transistor 200T and the memory device 420 included in the memory device layer 415 are The conductors 424 electrically connect the transistor 300 and each memory unit 47 The transistor 200T included in the transistor layer 413 in FIG. The conductor 426 is electrically connected to the source and drain of the transistor 200T. , and the transistor 200T through a conductor 428 electrically connected to one of the gates. The conductors 424 are preferably electrically connected to each layer of the memory device layer 415. In addition, the conductor 426 is preferably provided between the transistor layer 413 and the memory It is preferable that the light source is provided in each layer of the device layer 415.

[0191] As will be described in detail later, the side surfaces of the conductor 424 and the conductor 426 are not covered with water or It is preferable to provide an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. Examples of such insulators include silicon nitride, aluminum oxide, and silicon nitride oxide. etc. can be used.

[0192] The memory device 420 includes a transistor 200M and a capacitive element 292. The transistor 200M has the same structure as the transistor 200T of the transistor layer 413. In addition, transistor 200T and transistor 200M can be collectively referred to as transistor It is sometimes called Sta 200.

[0193] Here, the transistor 200 has a region where a channel is formed (hereinafter, referred to as a channel forming region A metal oxide (hereinafter referred to as an oxide semiconductor) that functions as an oxide semiconductor is added to a semiconductor containing It is preferable to use a conductive material.

[0194] As an oxide semiconductor, for example, In-M-Zn oxide (element M is aluminum, gallium, Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In addition, as the oxide semiconductor, a metal oxide such as indium oxide or In- Ga oxide and In-Zn oxide may also be used. By using a compound semiconductor, the on-current or field-effect mobility of the transistor can be increased. It is possible.

[0195] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Conductors can be deposited using methods such as sputtering, making them ideal for constructing highly integrated semiconductor devices. The transistor 200 can be used.

[0196] On the other hand, in a transistor using an oxide semiconductor, impurities and oxygen vacancies in the oxide semiconductor (V O The electrical characteristics of the material change depending on the oxygen vacancy. -on characteristics (a channel exists even when no voltage is applied to the gate electrode, and the transistor (characteristic of current flowing through the capacitor)

[0197] Therefore, an oxide semiconductor with a reduced impurity concentration and a reduced density of defect states is preferably used. In this specification and the like, a low impurity concentration and a low defect level density are referred to as a high purity intrinsic or or essentially high purity authentic.

[0198] Therefore, it is preferable that the impurity concentration in the oxide semiconductor be reduced as much as possible. Impurities in the oxide semiconductor include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like. Examples include metals such as iron, nickel, and silicon.

[0199] In particular, hydrogen as an impurity contained in an oxide semiconductor forms oxygen vacancies in the oxide semiconductor. In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V O It may be called H ) may generate electrons that act as carriers. In addition, some of the hydrogen atoms bond with metal atoms. It may react with oxygen to generate electrons that act as carriers.

[0200] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen has a normally-on In addition, hydrogen in the oxide semiconductor is easily degraded by stress such as heat or an electric field. Because hydrogen is easily mobile, the reliability of transistors deteriorates when a large amount of hydrogen is contained in an oxide semiconductor. There is also a risk that this may happen.

[0201] Therefore, the oxide semiconductor used in the transistor 200 does not contain impurities such as hydrogen and oxygen. It is preferable to use a high-purity intrinsic oxide semiconductor with reduced defects.

[0202] <Sealing structure> Therefore, in order to prevent the intrusion of impurities from the outside, materials that suppress the diffusion of impurities (hereinafter referred to as The transistor 200 is preferably sealed using a material having a barrier property against impurities. stomach.

[0203] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "logging."

[0204] For example, aluminum oxide is a material that has the function of suppressing the diffusion of hydrogen and oxygen. aluminum, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride Silicon nitride or silicon oxide nitride is particularly Since it has a high barrier property against hydrogen, it is preferable to use it as a sealing material.

[0205] Furthermore, for example, aluminum oxide is a material having the function of capturing and fixing hydrogen. Metal oxides such as aluminum, hafnium oxide, gallium oxide, and indium gallium zinc oxide There is.

[0206] Between the transistor 300 and the transistor 200, an insulating layer having a barrier property is provided. Preferably, an insulator 211, an insulator 212, and an insulator 214 are provided. 1. The insulator 212 and / or the insulator 214 are not subject to diffusion or permeation of impurities such as hydrogen. By using a material that suppresses over-conversion, the semiconductor substrate 311, the transistor 300, etc. This can prevent impurities such as hydrogen and water from diffusing into the transistor 200. At least one of the insulating material 211, the insulating material 212, and the insulating material 214 is made of a material that inhibits oxygen permeation. By using the material, the channel of the transistor 200 or the material included in the transistor layer 413 This can prevent oxygen from diffusing into the element layer 411. The insulator 212 is made of a material that suppresses the permeation of impurities such as hydrogen and water. It is preferable to use a material that suppresses the permeation of oxygen by using the insulator 214. It is more preferable to use a material that has absorbing and occluding properties. The insulator 212 is made of a nitride such as silicon nitride or silicon nitride oxide. The insulator 214 may be, for example, aluminum oxide, hafnium oxide, or oxide. Metal oxides such as gallium oxide and indium gallium zinc oxide can be used. In particular, it is preferable to use aluminum oxide as the insulator 214 .

[0207] In addition, the side surfaces of the transistor layer 413 and the memory device layer 415, i.e., the memory unit The sides of the unit 470 are preferably provided with an insulator 287, and the memory unit 47 It is preferable that an insulator 282 is provided on the upper surface of the insulating layer 282. It is preferable that the insulator 287 contacts the insulator 211, the insulator 212, and It is preferable that the insulator 287 and the insulator 214 are in contact with each other. It is preferable to use a material that can be used for the insulator 214 as the material 282 .

[0208] Insulators 283 and 287 are disposed so as to cover insulators 282 and 287. 84 is preferably provided, and the insulator 283 is In FIG. 34, the insulator 287 is preferably in contact with at least one of the insulators 214. The side of the insulator 214, the side of the insulator 212, and the top and side of the insulator 211 are in contact with each other. In the example in which the insulator 283 contacts the upper and side surfaces of the insulator 287 and the upper surface of the insulator 211, However, the present embodiment is not limited to this. and the top and side surfaces of the insulator 212, and the insulator 283 contacts the top and side surfaces of the insulator 287. The insulator 282 and the insulator 28 may be in contact with each other. 7, a material that can be used for the insulators 211 and 212 can be used. preferable.

[0209] In the above structure, the insulator 287 and the insulator 282 are made of a material that suppresses oxygen permeation. It is preferable to use a material that can capture hydrogen as the insulator 287 and the insulator 282. It is even more preferable to use a material that has good adhesion properties. By using a material that has the function of capturing and fixing hydrogen on the side close to the The hydrogen in the resistor 200 or the memory unit 470 is insulated by the insulator 214, the insulator 287, and insulator 282, trapping and securing the hydrogen concentration in transistor 200. In addition, hydrogen or water can be used as the insulator 283 and the insulator 284. It is preferable to use a material that inhibits the permeation of any impurities.

[0210] By adopting the above-described structure, the memory unit 470 is 2, insulator 214, insulator 287, insulator 282, insulator 283, and insulator 284 More specifically, the memory unit 470 is surrounded by the insulators 214, 287, and and an insulator 282 (sometimes referred to as a first structure), The first structure includes the insulator 211, the insulator 212, the insulator 283, and the The insulating material 284 (sometimes referred to as the second structure) surrounds the insulating material 284. A structure in which the memory unit 470 is surrounded by two or more layers of structures is called a nested structure. Here, the memory unit 470 being surrounded by multiple structures is called a memory The unit 470 may be described as being sealed by multiple insulators.

[0211] The second structure also seals the transistor 200 via the first structure. The hydrogen existing outside the second structure is absorbed by the second structure into the inside ( The diffusion of the first structure to the second structure (transistor 200 side) is suppressed. It can efficiently capture and fix hydrogen present in the internal structure of the body.

[0212] Specifically, the first structure contains a metal oxide such as aluminum oxide. The second structure may be made of a nitride such as silicon nitride. In the second embodiment, an aluminum oxide film is disposed between the transistor 200 and the silicon nitride film. It is good.

[0213] Furthermore, the material used for the structure can be used to adjust the hydrogen concentration in the film by appropriately setting the film formation conditions. can be reduced.

[0214] Generally, films formed using the CVD method have higher solubility than films formed using the sputtering method. On the other hand, the compound gas used in the CVD method often contains hydrogen, and The film formed by the VD method has a higher hydrogen content than the film formed by the sputtering method. The quantity is large.

[0215] Therefore, for example, a film having a reduced hydrogen concentration in the film adjacent to the transistor 200 may be used. (Specifically, a film formed by sputtering) is preferably used. As a film for suppressing diffusion, a film with high film coverage but a relatively high hydrogen concentration in the film (specifically When using a film formed by CVD, the hydrogen concentration is It has the function of capturing and fixing hydrogen between the highly effective and highly covering film, and also has the function of capturing and fixing hydrogen between the highly effective and highly covering film. It is advisable to provide a film with a reduced element concentration.

[0216] That is, the film disposed adjacent to the transistor 200 has a relatively low hydrogen concentration. On the other hand, a film with a relatively high hydrogen concentration in the film is preferably used at a location far from the transistor 200. It is advisable to place them apart.

[0217] Specifically, the transistor 200 is formed by a nitride film formed by a CVD method. When sealing with silicon, the transistor 200 and a nitride film formed by CVD are An aluminum oxide film formed by sputtering is placed between the silicon film. More preferably, the silicon nitride film is formed by a CVD method and the silicon nitride film is formed by a sputtering method. The aluminum oxide film formed by the sputtering method was placed between the aluminum oxide film formed by the sputtering method. A silicon nitride film may be disposed.

[0218] When forming a film using the CVD method, the film does not contain hydrogen atoms or the content of hydrogen atoms is By depositing the film using a compound gas with low hydrogen concentration, the hydrogen concentration in the deposited film is reduced. That's fine.

[0219] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device Preferably, an insulator 282 and an insulator 214 are also provided between the insulating layers 415 . In addition, it is preferable that an insulator 296 be provided between the insulator 282 and the insulator 214. The insulator 296 can be made of the same material as the insulators 283 and 284. Alternatively, silicon oxide or silicon oxynitride can be used. Insulating materials may be used. Here, insulator 282, insulator 296, and insulator 214 may be elements that constitute the transistor 200. The insulator 214 also serves as a component of the transistor 200, thereby enabling the semiconductor device to be manufactured. This is preferable because it can reduce the number of steps required.

[0220] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device Insulators 282, 296, and 214 are provided between the insulating layers 415, respectively. The side of the transistor is preferably in contact with the insulator 287. The resistor layer 413 and the memory device layer 415 are covered with the insulator 282 and the insulator 296, respectively. , insulator 214, insulator 287, insulator 283, and insulator 284. will be done.

[0221] In addition, the insulator 274 may be provided around the insulator 284. A conductor 430 is provided so as to be embedded in the insulators 284, 283, and 211. The conductor 430 may be a transistor 300, i.e., a circuit included in the element layer 411. and electrically connect it.

[0222] In the memory device layer 415, the capacitor element 292 is located in the same layer as the transistor 200M. Therefore, the height of the memory device 420 can be made to be approximately the same as that of the transistor 200M. This can prevent the height of each memory device layer 415 from becoming excessively large. This allows the number of memory device layers 415 to be increased relatively easily. For example, a stack of transistor layers 413 and memory device layers 415 is formed in 10 It may be around 0 layers.

[0223] <Transistor 200> 35A, the transistor 200T included in the transistor layer 413, and A transistor that can be used for the transistor 200M included in the memory device 420 Explain about 200.

[0224] As shown in FIG. 35(A), the transistor 200 is made up of an insulator 216 and a conductor 205 ( Conductor 205a and conductor 205b), insulator 222, insulator 224, and oxide 230 (oxide 230a, oxide 230b, and oxide 230c) and conductor 242 ( Conductor 242a and conductor 242b) and oxide 243 (oxide 243a and oxide conductor 243b), insulator 272, insulator 273, insulator 250, and conductor 260 ( conductor 260a, and conductor 260b).

[0225] The insulator 216 and the conductor 205 are provided on the insulator 214, and the insulator 27 3, an insulator 280 and an insulator 282 are provided. , and insulator 282 can be considered to be part of transistor 200. do.

[0226] In addition, in the semiconductor device of one embodiment of the present invention, a plug is electrically connected to the transistor 200. The conductor 240 (conductor 240a and conductor 240b) functions as a The insulator 241 (insulator 241a, In addition, on the insulator 282 and the conductor 240, The conductor 246 (conductor 246a) is electrically connected to the conductor 240 and functions as a wiring. , and conductor 246b).

[0227] The conductors 240a and 240b are made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing rubber as the main component. The body 240b may be a laminated structure.

[0228] In addition, when the conductor 240 has a layered structure, impurities such as water or hydrogen and oxygen It is preferable to use a conductive material that has the function of suppressing transmission. For example, tantalum, nitride tantalum oxide, titanium, titanium nitride, ruthenium, or ruthenium oxide. It is also preferable that the porous membrane has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. The conductive material may be used in a single layer or a multilayer structure. Impurities such as water or hydrogen diffused from the conductor 280 etc. are transferred to the conductor 240a and the conductor 2 40b, the insulator 230 can be further reduced from being mixed into the oxide 230. 280 from being absorbed by the conductors 240a and 240b. This can be done.

[0229] The insulator 241 provided in contact with the side surface of the conductor 240 may be, for example, silicon nitride. Silicon, aluminum oxide, silicon nitride oxide, or the like may be used. are provided in contact with the insulators 272, 273, 280, and 282. Therefore, impurities such as water or hydrogen from the insulator 280 etc. are transferred to the conductor 240a and the conductor It is possible to prevent the silicon nitride from being mixed into the oxide 230 through the body 240b. The insulator 280 is preferably made of polycarbonate because of its high blocking properties against hydrogen. This can prevent oxygen from being absorbed into the conductors 240a and 240b.

[0230] The conductor 246 is made of a conductive material based on tungsten, copper, or aluminum. The conductor may have a laminated structure, for example, titanium or Alternatively, the conductive material may be a laminate of titanium nitride and the conductive material. The insulating film may be formed so as to be embedded in the opening.

[0231] In transistor 200, conductor 260 functions as the first gate of the transistor. The conductor 205 functions as a second gate of the transistor. 2a and the conductor 242b function as a source electrode or a drain electrode.

[0232] The oxide 230 functions as a semiconductor having a channel formation region.

[0233] Insulator 250 serves as the first gate insulator and is connected to insulators 222 and 22 4 acts as the second gate insulator.

[0234] Here, the transistor 200 shown in FIG. 35(A) includes an insulator 280, an insulator 273, and an insulator The conductor 260 is formed in the openings provided in the insulator 272, the conductor 242, etc., and the oxide 230c and and insulator 250 are formed in a self-aligned manner.

[0235] That is, the conductor 260 is connected to the insulator 280 via the oxide 230c and the insulator 250. Since the conductive material 242 is formed to fill the openings provided in the conductive material 242a and the conductive material 242b, In this region, alignment of the conductor 260 is not required.

[0236] Here, it is preferable to provide an oxide 230c in an opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 are connected to the oxide 230c via the oxide 230c. 0b and the oxide 230a. Since the oxide 230c and the insulator 250 can be formed by successive film formation, Therefore, the interface between the oxide 230 and the insulator 250 can be kept clean. The effect on carrier conduction is reduced, and transistor 200 has a high on-state current and a high Wavenumber characteristics can be obtained.

[0237] In addition, in the transistor 200 shown in FIG. 35A, the bottom and side surfaces of the conductor 260 are The insulator 250 is in contact with the oxide 230c. do.

[0238] As shown in FIG. 35(A), the transistor 200 includes an insulator 282 and an oxide 2 30c are in direct contact with each other. This can suppress the diffusion of oxygen into the conductor 260.

[0239] Therefore, the oxygen contained in the insulator 280 is transferred to the oxide 230a and the oxide 230b via the oxide 230c. and oxide 230b, the oxide 230a and the oxide The oxygen vacancies in the layer 230b are reduced, and the electrical characteristics and reliability of the transistor 200 are improved. It can be done.

[0240] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0241] The transistor 200 includes an oxide 230 (oxide 230a, oxide 230b) including a channel forming region. The oxide 230c is provided with a metal oxide (hereinafter referred to as a metal oxide) that functions as an oxide semiconductor. It is preferable to use a semiconductor material other than a metal oxide semiconductor (also referred to as an oxide semiconductor).

[0242] For example, metal oxides that function as oxide semiconductors have an energy gap of 2 eV or more. It is preferable to use an energy gap of 2.5 eV or more. By using a thin metal oxide, the leakage current (on By using such a transistor, low It is possible to provide a semiconductor device with low power consumption.

[0243] Specifically, the oxide 230 is an In-M-Zn oxide (wherein the element M is aluminum, Gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel Kel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from the group consisting of tungsten, tantalum, magnesium, etc. In particular, the element M may be aluminum, gallium, yttrium, or the like. It is preferable to use thorium or tin. In addition, the oxide 230 may be an In-M oxide, an In -Zn oxide or M-Zn oxide may also be used.

[0244] As shown in FIG. 35(A), the oxide 230 is formed by the oxide 230a on the insulator 224 and the oxide 230b on the insulator 224. an oxide 230b on the oxide 230a; and a silicon dioxide film disposed on the oxide 230b, at least a portion of which is oxide. and an oxide 230c in contact with the upper surface of the oxide 230b. The side of the object 230c is made of oxide 243a, oxide 243b, conductor 242a, and conductor 242b. b, it is preferable that the insulating layer 272, the insulating layer 273, and the insulating layer 280 are provided in contact with each other. I wish.

[0245] That is, the oxide 230 is composed of an oxide 230a, an oxide 230b on the oxide 230a, and The oxide 230c is on the oxide 230b. The oxide 230a is on the oxide 230b. By having the oxide 230a, the structure formed below the oxide 230a can be transferred to the oxide 230b. The diffusion of impurities can be suppressed. By this, impurities from the structure formed above the oxide 230c are transferred to the oxide 230b. It is possible to suppress the spread of substances.

[0246] In the transistor 200, the oxide 23 is formed in the channel formation region and its vicinity. 2 shows a structure in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 230b, oxide 23 a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or For example, the oxide 230c may have a two-layer structure. In this case, a four-layer laminated structure may be provided.

[0247] The oxide 230 has a layered structure made of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. Things can be used.

[0248] Specifically, the oxide 230a has an atomic ratio of In:Ga:Zn=1:3:4. or a metal with a composition of 1:1:0.5 [atomic ratio] or a composition of 1:1:0.5 ... An oxide may be used.

[0249] The oxide 230b is In:Ga:Zn=4:2:3 [atomic ratio] or or a metal oxide having a composition of 1:1:1 [atomic ratio] or a composition of about 1:1:1. The oxide 230b may have an atomic ratio of In:Ga:Zn=5:1:3. Or a composition close to that, or In:Ga:Zn=10:1:3 [atomic ratio] or Metal oxides with compositions close to those may also be used. Oxides (e.g., In:Zn=2:1 [atomic ratio] or a composition close to that, In:Zn = 5:1 [atomic ratio] or a composition close to that, or In:Zn = 10:1 [atomic ratio] ] or a composition close thereto) may be used as the oxide 230b. may also be used.

[0250] In addition, the oxide 230c is In:Ga:Zn=1:3:4 [atomic ratio or its a composition in the vicinity of this ratio], Ga:Zn=2:1 [atomic ratio] or a composition in the vicinity of this ratio, or Ga: A metal oxide having a composition of Zn=2:5 [atomic ratio] or a composition close to that may be used. The oxide 230c is formed of a material that can be used for the oxide 230b, and may be formed as a single layer or a multilayer. For example, when the oxide 230c has a laminated structure, a specific example is In :Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and In:Ga:Zn= 1:3:4 [atomic ratio] or a laminated structure with a composition close to that, Ga:Zn=2:1 [atomic ratio] In:Ga:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof, The composition is a stacked structure with a composition close to that, Ga:Zn=2:5 [atomic ratio] or a combination close to that. and a laminated structure of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto. , gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto Examples include a laminated structure with

[0251] Note that the configuration of the OS transistor included in the memory cell array 30 shown in Embodiment 1 is The structure of the OS transistor in the element layer 40 may be different from that of the OS transistor in the memory cell layer 40. The oxide 230c of the OS transistor provided in the cell array 30 is made of In:Ga Zn=4:2:3 [atomic ratio] or a metal oxide having a composition close thereto, The oxide 230c of the OS transistor provided in SiO.sub.2 is In:Ga:Zn=5: 1:3 [atomic ratio] or a composition close to that, In:Ga:Zn=10:1:3 [atomic ratio] In:Zn=10:1 [atomic ratio] or a composition close to that. Composition: In:Zn=5:1 [atomic ratio] or a composition close to that, In:Zn=2:1 [atomic ratio] It is sufficient to use a metal oxide having a composition of [atomic number ratio] or a composition close to that ratio.

[0252] In addition, in the oxide 230b and the oxide 230c, the ratio of indium in the film is increased. This can increase the on-state current or field-effect mobility of the transistor, The aforementioned "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0253] The oxide 230b may also have crystallinity. For example, the oxide 230b may have crystallinity. S(c-axis aligned crystalline oxide semic It is preferable to use a crystalline oxide such as CAAC-OS. The material has few impurities and defects (such as oxygen vacancies), and has a highly crystalline, dense structure. Therefore, the extraction of oxygen from the oxide 230b by the source or drain electrode In addition, even if a heat treatment is performed, oxygen is not removed from the oxide 230b. Since the transistor 200 can be manufactured at high temperatures ( It is stable against the so-called thermal budget.

[0254] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Preferably, the conductor 205 is embedded in the insulator 216 .

[0255] When the conductor 205 functions as a gate electrode, the potential applied to the conductor 205 is By changing the potential applied to the transistor 20 independently of the potential applied to the transistor 260, the In particular, by applying a negative potential to the conductor 205, the threshold voltage (Vth) of By applying the voltage Vth, the Vth of the transistor 200 is increased and the off-current is reduced. Therefore, it is better to apply a negative potential to the conductor 205 than not to apply a negative potential to the conductor 205. The drain current when the potential applied to the conductor 260 is 0 V is smaller than that when the potential applied to the conductor 260 is 0 V. can be done.

[0256] As shown in FIG. 35(A), the conductor 205 is a conductor 242a of the oxide 230 and It is preferable that the area be larger than the area that does not overlap with the conductor 242b. However, the conductor 205 is in contact with the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. It is preferable that the oxide 230b extends to the outer region. The conductor 205 and the conductor 260 are disposed on the outer side of the side surface of the conductor 230 in the channel width direction. It is preferable that the conductor 205 overlaps with the insulating material interposed therebetween. Therefore, in the plasma processing in the manufacturing process after the formation of the conductor 205, local cha However, in one aspect of the present invention, The conductor 205 is not limited to this. The oxide 230 may overlap the oxide 230 located between the first and second electrodes.

[0257] In addition, with the bottom surface of the insulator 224 as a reference, the oxide 230a and the oxide 230b and the conductive The height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap is It is preferable that the bottom surface of the casing is located at a position lower than the height of the bottom surface of the casing.

[0258] Although not shown, the conductor 260 functioning as a gate in the channel width direction is The side and top surfaces of the oxide 230b in the panel formation region are covered with the oxide 230c and the insulator 250. By using a structure in which the conductor 260 is covered with the oxide 230b, the electric field generated from the conductor 260 is not generated in the oxide 230b. Therefore, the on-state voltage of the transistor 200 is increased. In this specification, the conductor 260 and the electric field of the conductor 205 electrically surrounds the channel forming region. The structure of the data is called the surrounded channel (S-channel) structure. .

[0259] The conductor 205a is a conductive material that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride may be used. The conductor 205b can be made of a material mainly containing tungsten, copper, or aluminum. It is preferable to use a conductive material that has a thickness of 100 μm. A multi-layer structure of more than one layer may also be used.

[0260] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and the oxide The insulating or conductive material located on the upper layer of the oxide semiconductor is formed by a different film without being exposed to the atmosphere. By successively depositing the seeds, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity This is preferable because a highly intrinsic oxide semiconductor film can be formed.

[0261] At least one of the insulator 222, the insulator 272 and the insulator 273 is water or Preventing impurities such as hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 222 preferably functions as a barrier insulating film that suppresses the At least one of the body 272 and the insulator 273 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, or the like. Diffusion of impurities such as atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. It is preferable to use an insulating material that has the function of suppressing diffusion (i.e., the impurities are difficult to penetrate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) can be suppressed. It is preferable to use an insulating material that has the function of preventing oxygen from permeating through the insulating material.

[0262] For example, silicon nitride or silicon nitride oxide is used as the insulator 273. The body 222 and the insulator 272 are made of aluminum oxide or hafnium oxide. It is preferable that

[0263] This allows impurities such as water or hydrogen to pass through the insulator 222 and into the transistor 200 Alternatively, oxygen contained in the insulator 224 can be prevented from diffusing to the other side. Diffusion to the substrate side via the insulator 222 can be suppressed.

[0264] In addition, impurities such as water or hydrogen are arranged via the insulators 272 and 273. This can prevent diffusion from the insulator 280 and the like to the transistor 200 side. In this way, the transistor 200 is protected from impurities such as water or hydrogen, and from the diffusion of oxygen. The structure can be such that the insulator 272 and the insulator 273 surround the insulator 272 and the insulator 273. preferable.

[0265] Here, it is preferable that the insulator 224 in contact with the oxide 230 releases oxygen by heating. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This can improve the reliability of the transistor 200.

[0266] Specifically, the insulator 224 is made of an oxide material from which part of the oxygen is released by heating. It is preferable that the oxides that desorb oxygen by heating are those that are determined by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (TDS) analysis revealed that oxygen The amount of molecules desorbed is 1.0×10 18 molecules / cm 3 More than 1.0x, preferably 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 mole cules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 That's all. The surface temperature of the film during the TDS analysis was 100°C or higher. A temperature of 700°C or lower, or a temperature in the range of 100°C to 400°C, is preferred.

[0267] The insulator 222 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 is , preferably have lower hydrogen permeability than insulator 224. 3, the insulator 224 and the oxide 230 are surrounded, and water or Impurities such as hydrogen can be prevented from entering the transistor 200.

[0268] Furthermore, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). Preferably, the body 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 2. 22, it is preferable because it can reduce the diffusion below. This can prevent the oxide 224 from reacting with the oxygen contained in the oxide 230.

[0269] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The release of impurities and the introduction of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0270] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0271] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST). For example, when the insulator 222 is a laminated layer, the insulating material may be a single layer or a laminated layer. A three-layer stack of zirconium oxide, aluminum oxide, and zirconium oxide formed in this order. layer, zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide The insulator 222 may be a four-layer laminate in which a hard film and a hard film are formed in this order. A compound containing fluorine and zirconium may also be used. As integration progresses, the gate insulator and the dielectric used in the capacitor element become thinner. This can cause problems such as leakage current in transistors and capacitors. and the use of high-k materials for the insulators that function as dielectrics in the capacitor elements. While maintaining the physical film thickness, the gate potential during transistor operation is reduced and the capacitance element is This makes it possible to secure capacity.

[0272] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. good.

[0273] Also, the oxide 230b and the conductor 242 functioning as a source electrode or a drain electrode are (conductor 242a and conductor 242b) and oxide 243 (oxide 243a and The conductor 242 and the oxide 230b may be arranged in such a manner that they are not in contact with each other. Therefore, the conductor 242 can be prevented from absorbing oxygen from the oxide 230b. This prevents oxidation of the conductor 242, thereby suppressing a decrease in the conductivity of the conductor 242. Therefore, the oxide 243 has a function of suppressing oxidation of the conductor 242. preferable.

[0274] The oxide 230b is formed between the conductor 242, which functions as a source electrode or a drain electrode. By disposing the oxide 243 having the function of suppressing the permeation of the conductor 242, the oxide This is preferable because the electrical resistance between the electrode 230b and the electrode 230a is reduced. The electrical characteristics and reliability of the transistor 200 can be improved. do.

[0275] Oxide 243 includes aluminum, gallium, yttrium, tin, copper, vanadium, Beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium Using a metal oxide containing one or more elements M selected from sodium, etc. In particular, the element M may be aluminum, gallium, yttrium, or tin. It is preferable that the oxide 243 has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. In addition, In Metal oxides such as M-Zn oxide may also be used. In the metal oxide, the atomic ratio of element M to In is In the oxide, the atomic ratio of element M to In is preferably larger than that of element M. The thickness of 43 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. m or less. In addition, it is preferable that the oxide 243 has crystallinity. When the oxide 230 has such a property, the release of oxygen from the oxide 230 can be suitably suppressed. For example, If the oxide 243 has a crystalline structure such as a hexagonal crystal, the release of oxygen from the oxide 230 can be prevented. It may be possible to suppress it.

[0276] The oxide 243 does not necessarily have to be provided. In that case, the conductor 242 (conductor 2 When the oxide 230 comes into contact with the conductive material 42a and the conductive material 242b, the oxide in the oxide 230 The element may diffuse into the conductor 242, causing the conductor 242 to oxidize. As a result, the conductivity of the conductor 242 is likely to decrease. The conductor 242 absorbs oxygen from the oxide 230. This can be rephrased.

[0277] In addition, oxygen in the oxide 230 is converted into conductor 242 (conductor 242a and conductor 242b ) to form a gap between the conductor 242a and the oxide 230b and between the conductor 242b A foreign layer may be formed between the conductive material 242 and the oxide 230b. Since the conductor 24 also contains a large amount of oxygen, it is presumed that the different layer has insulating properties. The three-layer structure of the oxide 230b, the hetero layer 230b, and the oxide 230c is a three-layer structure consisting of a metal, an insulator, and a semiconductor. It can be considered as a MIS (Metal-Insulator-Semiconductor) structure. In some cases, it is called a diode junction structure, or a MIS structure is mainly used. be.

[0278] The different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, a different layer may be formed between the conductor 242 and the oxide 230c, or between the conductor 242 and the oxide 230c. 42 and oxide 230b, and between conductor 242 and oxide 230c. There are cases where this happens.

[0279] On the oxide 243, a conductor 242 ( The conductor 242a and the conductor 242b are provided. The thickness of the conductor 242 is, for example, , 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0280] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, or the like. Tantalum oxide, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing strontium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium The oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0281] The insulator 272 is provided in contact with the upper surface of the conductor 242 and functions as a barrier layer. By adopting this configuration, the conductor 242 can effectively prevent the overcurrent of the insulator 280. Absorption of excess oxygen can be suppressed. In addition, by suppressing oxidation of the conductor 242, It is possible to suppress an increase in the contact resistance between the transistor 200 and the wiring. This can provide the transistor 200 with good electrical characteristics and reliability.

[0282] Therefore, it is preferable that the insulator 272 has a function of suppressing the diffusion of oxygen. Preferably, the insulator 272 has a function of suppressing oxygen diffusion more effectively than the insulator 280. The insulator 272 may be, for example, aluminum or hafnium. It is preferable to form an insulator containing oxide. The insulator 272 may be, for example, aluminum nitride. An insulator containing aluminum may be used.

[0283] As shown in FIG. 35(A), the insulator 272 is formed on a part of the upper surface of the conductor 242b and the Although not shown, the insulator 272 is in contact with the side surface of the conductor 242a. The insulator 272 is in contact with a part of the upper surface and the side surface of the conductor 242a. In this way, for example, oxygen added to the insulator 280 Absorption by the conductor 242 can be suppressed.

[0284] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide or silicon oxynitride. , silicon oxynitride, silicon nitride, silicon oxide with fluorine addition, carbon-added oxide silicon dioxide, silicon dioxide doped with carbon and nitrogen, and silicon dioxide with vacancies. In particular, silicon oxide and silicon oxynitride are stable to heat, This is preferable.

[0285] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing it in contact with the top surface of the oxide 230c, the channel forming region of the oxide 230b In addition, as with the insulator 224, the insulator 250 can effectively supply oxygen. It is preferable that the concentration of impurities such as water or hydrogen is reduced. , and it is preferable that the thickness is 1 nm or more and 20 nm or less.

[0286] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Moreover, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0287] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant. By making the insulating layer 250 and the metal oxide into a laminated structure, the insulating layer 250 is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0288] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more selected from the above can be used. Aluminum oxide, an insulator containing oxides of either or both aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a laminate.

[0289] Alternatively, the metal oxide may function as a part of the gate. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the conductive material on the channel forming region side, oxygen released from the conductive material can form a channel. It becomes easier to supply the area.

[0290] In particular, the metal oxide in which the channel is formed acts as a conductor that functions as a gate. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing silicon and nitrogen may also be used. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide or silicon-doped indium tin oxide may also be used. The use of such a material allows the channel to be formed. In some cases, hydrogen contained in the metal oxide formed on the surface of the catalyst can be captured. It may be possible to capture hydrogen that has entered from an insulator or the like.

[0291] Although the conductor 260 is shown as having a two-layer structure in FIG. 35(A), it may have a single-layer structure. Alternatively, it may have a laminated structure of three or more layers.

[0292] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least (i).

[0293] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can prevent the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum chloride, ruthenium, or ruthenium oxide.

[0294] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated structure. For example, it may be a laminated structure of titanium or titanium nitride and the above conductive material. stomach.

[0295] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0296] The metal oxide preferably contains at least indium or zinc. In addition to these, gallium, yttrium, and zinc are preferably contained. It is preferable that the alloy contains boron, titanium, iron, nickel, germanium, etc. nium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tungsten It contains one or more selected from the group consisting of thallium, tungsten, magnesium, etc. Good too.

[0297] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. (Element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium Aluminum, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum cerium, neodymium, hafnium, tantalum, tungsten, or magnesium In particular, the element M is aluminum. Preferably, aluminum, gallium, yttrium, or tin is used.

[0298] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0299] <Transistor 300> The transistor 300 will be described with reference to FIG. 35B. The transistor 300 is a semiconductor A conductor 316 is provided on the substrate 311 and functions as a gate. A gate insulator is provided on the substrate 311. a semiconductor region 313 formed of a portion of the semiconductor substrate 311; and a source region 314. The low resistance region 314a and the low resistance region 314b function as a gate or drain region. The transistor 300 may be either a p-channel or an n-channel type. .

[0300] Here, the transistor 300 shown in FIG. 35(B) has a semiconductor region 3 where a channel is formed. 13 (a part of the semiconductor substrate 311) has a convex shape. The upper surface of the substrate 310 is covered with a conductor 316 via an insulator 315. The conductive material 316 may be a material that can be adjusted to adjust the work function. It is also called a FIN type transistor because it utilizes the protruding portion of the semiconductor substrate 311. The insulating material is in contact with the top of the protrusion and functions as a mask for forming the protrusion. Here, a case where a protrusion is formed by processing a part of the semiconductor substrate 311 is shown. However, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0301] Note that the transistor 300 shown in FIG. 35B is an example and is not limited to this structure. Appropriate transistors may be used depending on the circuit configuration and driving method.

[0302] <Memory device 420> Next, the memory device 420 shown in FIG. 34 will be described with reference to FIG. Regarding the transistor 200M included in the memory device 420, Explanations that overlap with 0 will be omitted.

[0303] In the memory device 420, the conductor 242a of the transistor 200M is a capacitive element. 292, and the insulators 272 and 273 function as dielectrics. The conductor 242a is overlapped with the insulator 272 and the insulator 273 sandwiched therebetween. The conductor 290 is provided as shown in FIG. 2 and functions as the other electrode of the capacitor 292. 0 is used as the other electrode of the capacitance element 292 of the adjacent memory device 420. Alternatively, the conductor 290 may be the same as the conductor 290 of the adjacent memory device 420. may be electrically connected to

[0304] The conductor 290 is disposed on the upper surface of the conductor 242a with the insulators 272 and 273 sandwiched therebetween. and also disposed on the side surfaces of the conductor 242a. Since a capacitance larger than the capacitance obtained by the overlapping area of ​​a and the conductor 290 can be obtained, I wish.

[0305] The conductor 424 is electrically connected to the conductor 242b and is connected to the lower layer via the conductor 205. The conductor 424 is electrically connected to the conductor 424 located therein.

[0306] The dielectric of the capacitor element 292 may be silicon nitride, silicon nitride oxide, or aluminum oxide. and hafnium oxide. When the dielectric of the capacitance element 292 has a laminated structure, aluminum oxide and nitride A lamination of hafnium oxide and silicon oxide, or a lamination of hafnium oxide and silicon oxide can be used. For example, silicon nitride may be stacked on aluminum oxide. Alternatively, aluminum oxide may be laminated on silicon nitride.

[0307] Furthermore, as the dielectric of the capacitance element 292, zirconium oxide having a higher dielectric constant than the above materials is used. Zirconium oxide may be used as a single layer as the dielectric of the capacitance element 292. For example, zirconium oxide and aluminum oxide may be used as a laminate. The dielectric of the capacitor element 292 can be a three-layer laminate. Zirconium oxide is often used for the first layer and the third layer, and the first layer and the third layer A second layer in between may be aluminum oxide.

[0308] By using zirconium oxide having a high dielectric constant as the dielectric of the capacitance element 292, The area occupied by the capacitor element 292 in the memory device 420 can be reduced. This is preferable because it can reduce the area required for the device 420 and improve the bit cost.

[0309] The conductor 290 includes the conductor 205, the conductor 242, the conductor 260, and the conductor 42. Materials that can be used for 4 etc. can be used.

[0310] In this embodiment, the transistor 200M and the capacitor 200M are connected with the conductor 424 interposed therebetween. 92 are arranged symmetrically. By disposing the capacitor element 292, a conductor electrically connected to the transistor 200M is 424, thereby reducing the area required for the memory device 420. This is preferable because it can improve the bit cost.

[0311] When the insulator 241 is provided on the side of the conductor 424, the conductor 424 is 42b and at least a portion of the upper surface of 42b.

[0312] Conductor 424 and conductor 205 are used to connect transistors in memory unit 470. The star 200T and the memory device 420 can be electrically connected.

[0313] <Modification 1 of Memory Device 420> Next, referring to FIG. 36(B), as a modification of the memory device 420, The memory device 420A includes a transistor 200M and a transistor The capacitor 292A is electrically connected to the transistor 200M. It is located below register 200M.

[0314] In memory device 420A, conductor 242a is covered with oxide 243a, oxide 230b, The oxide 230a, the insulator 224, and the insulator 222 are disposed in openings therein. The bottom of the opening is electrically connected to the conductor 205. The conductor 205 is electrically connected to the capacitive element 292A. Connect to the target.

[0315] The capacitor 292A includes a conductor 294 that functions as one of the electrodes and a dielectric The conductor 297 has an insulator 295 that functions as the other electrode and a conductor 297 that functions as the other electrode. The conductor 297 overlaps with the conductor 294 with an insulator 295 sandwiched therebetween. 5 and electrically connected.

[0316] The conductor 294 is disposed at the bottom of an opening formed in an insulator 298 provided on an insulator 296. The insulator 295 is provided on the front and side surfaces of the insulator 298 and the conductor 294. The conductor 297 is provided so as to be embedded in a recess of the insulator 295. It can be done.

[0317] In addition, a conductor 299 is provided so as to be embedded in the insulator 296. 9 electrically connects to the conductor 294. The conductor 299 connects to the adjacent memory device 42. 0A conductor 294.

[0318] The conductor 297 is disposed on the upper surface of the conductor 294 and the lower surface of the conductor 294 with the insulator 295 sandwiched therebetween. At this time, the capacitor element 292A is formed by overlapping the conductor 294 and the conductor 297. This is preferable because it provides a larger capacity than that obtainable with a smaller area.

[0319] The insulator 295 that functions as a dielectric of the capacitance element 292A may be silicon nitride, silicon nitride oxide, or the like. Silicon oxide, aluminum oxide, hafnium oxide, etc. can be used. When the insulator 295 has a laminated structure, the oxide The stacked layers of aluminum nitride and silicon nitride, and hafnium oxide and silicon oxide are used. Here, the top and bottom of the stack is not limited. For example, nitride can be stacked on aluminum oxide. Silicon may be laminated, or aluminum oxide may be laminated on silicon nitride. stomach.

[0320] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 295. The insulator 295 may be a single layer of zirconium oxide or a laminate of zirconium oxide. For example, a laminate of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 295 may be a three-layer laminate, with the first and third layers being The second layer between the first and third layers is made of zirconium oxide. may also be used.

[0321] By using zirconium oxide having a high dielectric constant as the insulator 295, the capacitance element 2 92A can reduce the area occupied by the memory device 420A. This is preferable because it reduces the area required for 420A and improves the bit cost.

[0322] In addition, the conductor 297, the conductor 294, and the conductor 299 include the conductor 205, the conductor The material can be used for the conductive body 242, the conductive body 260, the conductive body 424, etc. Cut.

[0323] The insulator 298 may include the insulator 214, the insulator 216, the insulator 224, and the insulator Any material that can be used for the body 280 or the like can be used.

[0324] <Modification 2 of Memory Device 420> Next, referring to FIG. 36(C), as a modification of the memory device 420, The memory device 420B includes a transistor 200M and a transistor The capacitor 292B is electrically connected to the transistor 200M. It is located above register 200M.

[0325] The capacitor 292B has a conductor 276 that functions as one of the electrodes and a dielectric The conductor 278 has an insulator 277 that functions as the other electrode and a conductor 278 that functions as the other electrode. The conductor 276 overlaps with an insulator 277 sandwiched therebetween.

[0326] An insulator 275 is provided on the insulator 282, and a conductor 276 is provided between the insulator 275 and the insulator 282. 82, the insulator 280, the insulator 273, and the bottom of the opening formed in the insulator 272; The insulator 277 is provided to cover the insulator 282 and the conductor 276. The conductor 278 overlaps with the conductor 276 in the recess of the insulator 277. At least a part of the insulating material 275 is provided on the insulating material 277. The conductor 278 is connected to the capacitance element 292B of the adjacent memory device 420B. Alternatively, the conductor 278 may be used as the other pole of the adjacent memory device 420. It may be electrically connected to the conductor 278 of B.

[0327] The conductor 278 is disposed on the upper surface of the conductor 276 and the lower surface of the conductor 276 with the insulator 277 sandwiched therebetween. At this time, the capacitor element 292B is formed by overlapping the conductor 276 and the conductor 278. This is preferable because it provides a larger capacity than that obtainable with a smaller area.

[0328] In addition, an insulator 279 may be provided so as to fill the recessed portion of the conductor 278 .

[0329] The insulator 277 that functions as a dielectric of the capacitance element 292B may be silicon nitride, silicon nitride oxide, or the like. Silicon oxide, aluminum oxide, hafnium oxide, etc. can be used. When the insulator 277 has a laminated structure, the oxide The stacked layers of aluminum nitride and silicon nitride, and hafnium oxide and silicon oxide are used. Here, the top and bottom of the stack is not limited. For example, nitride can be stacked on aluminum oxide. Silicon may be laminated, or aluminum oxide may be laminated on silicon nitride. stomach.

[0330] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 277. The insulator 277 may be made of zirconium oxide in a single layer or in a multilayer structure. For example, a laminate of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 277 may be a three-layer laminate, with the first and third layers being The second layer between the first and third layers is made of zirconium oxide. may also be used.

[0331] By using zirconium oxide having a high dielectric constant as the insulator 277, the capacitance element 2 92B can reduce the area occupied by the memory device 420B. This is preferable because it reduces the area required for 420B and improves the bit cost.

[0332] The conductor 276 and the conductor 278 are the conductors 205, 242, and Materials that can be used for the body 260, the conductor 424, etc. can be used.

[0333] In addition, the insulators 275 and 279 may include the insulators 214, 216, and Materials that can be used for the body 224, the insulator 280, and the like can be used.

[0334] <Connection between memory device 420 and transistor 200T> In the region 422 surrounded by the dashed line in FIG. 34, the memory device 420 has conductors 4 24 and is electrically connected to the gate of transistor 200T via conductor 205. However, the present embodiment is not limited to this.

[0335] FIG. 37 shows memory device 420 including conductor 424, conductor 205, conductor 246b, and via conductor 240b as one of the source and drain of transistor 200T. 2 shows an example in which the conductor 242b is electrically connected to the conductor 242b.

[0336] In this way, the memory device 420 is configured according to the circuit function of the transistor layer 413. and the connection method of transistor 200T can be determined.

[0337] FIG. 38 shows a memory unit 470 in a transistor layer 41 having a transistor 200T. 3 and four memory device layers 415 (memory device layers 415_1 to 415_2) An example having a layer 415_4) is shown.

[0338] The memory device layers 415_1 to 415_4 each include a plurality of memory The device 420 is also included.

[0339] The memory device 420 is connected to different memory devices via electrical conductors 424 and electrical conductors 205. The memory device 420 in the device layer 415 and the transistor layer 413 Electrically connect to transistor 200T.

[0340] The memory unit 470 includes an insulator 211, an insulator 212, an insulator 214, an insulator 287, and an insulator 288. , and is sealed by insulator 282, insulator 283, and insulator 284. An insulator 274 is provided around the periphery. A conductor 430 is provided in the insulator 211 and is electrically connected to the element layer 411 .

[0341] An insulator 280 is provided inside the sealing structure. The insulator 280 is heated. The insulator 280 has a function of releasing oxygen, or has an excess oxygen region.

[0342] The insulators 211, 283, and 284 are blocking materials for hydrogen. Insulators 214, 282, and 283 are preferably made of a material having high adhesiveness. The insulator 287 is preferably a material having the function of capturing or fixing hydrogen. It is suitable.

[0343] For example, the material having a high blocking property against hydrogen is silicon nitride, Silicon nitride oxide and the like can also be used. Materials that have this function include aluminum oxide, hafnium oxide, and aluminum and Examples include oxides containing hafnium (hafnium aluminate).

[0344] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "logging."

[0345] In addition, the insulators 211, 212, 214, 287, 282, and The crystal structure of the material used for the insulator 283 and the insulator 284 is not particularly limited. For example, the structure may be amorphous or crystalline. As a material having an adhesive function, an amorphous aluminum oxide film is preferably used. Amorphous aluminum oxide exhibits better hydrogen trapping and The amount of adhesion may be large.

[0346] Here, the excess oxygen in the insulator 280 is converted into hydrogen in the oxide semiconductor in contact with the insulator 280. The following model can be considered for diffusion:

[0347] Hydrogen present in the oxide semiconductor is transferred to other The excess oxygen in the insulator 280 reacts with the oxygen in the oxide semiconductor to form OH bonds. The hydrogen atoms with OH bonds are then bonded to the insulator 280, and the hydrogen atoms diffuse through the insulator 280. The hydrogen reaches a material (typically an insulator 282) that has the function of trapping or fixing hydrogen. In this case, the hydrogen atoms bond with oxygen atoms that are bonded to atoms in the insulator 282 (e.g., metal atoms). The excess oxygen reacts with the insulator 282 and is trapped or fixed in the insulator 282. It is assumed that the oxygen atoms remain in the insulator 280 as excess oxygen. In the diffusion, excess oxygen in the insulator 280 likely plays a bridging role.

[0348] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors. .

[0349] For example, an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulating layer is formed on the oxide semiconductor. After that, a heat treatment is preferably performed. Specifically, the atmosphere should be oxygen-containing, nitrogen-containing, or a mixture of oxygen and nitrogen. The heat treatment is carried out at a temperature of 350°C or higher, preferably 400°C or higher. The heat treatment time is 1 hour or longer. The time is preferably 4 hours or more, and more preferably 8 hours or more.

[0350] By the heat treatment, hydrogen in the oxide semiconductor is oxidized into the insulators 280, 282, and and insulator 287. In addition, the absolute amount of hydrogen present in the vicinity of the oxide semiconductor can be reduced.

[0351] After the heat treatment, the insulators 283 and 284 are formed. The insulator 284 is a material having a high blocking property against hydrogen. The hydrogen diffused outward or the hydrogen present on the outside is then transferred to the inside, specifically, the oxide semiconductor. This can prevent the air from penetrating into the body or the insulator 280 side.

[0352] Regarding the above heat treatment, the following is performed after the insulator 282 is formed: For example, after forming the transistor layer 413 or after forming the memory After forming the re-device layer 415_1 to the memory device layer 415_3, the above-mentioned heating In addition, when hydrogen is diffused outward by the heat treatment, Hydrogen is diffused upward or laterally into the transistor layer 413. Similarly, the memory device layer When heat treatment is performed after forming the memory device layers 415_1 to 415_3, The elements are diffused upward or laterally.

[0353] In the above manufacturing process, the insulator 211 and the insulator 283 are bonded to each other. Thus, the above-mentioned sealing structure is formed.

[0354] As described above, the hydrogen concentration is reduced by using the above structure and manufacturing process. Therefore, a semiconductor device using an oxide semiconductor having high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. It is possible to provide a semiconductor device having the above structure.

[0355] 39(A) to 39(C) are diagrams showing examples in which the arrangement of the conductors 424 is different from that in FIG. 38. FIG. 39(A) shows a layout diagram of the memory device 420 as viewed from above. 39(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 39(A), 39(C) is a cross-sectional view of the area indicated by the dashed line B1-B2 in FIG. In FIG. 39(A), the conductor 205 is omitted for ease of understanding. When the conductor 205 is provided, the conductor 205 overlaps with the conductor 260 and the conductor 424. It has a region.

[0356] As shown in FIG. 39(A), the opening in which the conductor 424 is provided, that is, the conductor 424 , oxide 230a, and oxide 230b, as well as the regions overlapping oxide 230a, In FIG. 39(A), the conductor 424 is provided on the oxide 230b. 2 shows an example in which the oxide 230a and the oxide 230b are provided so as to extend to the B2 side. The conductor 424 is made of an oxide 230a and an oxide The object 230b may be provided so as to protrude on the B1 side, or on both the B1 side and the B2 side. It may be provided so as to extend beyond the

[0357] 39(B) and 39(C) show a memory device layer 415_p-1 on which a memory In this example, device layers 415_p are stacked (p is a natural number between 2 and n). The memory device 420 included in the memory device layer 415_p-1 includes a conductor 424 and a conductor 205, the memory device 420 included in the memory device layer 415_p is electrically connected to the Connect.

[0358] In FIG. 39(B), in the memory device layer 415_p-1, the conductor 424 is The conductor 242 of the memory device layer 415_p-1 and the conductor 242 of the memory device layer 415_p Here, the conductor 424 is connected to the conductor 242, the oxide 2 43, oxide 230b, and the memory device layer 415 on the outer side of the B2 side of oxide 230a. It is also connected to the conductor 205 of _p-1.

[0359] In FIG. 39(C), the conductor 424 is a conductor 242, an oxide 243, an oxide 230b, and and oxide 230a along the B2 side of insulator 280, insulator 273, The conductor 205 is connected to the edge 272, the insulator 224, and the opening formed in the insulator 222. Here, the conductor 424 is electrically connected to the conductor 242, the oxide 243, oxide 230b, and oxide 230a are provided along the B2 side of the oxide. In FIG. 39(B), the conductor 242, the oxide 243, and the oxide 230 are shown by dotted lines. b, the oxide 230a, the insulator 224, and the B2 side of the insulator 222 and the conductor 424 An insulator 241 may be formed between them.

[0360] By providing the conductor 424 in an area where it does not overlap with the conductor 242, etc., 420 is electrically connected to the memory device 420 provided in a different memory device layer 415. The memory device 420 is provided in the transistor layer 413. The transistor 200T can also be electrically connected to the transistor 200T.

[0361] In addition, when the conductor 424 is used as a bit line, if the conductor 424 overlaps with the conductor 242, etc. By providing it in an area where there is no bit line, the bit lines of the memory devices 420 adjacent in the B1-B2 direction As shown in FIG. 39(A), the distance between the conductive material 242 and the conductive material 242 can be increased. The distance between the oxides 230a and the insulators 224 is d1. The distance between the conductors 424 located in the openings formed in the insulator 222 is d2. Therefore, d2 is larger than d1. Compared to when the distance is d1, the parasitic capacitance of the conductor 424 is reduced by setting a part of the distance to d2. By reducing the parasitic capacitance of the conductor 424, the required capacitance of the capacitor 292 can be reduced. This is preferable because it allows for a reduction in capacity.

[0362] In the memory device 420, it acts as a common bit line for two memory cells. A conductor 424 is provided. The dielectric constant of the dielectric used for the capacitance and the parasitic capacitance between the bit lines are By appropriately adjusting the channel length, the cell size of each memory cell can be reduced. Estimated cell size of memory cell when the node size is 30 nm (also called the 30 nm node) The following describes the estimation of bit density and bit cost. 40(A) to 40(D) ​​described below, in order to facilitate understanding of the drawings, the conductor 20 When the conductor 205 is provided, the conductor 205 is connected to the conductor 260 and and a region overlapping with the conductor 424.

[0363] Figure 40(A) shows a capacitor element with a 10 nm thick hafnium oxide layer and a Then, 1 nm of silicon oxide is laminated on the silicon dioxide layer, and the conductive layers of each memory cell of the memory device 420 are formed. There are slits between the conductive material 242, the oxide 243, the oxide 230a, and the oxide 230b. and a conductor 242 and a conductor functioning as a bit line are provided so as to overlap the slit. The memory cell 432 thus obtained is called cell A. Boo.

[0364] The cell size in cell A is 45.25F 2 is.

[0365] FIG. 40(B) shows a capacitor element having a first zirconium oxide layer and an oxide layer thereon as a dielectric. Aluminum is layered on top of it, followed by a second layer of zirconium oxide, forming the memory device 420. The conductor 242, the oxide 243, the oxide 230a, and the oxide 230b of each memory cell are A slit is provided between the conductive body 242 and the conductive body 30b, and the conductive body 242 and the conductive body 30b are arranged so as to overlap the slit. In this example, a conductor 424 is provided to function as a bit line. Recell 433 is referred to as cell B.

[0366] Cell B has a higher dielectric constant than cell A, so the area of ​​the capacitance element is Therefore, the cell size of cell B can be reduced compared to cell A. The cell size in B is 25.53F 2is.

[0367] Cell A and cell B are shown in FIG. 34, FIG. 36(A) to FIG. 36(C), and FIG. The memory device 420, the memory device 420A, or the memory device 420B is enabled. The corresponding memory cells are

[0368] FIG. 40(C) shows a capacitor element having a first zirconium oxide layer and an oxide layer thereon as a dielectric. A second layer of zirconium oxide is deposited on top of the aluminum, and the memory device 420 is active. The conductor 242, the oxide 243, the oxide 230a, and the oxide 230b are connected to each other. The wires are shared by the conductor 242 and overlap with the conductor 242. In this example, a conductor 424 that functions as a bit line is provided. The selected memory cell 434 is called cell C.

[0369] The spacing of the conductors 424 in cell C is higher than that above the oxide 230 compared to above the conductors 242. Therefore, the parasitic capacitance of the conductor 424 can be reduced. , the area of ​​the capacitor element can be reduced. The oxide 230b is not provided with a slit. The cell size can be reduced compared to B. The cell size in cell C is 17.20F. 2 is.

[0370] FIG. 40(D) ​​shows an example in which the conductor 205 and the insulator 216 are not provided in the cell C. Such a memory cell 435 is called cell D.

[0371] By not providing the conductor 205 and the insulator 216 in the cell D, the memory device 4 Therefore, the memory device 20 can be made thinner. The layer 415 can be thinned, and a memory unit in which multiple memory device layers 415 are stacked The height of 470 can be reduced. Conductor 424 and conductor 205 are considered bit lines. When this is done, the bit lines can be shortened in the memory unit 470. This reduces the parasitic loading of the bit lines, further reducing the parasitic capacitance of conductor 424. The area of ​​the capacitor element can be reduced. No slits are provided in the oxide 230b and the substrate 230a. The cell size can be reduced compared to cell A, cell B, and cell C. Is 15.12F 2 is.

[0372] Cells C and D are the same as those in the memory device 420 shown in FIGS. 39(A) to 39(C). corresponds to the memory cells included in the

[0373] Here, the bits of cells A to D and cell E, which are multi-valued in cell D, are bit density and bit cost C b The estimates were also Compared with the bit density and bit cost projections for currently available DRAMs Ta.

[0374] The bit cost C in the semiconductor device according to one embodiment of the present invention b was estimated using Eq. .

[0375]

number

[0376] where n is the number of stacked memory device layers, P c The common part is mainly the element layer 411. Number of turns, P s The memory device layer 415 and the transistor layer 413 are The number of patternings, D d is the bit density of the DRAM, D 3d is the memory device layer 415 The bit density of one layer, P d indicates the number of patterning times for the DRAM. d In , including the increase due to scaling.

[0377] Table 1 shows the expected bit densities of commercially available DRAMs and semiconductors according to an embodiment of the present invention. The bit density of commercially available DRAM is estimated based on the process no. The thicknesses of the semiconductor device of one embodiment of the present invention are two types: 18 nm and 1X nm. The process node is set to 30 nm, and the number of stacked memory device layers in cells A to E is set to 5. Bit density estimates were performed for 1, 10, and 20 layers.

[0378] [Table 1]

[0379] Table 2 shows the bit cost of the semiconductor device according to one embodiment of the present invention based on the bit cost of commercially available DRAMs. The results of estimating the relative bit cost are shown below. A DRAM with a code of 1X nm was used. The thickness is set to 30 nm, and the number of stacked memory device layers in cells A to D is set to 5, 10, and , and 20 layers were estimated.

[0380] [Table 2]

[0381] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0382] (Embodiment 10) In this embodiment, the semiconductor device can be used for the OS transistor described in the above embodiment. The metal oxide (hereinafter also referred to as an oxide semiconductor) will be described.

[0383] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium, tin, etc. are contained. Also, boron, titanium, iron, nickel, etc. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One selected from aluminum, tantalum, tungsten, magnesium, cobalt, etc. One or more types may be included.

[0384] <Classification of crystal structures> First, classification of crystal structures of oxide semiconductors will be described with reference to FIG. FIG. 41A shows a structure of an oxide semiconductor, typically IGZO (In, Ga, Zn, FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides containing

[0385] As shown in FIG. 41(A), oxide semiconductors are roughly classified into “amorphous” and “non-amorphous” oxide semiconductors. "Crystalline" and "Crystal" , and are classified as. Also, among "Amorphous" there are Also, "Crystalline" contains CAAC (c -axis-aligned crystalline), nc(nanocrysta lline), and CAC (cloud-aligned composite) The classification of "Crystalline" includes single crystal, Polycrystalline and completely amorphous materials are excluded. Also, "Crystal" includes single crystal and poly Contains crystals.

[0386] The structure in the bold frame shown in Figure 41(A) is classified into "Amorphous" and " It is an intermediate state between "crystal" and "new crys" This structure belongs to the tetrahedral phase. It is completely different from the physically unstable "Amorphous" and "Crystal". This can be rephrased as a completely different structure.

[0387] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). The crystallinity can be evaluated using the crystallinity spectrum. CAAC-IGZO films classified as "Grazing-Incidence" The XRD spectrum obtained by the XRD measurement is shown in FIG. 41(B) (the vertical axis is the intensity (Int The density is expressed in arbitrary units (au). It is also called the Seemann-Bohlin method. The XRD spectrum obtained in this manner is simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 41(B) is 500 nm.

[0388] As shown in Figure 41(B), the XRD spectrum of the CAAC-IGZO film shows clear results. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating crystallinity. In the case of the SiO2 film, a peak indicating the c-axis orientation is detected near 2θ=31°. As shown, the peaks around 2θ=31° are asymmetrical on the left and right sides of the axis at which the peak intensity is detected. It is a title.

[0389] The crystal structure of the film or substrate was also analyzed by nanobeam electron diffraction (NBED). Diffraction patterns (ultra-small) observed by electron diffraction It can be evaluated by the electron diffraction pattern. The folding pattern is shown in Figure 41(C). Figure 41(C) shows the electron beam incident parallel to the substrate. The diffraction pattern observed by NBED is shown in Figure 41(C). The composition of the C-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the ultrafine electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0390] As shown in Figure 41(C), the diffraction pattern of the CAAC-IGZO film shows the c-axis orientation. Multiple spots are observed.

[0391] <<Oxide semiconductor structure>> Note that oxide semiconductors are classified differently from those in FIG. 41A in terms of their crystal structures. For example, oxide semiconductors may be classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, the above-mentioned CAAC- Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, Pseudo-amorphous oxide semiconductor (a-like OS) de semiconductor), amorphous oxide semiconductor, etc.

[0392] Here, for details on the above-mentioned CAAC-OS, nc-OS, and a-like OS, , and provide an explanation.

[0393] [CAAC-OS] The CAAC-OS has multiple crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. , in the normal direction to the surface on which the CAAC-OS film is formed, or in the normal direction to the surface of the CAAC-OS film. The crystalline region is a region in which the atomic arrangement has periodicity. When viewed as a crystal arrangement, the crystalline region is also a region with a uniform lattice arrangement. The OS has a region where multiple crystalline regions are connected in the ab-plane direction, and this region has strain. The distortion may occur in a region where multiple crystal regions are connected. The area where the orientation of the lattice arrangement changes between a region with one lattice arrangement and a region with a different lattice arrangement. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that has not been

[0394] Each of the plurality of crystalline regions is made up of one or more minute crystals (maximum diameter 10 When a crystalline region is made up of a single microcrystal (crystals less than 1 nm in size), The maximum diameter of the crystalline region is less than 10 nm. When such crystal regions are formed, the size of the crystal regions may be on the order of several tens of nanometers.

[0395] In-M-Zn oxide (element M is aluminum, gallium, yttrium, sulphur, CAAC-OS is a material selected from the group consisting of aluminum, titanium, and other materials. A layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the O layer) are formed. A layered crystal structure (also called a layered structure) is formed by stacking a layer having an element (hereinafter referred to as an (M, Zn) layer) and a layer having an element (hereinafter referred to as an (M, Zn) layer). Indium and element M are mutually substitutable. The (M,Zn) layer may contain indium. The In layer contains the element M. The In layer may contain Zn. In high-resolution TEM images, this is observed as a lattice pattern.

[0396] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ phase In the out-of-plane XRD measurement using a can, two peaks indicating the c-axis orientation were observed. The peak indicating the c-axis orientation is detected at or near θ=31°. ) may vary depending on the type and composition of the metal elements that make up the CAAC-OS.

[0397] For example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) Note that one spot and another spot are the incident electron beams that have passed through the sample. The spot (also called the direct spot) is the center of symmetry, and the points are observed at positions that are point-symmetric. can be.

[0398] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is a hexagonal lattice. However, the unit cell is not necessarily a regular hexagon, and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. -In OS, clear grain boundaries were confirmed even near the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is close-packed in the ab-plane direction. The bond distance between atoms changes when metal atoms are substituted. , it is believed that this is because distortion can be tolerated.

[0399] The crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries act as recombination centers, trapping carriers and forming transistors. It is highly likely that this will cause a decrease in on-state current and a decrease in field effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystal structure suitable for the semiconductor layer of a transistor. It is one of the crystalline oxides containing Zn to form CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are made of In oxide. This is preferable because it can suppress the generation of grain boundaries more effectively than oxides.

[0400] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, the CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. In addition, the crystallinity of oxide semiconductors may be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having a CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. C-OS is stable even under high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using CAAC-OS for OS transistors increases the flexibility of the manufacturing process. It becomes possible to

[0401] [nc-OS] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). In other words, nc-OS has a periodic atomic arrangement in the region of 3 nm or less. It has small crystals. The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. Since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, depending on the analytical method, nc-OS may be considered as a-like In some cases, it is difficult to distinguish between an OS and an amorphous oxide semiconductor. For example, in the case of an nc-OS film, , Structural analysis was performed using an XRD instrument, and out-of-plane analysis using θ / 2θ scan was performed. In the XRD measurement, no peaks indicating crystallinity were detected. However, electron beam circuits using electron beams with probe diameters larger than nanocrystals (e.g., 50 nm or larger) are being used. When electron diffraction (also called selected area electron diffraction) is performed, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, the size of the nanocrystals is close to or smaller than that of the nanocrystals. Electron beam diffraction (nanobeam) using an electron beam with a probe diameter (for example, 1 nm to 30 nm) When electron diffraction is performed, a ring-shaped region is formed around the direct spot. An electron diffraction pattern may be obtained in which multiple spots are observed.

[0402] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has pores or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0403] <<Oxide semiconductor structure>> Next, the details of the above-mentioned CAC-OS will be explained. Regarding the formation of

[0404] [CAC-OS] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are 0.5 nm to 10 nm in size. Preferably, the material is unevenly distributed in a size of 1 nm to 3 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in a metal oxide. The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A mixed state of particles with sizes of less than 1 m or close to that size is called a mosaic or patch state. .

[0405] Furthermore, CAC-OS is a material that is separated into a first region and a second region. The first regions are in a shape similar to a cloud, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud shape). ) In other words, the CAC-OS is a mixture of the first area and the second area. It is a composite metal oxide having a structure in which

[0406] Here, the I ratio of the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of n, Ga, and Zn are defined as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has [In] higher than the [In] in the second region. In this region, [Ga] is larger than [Ga] in the first region. In addition, the second region has a larger [Ga] than the [Ga] in the first region and a smaller [I [n] is smaller than [In] in the first region.

[0407] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region containing gallium oxide, gallium zinc oxide, etc. In other words, the first region is called a region in which In is the main component. The second region can be rephrased as a region containing Ga as the main component. It is possible.

[0408] Note that there are cases where a clear boundary between the first region and the second region cannot be observed. .

[0409] For example, in the case of CAC-OS in In-Ga-Zn oxide, energy dispersive X-ray diffraction (EDX) Optical method (EDX:Energy Dispersive X-ray spectrosc) The EDX mapping obtained using the opy revealed a region containing In as the main component (the first region). The structure has a structure in which a Ga-based region (first region) and a Ga-based region (second region) are unevenly distributed and mixed. It can be confirmed that this is the case.

[0410] When CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are The insulating properties due to the region act complementary to each other to provide a switching function (On In other words, CAC-OS can , a part of the material has a conductive function and a part of the material has an insulating function, and the whole of the material has a The material functions as a semiconductor. By separating the conductive function from the insulating function, Therefore, when using CAC-OS in transistors, This allows for a high on-state current (I on ), high field-effect mobility (μ), and good switching This allows for realizing a locking operation.

[0411] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductors in Two or more of AC-OS, nc-OS, and CAAC-OS may be included.

[0412] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0413] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0414] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. , the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 c m -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm - 3 In order to reduce the carrier concentration of the oxide semiconductor film, The impurity concentration in the semiconductor film may be reduced to reduce the defect state density. A low impurity concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. The oxide semiconductor having a low carrier concentration is preferably a high-purity intrinsic or substantially high-purity intrinsic oxide. These are sometimes called compound semiconductors.

[0415] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0416] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. This may be the case.

[0417] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In addition, in order to reduce the impurity concentration in the oxide semiconductor, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0418] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0419] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, they are oxidized. Defect levels are formed in semiconductors, which is why defects in silicon and carbon in oxide semiconductors The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0420] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may be included. Transistors using oxide semiconductors, which are widely used in semiconductors, tend to be normally on. Therefore, the concentration of alkali metals or alkaline earth metals in oxide semiconductors obtained by SIMS Degrees, 1 x 1018 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0421] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor becomes a semiconductor. The transistors used for the oxide semiconductors tend to be normally on. Therefore, if nitrogen is contained, trap levels may be formed. Therefore, the electrical properties of the oxide semiconductor obtained by SIMS may become unstable. The nitrogen concentration in 19 atoms / cm 3 Less than 5 x 10 18 ato ms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following are more preferred: Kuha 5 x 10 17 atoms / cm 3 Do the following:

[0422] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×1020 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Make it less than.

[0423] By using an oxide semiconductor with sufficiently reduced impurities for a channel formation region of a transistor, This makes it possible to impart stable electrical properties.

[0424] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0425] (Embodiment 11) In this embodiment, the semiconductor devices 10, 10A, 10B, and 10C described in the first to fourth embodiments are The peripheral circuit 20 in 0F will be described in detail.

[0426] FIG. 42 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device. The semiconductor device 10E includes a peripheral circuit 20 and a memory cell array 30. , a row decoder 71, a word line driver circuit 72, a column driver 22, and an output circuit 73. , and a control logic circuit 74. The row driver circuit 72 can be applied to the row driver described in the first embodiment and the like.

[0427] The column driver 22 includes a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84. The precharge circuit 82 precharges the wiring BL and the like. The amplifier circuit 83 amplifies the data signal read from the wiring BL. The amplified data signal is output via an output circuit 73 as a digital data signal. The data is output as RDATA to the outside of the semiconductor device 10E.

[0428] The semiconductor device 10E is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 20 A high power supply voltage (VDD) for the memory cell array 30 and a high power supply voltage (VIL) for the memory cell array 30 are supplied. do.

[0429] The semiconductor device 10E also includes control signals (CE, WE, RE), an address signal ADDR, A data signal WDATA is input from the outside. An address signal ADDR is input to the row decoder 7. 1 and the column decoder 81, and WDATA is input to the write circuit 84.

[0430] The control logic circuit 74 processes external input signals (CE, WE, RE). CE generates control signals for the row decoder 71 and the column decoder 81. WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 74 are not limited to these. Instead, other control signals may be input as needed. A control signal is input for the purpose of reading data from a specific memory cell address. They may be identified as good bits.

[0431] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0432] Generally, in semiconductor devices such as computers, various memory devices are used depending on the application. Figure 43 shows various storage devices by layer. The lower the storage device, the larger the storage capacity and the higher the recording speed. In Figure 43, the density is calculated by dividing the registers into the registers and the registers in the CPU or other processors. Embedded memory, SRAM (Static Random Access Memory) mory), DRAM (Dynamic Random Access Memory) , showing 3D NAND memory.

[0433] The memory embedded as a register in a CPU or other processing unit is used to temporarily store the results of calculations. Therefore, the frequency of access from the processor is high. The registers hold the setting information of the arithmetic processing unit. It also has functions.

[0434] SRAM is used, for example, for caches. Caches are used to store data stored in main memory. It has the function of duplicating and storing some of the information stored in the database. By replicating the data, you can increase the speed at which data can be accessed.

[0435] DRAM is used for main memory, for example. Main memory reads data from storage. DRAM has the function of storing programs and data. The recording density of DRAM is approximately 0.1~0.3Gbit / mm 2 is.

[0436] 3D NAND memory is used for storage, for example. It has the function of storing necessary data and various programs used by the processing unit. Therefore, storage devices require a large memory capacity and high recording density rather than high operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / m m 2 is.

[0437] A semiconductor device that functions as a memory device of one embodiment of the present invention has high operating speed and can be used for a long period of time. The semiconductor device according to one aspect of the present invention is a memory device that stores data in a memory area. Suitable as a semiconductor device located in the boundary area 901 including both the layer where the in-memory is located In addition, the semiconductor device of one embodiment of the present invention can be used for a main memory. As a semiconductor device located in a boundary area 902 including both a layer and a layer where a storage is located, It can be suitably used.

[0438] (Embodiment 12) In this embodiment mode, an electronic component and a semiconductor device or the like described in the above embodiment mode are incorporated. We will also explain the power consumption of electronic devices.

[0439] 44(A) and (B) are diagrams for explaining the power consumption of DRAM and DOSRAM. 44(A) shows the power consumption of DRAM, DOSRAM1, and DOSRAM2. B) shows the power consumption of DRAM and DOSRAM2, respectively.

[0440] Figures 44(A) and (B) show the results of estimates based on various assumed usage methods. In addition, in Figure 44(A), the active mode is 10% (in the usage situation of electronic devices, etc.). , assuming active mode 10% of the day) and standby mode 90% of the day General DRAM and electronic device according to one embodiment of the present invention (DOSRAM1, DOSRAM2) In addition, in Figure 44(B), the results of the estimation are shown. 1% of the day (assuming that 1% of the day is in active mode when using electronic devices, etc.) Assuming a standby mode of 99%. The figure shows the results of an estimate based on the assumed equipment (DOSRAM2).

[0441] In Figures 44(A) and (B), the vertical axis represents power consumption. On the other hand, in FIG. 44(A), the horizontal axis represents the DRA In FIG. 44(B), the horizontal axis indicates DRAM, DOSRAM2 is shown.

[0442] In addition, in Figure 44 (A) and (B), the lower part of the graph shows the power consumption during Active mode. The middle row shows the power consumption during standby mode, and the top row shows the power consumption during refresh mode. It represents.

[0443] DOSRAM2 is a power gate for DOSRAM1 during standby. This is intended to be used for conducting training.

[0444] As shown in FIG. 44A, the electronic device ( It can be seen that DOSRAM1 and DOSRAM2 have low power consumption. M2 is estimated to reduce power consumption by 75% compared to conventional DRAM.

[0445] Also, as shown in FIG. 44(B), in the case of 1% active mode, Compared to DRAM, the electronic device (DOSRAM2) of one embodiment of the present invention has a 95% power reduction efficiency. The results are estimated.

[0446] As described above, according to one embodiment of the present invention, a semiconductor device with reduced power consumption or a semiconductor device with reduced power consumption can be provided. Child devices can be provided.

[0447] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0448] (Embodiment 13) This embodiment mode will be described with reference to an electronic component incorporating the semiconductor device or the like shown in the above embodiment mode. An example of an electronic device is shown.

[0449] <Electronic components> First, an example of an electronic component incorporating the semiconductor device 10 is shown in FIGS. 45(A) and 45(B). This will be used to explain.

[0450] FIG. 45(A) shows an electronic component 700 and a substrate on which the electronic component 700 is mounted (mounting substrate 70 45(A) shows a perspective view of the electronic component 700 shown in FIG. The semiconductor device 10 has an element layer 34 stacked on a substrate 11. In order to show the inside of the electronic component 700, some parts are not shown in the figure. The land 712 is electrically connected to the electrode pad 713. The electrode pad 713 is electrically connected to the semiconductor device 10 by a wire 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of components are combined and electrically connected on the printed circuit board 702. This completes the mounting board 704.

[0451] 45(B) shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) em in package) or MCM (Multi Chip Module) This is an example. The electronic component 730 is mounted on a package substrate 732 (printed circuit board). An interposer 731 is provided, and a semiconductor device 735 and a plurality of memory cells are mounted on the interposer 731. An apparatus 100 is provided.

[0452] In the electronic component 730, the semiconductor device 10 is a high bandwidth memory (HBM). The semiconductor device 735 is used as a C Integrated circuits (semiconductor devices) such as PU, GPU, and FPGA can be used.

[0453] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be a silicon interposer, a resin interposer, or the like. An oil interposer or the like can be used.

[0454] The interposer 731 has a plurality of wirings and connects a plurality of integrated circuits with different terminal pitches. The wiring has a function of electrically connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 to the package substrate 7 32. The interposer is sometimes called a "rewiring substrate" or "intermediate substrate." 1, a through electrode is provided, and the integrated circuit and the package substrate 732 are electrically connected by the through electrode. In addition, in silicon interposers, TSV ( Through Silicon Via can also be used.

[0455] It is preferable to use a silicon interposer as the interposer 731. Since an interposer does not require active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring, which is difficult to do with resin interposers.

[0456] In HBM, many wires must be connected to achieve a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is recommended to use a silicon interposer for implementing HBM. It is preferable that:

[0457] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to differences in the expansion coefficient between the posers. The surface of the silicon interposer is highly flat, so the integrated circuit mounted on the silicon interposer and the silicon Connection failures between interposers are unlikely to occur. In particular, it is possible to mount multiple integrated circuits on an interposer. In a 2.5D package (2.5-dimensional mounting) where devices are arranged side by side, the silicon interposer It is preferable to use the

[0458] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. When providing the interposer 731, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the semiconductor device 10 and the semiconductor device 73 It is preferable to align the height of 5.

[0459] In order to mount the electronic component 730 on another substrate, electrodes 733 are attached to the bottom of the package substrate 732. In FIG. 45B, an example in which the electrode 733 is formed by a solder ball is shown. By providing solder balls in a matrix on the bottom of the package substrate 732, a BGA (B In addition, the electrode 733 can be connected with a conductive pin. The bottom of the package substrate 732 may be provided with conductive pins in a matrix. This allows for PGA (Pin Grid Array) implementation.

[0460] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) , or QFN (Quad Flat Non-leaded package) The implementation method can be used.

[0461] <Electronic equipment> Next, an example of an electronic device equipped with the above electronic component will be described with reference to FIG.

[0462] The robot 7100 is equipped with a light sensor, microphone, camera, speaker, and display. , various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The electronic component 730 includes a processor, etc. For example, the electronic component 700 may be a sensor. It has the function of storing the acquired data.

[0463] The microphone has the function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The bot 7100 analyzes the audio signal input via the microphone and The audio signal can be emitted from the speaker. It is possible to communicate with the user using a microphone and speaker. is.

[0464] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has the function of moving using a movement mechanism. The robot 7100 uses a camera to capture the surroundings. It can capture images of the vehicle and analyze them to detect whether there are any obstacles when moving around. .

[0465] The flying object 7120 has a propeller, a camera, a battery, etc., and flies autonomously. The electronic component 730 has the function of controlling these peripheral devices.

[0466] For example, image data captured by a camera is stored in the electronic component 700. 0 can analyze image data and detect the presence or absence of obstacles when moving. In addition, the remaining battery capacity can be estimated from the change in the battery storage capacity by the electronic component 730. This can be done.

[0467] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. It has a camera, brushes, operation buttons, various sensors, etc. Although not shown, the cleaning robot The cleaning robot 7300 is equipped with tires, a suction nozzle, etc. It can detect dust and suck it up through a suction port on the bottom.

[0468] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. In addition, image analysis can be used to detect wires and other objects that may be tangled in the brushes. If it detects an object that is likely to move, it can stop the brush from rotating.

[0469] The car 7160 has an engine, tires, brakes, steering, a camera, etc. For example, electronic components 730 may provide navigation information, speed, engine status, gear selection status, etc. Optimize the driving conditions of the car 7160 based on data such as the frequency of braking and other factors. For example, image data captured by a camera is stored in the electronic component 700. .

[0470] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (television receiver). Imaging device), smartphone 7210, PC (personal computer) 7220, 723 0, game console 7240, game console 7260, etc.

[0471] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic component 730 can perform functions such as noise reduction, resolution up-conversion, etc. Image processing such as:

[0472] The smartphone 7210 is an example of a mobile information terminal. It includes a microphone, camera, speaker, various sensors, and a display. Electronic Components 73 0 controls these peripherals.

[0473] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The C7230 is equipped with a keyboard 7232 and a monitor device 7233, which can be connected wirelessly or by wire. The game console 7240 is an example of a portable game console. This is an example of a stationary game console. The game console 7260 can be equipped with a wireless or wired controller. The controller 7262 is connected to the electronic component 700 and / or the power supply. Sub-components 730 can also be incorporated.

[0474] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0475] (Notes regarding the present specification) The following additional notes will be given regarding the above-described embodiments and the respective configurations in the embodiments. .

[0476] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments or examples. In addition, one embodiment may include a plurality of configurations. When examples are shown, the configuration examples can be combined as appropriate.

[0477] The contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the form, and / or one or more other The contents (or a part of the contents) described in the embodiment of the present invention may be applied, combined, or You can make substitutions etc.

[0478] The contents described in the embodiments are explained using various figures in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0479] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. Another figure (or a part thereof) described in the embodiment, and / or one or more The figures (or a part thereof) described in a plurality of different embodiments may be combined. allows for the construction of even more diagrams.

[0480] In addition, in the block diagrams in this specification, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into functional blocks. It is difficult to separate the functions into separate parts, and there are cases where multiple functions are involved in one circuit, or where a circuit is involved in multiple circuits. Therefore, the blocks in the block diagram may be The present invention is not limited to the components described above, and may be rephrased appropriately depending on the situation.

[0481] In addition, in the drawings, the size, layer thickness, and area are arbitrarily scaled for convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the sake of convenience, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing deviations. This may include variations in signal, voltage, or current due to the

[0482] In addition, the positional relationships of the components shown in the drawings are relative. When describing components by reference, the terms "above" and "below" that indicate positional relationships are used for convenience. The positional relationship of the components is not limited to the contents described in this specification, and may vary depending on the situation. It can be rephrased appropriately depending on the situation.

[0483] In this specification and the like, when describing the connection relationship of a transistor, the term "source or drain" is used. "one of the two" (or first electrode, or first terminal), "the other of the two The term "second electrode" is used to refer to the source and drain of a transistor. This is because the drain varies depending on the structure or operating conditions of the transistor. The names of the source and drain of a transistor are the source (drain) terminal and the source (drain) terminal. In) electrodes, etc., can be rephrased appropriately depending on the situation.

[0484] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0485] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. The potential difference from the reference potential. For example, the reference potential is the ground voltage (earth If we use the term "voltage", we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0486] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. The term "electrode," "conductive layer," "conductor," "impurity region," etc. may also be used. Lines and the like can be referred to as nodes.

[0487] In this specification, "A and B are connected" means that A and B are electrically connected. Here, A and B are electrically connected to each other. Objects (switches, transistor elements, diodes, etc.), or the elements and A connection that allows transmission of electrical signals between A and B when there is a circuit (including wiring, etc.) If A and B are electrically connected, it is considered that A and B are directly connected. Here, A and B being directly connected means that they are connected via the above object. Instead, electrical signals can be transmitted between A and B via wiring (or electrodes) between A and B. In other words, a direct connection is a connection that can be seen as the same circuit diagram when expressed as an equivalent circuit. This refers to the connection that can be made.

[0488] In this specification, a switch refers to a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It refers to a device that has the function of controlling whether or not current flows by entering a state where it is in a non-operating state. A switch is a device that has the function of selecting and switching a path through which a current flows.

[0489] In this specification and the like, the channel length is, for example, the length of a semiconductor the body (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the region where they overlap or where the channel is formed. It means separation.

[0490] In this specification, the channel width is, for example, the width of a semiconductor (or a transistor) when it is in an on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows in the semiconductor when the gate electrode is in the non-transistor state), or the channel The length of the portion where the source and drain face each other in the region where the capacitor is formed. .

[0491] In this specification, the terms "film" and "layer" are used in some cases or in other situations. For example, the term "conductive layer" can be used interchangeably with " It may be possible to change the term to "conductive film." In some cases, the term "insulating layer" can be changed to the term "insulating layer." [Explanation of symbols]

[0492] BL_1: bit line, DA1: data, PCL1: precharge line, PCL2: precharge Page line, T1: Period, T2: Period, T3: Period, T4: Period, T11: Period, T12: Period T13: period, T14: period, T15: period, T16: period, WL_N: word line, WL_1: word line, WL2: word line, 10: semiconductor device, 10A: semiconductor device, 10 B: Semiconductor device, 10C: Semiconductor device, 10D: Semiconductor device, 10E: Semiconductor device, 10 F: semiconductor device, 11: silicon substrate, 20: peripheral circuit, 21: row driver, 22: RAM driver, 22_A: Precharge circuit, 22_B: Precharge circuit, 22_C: Sense amplifier, 22_D: switch circuit, 22_E: switch circuit, 22_1: precharge 22_2: sense amplifier; 22_3: switch circuit; 23_A: switch; 3_B: Switch, 23_C: Switch, 23_D: Switch, 24_1: Transistor ,24_3: Transistor, 24_4: Transistor, 24_6: Transistor, 25: Circuit, 25_1: Transistor, 25_2: Transistor, 25_3: Transistor, 2 5_4: transistor, 26: element layer, 27: circuit, 27_M: circuit, 27_1: circuit, 28: transistor, 28_a: transistor, 28_b: transistor, 28_n: transistor Transistor, 28_1: Transistor, 29: Circuit, 30: Memory cell array, 30_M : unit, 30_1: unit, 31: memory cell, 31_M: memory cell, 31_N : memory cell, 31_N_A: memory cell, 31_N_B: memory cell, 31_1: memory Recell, 31_1_A: memory cell, 31_1_B: memory cell, 32: transistor, 32_N: transistor, 32_1: transistor, 32A: transistor, 32B: transistor Transistor, 33: Capacitor, 33_N: Capacitor, 33_1: Capacitor, 33A : capacitor, 33B: capacitor, 34: element layer, 34_i: element layer, 34_N: element Layer, 34_1: element layer, 40: element layer, 40_M: element layer, 40_1: element layer, 40A: Element layer, 40B: element layer, 40C: element layer, 40D: element layer, 41: transistor, 41 _a: transistor, 41_b: transistor, 42: transistor, 42_a: transistor Transistor, 42_b: Transistor, 43: Transistor, 43_a: Transistor, 43 _b: transistor, 44: transistor, 44_a: transistor, 44_b: transistor Register, 49: Circuit, 50: Unit, 50_M: Unit, 50_1: Unit, 51 : memory cell, 54: element layer, 55: transistor, 56: transistor, 57: capacitor child, 70A: sealing layer, 70B: sealing layer, 71: row decoder, 72: word line driver circuit 73: output circuit; 74: control logic circuit; 81: column decoder; 82: Precharge circuit, 83: amplifier circuit, 84: circuit, 98: switch circuit, 100: memory device Position, 200: Transistor, 200M: Transistor, 200T: Transistor, 205 : conductor, 205a: conductor, 205b: conductor, 211: insulator, 212: insulator, 2 14: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 2 30a: oxide, 230b: oxide, 230c: oxide, 240: conductor, 240a: conductor Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 24 2: conductor, 242a: conductor, 242b: conductor, 243: oxide, 243a: oxide , 243b: oxide, 246: conductor, 246a: conductor, 246b: conductor, 250: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 272: Insulator, 27 3: insulator, 274: insulator, 275: insulator, 276: conductor, 277: insulator, 27 8: conductor, 279: insulator, 280: insulator, 282: insulator, 283: insulator, 28 4: insulator, 287: insulator, 290: conductor, 292: capacitance, 292A: capacitance, 292 B: Capacitance, 294: Conductor, 295: Insulator, 296: Insulator, 297: Conductor, 298 : insulator, 299: conductor, 300: transistor, 311: semiconductor substrate, 313: semiconductor Body region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor body, 411: element layer, 413: transistor layer, 413_m: transistor layer, 413_ 1: transistor layer, 415: memory device layer, 415_n: memory device layer, 41 5_p: Memory device layer, 415_p-1: Memory device layer, 415_1: Memory device device layer, 415_3: memory device layer, 415_4: memory device layer, 420: memory memory device, 420A: memory device, 420B: memory device, 422: area, 424: Conductor, 426: Conductor, 428: Conductor, 430: Conductor, 432: Memory cell 433: memory cell, 434: memory cell, 435: memory cell, 470: memory unit Knit, 470_m: Memory unit, 470_1: Memory unit, 700: Electronic parts , 702: Printed circuit board, 704: Mounting board, 711: Mold, 712: Land, 71 3: electrode pad, 714: wire, 730: electronic component, 731: interposer, 732 : package substrate, 733: electrode, 735: semiconductor device, 901: boundary region, 902: boundary Boundary area, 7100: Robot, 7120: Flying object, 7140: Cleaning robot, 7160: Automobiles, 7200: TV equipment, 7210: Smartphones, 7220: PCs, 7230: PC, 7232: Keyboard, 7233: Monitor, 7240: Game console, 7260: Game console, 7262: Controller, 7300: Cleaning robot

Claims

[Claim 1] a first device layer having first memory cells; a second device layer having second memory cells; a third device layer having switching circuitry; a silicon substrate having a driving circuit; the first element layer is provided between the silicon substrate and the second element layer; the third element layer is provided between the silicon substrate and the first element layer; the first memory cell includes a first transistor and a first capacitor; the second memory cell includes a second transistor and a second capacitor; the switching circuit includes a third transistor having a function of controlling a conduction state between the first memory cell or the second memory cell and the drive circuit; one of the source or the drain of the first transistor and one of the source or the drain of the second transistor are electrically connected to wirings for electrical connection to one of the source or the drain of the third transistor, the other of the source and the drain of the third transistor is electrically connected to the drive circuit; the wiring is in contact with a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor, and is provided in a direction perpendicular or approximately perpendicular to a surface of the silicon substrate.

Images