Semiconductor memory device

Abstract

To improve the degree of freedom in designing a semiconductor memory device.SOLUTION: A semiconductor memory device according to an embodiment includes a first chip 1-1 including a substrate having a first region AR and a second region PR, and a second chip 1-2 that is in contact with the first chip 1-1 in a Z direction and is electrically connected to the first chip 1-1 via a plurality of connection pads provided in a boundary region with the first chip 1-1. The second chip 1-2 includes a memory cell array provided in the first region AR and including a source line, a plurality of word lines provided below the source line and spaced apart from each other in the Z direction, and a memory pillar having an upper end connected to the source line, a plurality of contacts 207 provided in the second region PR, extending in the Z direction, and each electrically connected to any one of the plurality of connection pads, a conductor pattern 32B in contact with upper ends of the plurality of contacts 207, and a first wiring layer 39 provided above the conductor pattern 32B and electrically connected to the conductor pattern 32B.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. NAND flash memory employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-141616 [Patent Document 2] Japanese Patent Application Publication No. 2024-319 Summary of the Invention [Problem to be solved by the invention]

[0004] The degree of freedom in designing a semiconductor memory device is improved. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a first chip including a substrate having a first region and a second region, and a second chip that contacts the first chip in a first direction intersecting the surface of the substrate and is electrically connected to the first chip via a plurality of connection pads provided in a boundary region with the first chip, wherein the second chip includes a memory cell array provided in the first region and having a source line, a plurality of word lines provided below the source line and spaced apart from each other in the first direction, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines and having an upper end connected to the source line, a plurality of contacts provided in the second region and extending in the first direction, each contact electrically connected to one of the plurality of connection pads, a conductor pattern contacting the upper ends of the plurality of contacts, and a first wiring layer provided above the conductor pattern and electrically connected to the conductor pattern. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 1 is a plan view showing an example of a planar layout of a semiconductor memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the first embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar of the semiconductor memory device according to the first embodiment. [Figure 8]FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of the semiconductor memory device according to the first embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing an example of a connection portion between a wiring layer and a contact in the semiconductor memory device according to the first embodiment. [Figure 10] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of a connection pad of the semiconductor memory device according to the first embodiment. [Figure 11] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 17] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 18] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 19] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 20] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a first modification of the first embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a second modification of the first embodiment. [Figure 23]FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a third modification of the first embodiment. [Figure 24] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a fourth modification of the first embodiment. [Figure 25] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a fifth modification of the first embodiment. [Figure 26] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a fifth modification of the first embodiment. [Figure 27] FIG. 10 is a plan view showing an example of a planar layout of a semiconductor memory device according to a second embodiment. [Figure 28] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a second embodiment. [Figure 29] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a second embodiment. [Figure 30] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 31] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 32] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 33] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 34] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 35] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 36] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 37] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 38]FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a first modified example of the second embodiment. [Figure 39] 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. 38, showing an example of connection of wiring layers in a semiconductor memory device according to a first modified example of the second embodiment. [Figure 40] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a second modification of the second embodiment. [Figure 41] FIG. 41 is a cross-sectional view taken along line XLI-XLI in FIG. 40, showing an example of connection of wiring layers in a semiconductor memory device according to a second modification of the second embodiment. [Figure 42] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a third modification of the second embodiment. [Figure 43] FIG. 43 is a cross-sectional view taken along line XLIII-XLIII in FIG. 42, showing an example of connection of wiring layers in a semiconductor memory device according to a third modification of the second embodiment. [Figure 44] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a fourth modification of the second embodiment. [Figure 45] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a fifth modification of the second embodiment. [Figure 46] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a sixth modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Note that the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. Furthermore, when particularly distinguishing between elements having similar configurations, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. First embodiment The semiconductor memory device according to the first embodiment will be described below.

[0009] 1.1 Configuration The configuration of the semiconductor memory device according to the first embodiment will be described.

[0010] 1.1.1 Memory System First, an example of the configuration of a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to the first embodiment.

[0011] The memory system 3 is, for example, an SSD (solid state drive) or SD TM The memory system 3 is a card. The memory system 3 is connected to, for example, an external host device (not shown). The memory system 3 stores data from the host device. The memory system 3 also reads data to the host device.

[0012] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0013] The semiconductor memory device 1 is, for example, a NAND flash memory. The semiconductor memory device 1 stores data in a nonvolatile manner. In the following, an example will be described in which the semiconductor memory device 1 is a NAND flash memory.

[0014] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 writes data to the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also reads data from the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also transmits the data read from the semiconductor memory device 1 to the host device.

[0015] The communication between the semiconductor memory device 1 and the memory controller 2 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0016] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 1, the semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0017] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(m-1) (m is an integer equal to or greater than 2). A block BLK is a set of a plurality of memory cells capable of storing data in a non-volatile manner. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. For example, one memory cell is associated with one bit line and one word line.

[0018] The command register 11 holds the command CMD that the semiconductor memory device 1 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, and the like.

[0019] The address register 12 holds address information ADD that the semiconductor memory device 1 receives from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. The page address PA, the block address BA, and the column address CA are used to select, for example, a word line, a block BLK, and a bit line, respectively.

[0020] The sequencer 13 controls the overall operation of the semiconductor memory device 1. Based on the command CMD stored in the command register 11, the sequencer 13 executes a read operation, a write operation, and an erase operation.

[0021] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PA held in the address register 12.

[0022] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0023] In a write operation, the sense amplifier module 16 transfers write data DAT received from the memory controller 2 to the memory cell array 10. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line. The sense amplifier module 16 transfers the result of this determination to the memory controller 2 as read data DAT.

[0024] 1.1.3 Memory cell array circuit configuration An example of the circuit configuration of the memory cell array 10 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device according to the first embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. In the example shown in Fig. 2, the block BLK includes four string units SU0, SU1, SU2, and SU3.

[0025] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BL(n-1) (n is an integer equal to or greater than 2). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage film. Each of the memory cell transistors MT0 to MT7 stores data in a non-volatile manner. The select transistors ST1 and ST2 are used to select the string unit SU during various operations. In the following description, when the bit lines BL0 to BL(n-1) are not distinguished from one another, each of the bit lines BL0 to BL(n-1) will simply be referred to as a bit line BL. When the memory cell transistors MT0 to MT7 are not distinguished from one another, each of the memory cell transistors MT0 to MT7 will simply be referred to as a memory cell transistor MT.

[0026] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the select transistor ST1 is connected to the bit line BL associated with the select transistor ST1. The other end of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. One end of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The other end of the select transistor ST2 is connected to a source line SL.

[0027] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistor ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of multiple select transistors ST2 in the same block BLK are commonly connected to a select gate line SGS. However, this is not limited to this, and the gates of multiple select transistors ST2 may be connected to multiple select gate lines SGS that are different for each string unit SU. In the following description, when the word lines WL0 to WL7 are not distinguished, each of the word lines WL0 to WL7 will simply be referred to as a word line WL. Furthermore, when the select gate lines SGD0 to SGD3 are not distinguished, each of the select gate lines SGD0 to SGD3 will simply be referred to as a select gate line SGD.

[0028] A different column address is assigned to each of the bit lines BL0 to BL(n-1). Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Word lines WL0 to WL7 are provided for each block BLK. A source line SL is shared, for example, among multiple blocks BLK.

[0029] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called a cell unit CU. For example, the storage capacity of a cell unit CU including multiple memory cell transistors MT, each storing one bit of data, is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0030] The circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, each block BLK may include any number of string units SU. Each NAND string NS may include any number of memory cell transistors MT and select transistors ST1 and ST2.

[0031] 1.1.4 Structure of semiconductor memory device An example of the structure of the semiconductor memory device 1 according to the first embodiment will be described.

[0032] In the following description, the X direction is approximately parallel to the semiconductor substrate of the semiconductor memory device 1. The X direction corresponds to the extension direction of the word lines WL. The Y direction is approximately parallel to the semiconductor substrate and perpendicular to the X direction. The Y direction corresponds to the extension direction of the bit lines BL. The Z1 and Z2 directions are approximately perpendicular to the semiconductor substrate. The Z1 direction corresponds to the direction from the semiconductor substrate of the semiconductor memory device 1 toward the electrode pads. The Z2 direction corresponds to the direction from the electrode pads toward the semiconductor substrate. When the Z1 and Z2 directions are not distinguished, each of the Z1 and Z2 directions will be simply referred to as the Z direction. Hereinafter, the Z1 direction side of a certain component will be referred to as one side in the Z direction (or simply one side), and the Z2 direction side of a certain component will be referred to as the other side in the Z direction (or simply the other side). Furthermore, the surface of a certain component facing the electrode pads will be referred to as the first surface, and the surface of a certain component facing the semiconductor substrate will be referred to as the second surface. The first surface and the second surface can also be called the surface on one side in the Z direction and the surface on the other side in the Z direction, respectively.

[0033] 1.1.4.1 Planar Configuration of Semiconductor Memory Devices An example of the planar configuration of the semiconductor memory device 1 will be described with reference to Fig. 3. Fig. 3 is a plan view showing an example of the planar layout of the semiconductor memory device according to the first embodiment.

[0034] 3, the semiconductor memory device 1 is divided into a circuit region CR, a wall region WR, and a kerf region KR. The circuit region CR is further divided into an array region AR and a peripheral region PR.

[0035] The circuit region CR is a region in which elements constituting the semiconductor memory device 1, such as a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16, are provided. The memory cell array 10 is provided in an array region AR within the circuit region CR. Electrode pads PD are further provided in the peripheral region PR. The electrode pads PD are exposed, for example, on the surface of the semiconductor memory device 1 and function as connection pads for connecting to devices external to the semiconductor memory device 1. The circuit region CR is, for example, a rectangular region.

[0036] The wall region WR is, for example, a region provided so as to surround the outer periphery of the circuit region CR. A sealing portion (not shown) is provided in the wall region WR so as to surround the outer periphery of the circuit region CR when viewed from above. The sealing portion functions, for example, as a crack stopper or an edge seal.

[0037] The kerf region KR is a region provided to surround the outer periphery of the wall region WR. The kerf region KR is located at the outermost periphery of the semiconductor memory device 1. For example, alignment marks used during manufacturing of the semiconductor memory device 1 and circuits for performance testing of the semiconductor memory device 1 are provided in the kerf region KR.

[0038] 1.1.4.2 Memory Cell Array Structure First, an example of the structure of the memory cell array 10 provided in the array region AR in the circuit region CR will be described.

[0039] 1.1.4.2.1 Overall Configuration of Memory Cell Array The overall configuration of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a plan view showing an example of a planar layout of the memory cell array included in the semiconductor memory device according to the first embodiment. Fig. 4 shows areas corresponding to four blocks BLK0 to BLK3.

[0040] The memory cell array 10 includes a stacked wiring structure and a plurality of components SLT and SHE. The stacked wiring structure includes select gate lines SGD and SGS and a plurality of word lines WL. The stacked wiring structure is a structure in which the select gate lines SGD and SGS and the plurality of word lines WL are stacked along the Z direction according to the number of layers. In the following description, the select gate lines SGD and SGS and the plurality of word lines WL are also collectively referred to as stacked wiring.

[0041] The stacked wiring structure is provided, for example, in the X direction across the memory region MR and the lead-out region HR.

[0042] The memory region MR is essentially a region where data is stored.

[0043] The lead-out region HR is a region used for connecting the stacked wiring to the peripheral circuits PERI such as the row decoder module 15.

[0044] Each member SLT extends in the X direction. Each member SLT crosses the stacked wiring structure in the X direction across the memory region MR and the lead region HR. Each member SLT has a structure (closed structure) in which, for example, an insulator or a plate-shaped conductor is embedded inside. Each member SLT separates adjacent stacked wirings via the member SLT. Each area separated by multiple members SLT corresponds to one block BLK. In the following description, the end of the blocks BLK0 to BLK3 on the block BLK0 side along the Y direction is referred to as one end in the Y direction. Furthermore, the end of the blocks BLK0 to BLK3 on the block BLK3 side along the Y direction is referred to as the other end in the Y direction.

[0045] Each member SHE extends in the X direction. In the first embodiment, a case will be described in which three members SHE are provided between adjacent members SLT. Each member SHE crosses the stacked wiring structure in the X direction across the memory region MR. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent select gate lines SGD via the member SHE, for example. Each area partitioned by multiple members SLT and SHE corresponds to one string unit SU.

[0046] In the memory cell array 10, for example, the planar layout shown in FIG. 4 is repeatedly arranged in the Y direction.

[0047] Note that the planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number depending on the number of string units SU.

[0048] 1.1.4.2.2 Memory Cell Array Structure in the Memory Area The structure of the memory cell array 10 in the memory region MR will be described.

[0049] 1.1.4.2.2.1 Planar structure The planar structure of the memory cell array 10 in the memory region MR will be described with reference to Fig. 5. Fig. 5 is a plan view showing an example of a planar layout of the memory cell array included in the semiconductor memory device according to the first embodiment.

[0050] In the memory region MR, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Each member SLT includes a core portion LI and a spacer SP.

[0051] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent members SLT. Then, for example, counting from one end in the Y direction, one member SHE overlaps with the fifth memory pillar MP, the tenth memory pillar MP, and the fifteenth memory pillar MP.

[0052] Each of the multiple bit lines BL extends in the Y direction. The multiple bit lines BL are also aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 5, each bit line BL is arranged so as to overlap two memory pillars MP for each string unit SU. One of the multiple bit lines BL overlapping with a memory pillar MP is electrically connected to the memory pillar MP via a contact CV. For example, no contact is provided between the memory pillar MP overlapping with the member SHE and the bit line BL. In other words, the memory pillar MP overlapping with the member SHE is not electrically connected to the bit line BL.

[0053] The core portion LI is a conductor extending in the X direction. The spacers SP are insulators provided on the side surfaces of the core portion LI. The core portion LI is sandwiched between the spacers SP. The core portion LI and the stacked wiring adjacent to the core portion LI in the Y direction are electrically separated by the spacers SP. As a result, the core portion LI and the stacked wiring adjacent to the core portion LI in the Y direction are electrically insulated from each other.

[0054] 1.1.4.2.2.2 Cross-sectional structure The cross-sectional structure of the memory region MR of the memory cell array 10 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the first embodiment.

[0055] The memory cell array 10 further includes conductor layers 30, 31, 32, 33, and 35, multiple conductor layers 34, 36, 37, and 38, insulator layers 40, 41, 43, 44, and 45, and multiple insulator layers 42. FIG. 6 shows five memory pillars MP out of the multiple memory pillars MP. FIG. 6 also shows a case where the multiple conductor layers 34 and multiple insulator layers 42 include eight conductor layers 34 and eight insulator layers 42. The memory cell array 10 is provided between the electrode pads PD of the semiconductor memory device 1 and a semiconductor substrate in the Z direction.

[0056] The conductor layer 30 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 30 is made of a conductive material. The conductive material is, for example, an N-type semiconductor doped with impurities.

[0057] A conductor layer 31 is provided on the first surface of the conductor layer 30. The conductor layer 31 is made of a conductive material. For example, the conductive material is doped polysilicon to which N-type impurities are added. As will be described later, the conductor layer 31 is formed on the conductor layer 30 and the first surfaces of the multiple memory pillars MP. As a result, the first surface of the conductor layer 31 has irregularities corresponding to, for example, the multiple memory pillars MP. In other words, the first surface of the conductor layer 31 does not need to be flat.

[0058] The conductor layer 32 is provided on the first surface of the conductor layer 31. The conductor layer 32 is made of a conductive material. The conductive material includes, for example, at least one of tungsten, aluminum, titanium, and titanium nitride. The conductor layer 32 is formed on the first surface of the conductor layer 31, as described below. As a result, the first surface of the conductor layer 32 has irregularities corresponding to the multiple memory pillars MP, similar to the first surface of the conductor layer 31. In other words, the first surface of the conductor layer 32 does not have to be flat, similar to the first surface of the conductor layer 31.

[0059] The conductive layers 30, 31, and 32 thus formed function as source lines SL.

[0060] An insulator layer 40 is stacked on the second surface of the conductor layer 30. A conductor layer 33 is stacked on the second surface of the insulator layer 40. The conductor layer 33 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 33 is used as a select gate line SGS. The conductor layer 33 includes, for example, tungsten.

[0061] An insulator layer 41 is stacked on the second surface of the conductor layer 33. Eight conductor layers 34 and eight insulator layers 42 are stacked on the second surface of the insulator layer 41 in the Z2 direction in the order conductor layer 34, insulator layer 42, ..., conductor layer 34, insulator layer 42. The conductor layer 34 is provided, for example, in the shape of a plate extending along the XY plane. The eight conductor layers 34 are used as word lines WL0 to WL7 in order along the Z2 direction. The conductor layers 34 include, for example, tungsten.

[0062] A conductor layer 35 is stacked on the second surface of the othermost insulator layer 42 in the Z direction among the eight insulator layers 42. The conductor layer 35 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 35 is used as a select gate line SGD. The conductor layer 35 includes, for example, tungsten. The conductor layer 35 is electrically insulated for each string unit SU by, for example, a plurality of members SHE.

[0063] An insulating layer 43 is stacked on the second surface of the conductive layer 35. A plurality of conductive layers 36 are stacked on the second surface of the insulating layer 43. Each conductive layer 36 is provided to extend along the Y direction. FIG. 6 illustrates one of the plurality of conductive layers 36. Each conductive layer 36 functions as a bit line BL. The plurality of conductive layers 36 are electrically connected to a plurality of memory pillars MP via a plurality of conductive layers 37 and 38.

[0064] The laminated structure including the conductive layers 30-33 and 35, the plurality of conductive layers 34 and 36-38, the insulator layers 40, 41, and 43, and the plurality of insulator layers 42 is provided so as to be surrounded by insulators. FIG. 6 shows the insulator layer 44 in contact with the first surface of the conductive layer 32 and the insulator layer 45 in contact with the second surface of the conductive layer 36. Although not shown in FIG. 6, the conductive layer 32 is electrically connected to the peripheral circuit PERI via a conductive layer on one side of the conductive layer 32, as will be described later. Although not shown in FIG. 6, each of the plurality of conductive layers 36 is electrically connected to the peripheral circuit PERI via, for example, a conductive layer on the other side of the plurality of conductive layers 36, as will be described later.

[0065] A plurality of memory pillars MP are provided extending along the Z direction on one side of the plurality of conductive layers 36. The plurality of memory pillars MP penetrate the conductive layers 30, 33, and 35 and the plurality of conductive layers 34.

[0066] Each of the multiple memory pillars MP includes, for example, a core member 50, a semiconductor film 51, and a stacked film 52. The core member 50 is provided extending along the Z direction. The semiconductor film 51 covers the periphery of the core member 50. The semiconductor film 51 contacts the conductor layer 31. The stacked film 52 covers the side surface of the semiconductor film 51 except for the portion where the semiconductor film 51 contacts the conductor layer 31. The core member 50 includes an insulator such as silicon oxide. The semiconductor film 51 includes, for example, silicon. The configuration of the stacked film 52 will be described later.

[0067] A conductor layer 37 is provided on the second surface of the semiconductor film 51. The conductor layer 37 functions, for example, as a columnar contact. A conductor layer 38 is provided on the second surface of the conductor layer 37. The conductor layer 38 functions, for example, as a contact CV. With the above configuration, the conductor layers 37 and 38 connect the semiconductor film 51 and the conductor layer 36. One conductor layer 37 and one conductor layer 38 are connected to one conductor layer 36 in each of the spaces partitioned by the members SLT and SHE.

[0068] The member SLT divides, for example, the conductive layers 30, 33, and 35 and the plurality of conductive layers 34. A core portion LI within the member SLT is provided along the member SLT. The second surface of the core portion LI is located between the conductive layer 35 and the conductive layer 36. The first surface of the core portion LI is located, for example, between the conductive layer 30 and the insulating layer 44. A spacer SP is provided between the core portion LI and the conductive layers 30, 31, 33, and 35 and the plurality of conductive layers 34. The core portion LI is separated and electrically insulated from the conductive layers 30, 31, 33, and 35 and the plurality of conductive layers 34 by the spacer SP. Although not shown in FIG. 6 , the core portion LI may include a barrier metal. That is, the core portion LI may have a structure in which a barrier metal covers the first surface and side surfaces of a conductive member containing a metal such as tungsten. Moreover, the core portion LI may be formed of a semiconductor member, or may have a structure in which the entire member SLT is embedded in the insulating material of the spacer SP.

[0069] The intersections of the memory pillars MP and the conductive layer 33 function as select transistors ST2. The intersections of the memory pillars MP and the conductive layers 34 function as memory cell transistors MT. The intersections of the memory pillars MP and the conductive layer 35 function as select transistors ST1.

[0070] 1.1.4.2.2.3 Cross-sectional structure of memory pillar The structure of the memory pillar MP will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of the cross-sectional structure of the memory pillar of the semiconductor memory device according to the first embodiment.

[0071] The stacked film 52 includes a tunnel insulating film 53, a charge storage film 54, and a block insulating film 55. The tunnel insulating film 53 covers the side surface of the semiconductor film 51 except for the portion where the semiconductor film 51 and the conductor layer 31 contact each other. The charge storage film 54 covers the side surface of the tunnel insulating film 53. The block insulating film 55 covers the side surface of the charge storage film 54.

[0072] The tunnel insulating film 53 and the block insulating film 55 include, for example, silicon oxide. The charge storage film 54 includes, for example, silicon nitride. The charge storage film 54 is a film that can store electric charges.

[0073] In the above configuration, the semiconductor film 51 functions as the channels of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The charge storage film 54 has the function of storing an amount of charge corresponding to the data stored in the memory cell transistors MT. By turning on the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2, the semiconductor memory device 1 passes a current between the source line SL and the bit line BL via the memory pillar MP and the conductor layers 37 and 38.

[0074] 1.1.4.3 Overall cross-sectional structure of semiconductor memory device The overall cross-sectional structure of the semiconductor memory device 1 will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the first embodiment. Fig. 8 shows the cross-sectional structure of a portion of the semiconductor memory device 1.

[0075] The semiconductor memory device 1 has a structure in which a circuit chip 1-1 and a memory chip 1-2 are bonded together.

[0076] 1.1.4.3.1 Circuit Chip First, the cross-sectional structure of the circuit chip 1-1 will be described.

[0077] The circuit chip 1-1 includes, for example, a semiconductor substrate 70, a plurality of conductor layers 101, 102, 103, 104, 105, and 106 that form part of the peripheral circuit PERI, and insulator layers 46 and 60. The semiconductor substrate 70 is made of, for example, a P-type semiconductor doped with impurities.

[0078] The plurality of conductive layers 101 to 106 each function as, for example, a columnar contact or wiring. The plurality of conductive layers 103 includes conductive layers 103-1 and 103-2. The plurality of conductive layers 104 includes conductive layers 104-1 and 104-2. The plurality of conductive layers 105 includes conductive layers 105-1 and 105-2. The plurality of conductive layers 106 includes conductive layers 106-1 and 106-2.

[0079] An insulator layer 46 is provided on the first surface of the semiconductor substrate 70. The insulator layer 46 includes, for example, silicon oxide. A plurality of conductor layers 101, 102, 103, 104, and 105 are provided within the insulator layer 46.

[0080] A peripheral circuit PERI is provided in a circuit region CR on the first surface of the semiconductor substrate 70. In FIG. 8, transistors Tr1 and Tr2 are shown as examples of components included in the peripheral circuit PERI. In the following description, when there is no need to distinguish between the transistors Tr1 and Tr2, the transistors Tr1 and Tr2 will simply be referred to as transistors Tr. Each transistor Tr includes a gate insulating film, a gate electrode, and a source and a drain (not shown) provided in the semiconductor substrate 70.

[0081] A plurality of conductive layers 101 are provided on the first surfaces of the gate electrode, source, and drain of transistor Tr1 and the gate electrode, source, and drain of transistor Tr2. A plurality of conductive layers 102 are connected to the first surfaces of the plurality of conductive layers 101, respectively.

[0082] Each of the plurality of conductive layers 103 is connected to a first surface of the conductive layer 102 corresponding to that conductive layer 103 among the plurality of conductive layers 102. Conductive layers 103-1 and 103-2 are electrically connected to transistors Tr1 and Tr2, respectively.

[0083] The conductive layers 104-1 and 104-2 are connected to the first surfaces of the conductive layers 103-1 and 103-2, respectively.

[0084] The conductive layers 105-1 and 105-2 are connected to the first surfaces of the conductive layers 104-1 and 104-2, respectively. The first surfaces of the plurality of conductive layers 105 are provided so as to be flush with the first surface of the insulating layer 46.

[0085] An insulator layer 60 is provided on the insulator layer 46 and the first surfaces of the plurality of conductor layers 105. The insulator layer 60 includes, for example, silicon oxide.

[0086] A plurality of conductor layers 106 are provided on the same layer as the insulator layer 60. The conductor layers 106-1 and 106-2 are connected to first surfaces of the conductor layers 105-1 and 105-2, respectively. The first surfaces of the plurality of conductor layers 106 are provided so as to be flush with the first surface of the insulator layer 60. The plurality of conductor layers 106 include, for example, copper. The plurality of conductor layers 106 function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. The connection pads are also called bonding pads.

[0087] 1.1.4.3.2 Memory Chips Next, the cross-sectional structure of the memory chip 1-2 will be described with reference to FIG.

[0088] The memory chip 1-2 includes, for example, a plurality of conductive layers 201, 202, 203, 204, 205, 206, and 207, a conductive layer 39, insulator layers 44, 45, 47, 48a, 48b, 48c, 61, and 62, semiconductor layers 301 and 302, a plurality of connecting portions V1 and V2, and a memory cell array 10.

[0089] The plurality of conductor layers 201 to 207 each function as, for example, a columnar contact or wiring. The plurality of conductor layers 201 includes conductor layers 201-1 and 201-2. The plurality of conductor layers 202 includes conductor layers 202-1 and 202-2. The plurality of conductor layers 203 includes conductor layers 203-1 and 203-2. The plurality of conductor layers 204 includes conductor layers 204-1 and 204-2. The plurality of conductor layers 205 includes conductor layers 36 (205) and 205-1. The plurality of conductor layers 206 includes conductor layers 206-1, 206-2, and 206-3. The plurality of conductor layers 207 includes conductor layers 207-1, 207-2, and 207-3.

[0090] In the memory chip 1-2, an insulating layer 61 is provided on the first surface of the circuit chip 1-1. The insulating layer 61 includes, for example, silicon oxide.

[0091] A plurality of conductor layers 201 are provided on the same layer as the insulator layer 61. The conductor layers 201-1 and 201-2 are connected to first surfaces of the conductor layers 106-1 and 106-2, respectively. The second surfaces of the plurality of conductor layers 201 are provided so as to be flush with the second surface of the insulator layer 61. The plurality of conductor layers 201 include, for example, copper. The plurality of conductor layers 201 function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. With the above-described configuration, the circuit chip 1-1 and the memory chip 1-2 are electrically connected by the plurality of conductor layers 106 and 201.

[0092] An insulating layer 45 is provided on the first surfaces of the insulating layer 61 and the plurality of conductor layers 201. In the insulating layer 45, the plurality of conductor layers 202 to 206, a portion of the plurality of conductor layers 207, and a portion of the memory cell array 10 are provided.

[0093] The memory cell array 10 is provided so that the conductive layer 32 is disposed on one side in the Z direction, and the conductive layer 36 (205) is disposed on the other side in the Z direction.

[0094] Conductor layer 202-1 is provided on a first surface of conductive layer 201-1. Conductor layer 203-1 is connected to the first surface of conductive layer 202-1. Conductor layer 204-1 is connected to the first surface of conductive layer 203-1. The first surface of conductive layer 204-1 is connected to conductive layer 36 (205). With the above configuration, conductive layer 36 and transistor Tr1 are connectable. That is, bit lines BL of memory cell array 10 and peripheral circuit PERI are electrically connected.

[0095] A conductor layer 202-2 is provided on the first surface of the conductor layer 201-2. A conductor layer 203-2 is provided on the first surface of the conductor layer 202-2. A conductor layer 204-2 is provided on the first surface of the conductor layer 203-2. A conductor layer 205-1 is provided on the first surface of the conductor layer 204-2. A conductor layer 206-1, 206-2, and 206-3 are provided on the first surface of the conductor layer 205-1. A conductor layer 207-1 is provided on the first surface of the conductor layer 206-1. The conductor layer 207-1 extends in the Z direction. One side of the conductor layer 207-1 protrudes from the insulator layer 45. The conductor layer 207-1 functions, for example, as a columnar contact.

[0096] Similar to the conductor layer 206-1, conductor layers 207-2 and 207-3 are provided on the first surfaces of the conductor layers 206-2 and 206-3, respectively. Similar to the conductor layer 207-1, the conductor layers 207-2 and 207-3 extend in the Z direction. One side of each of the conductor layers 207-2 and 207-3 protrudes from the insulating layer 45. The conductor layers 207-2 and 207-3 function as, for example, columnar contacts. The conductor layers 207-1, 207-2, and 207-3 are electrically connected to the common conductor layer 201-2 via the conductor layer 205-1 in the insulating layer 45. In addition, each of the conductive layers 207-1, 207-2, and 207-3 may be electrically connected to the conductive layer 201-2 via the common conductive layer 203-2, and also via a plurality of conductive layers 204 and a plurality of conductive layers 205, respectively, provided on the first surface of the conductive layer 203-2.

[0097] In a region excluding the memory cell array 10, for example, a semiconductor layer 301 is provided on a portion of the first surface of the insulator layer 45, sandwiching a region R1 including a portion where the plurality of conductor layers 207 are provided, and adjacent to the region R1. The semiconductor layer 301 and the conductor layer 30 in the memory cell array 10 are provided in the same layer. An insulator layer 62 is provided on the first surface of the semiconductor layer 301. A semiconductor layer 302 is provided on the first surface of the insulator layer 62. The semiconductor layers 301 and 302 are, for example, non-doped polysilicon. The semiconductor layers 301 and 302 are electrically insulated from the source line SL. An insulator layer 47 is provided on the first surface of the semiconductor layer 302. With the above configuration, in FIG. 8 , the region R1 is sandwiched in the Y direction between two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62.

[0098] The first surface of the insulator layer 45 in the region R1 is located, for example, on the other side of the first surface of the insulator layer 45 in a region adjacent to the region R1 in a region excluding the memory cell array 10. In other words, the first surface of the insulator layer 45 in the region R1 is located, for example, on the other side of the second surface of the semiconductor layer 301.

[0099] In region R1, a conductor layer 32B is provided on a portion of the first surface of the insulator layer 45. The conductor layer 32B contacts one side portions of the multiple conductor layers 207 protruding from the insulator layer 45. The conductor layer 32B is made of, for example, the same conductive material as the conductive material constituting the conductor layer 32. The conductor layer 32B is provided, for example, to have a plate-like pattern extending along the XY plane. The conductor layer 32B is provided to cover one side portions of the multiple conductor layers 207. The first surface of the conductor layer 32B has, for example, irregularities corresponding to the multiple conductor layers 207. In other words, the first surface of the conductor layer 32B does not have to be flat. However, this is not a limitation, and the first surface of the conductor layer 32B may be flat.

[0100] A plurality of connection portions V1 are provided on the first surface of the conductive layer 32. The plurality of connection portions V1 are made of a conductive material. The conductive material includes, for example, tungsten. Although FIG. 8 shows an example in which two connection portions V1 are provided on the first surface of the conductive layer 32, the present invention is not limited to this. The number of connection portions V1 may be one or more.

[0101] A plurality of connection portions V2 are provided on the first surface of the conductive layer 32B. The plurality of connection portions V2 are made of a conductive material. The conductive material includes, for example, tungsten. Although FIG. 8 shows an example in which three connection portions V2 are provided on the first surface of the conductive layer 32B, the present invention is not limited to this. The number of connection portions V2 may be one or more.

[0102] An insulator layer 44 is provided on the first surface of the insulator layer 45 in the region R1 excluding the portion where the conductor layer 32B is provided, on the first surface of the insulator layer 47, and on the first surfaces of the conductor layers 32 and 32B excluding the portions where the multiple connection portions V1 and V2 are provided. The first surface of the insulator layer 44 has, for example, a uniform height. The first surface of the insulator layer 44 is provided so as to be flush with the first surfaces of the multiple connection portions V1 and V2. Note that, as shown in a fourth modified example of the first embodiment described below, the first surface of the insulator layer 44 may have a step.

[0103] Conductor layers 31A and 32A resulting from the formation of conductor layers 31 and 32, which will be described later, may be provided on two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62, sandwiching region R1 in the Y direction. Note that in a region not shown in FIG. 8 , region R1 may also be sandwiched in the X direction using a similar configuration. That is, the semiconductor memory device 1 may have, for example, two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62, sandwiching region R1 in the X direction. Conductor layers 31A and 32A resulting from the formation of conductor layers 31 and 32, which will be described later, may also be provided on these two wall surfaces. As described above, region R1 is surrounded by four wall surfaces, for example, when viewed from above. With the above configuration, conductor layers 31A and 32A may be provided between each of the wall surfaces and the insulator layer 44. The conductive layers 31A and 32A may be provided on a portion of each wall surface or on the entire surface.

[0104] The conductor layer 39 includes, for example, portions provided on the first surfaces of the plurality of connection portions V1 and on portions of the first surface of the insulator layer 44 surrounding the plurality of connection portions V1 so as to be in contact with the plurality of connection portions V1, and portions provided on the first surfaces of the plurality of connection portions V2 and on portions of the first surface of the insulator layer 44 surrounding the plurality of connection portions V2 so as to be in contact with the plurality of connection portions V2. The conductor layer 39 functions as a wiring layer extending in the Y direction. The portions of the conductor layer 39 in contact with the plurality of connection portions V1 and the portions of the conductor layer 39 in contact with the plurality of connection portions V2 are provided at the same height. The conductor layer 39 includes, for example, aluminum.

[0105] In the above configuration, each of the plurality of connection portions V1 can be said to be a via filled with the space between the portion of the conductive layer 39 in contact with the plurality of connection portions V1 and the conductive layer 32. Also, each of the plurality of connection portions V2 can be said to be a via filled with the space between the portion of the conductive layer 39 in contact with the plurality of connection portions V2 and the conductive layer 32B.

[0106] The portion of the conductive layer 39 in contact with the plurality of connection portions V2 includes a region exposed on the first surface of the semiconductor memory device 1. This region constitutes, for example, an electrode pad PD that is connected to an external device of the semiconductor memory device 1. The electrode pad PD is provided at a position overlapping with the region R1 in the Z direction. As a result, the semiconductor layers 301 and 302 are not provided in the region overlapping with the electrode pad PD in the Z direction. Furthermore, the electrode pad PD is provided at a position at least partially overlapping with, for example, the plurality of connection portions V2, the plurality of conductive layers 207, and the conductive layer 32B in the Z direction. Note that the electrode pad PD is provided such that, for example, the area of ​​the conductive layer 32B is smaller than the area of ​​the electrode pad PD when viewed in the Z direction.

[0107] With the above-described configuration, for example, the electrode pad PD and the transistor Tr2 are connectable via the conductive layers 32B, 101 to 106, and 201 to 207 and the plurality of connection portions V2. That is, the electrode pad PD and the peripheral circuit PERI are electrically connected.

[0108] Note that the portion of the conductive layer 39 in contact with the plurality of connection portions V1 and the portion of the conductive layer 39 in contact with the plurality of connection portions V2 are, for example, electrically isolated from each other. In this case, although not shown, for example, the portion of the conductive layer 39 in contact with the plurality of connection portions V1 is configured to be connected to the peripheral circuit PERI of the circuit chip 1-1 by a configuration similar to that of the conductive layers 201-207. This allows the conductive layer 32 and the peripheral circuit PERI to be connectable via the conductive layers 39, 101-106, and 201-207 and the plurality of connection portions V1. However, the configuration is not limited to the above, and although not shown, the portion of the conductive layer 39 in contact with the plurality of connection portions V1 and the portion of the conductive layer 39 in contact with the plurality of connection portions V2 may be connected to each other.

[0109] On one side of the semiconductor memory device 1, except for the portion where the electrode pads PD are provided, insulator layers 48a, 48b, and 48c are stacked in this order on one side in the Z direction. The insulator layer 48a is an insulator containing, for example, silicon oxide. The insulator layers 48b and 48c contain, for example, silicon nitride and a resin material. The insulator layers 48b and 48c function, for example, as a passivation film.

[0110] 1.1.4.3.3 Structure around multiple connection parts V2 The structure around the multiple connection portions V2 will be further described with reference to Fig. 9. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 8, showing an example of a connection portion between a wiring layer and a contact in the semiconductor memory device according to the first embodiment.

[0111] In the XY cross section, the plurality of conductor layers 207 functioning as contacts are arranged, for example, in a lattice pattern. In Fig. 9, nine conductor layers 207 indicated by dotted lines are arranged in a 3-row, 3-column lattice pattern. The shape of the XY cross section of each of the plurality of conductor layers 207 may be circular or rectangular.

[0112] In the XY cross section, the multiple connection portions V2 are arranged in a lattice pattern, for example, similar to the multiple conductive layers 207. In Fig. 9, nine connection portions V2 are arranged in a lattice pattern of 3 rows and 3 columns, similar to the multiple conductive layers 207. The multiple connection portions V2 may or may not overlap with the multiple conductive layers 207 when viewed in the Z direction. The shape of each of the multiple connection portions V2 in the XY cross section may be circular or rectangular.

[0113] In addition, in each of the X direction and the Y direction, the interval (pitch) at which the plurality of connection portions V2 are provided and the interval at which the plurality of conductive layers 207 are provided can be set independently.

[0114] 1.1.4.3.4 Cross-sectional structure of connection pads The cross-sectional structure of the connection pad will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view showing an example of the cross-sectional structure of the connection pad of the semiconductor memory device according to the first embodiment. Note that, although the following describes the portion where the conductor layer 106-1 and the conductor layer 201-1 are connected, the same applies to the portions where each of the other plurality of conductor layers 106 is connected to the conductor layer 201 corresponding to that conductor layer 106.

[0115] On the bonding surface where the circuit chip 1-1 and the memory chip 1-2 are bonded together, the area of ​​the conductor layer 106-1 and the area of ​​the conductor layer 40-1 are, for example, equal. If the conductor layers 106-1 and 201-1 are copper, they may become integrated, making it difficult to identify the boundary between the copper layers. However, for example, the bonding can be confirmed by the distortion of the bonded shape of the conductor layers 106-1 and 201-1 due to misalignment during bonding. Furthermore, the bonding can be confirmed by the misalignment of the copper barrier metal, for example. That is, the bonding can be confirmed by the occurrence of discontinuities on the side surfaces.

[0116] Furthermore, when the conductive layers 106-1 and 201-1 are formed by the damascene method, their respective side surfaces have a tapered shape. As a result, the sidewalls of the conductive layers 106-1 and 201-1 are not linear. As a result, the cross section along the Z direction at the bonded portion of the conductive layers 106-1 and 201-1 is non-rectangular.

[0117] Furthermore, when the conductive layers 106-1 and 201-1 are bonded together, the first, second, and side surfaces of the copper that forms them are covered with a barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbide containing nitrogen) that functions to prevent oxidation of copper is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0118] 1.2 Manufacturing method of semiconductor memory device A method for manufacturing the semiconductor memory device 1 will be described with reference to Figures 11 to 20. Figures 11 to 20 are cross-sectional views for explaining an example of a method for manufacturing the semiconductor memory device according to the first embodiment. The cross-sectional views shown in Figures 11 to 20 show the region corresponding to Figure 8.

[0119] 11, the transistors Tr1 and Tr2 included in the peripheral circuit PERI, the plurality of conductor layers 101 to 106, and the insulator layers 46 and 60 are formed on the semiconductor substrate 70. That is, the circuit chip 1-1 is formed.

[0120] 12, on the second surface of semiconductor substrate 71 made of an impurity-doped P-type semiconductor, insulator layer 47, conductor layers 33 and 35, multiple conductor layers 34 and 201-207, semiconductor layers 301 and 302, insulator layers 40, 41, 43, and 62, multiple insulator layers 42, structures corresponding to multiple memory pillars MP, multiple members SLT, and portions of insulator layer 45 and insulator layer 61 covering these are formed. In other words, a structure corresponding to memory chip 1-2 is formed. Note that semiconductor layers 301 and 302 and insulator layers 47 and 62 are entirely formed on the second surface of semiconductor substrate 71.

[0121] 13, the circuit chip 1-1 and the structure corresponding to the memory chip 1-2 are bonded together by a bonding process. More specifically, a plurality of conductor layers 106 functioning as connection pads in the circuit chip 1-1 and a plurality of conductor layers 201 functioning as connection pads in the memory chip 1-2 are arranged to face each other. The facing connection pads are then bonded together by a heat treatment. Thereafter, the semiconductor substrate 71 is removed by, for example, CMP (Chemical Mechanical Polishing).

[0122] 14, the insulator layer 47 and the semiconductor layer 302 are removed from the portion corresponding to the memory cell array 10 and the portion corresponding to the region R1. The removal of the portion corresponding to the memory cell array 10 and the portion corresponding to the region R1 is performed, for example, all at once.

[0123] Furthermore, in the memory pillar MP, a portion of the stacked film 52 on one side of the insulator layer 62 is removed. As a result, the semiconductor film 51 on one side of the insulator layer 62 is exposed to the surface. Furthermore, the insulator layer 62 is removed in a portion corresponding to the memory cell array 10 and a portion corresponding to the region R1. As a result, the semiconductor layer 301 is exposed to the surface in a portion corresponding to the memory cell array 10 and a portion corresponding to the region R1. Note that in the portion corresponding to the memory cell array 10, for example, portions on one side of the plurality of members SLT are also exposed to the surface. Furthermore, in the portion corresponding to the region R1, for example, portions on one side of the plurality of conductor layers 207 are also exposed to the surface.

[0124] Next, as shown in FIG. 15 , a conductor layer 31 is stacked on the exposed portions of the first surface of the semiconductor layer 301, the exposed portions of the memory pillars MP, the first surface of the insulator layer 47, the portions on one side of the plurality of members SLT, and the portions on one side of the plurality of conductor layers 207. At this time, the portion of the semiconductor layer 301 corresponding to the memory cell array 10 is transformed into the conductor layer 30 by impurity diffusion. More specifically, in the above process, amorphous silicon is first deposited on the exposed portions of the first surface of the semiconductor layer 301, the exposed portions of the memory pillars MP, the first surface of the insulator layer 47, the portions on one side of the plurality of members SLT, and the portions on one side of the plurality of conductor layers 207. Then, by introducing impurities into the deposited amorphous silicon and subsequent heat treatment, the impurities diffuse into the semiconductor layer 301, and the deposited amorphous silicon is transformed into polysilicon. As a result, the conductive layers 30 and 31 are formed.

[0125] 16, a portion of the conductive layer 31 formed as described above, excluding the memory cell array 10, is removed by etching or the like using a mask. At this time, the semiconductor layer 301 and one side of the insulator layer 45 are also removed in the portion corresponding to region R1. As a result, the first surface of the insulator layer 45 and one side of each of the plurality of conductive layers 207 protruding from the insulator layer 45 are exposed to the surface in the portion corresponding to region R1. Also, in FIG. 16, a conductive layer 31A is formed as a trace of the conductive layer 31 on the wall surface formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62 by the above-described process.

[0126] Then, as shown in FIG. 17, a conductor layer 32 is laminated on the first surface of the conductor layer 31, on the conductor layer 31A, on the first surface of the insulator layer 47, on the exposed portion of the first surface of the insulator layer 45, and on one side portions of the multiple conductor layers 207 protruding from the insulator layer 45.

[0127] 18, the conductive layer 32 formed as described above is removed except for the regions corresponding to the memory cell array 10 and the conductive layer 32B. This forms the conductive layer 32 and the conductive layer 32B of the memory cell array 10. In FIG. 18, the conductive layer 32A is formed as a trace of the conductive layer 32 on the wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62 by the above-described process. Note that in this process, a portion on one side of the insulator layer 45 can also be removed, similar to the process of removing the conductive layer 31 and the semiconductor layer 301 in the portion corresponding to the region R1 described above.

[0128] 19, an insulator layer 44 is formed on the first surface of the conductor layer 32, the first surface of the conductor layer 32B, the first surface of the insulator layer 47, a portion of the first surface of the insulator layer 45 that is exposed at the surface in a portion corresponding to the region R1, and the conductor layers 31A and 32A. Also, a portion on one side of the insulator layer 44 is removed by CMP.

[0129] Next, grooves corresponding to the multiple connection portions V1 and V2 are formed. More specifically, regions where the multiple connection portions V1 and V2 are to be formed are collectively removed by anisotropic etching using a mask including openings corresponding to the multiple connection portions V1 and V2. This forms the grooves. The anisotropic etching is performed, for example, until the conductive layer 32B is exposed in each region that overlaps in the Z direction with the openings corresponding to the multiple connection portions V2. The anisotropic etching in this process is, for example, RIE. The mask is then removed.

[0130] 20, a conductive material is filled into the grooves corresponding to the plurality of connection portions V1 and the grooves corresponding to the plurality of connection portions V2, thereby forming the plurality of connection portions V1 and V2.

[0131] Then, a conductor layer 39 is formed on the first surface of the insulator layer 44 and on the first surfaces of the plurality of connection portions V1 and V2. Furthermore, on the first surface of the structure formed as described above, excluding the regions of the conductor layer 39 corresponding to the electrode pads PD, insulator layers 48a, 48b, and 48c are formed.

[0132] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0133] It should be noted that the manufacturing process described above is merely an example, and other processes may be inserted between the respective manufacturing processes, or the order of the manufacturing processes may be changed. For example, since the structures corresponding to the circuit chip 1-1 and the memory chip 1-2 are formed using different semiconductor substrates 70 and 71, the process of forming the circuit chip 1-1 shown in Figure 11 and the process of forming the structure corresponding to the memory chip 1-2 shown in Figure 12 can be carried out in parallel.

[0134] 1.3 Effects According to the first embodiment, it is possible to improve the degree of freedom in designing a semiconductor memory device. The effects of the first embodiment will be described below.

[0135] In the first embodiment, the semiconductor memory device 1 includes a circuit chip 1-1 including a semiconductor substrate 70 having an array region AR and a peripheral region PR, and a memory chip 1-2 that contacts the circuit chip 1-1 in the Z direction and is electrically connected to the circuit chip 1-1 via multiple connection pads provided in the boundary region with the circuit chip 1-1. The memory chip 1-2 includes a memory cell array 10, multiple conductor layers 207, and conductor layers 32B and 39. The memory cell array 10 is provided in the array region AR and includes a source line SL, multiple word lines WL spaced apart from each other in the Z direction below the source line SL, and memory pillars MP extending in the Z direction to intersect with the multiple word lines WL and connected at their upper ends to the source line SL. Each of the multiple conductor layers 207 is provided in the peripheral region PR, extends in the Z direction, and is electrically connected to one of the multiple connection pads. Each of the multiple conductor layers 207 functions as a contact. The conductor layer 32B contacts the upper ends of the multiple conductor layers 207. The conductor layer 39 is provided above the conductor layer 32B and is electrically connected to the conductor layer 32B. The conductor layer 39 functions as a wiring layer provided above the conductor layer 32B. With the above configuration, the conductor layer 39 and the plurality of conductor layers 207 are connected via the conductor layer 32B. This facilitates the connection between the conductor layer 39 and the plurality of conductor layers 207, improving the degree of freedom in designing the semiconductor memory device 1.

[0136] Additionally, in the first comparative example, in which a plurality of contacts electrically connected to connection pads that connect a circuit chip and a memory chip are directly connected to a wiring layer provided above the plurality of contacts via a plurality of connection portions corresponding to the plurality of contacts, it is necessary to align the positions of the plurality of contacts with the plurality of connection portions in order to prevent connection failures between the plurality of contacts and the plurality of connection portions. Furthermore, in order to align the positions in this way, the spacing between the plurality of contacts and the spacing between the plurality of connection portions must be made equal.

[0137] According to the first embodiment, the conductive layer 39 and the plurality of conductive layers 207 are connected via the pattern of the conductive layer 32B, which is provided in a plate shape extending along the XY plane. This makes it possible to prevent connection failures when connecting the plurality of conductive layers 207 and the conductive layer 39 without having to align the plurality of conductive layers 207 with the plurality of connection portions V2. Furthermore, the spacing between the plurality of conductive layers 207 and the spacing between the plurality of connection portions V2 can be set independently. This improves the degree of freedom in designing the semiconductor memory device 1.

[0138] As a result, according to the first embodiment, it is possible to eliminate the alignment step and reduce the number of steps compared to the first comparative example.

[0139] Furthermore, according to the first embodiment, it is possible to prevent damage (breakage, chipping, and cracking) to the contacts.

[0140] To further add, for example, in the case of the second comparative example, in which the wiring layer connected to the contact has a stepped structure in the YZ cross section, the contact is connected to a plate-like portion of the stepped wiring layer that is parallel to the semiconductor substrate. In this case, if the contact and the electrode pad are arranged to overlap when viewed from above in order to reduce the size of the semiconductor memory device, the plate-like portion directly connected to the contact will function as the electrode pad. This may result in damage (bending, chipping, and cracking) to the contact. That is, for example, pressure applied by a probe needle during evaluation may damage the contact provided directly below the electrode pad.

[0141] According to the first embodiment, even if the electrode pad PD and the multiple conductor layers 207 are arranged so as to overlap, the conductor layer 39 and the multiple conductor layers 207 are connected via the connection portion V2 and the conductor layer 32B, thereby preventing damage to the contacts.

[0142] Furthermore, according to the first embodiment, the electrode pads PD are provided at positions overlapping with the region R1 when viewed in the Z direction. That is, the semiconductor layers 301 and 302 are removed in the regions overlapping with the electrode pads PD in the Z direction. This suppresses interference between the electrode pads PD and the conductive layer provided on the other side of the electrode pads PD and having a different potential from that of the electrode pads PD. Therefore, it is possible to suppress a decrease in interface speed.

[0143] 2. Modification of the First Embodiment The first embodiment described above can be modified in various ways, and semiconductor memory devices according to modifications of the first embodiment will be described below.

[0144] 2.1 First Modification of the First Embodiment In the first embodiment described above, the case where the multiple connection portions V1 and V2 have a different configuration from the conductive layer 39 has been described, but this is not limiting. The multiple connection portions V1 and V2 may be part of the conductive layer 39. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the first modification of the first embodiment will be described, focusing on the differences from the configuration and manufacturing method of the semiconductor memory device according to the first embodiment.

[0145] The configuration of a semiconductor memory device 1 according to a first modification of the first embodiment will be described with reference to Fig. 21. Fig. 21 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the first modification of the first embodiment.

[0146] 21 , in the semiconductor memory device 1 according to the first modification of the first embodiment, the conductor layer 39 connected to the conductor layer 32 includes an extension portion extending in the Y direction and a plurality of connection portions V1 connecting the extension portion to the conductor layer 32. That is, in the first modification of the first embodiment, the plurality of connection portions V1 are configured to be included in the conductor layer 39.

[0147] Furthermore, the conductor layer 39 connected to the conductor layer 32B includes an extending portion extending in the Y direction and a plurality of connection portions V2 connecting the extending portion to the conductor layer 32B. That is, in the first modification of the first embodiment, the plurality of connection portions V2 are configured to be included in the conductor layer 39.

[0148] Although not shown, the aspect ratio H1 / W1 of the height H1 of the connection portion V1 to the width W1 of the connection portion V1 along the Y direction is, for example, approximately 1.5 or less. The aspect ratio H1 / W2 of the height H1 to the width W2 of the connection portion V1 along the X direction (not shown) is also, for example, approximately 1.5 or less. The aspect ratio H2 / W3 of the height H2 of the connection portion V2 to the width W3 of the connection portion V2 along the Y direction is, for example, approximately 1.5 or less. The aspect ratio H2 / W4 of the height H2 of the connection portion V2 to the width W4 of the connection portion V2 along the X direction (not shown) is also, for example, approximately 1.5 or less. With the above-described configuration of the connection portions V1 and V2, when forming the conductive layer 39 in the manufacturing process of the semiconductor memory device 1, the trenches corresponding to the connection portions V1 and V2 are not insufficiently filled with a conductor.

[0149] Next, the method for manufacturing the semiconductor memory device 1 according to the first modification of the first embodiment will be described with respect to the differences from the method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0150] In the first modification of the first embodiment, after grooves corresponding to the plurality of connection portions V1 and V2 are formed, the grooves are filled with a conductor, thereby forming the conductor layer 39.

[0151] The first modification of the first embodiment also provides the same effects as the first embodiment.

[0152] Furthermore, according to the first modification of the first embodiment, the plurality of connection portions V1 and V2 and the extension portion can be formed in the same process, which makes it possible to suppress an increase in manufacturing costs.

[0153] 2.2 Second Modification of the First Embodiment In the above-described first embodiment and first modification of the first embodiment, the electrode pad is provided so as to overlap with the plurality of connection portions V2, the plurality of conductor layers 207, and the conductor layer 32B in the Z direction, but this is not limiting. Below, the configuration of the semiconductor memory device 1 according to the second modification of the first embodiment will be described, focusing on differences from the configuration of the semiconductor memory device according to the first modification of the first embodiment. The method for manufacturing the semiconductor memory device 1 according to the second modification of the first embodiment is the same as the method for manufacturing the semiconductor memory device according to the first modification of the first embodiment.

[0154] The configuration of a semiconductor memory device 1 according to a second modification of the first embodiment will be described with reference to Fig. 22. Fig. 22 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the second modification of the first embodiment.

[0155] 22 , the electrode pad PD of the conductor layer 39 is provided at a position different from, for example, the multiple connection portions V2, the multiple conductor layers 207, and the conductor layer 32B when viewed in the Z direction. With the above-described configuration, in the region overlapping with the electrode pad PD in the Z direction, the insulator layer 44 is provided in the same layer as the conductor layer 30, the semiconductor layers 301 and 302, and the insulator layer 62. Even with this configuration, the electrode pad PD is not close to a conductor layer that is provided on the other side of the electrode pad PD and has a different potential from that of the electrode pad PD.

[0156] The second modification of the first embodiment also makes it possible to improve the degree of freedom in designing a semiconductor memory device, reduce the number of processes, and prevent damage to contacts, similar to the first embodiment. Also, similar to the first modification of the first embodiment, it makes it possible to prevent an increase in manufacturing costs.

[0157] Note that, in the second modified example of the first embodiment, similarly to the first modified example of the first embodiment, an example is shown in which the multiple connection portions V1 and V2 are part of the conductive layer 39, but this is not limiting. Similar to the first embodiment, the multiple connection portions V1 and V2 may have a configuration different from the conductive layer 39. Also, unlike the first embodiment and the first modified example of the first embodiment described above, the multiple connection portions V2 are not provided so as to correspond to each of the multiple conductive layers 207. In other words, it is sufficient that the multiple connection portions V2 are connected to the conductive layer 32B, and they do not have to be provided so as to correspond to each of the multiple conductive layers 207.

[0158] 2.3 Third Modification of the First Embodiment In the above-described first embodiment, first modification of the first embodiment, and second modification of the first embodiment, the wiring layer above the plurality of connection portions V1 and V2 is configured with a single conductor layer, but this is not limited thereto. The wiring layer above the plurality of connection portions V1 and V2 may be configured with a plurality of conductor layers. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the third modification of the first embodiment will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the first modification of the first embodiment.

[0159] The configuration of a semiconductor memory device 1 according to a third modification of the first embodiment will be described with reference to Fig. 23. Fig. 23 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the third modification of the first embodiment.

[0160] As shown in FIG. 23, in the semiconductor memory device 1 according to the third modification of the first embodiment, the conductive layer 39 is made up of conductive layers 39-1 and 39-2.

[0161] The conductive layer 39-1 includes a portion of the conductive layer 39-1 in contact with the conductive layer 32 and a portion of the conductive layer 39-1 in contact with the conductive layer 32B. The portion of the conductive layer 39-1 in contact with the conductive layer 32 includes an extending portion extending in the Y direction and a plurality of connection portions V1 connecting the extending portion and the conductive layer 32. Each of the plurality of connection portions V1 can be considered to be a via filled with the space between the extending portion and the conductive layer 32. Furthermore, the portion of the conductive layer 39-1 in contact with the conductive layer 32B includes an extending portion extending in the Y direction and a plurality of connection portions V2 connecting the extending portion and the conductive layer 32B. Each of the plurality of connection portions V2 can be considered to be a via filled with the space between the extending portion and the conductive layer 32B. The conductive layer 39-1 includes, for example, tungsten.

[0162] A conductive layer 39-2 is provided on a first surface of the portion of the conductive layer 39-1 including the plurality of connection portions V1 and on a first surface of the portion of the conductive layer 39-1 including the plurality of connection portions V2. The conductive layer 39-2 includes, for example, aluminum.

[0163] In the third modified example of the first embodiment, unlike the first modified example of the first embodiment, the aspect ratios H1 / W1, H1 / W2, H2 / W3, and H2 / W4 of the connection portions V1 and V2 are not limited to approximately 1.5 or less, and may be greater than 1.5.

[0164] The method for manufacturing the semiconductor memory device 1 according to the third modification of the first embodiment is the same as the method for manufacturing the semiconductor memory device according to the first modification of the first embodiment, except that, similar to the formation of the conductive layer 39 in the first modification of the first embodiment, the conductive layer 39-1 is formed so as to fill the trench, and then the conductive layer 39-2 is formed. Note that after the conductive layer 39-1 is formed, for example, no CMP processing of the first surface of the conductive layer 39-1 is performed before the conductive layer 39-2 is formed.

[0165] The third modified example of the first embodiment also provides the same effects as the first embodiment.

[0166] Furthermore, according to the third modification of the first embodiment, the crack resistance of the wiring layer can be improved. Supplementally, as described above, the wiring layer provided on one side of the conductive layer 32B is composed of a plurality of conductive layers including the conductive layers 39-1 and 39-2. This configuration prevents cracks from occurring in the wiring layer when a probe is brought into contact with an electrode pad provided on the wiring layer, when a wire or the like is bonded, or the like.

[0167] 2.4 Fourth Modification of the First Embodiment In the above-described first embodiment, first modified example of the first embodiment, second modified example of the first embodiment, and third modified example of the first embodiment, the first surface of the insulator layer 44 has a uniform height, but this is not limiting. The first surface of the insulator layer 44 may have a step. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the fourth modified example of the first embodiment will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the first modified example of the first embodiment.

[0168] The configuration of a semiconductor memory device 1 according to a fourth modification of the first embodiment will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of a semiconductor memory device according to the fourth modification of the first embodiment.

[0169] In the fourth modified example of the first embodiment, the first surface of the insulator layer 44 in the region R1 is located on the other side of the first surface of the insulator layer 44 on the first surface of the insulator layer 47. The first surface of the insulator layer 44 in the region R1 is located, for example, at approximately the same height as the first surface of the insulator layer 44 on the first surface of the conductor layer 32. Although not shown in FIG. 24 , the first surface of the insulator layer 44 also has a step, for example, near the boundary between the region where the conductor layer 32 is provided and the region adjacent to that region.

[0170] The manufacturing method of the semiconductor memory device 1 according to the fourth variant of the first embodiment is the same as the manufacturing method of the semiconductor memory device according to the first variant of the first embodiment, except that in the manufacturing process corresponding to FIG. 19 of the first embodiment, removal by CMP is not performed until the first surface of the insulator layer 44 becomes flat.

[0171] The fourth modified example of the first embodiment also provides the same effects as the first modified example of the first embodiment.

[0172] 2.5 Fifth Modification of the First Embodiment In the above-described first embodiment, first modified example of the first embodiment, second modified example of the first embodiment, third modified example of the first embodiment, and fourth modified example of the first embodiment, the cases where the multiple connection portions V2 are arranged in a grid pattern have been described, but this is not limiting. Below, the configuration of the semiconductor memory device 1 according to the fifth modified example of the first embodiment will be described, focusing on differences from the configuration of the semiconductor memory device according to the first embodiment. The method for manufacturing the semiconductor memory device 1 according to the fifth modified example of the first embodiment is substantially similar to the method for manufacturing the semiconductor memory device according to the first embodiment.

[0173] The configuration of a semiconductor memory device 1 according to a fifth modification of the first embodiment will be described with reference to Fig. 25 and Fig. 26. Fig. 25 and Fig. 26 are cross-sectional views showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a fifth modification of the first embodiment. Fig. 25 and Fig. 26 are drawings showing a region corresponding to Fig. 9 of the first embodiment.

[0174] 25, each of the multiple connection portions V2 is provided so as to extend in the X direction in the XY cross section. That is, the multiple connection portions V2 are provided so that multiple line-shaped structures are aligned in the Y direction. Each of the multiple connection portions V2 may be shifted in the Y direction relative to the multiple conductor layers 207 in the XY cross section.

[0175] 26, the semiconductor memory device 1 may have one connection portion V2 connecting the conductive layers 32B and 39. In this case, the connection portion V2 has a mesh-like structure including, for example, a plurality of portions extending in the X direction and a plurality of portions extending in the Y direction in the XY cross section.

[0176] The fifth modified example of the first embodiment also provides the same effects as the first embodiment.

[0177] 3 Second embodiment Next, a semiconductor memory device according to a second embodiment will be described.

[0178] 3.1 Configuration The configuration of the semiconductor memory device according to the second embodiment will be described below, focusing on the differences between the configuration of the semiconductor memory device according to the second embodiment and the semiconductor memory device according to the first embodiment.

[0179] 3.1.1 Wiring layers of semiconductor memory devices An example of a wiring layer provided in the semiconductor memory device 1 according to the second embodiment will be described with reference to Fig. 27. Fig. 27 is a plan view showing an example of a planar layout of the semiconductor memory device according to the second embodiment.

[0180] The semiconductor memory device 1 according to the second embodiment includes a plurality of conductive layers 39 A and 39 B. The plurality of conductive layers 39 A and 39 B correspond to the conductive layer 39 in the first embodiment.

[0181] Each of the plurality of conductive layers 39A and 39B is provided so as to extend in the Y direction. The plurality of conductive layers 39A and 39B are provided so that, for example, the conductive layers 39A and the conductive layers 39B are alternately arranged in the X direction.

[0182] Each of the plurality of conductive layers 39A includes a plurality of connection portions V1, similar to the conductive layers 39 of the first and second modified examples of the first embodiment, for example. As a result, each of the plurality of conductive layers 39A is connected to the source line SL via the plurality of connection portions V1.

[0183] Furthermore, each of the plurality of conductor layers 39A and 39B includes a plurality of connection portions V2, similar to, for example, the conductor layer 39 of the first and second modified examples of the first embodiment, so that each of the plurality of conductor layers 39A and 39B is connected to the peripheral circuit PERI via the plurality of connection portions V2.

[0184] Furthermore, the conductive layer 39B includes an area that forms the electrode pad PD, as will be described later.

[0185] 3.1.2 Overall cross-sectional structure of semiconductor memory device Regarding the overall cross-sectional structure of the semiconductor memory device 1, the cross-sectional structures of a portion including the conductive layer 39A and a portion including the conductive layer 39B will be described.

[0186] 3.1.2.1 Cross-sectional structure of a semiconductor memory device including the conductive layer 39A The cross-sectional structure of the semiconductor memory device 1 including the conductive layer 39A will be described with reference to Fig. 28. Fig. 28 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the second embodiment. Fig. 28 shows the cross-sectional structure of a portion of the semiconductor memory device 1 including the conductive layer 39A.

[0187] The cross-sectional structure of the circuit chip 1-1 shown in FIG. 28 is the same as that of the circuit chip 1-1 in the first embodiment, except that the transistor Tr2 and the conductive layers 101 to 106 connected to the transistor Tr2 are not included.

[0188] The memory chip 1-2 includes, for example, conductor layers 36 (205), 39A, 130, 131, 132, 201-1, 202-1, 203-1, and 204-1, insulator layers 44, 45, 47, 48a, 48b, 48c, 61, and 62, semiconductor layers 301 and 302, and a memory cell array 10. The configurations of the conductor layers 201-1, 202-1, 203-1, and 204-1 and the insulator layer 61 are similar to those in the first embodiment.

[0189] The configuration of the insulator layer 45 is the same as that of the first embodiment except for the height of the first surface of the insulator layer 45. In the region excluding the memory cell array 10 in the cross section shown in FIG. 28, the first surface of the insulator layer 45 has a height equivalent to, for example, the second surface of the conductor layer 30 in the memory cell array 10.

[0190] In the region excluding the memory cell array 10, for example, conductor layers 130, 131, and 132 are stacked in this order on the first surface of the insulator layer 45. The conductor layers 130, 131, and 132 are made of a conductive material. The conductive material of the conductor layer 130 is the same as the conductive material of the conductor layer 30. The conductive material of the conductor layer 131 is the same as the conductive material of the conductor layer 31. The conductive material of the conductor layer 132 is the same as the conductive material of the conductor layer 32. The conductor layer 130 is included in the same layer as the conductor layer 30 on the other side of the conductor layer 31. The conductor layers 131 and 132 are formed, for example, by the same process as the formation of the conductor layers 31 and 32, as described below. Hereinafter, the region of the first surface of the insulator layer 45 including the portions where the conductor layers 130, 131, and 132 are provided and the portions surrounding these portions will be referred to as region R2. In the region R2, the conductive layer 30 and the insulating layers 47 and 62 are not provided.

[0191] In the region excluding the memory cell array 10, a semiconductor layer 301 is provided on a portion adjacent to region R2. The semiconductor layer 301 and the conductor layers 30 and 130 are provided in the same layer. An insulator layer 62 is provided on a first surface of the semiconductor layer 301. A semiconductor layer 302 is provided on a first surface of the insulator layer 62. As in the first embodiment, the semiconductor layers 301 and 302 are electrically insulated from the source line SL. An insulator layer 47 is provided on the first surface of the semiconductor layer 302. With the above configuration, in FIG. 28 , region R2 is sandwiched in the Y direction between two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62.

[0192] An insulator layer 44 is provided on the first surface of the insulator layer 45 in region R2 excluding the portions where the conductor layers 130, 131, and 132 are provided, on the first surface of the insulator layer 47, and on the first surfaces of the conductor layers 32 and 132 excluding the portions where the plurality of connection portions V1 and V3 (described later) are provided. The first surface of the insulator layer 44 has, for example, a uniform height. Note that, as in the fourth modification of the first embodiment described above, the first surface of the insulator layer 44 may have a step near the boundary between region R2 and the regions sandwiching region R2.

[0193] Conductor layers 31A and 32A resulting from the formation of conductor layers 31, 32, 131, and 132 (described later) may be provided on two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62, sandwiching the region R2 in the Y direction. Similar to the region R1 of the first embodiment, in a region not shown in FIG. 28 , the semiconductor memory device 1 has, for example, two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62, sandwiching the region R2 in the X direction. As a result, the region R2 is surrounded by four wall surfaces, for example, when viewed from above. Conductor layers 31A and 32A resulting from the formation of conductor layers 31, 32, 131, and 132 (described later) may also be provided on these two wall surfaces. With the above-described configuration, conductor layers 31A and 32A may be provided between the wall surfaces and the insulator layer 44. The conductive layers 31A and 32A may be provided on a portion of each wall surface or on the entire surface.

[0194] A conductor layer 39A is provided on the first surface of the insulator layer 44, on portions of the first surface of the conductor layer 32 where the insulator layer 44 is not provided, and on portions of the first surface of the conductor layer 132 where the insulator layer 44 is not provided. The conductor layer 39A includes a plurality of connection portions V1 and V3 and an extension portion extending in the Y direction. The extension portion electrically connects the plurality of connection portions V1 and V3. The plurality of connection portions V1 can be said to be vias in which the space between the extension portion and a portion of the first surface of the conductor layer 32 is filled. The plurality of connection portions V3 can be said to be vias in which the space between the extension portion and a portion of the first surface of the conductor layer 132 is filled.

[0195] With the above configuration, the conductor layer 32 is connected to the conductor layers 130, 131, and 132. As a result, the conductor layers 130, 131, and 132 function as lining wiring. Furthermore, the conductor layers 130, 131, and 132 function as extended source lines SL.

[0196] 27, the conductor layer 39A is configured to be connected to the peripheral circuit PERI of the circuit chip 1-1, for example, by the same configuration as the conductor layers 201 to 207. This allows the conductor layer 32 and the peripheral circuit PERI to be connectable via the conductor layers 39A, 101 to 106, and 201 to 207, and a plurality of connection parts V1.

[0197] Although not shown, the aspect ratio H3 / W5 of the height H3 of the connection portion V3 to the width W5 of the connection portion V3 along the Y direction is, for example, about 1.5 or less. The aspect ratio H3 / W6 of the height H3 to the width W6 of the connection portion V3 along the X direction (not shown) is also, for example, about 1.5 or less. With the above-described configuration of the connection portion V3, when the conductive layer 39A is formed during the manufacturing process of the semiconductor memory device 1, the trench corresponding to the connection portion V3 is not insufficiently filled with a conductor.

[0198] 3.1.2.2 Cross-sectional structure of semiconductor memory device including conductive layer 39B The cross-sectional structure of the semiconductor memory device 1 including the conductive layer 39B will be described with reference to Fig. 29. Fig. 29 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the second embodiment. Fig. 29 shows the cross-sectional structure of a portion of the semiconductor memory device 1 including the conductive layer 39B.

[0199] 29 is similar to the cross-sectional structure of the circuit chip 1-1 in the first embodiment, except that, instead of transistor Tr1 and conductor layers 101-1 to 106-1, a transistor Tr3 having an equivalent configuration to these, and conductor layers 101-3, 102-3, 103-3, 104-3, 105-3, and 106-3 connected to transistor Tr3, are included. Also, the cross-sectional structure of memory chip 1-2 is similar to the cross-sectional structure of memory chip 1-2 in the first embodiment, except that, in the memory cell array 10 portion, instead of conductor layers 201-1, 202-1, 203-1, and 204-1, conductor layers 201-3, 202-3, 203-3, and 204-3 having an equivalent configuration to these layers are included.

[0200] The following mainly describes the configuration of memory chip 1-2 in the cross section shown in Fig. 29, focusing on differences from the cross section shown in Fig. 28. In the cross section shown in Fig. 29, semiconductor memory device 1 includes a conductive layer 39B.

[0201] In the region excluding the memory cell array 10, region R2 includes a portion where multiple conductor layers 207 are provided, similar to region R1 in the first embodiment. One side portion of the multiple conductor layers 207 protrudes from the first surface of the insulator layer 45. In the region excluding the memory cell array 10, a portion of the first surface of the insulator layer 45 that surrounds the multiple conductor layers 207 in region R2 is located, for example, on the other side of the portion excluding this portion.

[0202] In the region excluding the memory cell array 10, two walls are provided that are configured by the semiconductor layers 301 and 302 and the insulator layers 47 and 62 and sandwich the region R2 in the Y direction, similar to the cross section shown in Fig. 28. Note that, although not shown in Fig. 29, even in the cross section including the conductor layer 39B, conductor layers 31A and 32A resulting from the formation of the conductor layers 31, 32, 131, and 132 may be provided on the two wall surfaces configured by the semiconductor layers 301 and 302 and the insulator layers 47 and 62.

[0203] An insulator layer 44 is provided on the first surface of the insulator layer 45 in region R2 and on the first surface of the insulator layer 47, except for the portion of the first surface of the insulator layer 45 surrounding the multiple conductor layers 207 in region R2 and the portion on one side of the multiple conductor layers 207.

[0204] A conductor layer 39B is provided on a portion of the first surface of the insulator layer 44, on a portion of the first surface of the insulator layer 45 that surrounds the plurality of conductor layers 207 in region R2, and on portions on one side of the plurality of conductor layers 207. The conductor layer 39B is provided so as to cover the portions on one side of the plurality of conductor layers 207. The conductor layer 39B has a step at the portion connected to the plurality of conductor layers 207.

[0205] The conductive layer 39B includes a region exposed on the first surface of the semiconductor memory device 1. This region constitutes, for example, an electrode pad PD connected to an external device of the semiconductor memory device 1. The electrode pad PD is provided at a position overlapping with the region R2 in the Z direction. As a result, the semiconductor layers 301 and 302 are not provided in the region overlapping with the electrode pad PD in the Z direction. Furthermore, the electrode pad PD is provided at a different position from the plurality of conductive layers 207 when viewed in the Z direction. The electrode pad PD is provided, for example, above the first surface of the insulator layer 44. That is, in the region overlapping with the electrode pad PD in the Z direction, the insulator layer 44 is provided in the same layer as the semiconductor layers 301 and 302 and the insulator layer 62.

[0206] With the above configuration, for example, the electrode pad PD and the transistor Tr2 are connectable via the conductive layers 101 to 106 and 201 to 207. That is, the electrode pad PD and the peripheral circuit PERI are electrically connected.

[0207] 29 and the portion including the conductor layers 130, 131, and 132 shown in FIG. 28 may be separated, for example, along the X direction, by a wall including the semiconductor layers 301 and 302 and the insulator layers 47 and 62. In other words, the portion including the conductor layers 207 and the portion including the conductor layers 130, 131, and 132 may not be provided in the same region R2, but may be provided in different regions surrounded by a wall including the semiconductor layers 301 and 302 and the insulator layers 47 and 62.

[0208] 3.2 Manufacturing method of semiconductor memory device A method for manufacturing the semiconductor memory device 1 will be described with reference to FIGS. 30 to 37. FIGS. 30 to 37 are cross-sectional views for explaining an example of a method for manufacturing the semiconductor memory device according to the second embodiment. The cross-sectional views shown in FIGS. 30, 32, 34, and 36 show the region corresponding to FIG. 28. The cross-sectional views shown in FIGS. 31, 33, 35, and 37 show the region corresponding to FIG. 29.

[0209] First, the same steps as those described with reference to FIGS. 11 to 13 in the first embodiment are carried out.

[0210] 30 and 31, the insulator layer 47 and the semiconductor layer 302 are removed in a portion corresponding to the memory cell array 10. In addition to this removal, the insulator layer 47 and the semiconductor layer 302 are removed in a portion corresponding to region R2 in the region corresponding to FIG. 28, as shown in FIG.

[0211] Next, in the portion corresponding to the memory cell array 10, the portion of the stacked film 52 on one side of the insulator layer 62 is removed, thereby exposing the semiconductor film 51 on the surface on one side of the insulator layer 62. Also, the insulator layer 62 is removed in the portion corresponding to the memory cell array 10 and in the portion corresponding to region R2 in the region corresponding to FIG. 28. As a result, the semiconductor layer 301, portions on one side of the multiple memory pillars MP, and portions on one side of the multiple members SLT are exposed to the surface in the portion corresponding to the memory cell array 10 and in the portion corresponding to region R2 in the region corresponding to FIG. 28.

[0212] 28 and 29, as shown in Figures 32 and 33, conductor layers 31 and 32 are laminated in this order on the portions of the first surface of the semiconductor layer 301 that are exposed to the surface, on the portions of the memory pillar MP that are exposed to the surface, on portions on one side of the multiple members SLT, and on the first surface of the insulator layer 47. Furthermore, the portions of the semiconductor layer 301 that correspond to the conductor layers 30 and 130 are made into conductor portions by the diffusion of impurities.

[0213] Then, as shown in FIGS. 34 and 35 , semiconductor layer 301 including conductor portions corresponding to conductor layers 30 and 130, and conductor layers 31 and 32 except for conductor layers 30, 130, 131, and 132, are removed by etching using a mask or the like. Through the above process, conductor layers 30, 130, 131, and 132 are formed. Furthermore, in a portion corresponding to region R2, a first surface portion of insulator layer 45 is exposed to the surface. In a portion corresponding to region R2 in the region corresponding to FIG. 29 , for example, one side portions of multiple conductor layers 207 are also exposed to the surface, as shown in FIG. 35 . Furthermore, in the region corresponding to FIG. 28 , as shown in FIG. 34 , conductor layers 31A and 32A are formed as traces of conductor layers 31, 32, 131, and 132 on the wall surfaces formed by semiconductor layers 301 and 302 and insulator layers 47 and 62 by the above process.

[0214] Then, the insulator layer 44 is formed on the first surface of the conductor layer 32, the first surface of the conductor layer 132, the first surface of the insulator layer 47, the portion of the first surface of the insulator layer 45 that is exposed to the surface in a portion corresponding to the region R2, and the conductor layers 31A and 32A. Also, a portion on one side of the insulator layer 44 is removed by CMP.

[0215] Then, in the region corresponding to Fig. 28, grooves corresponding to the plurality of connection portions V1 and V3 are formed as shown in Fig. 36. The formation of the grooves is similar to the formation of the grooves corresponding to the plurality of connection portions V1 and V2 in the first embodiment. Furthermore, in the region corresponding to Fig. 29, as shown in Fig. 37, the insulator layer 44 in the portion surrounding the plurality of conductor layers 207 in region R2 and a portion on one side of the insulator layer 45 are removed.

[0216] Furthermore, the conductor layer 39A is formed to a height on one side higher than the insulator layer 44 so as to be embedded in the grooves corresponding to the plurality of connection portions V1 and V3. Furthermore, the conductor layer 39B is formed on portions of the first surfaces of the insulator layers 44 and 45 so as to be in contact with the plurality of conductor layers 207. Then, on the first surface of the structure formed as described above, excluding the regions of the conductor layer 39B corresponding to the electrode pads PD, the insulator layers 48a, 48b, and 48c are formed.

[0217] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0218] 3.3 Effects The second embodiment also makes it possible to improve the degree of freedom in designing a semiconductor memory device. The effects of the second embodiment will be described below.

[0219] In the second embodiment, the semiconductor memory device 1 includes a circuit chip 1-1 including a semiconductor substrate 70 having an array region AR and a peripheral region PR, and a memory chip 1-2 that contacts the circuit chip 1-1 in the Z direction and is electrically connected to the circuit chip 1-1 via multiple connection pads provided in the boundary region between the circuit chip 1-1 and the circuit chip 1-1. The memory chip 1-2 includes a memory cell array 10, conductor layers 39A, 130-132, and 207, and a semiconductor layer 301. The memory cell array 10 is provided in the array region AR and includes a source line SL, multiple word lines WL provided below the source line SL and spaced apart from each other in the Z direction, and memory pillars MP extending in the Z direction to intersect with the multiple word lines WL and connected at their upper ends to the source line SL. Each of the multiple conductor layers 207 is provided in the peripheral region PR, extends in the Z direction, and is electrically connected to one of the multiple connection pads. The conductor layers 130-132 are provided in the peripheral region PR, are included in the same layer as the source line SL, and are separated from each other by the source line SL. The conductor layers 130-132 are disposed at positions that do not overlap any of the plurality of conductor layers 207 when viewed in the Z direction. The conductor layer 39A includes a portion electrically connected to the conductor layers 130-132 and any of the plurality of conductor layers 207. This portion of the conductor layer 39A functions as a wiring layer disposed on one side of the conductor layers 130-132. The semiconductor layer 301 is included in the same layer as the source lines SL within the peripheral region PR. Furthermore, the semiconductor layer 301 has a structure in which portions that overlap with the plurality of conductor layers 207 and the conductor layers 130-132 when viewed in the Z direction are removed. In the above configuration, the conductor layers 130-132 function as backing wiring for the conductor layer 39A. This prevents the wiring from becoming too complicated, improving the design flexibility of the semiconductor memory device 1.

[0220] Additionally, in the third comparative example, the space remaining in the peripheral region, including the conductive layer containing polysilicon or the like for forming the source line, is considered dead space that does not function as part of the circuit of the semiconductor memory device, and additional wiring is provided in the same layer as the wiring layer, for example, to reduce the resistance of the wiring or to improve EM (Electro Migration) resistance, which may result in the wiring becoming more complicated.

[0221] According to the second embodiment, the conductive layers 130-132 provided in the peripheral region PR for forming the source lines function as backing wiring for the conductive layer 39A. By using the conductive layers 130-132, which originate from the conductive layers provided for forming the source lines, as wiring, it is possible to effectively utilize the space that was dead space in the third comparative example. This makes it possible to prevent the wiring from becoming complicated when reducing the resistance of the wiring or improving EM resistance. This improves the degree of freedom in designing the semiconductor memory device 1.

[0222] Furthermore, as described above, by using the conductive layers 130 to 132 provided in regions corresponding to regions that would become dead spaces in the third comparative example as backing wiring, it is possible to suppress an increase in the size of the semiconductor memory device 1.

[0223] 4. Modification of the Second Embodiment The second embodiment described above can be modified in various ways, and semiconductor memory devices according to modifications of the second embodiment will be described below.

[0224] 4.1 First Modification of the Second Embodiment In the second embodiment described above, the conductor layers 130, 131, and 132 function as lining wiring for the conductor layer 39A, but this is not limiting. In addition to functioning as lining wiring, the conductor layers 130, 131, and 132 may also function as wiring for connecting two different conductor layers 39A. The following describes the configuration of the semiconductor memory device 1 according to the first modification of the second embodiment, focusing on differences from the configuration of the semiconductor memory device according to the second embodiment. The method for manufacturing the semiconductor memory device 1 according to the first modification of the second embodiment is substantially similar to the method for manufacturing the semiconductor memory device according to the second embodiment.

[0225] The configuration of a semiconductor memory device 1 according to a first modification of the second embodiment will be described with reference to Figures 38 and 39. Figure 38 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of a semiconductor memory device according to a first modification of the second embodiment. Figure 39 is a cross-sectional view taken along line XXXIX-XXXIX in Figure 38, showing an example of connection of wiring layers in a semiconductor memory device according to a first modification of the second embodiment.

[0226] The cross-sectional structure shown in Fig. 38 is a cross-sectional structure including region R2. Fig. 38 shows an example in which region R2 includes two conductor layers 39A and one conductor layer 39B in the XZ cross section.

[0227] 38 and 39, in the first modification of the second embodiment, the conductor layers 130, 131, and 132 extend in the X direction so as to connect two conductor layers 39A arranged side by side in the X direction. Each of the two conductor layers 39A is connected to the conductor layers 130, 131, and 132 via a connection portion V3 of the conductor layer 39A.

[0228] With the above-described configuration, the conductive layers 130, 131, and 132 function as backing wiring that bypasses and connects the two conductive layers 39A on the other side of the conductive layer 39A.

[0229] In the first modification of the second embodiment described above, the lining wiring that connects the two conductor layers 39A in a detour has been described, but the present invention is not limited to this. Although not shown, the conductor layers 130, 131, and 132 may be provided as lining wiring that connects the two conductor layers 39B in a detour. In this case, each of the two conductor layers 39B is connected to the conductor layers 130, 131, and 132 by a configuration similar to the connection portion V3 of the conductor layer 39A.

[0230] The first modified example of the second embodiment also provides the same effects as the second embodiment.

[0231] 4.2 Second Modification of the Second Embodiment In the second embodiment and the first modification of the second embodiment described above, the conductor layers 130, 131, and 132 function as backing wiring for the conductor layer 39A, but this is not limiting. The conductor layers 130, 131, and 132 may also be configured to function as elements. Below, differences between the configuration and manufacturing method of the semiconductor memory device 1 according to the second modification of the second embodiment and the configuration and manufacturing method of the semiconductor memory device according to the second embodiment will be described.

[0232] The configuration of a semiconductor memory device 1 according to a second modification of the second embodiment will be described with reference to Fig. 40 and Fig. 41. Fig. 40 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a second modification of the second embodiment. Fig. 41 is a cross-sectional view taken along line XLI-XLI in Fig. 40, showing an example of connection of wiring layers in a semiconductor memory device according to a second modification of the second embodiment.

[0233] As shown in FIG. 40 , in an area excluding the memory cell array 10, for example, conductor layers 130A, 131A, and 132A are stacked in this order on a portion of the first surface of the insulator layer 45. Furthermore, in an area excluding the memory cell array 10, for example, conductor layers 130B, 131B, and 132B are provided on a portion of the first surface of the insulator layer 45 at positions different from the conductor layers 130A, 131A, and 132A in the Y direction, and are electrically isolated from the conductor layers 130A, 131A, and 132A. The conductor layers 130A, 130B, 131A, 131B, 132A, and 132B are made of a conductive material. The conductive material making up the conductor layers 130A and 130B is the same material as the conductive material making up the conductor layer 30. The conductive material making up the conductor layers 131A and 131B is the same material as the conductive material making up the conductor layer 31. The conductive material constituting the conductor layers 132A and 132B is the same material as the conductive material constituting the conductor layer 32. The conductor layers 130A and 130B are included in the same layer as the conductor layer 30. The conductor layers 131A, 131B, 132A, and 132B are formed, for example, in the same process as the formation of the conductor layers 31 and 32, similar to the conductor layers 131 and 132. Hereinafter, a region of the first surface of the insulator layer 45 including the portions where the conductor layers 130A, 130B, 131A, 131B, 132A, and 132B are provided and the portion surrounding these portions will be referred to as region R3. The semiconductor layers 301 and 302, the conductor layer 30, and the insulator layers 47 and 62 are not provided in region R3.

[0234] The semiconductor memory device 1 includes conductive layers 39C1 and 39C2 aligned in the Y direction in the same layer as conductive layers 39A and 39B. Conductive layers 39C1 and 39C2 are electrically isolated from each other. Conductive layer 39C1 includes an extension portion extending in the Y direction and at least one connection portion V4A. Each of the multiple connection portions V4A can be considered to be a via filled with the space between the extension portion and conductive layer 132A. Conductive layer 39C2 includes an extension portion extending in the Y direction and at least one connection portion V4B. Each of the multiple connection portions V4B can be considered to be a via filled with the space between the extension portion and conductive layer 132B.

[0235] Although not shown, the aspect ratio H4 / W7 between the height H4 of the connection portions V4A and V4B and the width W7 of the connection portions V4A and V4B along the Y direction is, for example, approximately 1.5 or less. Furthermore, the aspect ratio H4 / W8 between the height H4 and the width W8 (not shown) of the connection portions V4A and V4B along the X direction is also, for example, approximately 1.5 or less. With the above-described configuration of the connection portions V4A and V4B, when forming the conductor layers 39C1 and 39C2 during the manufacturing process of the semiconductor memory device 1, the grooves corresponding to the connection portions V4A and V4B are not insufficiently filled with conductor.

[0236] As shown in FIG. 41 , in the XY plane, the conductor layer 132A has a portion extending in the X direction and multiple portions connected to one side in the Y direction of the portion and extending in the Y direction. Here, the one side in the Y direction is the conductor layer 39C2 side of the conductor layers 39C1 and C2. The other side in the Y direction is the conductor layer 39C1 side of the conductor layers 39C1 and C2. On the other hand, the conductor layer 132B has a portion extending in the X direction on one side in the Y direction of the portion extending in the X direction of the conductor layer 132A and multiple portions connected to the other side in the Y direction of the portion extending in the Y direction. With the above configuration, each of the conductor layers 132A and 132B has a comb-shaped pattern structure when viewed in the Z direction. Furthermore, the conductor layers 132A and 132B are arranged such that the portions of the conductor layer 132A extending in the Y direction and the portions of the conductor layer 132B extending in the Y direction are alternately arranged in the X direction. Although not shown, the conductor layers 131A and 130A also have a comb-shaped pattern structure similar to that of the conductor layer 132A on the second surface of the conductor layer 132A. Similarly, although not shown, the conductor layers 131B and 130B also have a comb-shaped pattern structure similar to that of the conductor layer 132B on the second surface of the conductor layer 132B.

[0237] The conductive layers 39C1 and 39C2 are each electrically connected to a structure similar to that of the conductive layer 207 in a cross section (not shown), and are thereby connected to the peripheral circuit PERI.

[0238] With the above configuration, the conductive layers 130A, 130B, 131A, 131B, 132A, and 132B function as a capacitor, that is, the conductive layers 130A, 130B, 131A, 131B, 132A, and 132B form a so-called interdigital capacitor.

[0239] The manufacturing method of the semiconductor memory device 1 according to the second variant of the second embodiment can be the same as the manufacturing method of the semiconductor memory device according to the second embodiment, except that conductor layers 39C1 and 39C2 are formed in the same manner as conductor layers 39A and 39B in the second embodiment, and conductor layers 130A, 130B, 131A, 131B, 132A, and 132B are formed in the same manner as conductor layers 130, 131, and 132 in the second embodiment.

[0240] The second modification of the second embodiment also provides the same effects as the second embodiment.

[0241] 4.3 Third Modification of the Second Embodiment In the second modification of the second embodiment described above, the case where the comb capacitor is provided on one side of the insulator layer 45 has been described, but this is not limiting. The semiconductor memory device may also have an element other than the comb capacitor provided on one side of the insulator layer 45. Below, differences between the configuration of the semiconductor memory device 1 according to the third modification of the second embodiment and the configuration of the semiconductor memory device according to the second modification of the second embodiment will be described. The method for manufacturing the semiconductor memory device 1 according to the third modification of the second embodiment is substantially similar to the method for manufacturing the semiconductor memory device according to the second modification of the second embodiment.

[0242] The configuration of a semiconductor memory device 1 according to a third modification of the second embodiment will be described with reference to Figures 42 and 43. Figure 42 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of a semiconductor memory device according to a third modification of the second embodiment. Figure 43 is a cross-sectional view taken along line XLIII-XLIII in Figure 42, showing an example of connection of wiring layers in a semiconductor memory device according to the third modification of the second embodiment.

[0243] As shown in FIG. 42 , in an area excluding the memory cell array 10, for example, conductor layers 130C, 131C, and 132C are stacked in this order on a portion of the first surface of the insulating layer 45. The conductor layers 130C, 131C, and 132C are made of a conductive material. The conductive material making up the conductor layer 130C is the same as the conductive material making up the conductor layer 30. The conductive material making up the conductor layer 131C is the same as the conductive material making up the conductor layer 31. The conductive material making up the conductor layer 132C is the same as the conductive material making up the conductor layer 32. The conductor layers 130C, 131C, and 132C are each provided so as to have a plate-like pattern extending along the XY plane. The conductor layer 130C is included in the same layer as the conductor layer 30. The conductor layers 131C and 132C are formed, for example, in the same process as the formation of the conductor layers 31 and 32, similar to the conductor layers 131 and 132. In the third modified example of the second embodiment, the region R3 is a region including the region of the first surface of the insulator layer 45 including the portion where the plate-like pattern portions of the conductor layers 130C, 131C, and 132C are provided and the portion surrounding this portion.

[0244] The semiconductor memory device 1 includes a conductor layer 39D1 in the same layer as the conductor layers 39A and 39B. The conductor layer 39D1 includes an extending portion that extends in the Y direction above an edge region on one side of the plate-like pattern portion of the conductor layer 132C, and at least one or more connection portions V5. Each of the multiple connection portions V5 can be said to be a via in which the space between the extending portion and the conductor layer 132C is filled.

[0245] Although not shown, the aspect ratio H5 / W9 between the height H5 of the connection portion V5 and the width W9 of the connection portion V5 along the Y direction is, for example, approximately 1.5 or less. Furthermore, the aspect ratio H5 / W10 between the height H5 and the width W10 (not shown) of the connection portion V5 along the X direction is also, for example, approximately 1.5 or less. With the above-described configuration of the connection portion V5, when the conductive layer 39D1 is formed during the manufacturing process of the semiconductor memory device 1, the trench corresponding to the connection portion V5 is not insufficiently filled with a conductor.

[0246] The semiconductor memory device 1 also includes a conductor layer 39D2 that is provided in the same layer as the conductor layer 39D1 but separated from the conductor layer 39D1. As shown in FIG. 43 , the conductor layer 39D2 is provided adjacent to the extended portion of the conductor layer 39D1 in the X direction, for example. The conductor layer 39D2 is provided so as to overlap the conductor layer 132C in the Z direction at a position different from the edge region on one side of the plate-like pattern portion of the conductor layer 132C provided above the extended portion of the conductor layer 39D1. The conductor layer 39D2 is provided in the shape of a plate that extends along the XY plane, for example.

[0247] In addition, the conductive layers 39D1 and 39D2 are each electrically connected to a configuration similar to that of the conductive layer 207 in a cross section not shown, and are thereby connected to the peripheral circuit PERI, similar to the conductive layers 39C1 and 39C2 of the second variant of the second embodiment, for example.

[0248] With the above configuration, the conductive layer 132C connected to the conductive layer 39D1 and the conductive layer 39D2 function as a plate-type capacitor.

[0249] The third modified example of the second embodiment also provides the same effects as the second embodiment.

[0250] 4.4 Fourth Modification of the Second Embodiment In the above-described second embodiment, first modification of the second embodiment, second modification of the second embodiment, and third modification of the second embodiment, an extended portion of a wiring layer provided on one side of the upper surface of a source line SL is connected to a conductive layer on the other side of the wiring layer through a via (connection portion) filled with a conductor. However, this is not limited to this. The wiring layer provided on one side of the upper surface of the source line SL may be connected to a conductive layer on the other side of the wiring layer through an unblocked via. Below, differences in the configuration of a semiconductor memory device 1 according to a fourth modification of the second embodiment from the configuration of the semiconductor memory device according to the second embodiment will be described. A method for manufacturing a semiconductor memory device 1 according to the fourth modification of the second embodiment is substantially similar to the method for manufacturing a semiconductor memory device according to the second embodiment.

[0251] The configuration of a semiconductor memory device 1 according to a fourth modification of the second embodiment will be described with reference to Fig. 44. Fig. 44 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of a semiconductor memory device according to the fourth modification of the second embodiment.

[0252] In the fourth modified example of the second embodiment, the connection portion V1 of the conductive layer 39A has a first surface located at a height lower than the second surface of the conductive layer 39A in the portion (extension portion) excluding the connection portions V1 and V3, and a second surface in contact with the conductive layer 32. The connection portion V3 of the conductive layer 39A has a first surface located at a height lower than the second surface of the conductive layer 39A in the extension portion, and a second surface in contact with the conductive layer 132.

[0253] With the above-described configuration, the connection portion V1 has a shape such that, for example, the space on the other side of the first surface (the second surface of the extending portion) of the insulator layer 44 is not completely blocked, but the space is partially filled. Also, the connection portion V3 has a shape such that, for example, the space on the other side of the first surface (the second surface of the extending portion) of the insulator layer 44 is not completely blocked, but the space is partially filled. With the above-described configuration, the conductor layer 39A includes a shape having a step at the connection portions V1 and V3.

[0254] Although only one connection portion V1 is shown in FIG. 44, multiple connection portions V1 may be included.

[0255] The fourth modified example of the second embodiment also provides the same effects as the second embodiment.

[0256] 4.5 Fifth Modification of the Second Embodiment In the above-described second embodiment, first modified example of the second embodiment, second modified example of the second embodiment, third modified example of the second embodiment, and fourth modified example of the second embodiment, the wiring provided on the first surface of the insulator layer 45 in regions R2 and R3 is configured with multiple conductor layers, but this is not limited to this. The wiring may be configured with a single conductor layer. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the fifth modified example of the second embodiment will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the second embodiment.

[0257] The configuration of a semiconductor memory device 1 according to a fifth modification of the second embodiment will be described with reference to Fig. 45. Fig. 45 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of a semiconductor memory device according to a fifth modification of the second embodiment.

[0258] The semiconductor memory device 1 according to the fifth modification of the second embodiment includes a conductive layer 400. The conductive layer 400 is provided on a portion of the first surface of the insulator layer 45 in the region R2. The first surface of the conductive layer 400 is in contact with the connection portion V3 of the conductive layer 39A. The conductive layer 400 is made of a conductive material. The conductive material includes, for example, tungsten, aluminum, titanium, or titanium nitride.

[0259] In the fifth modification of the second embodiment, for example, the conductor layers 31A and 32A are not provided on two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62, which sandwich the region R2 in the Y direction.

[0260] A method for manufacturing the semiconductor memory device 1 according to the fifth modification of the second embodiment will be described.

[0261] 30 of the second embodiment, the insulator layer 47 and the semiconductor layer 302 are removed in a portion corresponding to the memory cell array 10, while, for example, the removal is not performed in a portion corresponding to the region R2. That is, the state in which the insulator layer 47 and the semiconductor layer 302 are included is maintained in the portion corresponding to the region R2.

[0262] Thereafter, in the portion corresponding to region R2, for example, semiconductor layers 301 and 302 and insulator layers 47 and 62 are removed. As a result, the first surface of insulator layer 45 is entirely exposed in the portion corresponding to region R2 in the region corresponding to FIG. 45 .

[0263] Then, for example, before the insulating layer 44 is formed, the conductive layer 400 is formed on the exposed portion of the first surface of the insulating layer 45 in the portion corresponding to the region R2.

[0264] The fifth modified example of the second embodiment also provides the same effects as the second embodiment.

[0265] 4.6 Sixth Modification of the Second Embodiment In the second embodiment described above, the conductive layer having the electrode pads is in direct contact with the plurality of contacts, but this is not limiting. The conductive layer having the electrode pads may be connected to the plurality of contacts via a plate-shaped conductive layer, as in the first embodiment. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the sixth modification of the second embodiment will be described, focusing on the differences from the configuration and manufacturing method of the semiconductor memory device according to the second embodiment.

[0266] The configuration of a semiconductor memory device 1 according to a sixth modification of the second embodiment will be described with reference to FIG. 46. FIG. 46 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of a semiconductor memory device according to the sixth modification of the second embodiment. The cross-sectional structure shown in FIG. 46 corresponds to the cross-sectional structure shown in FIG. 29 of the second embodiment. Differences between the cross-sectional structure shown in FIG. 46 and the cross-sectional structure shown in FIG. 29 will be described below.

[0267] In a sixth modified example of the second embodiment, a conductor layer 500 is provided on one side portions of the plurality of conductor layers 207 and on a portion of the first surface of the insulator layer 45 surrounding the plurality of conductor layers 207. The conductor layer 500 is provided so as to cover one side portions of the plurality of conductor layers 207. The conductor layer 500 is provided, for example, so as to have a plate-like pattern extending along the XY plane. The first surface of the conductor layer 500 has, for example, projections and depressions corresponding to the plurality of conductor layers 207. In other words, the first surface of the conductor layer 500 does not have to be flat. However, this is not a limitation, and the first surface of the conductor layer 500 may be flat.

[0268] In the region R2 of the sixth modified example of the second embodiment, the height of the first surface of the insulating layer 45 is uniform and is equal to the height of the second surface of the conductive layer 30 in the memory cell array .

[0269] The conductive layer 39B is provided so as to be in contact with the first surface of the conductive layer 500, instead of being in direct contact with the plurality of conductive layers 207 in the second embodiment.

[0270] In the method for manufacturing the semiconductor memory device 1 according to the sixth modification of the second embodiment, the conductor layer 500 is formed so as to be in contact with the plurality of conductor layers 207, for example, after the step corresponding to Fig. 35 of the second embodiment. Furthermore, similar to the conductor layer 32B in the first embodiment, the conductor layer 500 may be formed by the same step as the formation of the conductor layer 32.

[0271] The sixth modified example of the second embodiment also provides the same effects as the second embodiment.

[0272] 5. Other Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0273] 1...semiconductor memory device, 2...memory controller, 3...memory system, 10...memory cell array, 11...command register, 12...address register, 13...sequencer, 14...driver module, 15...row decoder module, 16...sense amplifier module, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...select transistor, BL...bit line, WL...word line, SGS, SGD...select gate line, SHE...component.

Claims

1. a first chip including a substrate having a first region and a second region; a second chip that contacts the first chip in a first direction intersecting the surface of the substrate and is electrically connected to the first chip via a plurality of connection pads provided in a boundary region between the first chip and the second chip; Equipped with The second chip is a memory cell array provided in the first region, the memory cell array including a source line, a plurality of word lines provided below the source line and spaced apart from one another in the first direction, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the upper end of which is connected to the source line; a plurality of contacts provided in the second region, extending in the first direction, each electrically connected to one of the plurality of connection pads; a conductive pattern in contact with upper ends of the plurality of contacts; a first wiring provided above the conductor pattern and electrically connected to the conductor pattern; Including, Semiconductor memory device.

2. a first connection portion that is in contact with the conductor pattern and the first wiring and is located between the conductor pattern and the first wiring in the first direction; 2. The semiconductor memory device according to claim 1.

3. The first wiring is an extension portion that extends in a second direction intersecting with the first direction at a position above an upper surface of the source line in the first direction; and a first connection portion that is in contact with the extension portion and the conductor pattern between the extension portion and the conductor pattern in the first direction; Including, 2. The semiconductor memory device according to claim 1.

4. the conductor pattern is included in the same layer as the source line; 2. The semiconductor memory device according to claim 1.

5. a first chip including a substrate having a first region and a second region; a second chip that contacts the first chip in a first direction intersecting the surface of the substrate and is electrically connected to the first chip via a plurality of connection pads provided in a boundary region between the first chip and the second chip; Equipped with The second chip is a memory cell array provided in the first region, the memory cell array including a source line, a plurality of word lines provided below the source line and spaced apart from one another in the first direction, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the upper end of which is connected to the source line; a plurality of contacts provided in the second region, extending in the first direction, each electrically connected to one of the plurality of connection pads; a first conductor layer provided in the second region, included in the same layer as the source line, and separated from the source line at a position not overlapping any of the plurality of contacts when viewed from above; a first wiring layer provided above the first conductive layer and including a portion electrically connected to the first conductive layer and any of the plurality of contacts; a pattern portion included in the same layer as the source line in the second region, the pattern portion being obtained by removing portions that overlap with the plurality of contacts and the first conductive layer when viewed from above; Including, Semiconductor memory device.

Images