Display device

Abstract

To provide a display device capable of improving yield.SOLUTION: According to an embodiment, a display device includes a substrate having a display region and a peripheral region, an organic insulating layer disposed in the display region and the peripheral region, a plurality of pixels each including a lower electrode, an upper electrode, and an organic layer and disposed in the display region, a first partition wall disposed in the display region and surrounding each of the plurality of pixels, a second partition wall disposed in the peripheral region and connected to the first partition wall, a third partition wall disposed outside the second partition wall in the peripheral region and separated from the second partition wall via a slit, and a dam portion disposed in the peripheral region and surrounding the organic insulating layer, the second partition wall, and the third partition wall. Each of the first partition wall, the second partition wall, and the third partition wall includes a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. The third partition wall is located above the organic insulating layer and is separated from the dam portion.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes a substrate having a display region for displaying an image and a peripheral region surrounding the display region; an organic insulating layer disposed in the display region and the peripheral region; a plurality of pixels disposed in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition disposed in the display region and surrounding each of the plurality of pixels; a second partition disposed in the peripheral region and connected to the first partition; a third partition disposed outside the second partition in the peripheral region and separated from the second partition by a slit; and a dam portion disposed in the peripheral region and surrounding the organic insulating layer, the second partition, and the third partition. The first partition, the second partition, and the third partition each include a conductive lower portion and an upper portion having an end protruding from a side surface of the lower portion. The third partition is disposed above the organic insulating layer and separated from the dam portion.

[0006] According to another embodiment, a display device includes a substrate having a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed in the display area and the peripheral area; a lower electrode, an upper electrode positioned above the lower electrode, and an organic layer positioned between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition disposed in the display area and surrounding each of the pixels; a second partition disposed in the peripheral area and connected to the first partition; a third partition disposed outside the second partition in the peripheral area and separated from the second partition by a slit; and a first resin layer covering the display area and a portion of the peripheral area. The first partition, the second partition, and the third partition each include a conductive lower portion and an upper portion having an end protruding from a side surface of the lower portion. The end of the organic insulating layer is located between an end of the substrate and the third partition. The substrate has a peripheral area located between the end of the organic insulating layer and the end of the substrate. Furthermore, the first resin layer covers the third partition wall and does not overlap the outer periphery region. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the display device according to the first embodiment. [Figure 5] FIG. 5 is a schematic plan view showing an enlarged area enclosed by a frame V in FIG. [Figure 6] FIG. 6 is a schematic plan view showing a further enlarged portion of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the peripheral region of the display device according to the first embodiment. [Figure 8] FIG. 8 is a schematic plan view of the motherboard according to the first embodiment. [Figure 9] FIG. 9 is a schematic plan view of the panel unit according to the first embodiment. [Figure 10] FIG. 10 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing a step subsequent to FIG. 11A. [Figure 11C] FIG. 11C is a schematic cross-sectional view showing a step subsequent to FIG. 11B. [Figure 11D] FIG. 11D is a schematic cross-sectional view showing a step subsequent to FIG. 11C. [Figure 11E] FIG. 11E is a schematic cross-sectional view showing a step subsequent to FIG. 11D. [Figure 11F] FIG. 11F is a schematic cross-sectional view showing a step subsequent to FIG. 11E. [Figure 11G] FIG. 11G is a schematic cross-sectional view showing a step subsequent to FIG. 11F. [Figure 12A] FIG. 12A is a schematic cross-sectional view of a display device according to a comparative example, showing how droplets of a resin layer are ejected. [Figure 12B] FIG. 12B is a schematic cross-sectional view of a display device according to a comparative example, showing the state after droplets of the resin layer have been attached. [Figure 13A] FIG. 13A is a schematic cross-sectional view of the display device according to the first embodiment, showing how droplets of a resin layer are ejected. [Figure 13B] FIG. 13B is a schematic cross-sectional view of the display device according to the first embodiment, showing the state after the droplets of the resin layer have been attached. [Figure 14] FIG. 14 is a schematic cross-sectional view of the peripheral area of ​​the display area according to the second embodiment. [Figure 15] FIG. 15 is a schematic plan view showing the configuration of a display device according to the third embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the peripheral region of the display device according to the third embodiment. [Figure 17] FIG. 17 is a schematic plan view of a panel unit in the third embodiment. [Figure 18A] FIG. 18A is a schematic cross-sectional view showing a state in which droplets are ejected during the manufacture of the display device according to the third embodiment. [Figure 18B] FIG. 18B is a schematic cross-sectional view showing the state after the droplet has adhered. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not limiting.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1, AP2, and AP3 are all rectangular. The area of ​​the pixel opening AP1 is larger than the area of ​​the pixel opening AP3. The area of ​​the pixel opening AP2 is also larger than the area of ​​the pixel opening AP1. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The lower electrode LE1, upper electrode UE1, and organic layer OR1 form the display element DE1 of subpixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 form the display element DE2 of subpixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 form the display element DE3 of subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6A (first partition wall) is disposed above the rib layer 5. The partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6A entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. The partition wall 6A surrounds the subpixels SP1, SP2, and SP3.

[0025] The partition 6A has a plurality of slits SLa extending in the Y direction. In the example of FIG. 2, the subpixels SP1, SP2, and SP3 that make up one pixel PX are arranged between two slits SLa in the X direction. Furthermore, the partition 6A has connecting portions CT that connect the portions separated by the slits SLa. Note that the arrangement of the slits SLa and the connecting portions CT is not limited to the example of FIG. 2. For example, there may be slits SLa that are continuous between both ends of the display area DA in the Y direction.

[0026] Sealing layers SE11, SE12, and SE13 (first sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6A around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6A around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6A around it.

[0027] 2, the sealing layers SE11, SE12, and SE13 do not overlap with the slit SLa. As another example, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SLa.

[0028] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The peripheral edges of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0030] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6A has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0031] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0032] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0034] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers to improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0036] Sealing layers SE11, SE12, and SE13 (first sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the stacked film FL1 and the surrounding partition wall 6A. The sealing layer SE12 continuously covers the stacked film FL2 and the surrounding partition wall 6A. The sealing layer SE13 continuously covers the stacked film FL3 and the surrounding partition wall 6A.

[0037] 3, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6A.

[0038] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6A. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0039] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1 (first resin layer). The resin layer RS1 is covered with a sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered with a resin layer RS2 (second resin layer). The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously at least over the entire display area DA, with portions thereof extending into the peripheral area SA.

[0040] 3, a touch panel electrode TP for detecting a touch operation by a user is disposed on the sealing layer SE2. The touch panel electrode TP is made of, for example, a metal material, and has the same shape as the partition wall 6A in plan view.

[0041] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0042] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0044] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0045] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0046] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0047] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0048] The first top layer 65 of the partition wall 6A is formed of, for example, a metal material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0049] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line S is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0050] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0051] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0052] 4 is a schematic plan view of the display device DSP. In the example of this figure, a dummy pixel region DMY, a partition 6B (second partition), a partition 6C (third partition), a sealing layer SE1x (first sealing layer), and a dam structure DS1 are arranged in the peripheral region SA. For example, the dummy pixel region DMY, the partition 6B, the partition 6C, the sealing layer SE1x, and the dam structure DS1 are all circular and concentric with the display region DA.

[0053] The dummy pixel region DMY surrounds the display region DA. The partition 6B is located outside the dummy pixel region DMY (on the side farther from the display region DA). The partition 6C is located outside the partition 6B. In the example of FIG. 4, the partitions 6B and 6C surround the display region DA. The partitions 6B and 6C are separated from each other by an annular slit SLb. The slit SLb surrounds the display region DA, the dummy pixel region DMY, and the partition 6B.

[0054] The sealing layer SE1x overlaps the partition wall 6B but does not overlap the partition wall 6C. In the example of Fig. 4, the sealing layer SE1x surrounds the display area DA.

[0055] The partition walls 6B are connected to the underlying relay layer RL and power supply lines PW (see FIG. 7) via a plurality of contact portions CN1. The power supply lines PW are connected to the terminal portions T and supply a common voltage to the partition walls 6B. The partition walls 6A arranged in the display area DA are connected to the partition walls 6B. That is, the common voltage of the power supply lines PW is supplied to the partition walls 6A via the partition walls 6B, and further supplied to the upper electrodes UE1, UE2, and UE3 in contact with the partition walls 6A.

[0056] 4, a plurality of contact portions CN1 are arranged in an arc shape on the side of the terminal portion T. All of these contact portions CN1 are located between the slit SLb and the display area DA, and overlap with the partition wall 6B.

[0057] The dam structure DS1 is located outside the partition wall 6C and surrounds the display area DA, the dummy pixel area DMY, the partition wall 6B, the partition wall 6C, and the sealing layer SE1x. The terminal portion T is located outside the dam structure DS1.

[0058] As will be described in detail later, the resin layer RS1 shown in Fig. 3 is formed by an inkjet method. In Fig. 4, the outer edge OL of the range into which droplets are ejected when forming the resin layer RS1 is indicated by a dashed line. The outer edge OL is located between the partition wall 6B and the dam structure DS1.

[0059] 5 is a schematic plan view showing an enlarged view of the area surrounded by frame V in FIG. 4. A plurality of dummy pixels DPX are arranged in the dummy pixel area DMY. For example, the dummy pixel DPX includes dummy subpixels DP1, DP2, and DP3. The dummy subpixels DP1, DP2, and DP3 have structures similar to those of the subpixels SP1, SP2, and SP3 shown in FIG. 2, respectively.

[0060] That is, the dummy subpixel DP1 includes a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a sealing layer SE11. The dummy subpixel DP2 includes a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a sealing layer SE12. The dummy subpixel DP3 includes a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a sealing layer SE13.

[0061] However, the dummy subpixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy subpixels DP1, DP2, and DP3. Alternatively, the pixel openings AP1, AP2, and AP3 may be omitted from each of the dummy subpixels DP1, DP2, and DP3. This intervenes between the organic layers OR1, OR2, and OR3 and the lower electrodes LE1, LE2, and LE3, and prevents the application of a voltage to the organic layers OR1, OR2, and OR3 to cause them to emit light.

[0062] A portion of the partition wall 6A is located in the dummy pixel region DMY and surrounds each of the dummy pixels DPX. More specifically, the partition wall 6A surrounds each of the dummy subpixels DP1, DP2, and DP3. The shape and layout of the openings of the partition wall 6A in each of the dummy subpixels DP1, DP2, and DP3 are the same as the shape and layout of the openings of the partition wall 6A in each of the subpixels SP1, SP2, and SP3. The dummy pixel region DMY also has the slits SLa and connection portions CT shown in FIG. 2.

[0063] The dam structure DS1 includes a dam portion DM1 surrounding the partition wall 6C, a dam portion DM2 surrounding the dam portion DM1, and a dam portion DM3 surrounding the dam portion DM2. The partition wall 6C is spaced apart from the dam portion DM1. The number of dam portions included in the dam structure DS1 is not limited to three. For example, the dam portions DM1, DM2, and DM3 are circular and surround the display area DA.

[0064] 5, a plurality of partition walls 6D are arranged outside the dam portion DM3, and these partition walls 6D are lined up along the dam portion DM3 at intervals.

[0065] The sealing layer SE1x overlaps the entire partition wall 6B. The end portion Ex of the sealing layer SE1x is located in the slit SLb. The sealing layer SE1x is made of the same inorganic insulating material as the sealing layers SE11, SE12, and SE13.

[0066] Fig. 6 is a schematic plan view further enlarging a portion of Fig. 5. The partition wall 6B has a large number of openings 101. For example, the openings 101 have a shape that is elongated in the Y direction. However, the shape of the openings 101 is not limited to this example.

[0067] The partition 6B further has a slit SLx extending in the X direction and a slit SLy extending in the Y direction. The slit SLx connects two or more openings 101 aligned in the X direction. The slit SLy intersects with the slit SLx.

[0068] 6, the partition wall 6B further has a recess 102 recessed from the end Eb of the partition wall 6B. The recess 102 is connected to the opening 101 adjacent in the X direction by a slit SLx.

[0069] The contact portion CN1 entirely overlaps the partition wall 6B. As shown in Fig. 6, the width of the opening 101 in the X direction may be reduced near the contact portion CN1. This makes it possible to ensure a space for providing the contact portion CN1.

[0070] The partition walls 6C include a plurality of partition walls 6C1 aligned along the slit SLb and a plurality of partition walls 6C2 positioned outside the partition walls 6C1. The plurality of partition walls 6C1 and the plurality of partition walls 6C2 are spaced apart from each other.

[0071] The partition wall 6C1 has recesses 103 and 104. The partition wall 6C2 has recesses 105 and 106. The recesses 103 and 104 of adjacent partition walls 6C1 form a shape similar to that of the opening 101. Furthermore, the recesses 105 and 106 of adjacent partition walls 6C2 form a shape similar to that of the recess 102.

[0072] 7 is a schematic cross-sectional view of the peripheral area SA of the display device DSP. In this figure, the opening 101 and the slits SLx and SLy of the partition wall 6B are omitted. Also, the partition wall 6C is shown as a single unit without being divided into partition walls 6C1 and 6C2.

[0073] The partition walls 6B, 6C, and 6D have the same structure as the partition wall 6A. That is, the partition walls 6B, 6C, and 6D include a lower portion 61 and an upper portion 62. The lower portion 61 includes a bottom layer 63 and a shaft layer 64, and the upper portion 62 includes a first top layer 65 and a second top layer 66. At the ends of the partition walls 6B, 6C, and 6D, the upper portions 62 protrude beyond the side surfaces of the lower portions 61.

[0074] The circuit layer 11 shown in FIG. 3 includes inorganic insulating layers 31, 32, and 33 formed of an inorganic insulating material, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed on the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0075] Dam portions DM1, DM2, and DM3 all protrude above the substrate 10. In the example of FIG. 7, dam portion DM1 is formed from organic insulating layers 12 and 34. Dam portions DM2 and DM3 are also formed from organic insulating layers 12 and 34. That is, in this embodiment, dam portions DM1, DM2, and DM3 are formed from the same material as organic insulating layers 12 and 34 and in the same layer as organic insulating layers 12 and 34.

[0076] A power supply line PW to which a common voltage is applied is disposed below the dam portions DM1 and DM2. The power supply line PW has a first wiring W1 formed by the metal layer 42 and a second wiring W2 formed by the metal layer 43.

[0077] 7, the first wiring W1 and the second wiring W2 are in contact with each other at a contact portion CN0 located between the dam portions DM1 and DM2. In each of the dam portions DM1 and DM2, a portion of the second wiring W2 is located between the organic insulating layers 12 and 34.

[0078] The peripheral area SA is further provided with a conductive relay layer RL that connects the partition wall 6B and the power supply line PW, and a rib layer 5. The relay layer RL is formed, for example, from the same material and by the same process as the above-described lower electrodes LE1, LE2, and LE3.

[0079] The relay layer RL is located closer to the display area DA side (left side in the drawing) than the dam portion DM1, and covers the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the dam portions DM1, DM2, and DM3.

[0080] The partition walls 6B, 6C, and 6D are disposed on the rib layer 5. The partition wall 6B is in contact with the relay layer RL at the contact portion CN1, which is also shown in FIGS. 4 to 6. Specifically, the rib layer 5 has an opening at the contact portion CN1, and a lower portion 61 (specifically, a bottom layer 63) of the partition wall 6B is in contact with the relay layer RL through this opening. The contact portion CN1 is located above the organic insulating layer 12.

[0081] The relay layer RL is in contact with the second wiring W2 of the power supply line PW at the contact portion CN2, which is located between the end E0 of the organic insulating layer 12 and the dam portion DM1 in plan view.

[0082] A stacked film FLx is disposed on the partition wall 6B. The partition wall 6B and the stacked film FLx are covered with a sealing layer SE1x. The stacked film FLx is formed by the same process and from the same material as any one of the stacked films FL1, FL2, and FL3 shown in FIG. 3. The sealing layer SE1x is formed by the same process and from the same material as any one of the sealing layers SE11, SE12, and SE13 shown in FIG. 3. In this embodiment, it is assumed that the stacked film FLx and the sealing layer SE1x are formed by the same process and from the same material as the stacked film FL3 and the sealing layer SE13, respectively. That is, the stacked film FLx includes an upper electrode UE3, an organic layer OR3, and a cap layer CP3.

[0083] The partition wall 6C is not covered with the stacked film FLx and the sealing layer SE1x. As shown in Figures 5 and 6, the end Ex of the sealing layer SE1x is located in the slit SLb between the partition walls 6B and 6C.

[0084] Above the sealing layer SE1x, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 3 are arranged. Also, above the sealing layer SE2, the touch panel wiring TPL connected to the touch panel electrodes TP shown in Fig. 3 is arranged. For example, the touch panel wiring TPL is made of the same material as the touch panel electrodes TP.

[0085] The resin layer RS1 covers the sealing layer SE1x and the rib layer 5. The resin layer RS1 also directly covers the partition wall 6C. The dam portions DM1, DM2, and DM3 serve to block the resin layer RS1 before it hardens during the manufacture of the display device DSP. In the example of FIG. 7, the end portion Er1 of the resin layer RS1 is located above the dam portion DM2. That is, the resin layer RS1 covers the dam portion DM1 and a part of the dam portion DM2. However, the position of the end portion Er1 is not limited to this example.

[0086] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1. The sealing layer SE2 is in contact with the rib layer 5 in an area outside the end portion Er1 (to the right in the figure). The sealing layer SE2 also covers the partition wall 6D. In the example of FIG. 7, the sealing layer SE2 is removed near the dam portion DM3. The resin layer RS1 is surrounded by the sealing layer SE1x, the rib layer 5, and the sealing layer SE2. This prevents moisture from penetrating the resin layer RS1.

[0087] 7, the organic insulating layer 12 may have a first portion PN1 and a second portion PN2 that is thinner than the first portion PN1. The second portion PN2 is formed on the periphery of the first portion PN1. That is, the second portion PN2 surrounds the first portion PN1 in a plan view. The partition wall 6B, the partition wall 6C, the stacked film FLx, and the sealing layer SE1x are all located above the first portion PN1.

[0088] 7, the organic insulating layer 34 is disposed below the first portion PN1, and the organic insulating layer 34 is not disposed below the second portion PN2. A step portion 12a is formed in the organic insulating layer 12 near the end of the organic insulating layer 34. For example, the portion of the organic insulating layer 12 closer to the dam portion DM1 than the step portion 12a corresponds to the second portion PN2.

[0089] The relay layer RL covers the first portion PN1, the second portion PN2, and the step portion 12a. If the organic insulating layer 12 did not have the second portion PN2, the step portion 12a would be steeper. If the relay layer RL were formed to cover such a steep step portion 12a, an abnormal shape of the relay layer RL could occur. In contrast, if the second portion PN2 is provided, the step portion 12a can be reduced, and the relay layer RL can be formed well.

[0090] The cross-sectional structure shown in FIG. 7 can be applied to any position in the peripheral area SA except for the vicinity of the terminal portion T. However, the structure of the peripheral area SA is not necessarily limited to that shown in FIG. 7. For example, the organic insulating layer 12 does not necessarily have to have the second portion PN2. Furthermore, the structure for connecting the partition wall 6B and the power supply line PW can be modified as appropriate based on the position of the power supply line PW, the layer configuration of the circuit layer 11, etc.

[0091] Next, an example of a method for manufacturing the display device DSP will be described. When manufacturing the display device DSP, a large mother substrate is fabricated on which a plurality of regions (panel portions) each including a portion corresponding to the display device DSP is formed.

[0092] 8 is a schematic plan view of the mother substrate MB (mother substrate for a display device) according to this embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but may have another shape such as a circle.

[0093] The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA surrounding the panel portions PP. In the example of Fig. 8, the panel portions PP are lined up in the X and Y directions with blank areas BA between them. However, the arrangement of the plurality of panel portions PP on the mother substrate MB is not limited to this example. As another example, some panel portions PP may be lined up without blank areas BA between them.

[0094] 9 is a schematic plan view of the panel portion PP. The outer shape of the panel portion PP corresponds to the cutting lines CL1 for cutting out each panel portion PP from the motherboard MB.

[0095] The panel unit PP has the above-mentioned display area DA and peripheral area SA. The peripheral area SA in the panel unit PP corresponds to the area between the display area DA and the cut line CL1.

[0096] The peripheral area SA further has a cut line CL2 that defines the outline of the substrate 10 of the display device DSP. When manufacturing the display device DSP, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Furthermore, the display device DSP is cut out from the panel portion PP along the cut line CL2.

[0097] The panel portion PP includes a dam structure DS2 in addition to the dam structure DS1 described above. The dam structure DS2 serves to block the resin layer RS2 before curing. For example, the dam structure DS2 includes multiple dam portions formed of the organic insulating layers 12 and 34, similar to the dam portions DM1, DM2, and DM3.

[0098] Dam structure DS1 is located between cut line CL2 and display area DA and surrounds display area DA. Dam structure DS2 is located between cut lines CL1 and CL2 and surrounds cut line CL2. In the example of Fig. 9, dam structures DS1 and DS2 join near terminal portion T, and this joined portion passes between terminal portion T and display area DA.

[0099] Most of the cut line CL2 is located between the dam structures DS1 and DS2. However, in the example of Fig. 9, the cut line CL2 is located outside the dam structures DS1 and DS2 near the terminal portion T. In other words, the cut line CL2 crosses the dam structure DS2 near the terminal portion T.

[0100] Fig. 10 is a flowchart showing an example of a manufacturing method of the display device DSP. Fig. 11A to Fig. 11G are schematic cross-sectional views showing the manufacturing process of the display device DSP. Fig. 11A to Fig. 11G mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0101] In forming the panel portion PP, first, a circuit layer 11 including the inorganic insulating layers 31, 32, and 33, the organic insulating layer 34, and the metal layers 41, 42, and 43 is formed above the substrate 10 of the motherboard MB (step PR1 in FIG. 10). Further, an organic insulating layer 12 is formed to cover the circuit layer 11 (step PR2 in FIG. 10). At this time, dam structures DS1 and DS2 are also formed.

[0102] After step PR2, as shown in FIG. 11A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in FIG. 10). Furthermore, as shown in FIG. 11A, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR4 in FIG. 10). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0103] After the rib layer 5 is formed, as shown in Fig. 11B, the partition walls 6A are formed on the rib layer 5 (step PR5 in Fig. 10). The partition walls 6B, 6C, and 6D in the peripheral region SA are also formed together with the partition walls 6A.

[0104] 11C, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 (step PR6 in FIG. 10). The pixel openings AP1, AP2, and AP3 may be formed before the partition walls 6A, 6B, 6C, and 6D.

[0105] After step PR6, a step for forming display element DE1 is performed (step PR7 in FIG. 10). To form display element DE1, first, as shown in FIG. 11D, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0106] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including the display area DA of each panel unit PP, the peripheral area SA, and the margin area BA. The laminated film FL1 is divided by overhanging partition walls 6A, 6B, 6C, and 6D. The sealing layer SE11 continuously covers the divided portions of the laminated film FL1 and the partition walls 6A, 6B, 6C, and 6D.

[0107] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist RT is disposed on the sealing layer SE11, as shown in Fig. 11D. The resist RT covers the subpixel SP1 and part of the partition wall 6A around it.

[0108] Then, an etching process is performed using the resist RT as a mask. As a result, as shown in FIG. 11E, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist RT are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist RT is removed (stripped).

[0109] After step PR7, a step for forming display element DE2 is performed (step PR8 in FIG. 10). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0110] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 11F. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0111] After step PR8, a step for forming display element DE3 is performed (step PR9 in FIG. 10). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0112] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 11G.

[0113] For example, in most of the peripheral area SA and the marginal area BA, the stacked film FL3 and the sealing layer SE13 are removed by etching during the patterning. However, portions of the stacked film FL3 and the sealing layer SE13 that cover the partition wall 6B are left. These remaining portions correspond to the stacked film FLx and the sealing layer SE1x described above.

[0114] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0115] After step PR9, a resin layer RS1 is formed (step PR10 in FIG. 10). The resin layer RS1 can be formed inside the dam structure DS1 by, for example, an inkjet method. After step PR10, a sealing layer SE2 is formed by, for example, CVD (step PR11 in FIG. 10).

[0116] After step PR11, etching is performed to remove the rib layer 5 and the sealing layer SE2 that cover the terminal portions T (step PR12 in FIG. 10). This etching is, for example, dry etching.

[0117] After step PR12, touch panel electrodes TP and touch panel wiring TPL are formed on the sealing layer SE2 (step PR13 in FIG. 10). Furthermore, a resin layer RS2 is formed (step PR14 in FIG. 10). The resin layer RS2 can be formed inside the dam structure DS2 by, for example, an inkjet method. The dam structure DS2 serves to block the resin layer RS2 before it hardens.

[0118] After step PR14, the mother substrate MB is cut along the cut lines CL1 (step PR15 in FIG. 10). Furthermore, the panel portion PP is cut along the cut lines CL2 (step PR16 in FIG. 10). This completes the display device DSP. For cutting in steps PR15 and PR16, for example, laser cutting can be used, in which an infrared laser is irradiated along the cut lines CL1 and CL2. However, cutting in steps PR15 and PR16 may also be performed by other methods, such as scribe cutting.

[0119] According to the above-described embodiment, it is possible to improve the yield of the display device DSP. That is, the laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the base. Therefore, there is a possibility that the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may peel off from the base during the manufacturing of the display device DSP.

[0120] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the stacked films FL1, FL2, and FL3 are finely divided by the partition walls 6A, which prevents the peeling.

[0121] In this embodiment, the partition wall 6B having a plurality of openings 101 (see FIG. 6) and the partition wall 6C divided into partition walls 6C1 and 6C2 are arranged in the peripheral area SA, whereby the stacked films FL1, FL2, and FL3 are divided into small pieces also in the peripheral area SA, thereby suppressing the peeling.

[0122] Furthermore, with the configuration of the display device DSP according to this embodiment, it is possible to obtain the effects described below, for example. 12A and 12B are schematic cross-sectional views of a display device DSPa according to a comparative example. 13A and 13B are schematic cross-sectional views of a display device DSP according to the present embodiment. These figures focus on the vicinity of the end Ex of the sealing layer SE1x.

[0123] 12A and 13A show droplets D being ejected toward the mother substrate MB when the resin layer RS1 is formed by the inkjet method in the above-described process PR10, and FIGS. 12B and 13B show the state after the droplets D have adhered.

[0124] 12A, no partition wall 6C is provided. Also, the outer end OL of the range into which the droplets D are discharged is positioned so as to overlap with the sealing layer SE1x. That is, the droplets D do not adhere to the outer side (the right side in the figure) of the end Ex of the sealing layer SE1x.

[0125] In the comparative example, the droplet D deposited on the sealing layer SE1x spreads to form a resin layer RS1, as shown in Fig. 12B. At this time, the surface tension near the end Ex may hinder the spreading of the resin layer RS1, and the end Er1 of the resin layer RS1 may not reach the dam portions DM1 and DM2 as shown in Fig. 7.

[0126] 12B, the sealing layer SE2 is formed so as to cover the steep steps caused by the ends Ex and Er1. In this case, cracks and gaps may occur in the sealing layer SE2 made of an inorganic insulating material, which may form paths for moisture penetration.

[0127] One possible solution to this situation is to position the outer end OL of the range into which the droplets D are discharged outside the end portion Ex. However, from the viewpoint of the accuracy of forming the resin layer RS1, it is necessary to provide a certain distance between the dam portions DM1, DM2, DM3 and the outer end OL, and it may be difficult to shift the position of the outer end OL outward.

[0128] Another possible solution is to move the end Ex toward the display area DA (left side in the figure). However, in this case, the position of the end of the partition 6B must also be moved along with the sealing layer SE1x. That is, if there is an area where the stacked film FLx is exposed from the sealing layer SE1x, moisture may penetrate into the display area DA through the stacked film FLx. Therefore, in order to completely seal the stacked film FLx on the partition 6B, the position of the end of the partition 6B must also be moved toward the display area DA so that the sealing layer SE1x is formed beyond the end of the partition 6B. However, in such a configuration, a wide area is formed between the partition 6B and the dam portion DM1, and the above-mentioned peeling may occur in this area.

[0129] On the other hand, in the configuration of this embodiment shown in FIG. 13A, the partition 6C is disposed outside the partition 6B. With this configuration, the partition 6C also suppresses the above-mentioned peeling in the region between the partition 6B and the dam portion DM1. Therefore, the partition 6B can be positioned closer to the display area DA than in the configuration of FIG. 12A. Accordingly, the position of the end Ex of the sealing layer SE1x can also be moved closer to the display area DA than in the configuration of FIG. 12A, and can be positioned, for example, at the slit SLb.

[0130] For example, if the position of the outer end OL is the same in the comparative example and this embodiment, the droplet D can be deposited in an area outside the end Ex, as shown in Figure 13A. In this case, the droplet D spreading on the end Ex and the droplet D spreading in the area outside the end Ex1 merge to form a resin layer RS1 that adequately covers the end Ex. Therefore, the steep steps described above in the comparative example are not generated, cracks in the sealing layer SE2 are suppressed, and a display device DSP with excellent moisture resistance can be obtained.

[0131] 4 to 6, if the end portion Ex of the sealing layer SE1x is positioned in the slit SLb along the entire periphery, it is possible to effectively suppress moisture penetration through the laminated film FLx. Even if the partition walls 6B and 6C are completely separated by the slit SLb, the supply of the common voltage to the display area DA through the partition wall 6B is not hindered because the contact portion CN1 is provided at a position overlapping with the partition wall 6B.

[0132] 12B does not occur, the present embodiment suppresses poor application of liquid resins such as various resists that are applied after the formation of the resin layer RS1. Examples of such liquid resins include resists for processing the rib layer 5 and the sealing layer SE2 in step PR12, and resists for processing the touch panel electrodes TP and the touch panel wiring TPL in step PR13.

[0133] The display device DSP may include a plurality of color filters corresponding to the colors of the subpixels SP1, SP2, and SP3, and a black matrix located at the boundaries of the subpixels SP1, SP2, and SP3. For example, these color filters and black matrix may be disposed above the sealing layer SE2. By reducing the steps caused by the ends Er1 and Ex, it is possible to prevent poor application of the resin that is the material for these color filters and black matrix.

[0134] [Second embodiment] 14 is a schematic cross-sectional view of the peripheral area SA of the display area DA according to the second embodiment. The structure shown in this figure differs from the structure shown in FIG. 7 in that a partition wall 6E (fourth partition wall) is further disposed between the partition wall 6C and the dam portion DM1. For example, the partition wall 6E is located above the second portion PN2 of the organic insulating layer 12.

[0135] Like the partition walls 6B, 6C, and 6D, the partition wall 6E has a lower portion 61 and an upper portion 62. The lower portion 61 of the partition wall 6E includes a bottom layer 63 and an axial layer 64, and the upper portion 62 of the partition wall 6E includes a first top layer 65 and a second top layer 66.

[0136] With this configuration, during the manufacturing of the display device DSP, the partition 6E can suppress peeling of the stacked films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 even in the region between the partition 6C and the dam portion DM1, thereby further improving the yield of the display device DSP.

[0137] 14, a partition wall may be disposed between the dam portions DM1 and DM2 or between the dam portions DM2 and DM3. Also, a partition wall may be disposed so as to overlap with the dam portions DM1, DM2, and DM3.

[0138] [Third embodiment] 15 is a schematic plan view showing the configuration of a display device DSP according to the third embodiment. This plan view shows the structure in the vicinity of an end E10 of a substrate 10.

[0139] In this embodiment, the dam structure DS1 (dam portions DM1, DM2, DM3) is not arranged in the peripheral area SA, which makes it possible to reduce the width of the peripheral area SA compared to the first embodiment (see FIG. 4).

[0140] The end E0 of the organic insulating layer 12 is located closer to the display area DA than the end E10 of the substrate 10. This causes the substrate 10 to have an outer periphery area OA where the organic insulating layer 12 is not disposed. The outer periphery area OA is the portion located between the end E0 and the end E10.

[0141] As in the first embodiment, partitions 6A (first partitions) are arranged in the display area DA, and partitions 6B (second partitions), 6C (third partitions), and 6D are arranged in the peripheral area SA. The planar shapes of the partitions 6A, 6B, and 6D are the same as those shown in FIGS. 5 and 6.

[0142] An end E0 of the organic insulating layer 12 is located between an end E10 of the substrate 10 and the partition wall 6C. That is, the partition walls 6B and 6C overlap with the organic insulating layer 12. On the other hand, the partition wall 6D is located in the outer peripheral region OA and does not overlap with the organic insulating layer 12.

[0143] The partition wall 6C is separated from the partition wall 6B by a slit SLb. In the example of Fig. 15, the partition wall 6C includes a plurality of partition walls 6Ca and a plurality of partition walls 6Cb. For example, the partition walls 6Ca and 6Cb have a rectangular or arc shape that extends along the end portion Ex of the sealing layer SE1x.

[0144] The plurality of partition walls 6Ca are located between the end Ex of the sealing layer SE1x and the end E0 of the organic insulating layer 12, and are aligned along the ends Ex and E0 at regular intervals. The plurality of partition walls 6Cb are located between the row of partition walls 6Ca and the end E0, and are aligned at regular intervals like the partition walls 6Ca. From the viewpoint of suppressing peeling of the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 during the manufacture of the display device DSP, it is preferable that the distance Ds between the partition wall 6B and the partition wall 6Ca be less than 80 μm.

[0145] 15, the gap GPa between adjacent partition walls 6Ca and the gap GPb between adjacent partition walls 6Cb are misaligned in the arrangement direction of the partition walls 6Ca and 6Cb (the direction along the ends Ex and E0). However, the gaps GPa and GPb do not necessarily need to be misaligned over the entire peripheral area SA and may be aligned at least partially.

[0146] 16 is a schematic cross-sectional view of the peripheral area SA of the display device DSP according to the third embodiment. As in the example of FIG. 7, the organic insulating layer 12 has a first portion PN1 and a second portion PN2 that is thinner than the first portion PN1. However, the organic insulating layer 12 does not necessarily have to have the second portion PN2.

[0147] For example, neither the organic insulating layer 12 nor the organic insulating layer 34 is disposed in the outer peripheral area OA. However, the organic insulating layer 34 may be disposed in at least a part of the outer peripheral area OA.

[0148] In this embodiment, the end portion Er1 of the resin layer RS1 is located above the organic insulating layer 12. Specifically, in the example of Fig. 16, the end portion Er1 is located near a corner portion 5a of the rib layer 5 formed by the step portion 12a. In other words, the resin layer RS1 does not overlap with the outer circumferential area OA.

[0149] Like the partition wall 6B, the partition walls 6Ca and 6Cb include a lower portion 61 and an upper portion 62. As described above, the partition walls 6Ca and 6Cb are located between the end portion Ex of the sealing layer SE1x and the end portion E0 of the organic insulating layer 12. In other words, the partition walls 6Ca and 6Cb are not covered by the sealing layer SE1x. The partition walls 6Ca and 6Cb are located on the rib layer 5 and are covered by the resin layer RS1.

[0150] As in the first embodiment, the resin layer RS1 is covered with the sealing layer SE2. The sealing layer SE2 is in contact with the rib layer 5 in the outer peripheral area OA. In the example of Fig. 16, the sealing layer SE2 is divided in the outer peripheral area OA.

[0151] 15 and 16 can be applied to any position in the peripheral area SA except for the vicinity of the terminal portion T. However, the structure of the peripheral area SA is not necessarily limited to that shown in these figures. For example, like the partition wall 6E shown in FIG. 14 in the second embodiment, a partition wall may be disposed above the second portion PN2 or between the end portion E0 and the partition wall 6D.

[0152] Next, an example of a manufacturing method of the display device DSP according to this embodiment will be described. The display device DSP according to this embodiment can be manufactured in a flow similar to the steps described in the first embodiment using Figures 10 and 11A to 11G. That is, when manufacturing the display device DSP, a large mother substrate is produced on which a plurality of panel sections PP each including a portion corresponding to the display device DSP is formed, and the display devices DSP are cut out from this mother substrate.

[0153] Fig. 17 is a schematic plan view of the panel unit PP in this embodiment. As in the example of Fig. 9, the panel unit PP includes a display area DA, a peripheral area SA, a cut line CL2, and a dam structure DS2. However, in this embodiment, the panel unit PP does not include the dam structure DS1.

[0154] As described above, in this embodiment, since the dam structure DS1 is not provided, the way in which the droplets D spread when the resin layer RS1 is formed by the inkjet method differs from that shown in Figures 13A and 13B. This point will be explained below.

[0155] Fig. 18A is a schematic cross-sectional view showing a state in which droplets D are discharged during the manufacture of the display device DSP according to this embodiment, and Fig. 18B is a schematic cross-sectional view showing the state after droplets D have adhered.

[0156] In this embodiment, the outer end OL of the range into which the droplets D are discharged is located between the end Ex of the sealing layer SE1x and the corner 5a of the rib layer 5. Specifically, in the example of Fig. 18A, the outer end OL is located between the end Ex and the partition wall 6Ca. Note that the position of the outer end OL is not limited to this example, and it may overlap with the partition walls 6Ca, 6Cb or the area between the partition walls 6Ca, 6Cb.

[0157] The droplets D attached to the sealing layer SE1x spread as shown in FIG. 18B. At this time, the partition walls 6Ca and 6Cb inhibit the spreading of the droplets D. Furthermore, surface tension acts on the droplets D that have spread beyond the partition walls 6Ca and 6Cb near the corners 5a. As a result, the spreading of the droplets D stops near the corners 5a, and a resin layer RS1 is formed with its end Er1 located near the corners 5a.

[0158] As shown in Figure 15, when the gap GPa between adjacent partition walls 6Ca and the gap GPb between adjacent partition walls 6Cb are misaligned, the spread of the droplets D can be suitably suppressed. In other words, if the gaps GPa and GPb overlap, the spread of the droplets D cannot be sufficiently suppressed in that area. As a result, the droplets D may spread beyond the corner 5a. In contrast, when the gaps GPa and GPb are misaligned, the spread of the droplets D is inhibited at various locations by at least one of the partition walls 6Ca and 6Cb.

[0159] Furthermore, if the partition walls 6Ca, 6Cb were linear and did not have gaps GPa, GPb, the spread of the droplets D would be too hindered, and there would be locations where the resin layer RS1 could not be formed up to the vicinity of the corners 5a. In contrast, if gaps GPa, GPb are provided in various locations, the droplets D can pass through appropriately, and the resin layer RS1 can be formed up to the vicinity of the corners 5a.

[0160] If it is necessary to further suppress the spread of the droplets D by the partition 6C, an additional partition may be disposed between the partition 6Cb and the corner 5a. If it is necessary to weaken the effect of the partition 6C in suppressing the spread of the droplets D, one of the partitions 6Ca and 6Cb may be omitted.

[0161] In each of the above embodiments, the term "partition wall" includes various overhanging structures. Even if the overhanging structure has a shape different from the partition wall disclosed in each embodiment, the part that protrudes to the side corresponds to the "upper part," and the part that recedes below the part that protrudes to the side corresponds to the "lower part."

[0162] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices disclosed in each embodiment also fall within the scope of the present invention as long as they include the gist of the present invention.

[0163] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0164] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0165] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE1x, SE2...sealing layer, RS1, RS2...resin layer, MB...motherboard, PP...panel portion, 5...rib layer, 6A, 6B, 6C, 6D...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a substrate having a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed in the display area and the peripheral area; a plurality of pixels arranged in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall disposed in the display region and surrounding each of the plurality of pixels; a second partition wall disposed in the peripheral region and connected to the first partition wall; a third partition wall disposed outside the second partition wall in the peripheral region and separated from the second partition wall via a slit; a dam portion disposed in the peripheral region and surrounding the organic insulating layer, the second partition wall, and the third partition wall; Equipped with the first partition wall, the second partition wall, and the third partition wall each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; the third partition wall is located above the organic insulating layer and is spaced apart from the dam portion; Display device.

2. the second partition, the dam portion, and the third partition surround the display area. The display device according to claim 1 .

3. a first sealing layer formed of an inorganic insulating material and covering a laminated film including the organic layer and the upper electrode; the first sealing layer covers the second partition wall but does not cover the third partition wall; The display device according to claim 1 .

4. an end of the first sealing layer located in the slit; The display device according to claim 3 .

5. The slit surrounds the display area. The display device according to claim 4 .

6. a first resin layer that covers the display area and a part of the peripheral area; The first resin layer covers at least a portion of the dam portion. The display device according to claim 3 .

7. the first resin layer directly covers the third partition wall; The display device according to claim 6.

8. a second sealing layer formed of an inorganic insulating material and covering the first resin layer; The display device according to claim 6.

9. Further comprising a second resin layer covering the second sealing layer. The display device according to claim 8 .

10. The organic insulating layer is A first part; and a second portion formed on a periphery of the first portion and thinner than the first portion; Including, The display device according to claim 1 .

11. the second partition wall and the third partition wall are disposed above the first portion. The display device according to claim 10.

12. further comprising a fourth partition wall disposed above the second portion; The display device according to claim 10.

13. a power supply line disposed in the peripheral region; a conductive relay layer disposed in the peripheral region and connecting the second partition wall and the power supply line; Further provided with The display device according to claim 1 .

14. the second partition wall is in contact with the relay layer at a first contact portion located above the organic insulating layer; The display device according to claim 13.

15. the relay layer is in contact with the power supply line at a second contact portion located between an end of the organic insulating layer and the dam portion in a plan view; The display device according to claim 14.

16. the first contact portion is located between the slit and the display area in a plan view; The display device according to claim 14.

17. the dam portion is formed of the same material as the organic insulating layer; The display device according to claim 1 .

18. The second partition has a plurality of openings. The display device according to claim 1 .

19. The second partition wall further has a slit connected to at least one of the plurality of openings.

19. The display device according to claim 18.

20. the display area, the second partition wall, the third partition wall, and the dam portion are circular.

20. A display device according to any one of claims 1 to 19.

21. a substrate having a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed in the display area and the peripheral area; a plurality of pixels arranged in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall disposed in the display region and surrounding each of the plurality of pixels; a second partition wall disposed in the peripheral region and connected to the first partition wall; a third partition wall disposed outside the second partition wall in the peripheral region and separated from the second partition wall via a slit; a first resin layer covering the display area and a part of the peripheral area; Equipped with the first partition wall, the second partition wall, and the third partition wall each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; an end of the organic insulating layer is located between an end of the substrate and the third partition wall; the substrate has a peripheral region located between the edge of the organic insulating layer and the edge of the substrate; the first resin layer covers the third partition wall and does not overlap the outer circumferential region; Display device.

22. a first sealing layer formed of an inorganic insulating material and covering a laminated film including the organic layer and the upper electrode; the first sealing layer is located below the first resin layer, covers the second partition wall, and does not cover the third partition wall; The display device according to claim 21.

23. a rib layer formed of an inorganic insulating material and positioned below the second partition wall and the third partition wall; a second sealing layer formed of an inorganic insulating material and covering the first resin layer; Furthermore, The rib layer and the second sealing layer are in contact with each other in the outer peripheral region.

23. The display device according to claim 21 or 22.

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