Semiconductor device

Abstract

To provide a small semiconductor device in which output voltage variation due to high frequency noise is suppressed.SOLUTION: An internal circuit is formed on the main surface of a substrate 1, a printed circuit 3 is formed on the rear surface, and a chip capacitor 5a as a mounting component is mounted on the printed circuit 3. A lead frame 6 which is a fan-out member is attached to it, and the semiconductor substrate, the mounted component, and the fan-out member are covered with a mold resin 11 so that only the external connection part of the fan-out member is exposed. To suppress the output voltage fluctuation of an internal circuit by forming a low-pass filter by parasitic capacitance generated in the internal circuit of a semiconductor substrate, a printed circuit and mounted components.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that is resistant to high frequency noise that enters a positive power supply terminal. [Background technology]

[0002] The widespread use of wireless communication devices has created a demand for semiconductor devices that can operate stably even in high-frequency noise environments in the gigahertz band. For example, in operational amplifiers and comparators, measures are now being taken to prevent high-frequency noise not only from the input terminals but also from the power supply terminals. Countermeasures against high-frequency noise at power supply terminals will be explained below using an operational amplifier as an example. Figure 13 is a conceptual diagram of a conventional operational amplifier. As shown in Figure 13(a), when high-frequency noise is mixed into the positive power supply terminal VCC, the DC level of the output voltage of the operational amplifier OP changes (Figure 13(b)). Such changes in the DC level of the output voltage may cause malfunctions in applications in which the operational amplifier is used. Therefore, as in Patent Document 1, operational amplifiers have been proposed that have countermeasures against high-frequency noise at the power supply terminals. A circuit diagram of the operational amplifier with high frequency noise countermeasures disclosed in Patent Document 1 is shown in Fig. 14. The feature of Fig. 14 is that the power supply voltage supplied to the operational amplifier OP is applied via a low-pass filter LPF.

[0003] The circuit configuration of Figure 14 will be explained. A series circuit consisting of resistor RX1 and diode DX1 is connected between the power rails, which consist of a high-potential rail connected to the positive power supply terminal VCC and a low-potential rail connected to the negative power supply terminal VEE. Capacitor CX1 is connected in parallel with resistor RX1 in this series circuit. Diode DX1 has its anode connected to the connection node between resistor RX1 and capacitor CX1, and its cathode connected to the low-potential power rail. Parasitic inductance L1 exists in the power rail wiring, parasitic capacitance CbX1 exists between the anode and cathode of diode DX1, and parasitic capacitance Cb0 exists between the power rails, which is made up of the PN junction capacitance of the transistor. A low-pass filter LPF is formed by these parasitic inductances L1, resistor RX1, diode DX1, capacitor CX1, and parasitic capacitances CbX1 and Cb0. On the other hand, the positive power supply line HBL connected to the positive bias terminal of the operational amplifier OP is connected to the high-potential power supply rail at node H, and the negative power supply line LBL connected to the negative bias terminal is connected to the low-potential power supply rail at node L. Note that feedback resistors, phase-shift compensation capacitances, and other circuits are not shown in the figure. 14 is configured as described above, the noise input from the positive power supply terminal VCC and transmitted to the power supply rail is reduced by the low-pass filter LPF. As a result, a voltage with little noise is applied to the positive bias terminal (not shown) of the operational amplifier OP via node H and the positive power supply line HBL, thereby suppressing output voltage fluctuations due to high-frequency noise. In Patent Document 1, the circuit constants are set so as to satisfy the following conditional expressions: (CX1xCbX1) / (CX1+CbX1)>[1 / {(2πfc) 2 xL1}-Cb0 However, the meanings of the symbols in the above formula are as follows: CX1: Capacitance value of capacitor CX1 CbX1: Parasitic capacitance value of diode DX1 Cb0: The capacitance of the parasitic capacitance formed between the power rails fc: Cutoff frequency that attenuates high frequency noise L1: Parasitic inductance value generated by wiring In this way, in Patent Document 1, high frequency noise countermeasures are implemented for the power supply terminals using the circuit diagram in FIG. 14 and the conditions of the above formula. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-29310 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, high-frequency noise countermeasures for power supply terminals are implemented by incorporating resistors, diodes, and capacitors inside the chip. However, placing these elements inside the chip increases the chip size, which is an issue. In view of the above problems, an object of the present invention is to provide a small semiconductor device that suppresses output voltage fluctuations due to high frequency noise. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a plurality of electrodes formed on a main surface thereof, an internal circuit electrically connected to the plurality of electrodes, and a printed circuit formed on a back surface thereof; at least one mounted component mounted on the printed circuit; a fan-out member supporting the semiconductor substrate from the back surface thereof, the fan-out member having a plurality of internal connections made of a conductive material and a plurality of external connections made of a conductive material that are electrically conductive with at least some of the plurality of internal connections; and a resin that covers the semiconductor substrate, the mounted components, and the fan-out member so as to expose only the external connections of the fan-out member, wherein at least some of the plurality of electrodes of the semiconductor substrate are electrically connected to the internal connections of the fan-out member, and a portion of the printed circuit is electrically connected to the mounted component, and another portion is electrically connected to the internal connections of the fan-out member. Here, the fan-out member may be a lead frame, and the leads of the lead frame may have bent portions formed thereon. Furthermore, a low-pass filter may be formed by the parasitic capacitance of the internal circuit, the printed circuit, and the mounted components. Furthermore, the printed circuit may be replaced by a circuit made of a plating pattern.The resistance component of the printed circuit may be formed by a printed resistor, which may be replaced by a resistance component in some cases. The semiconductor substrate and the printed circuit may be insulated from each other, and a ceramic substrate may be used as the insulating means. [Effects of the Invention]

[0007] According to one aspect of the present invention, by forming a circuit that constitutes the main part of the low-pass filter on the back surface of the chip, it is possible to reduce the chip area and suppress output voltage fluctuations due to high-frequency noise. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a side cross-sectional view of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a bottom view of the semiconductor device according to the first embodiment of the present invention. [Figure 3] 1 is a top view of a semiconductor device according to a first embodiment of the present invention. [Figure 4] 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. [Figure 5] FIG. 4 is a side cross-sectional view of a semiconductor device according to a second embodiment of the present invention. [Figure 6] FIG. 4 is a top view of a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a side cross-sectional view of a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 10 is a top view of a semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 10 is a circuit diagram of a semiconductor device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is a side cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] FIG. 10 is a top view of a semiconductor device according to a fourth embodiment of the present invention. [Figure 12] 3 is a bottom view showing a modified example of the semiconductor device shown in FIG. 2. FIG. [Figure 13] FIG. 1 is a diagram illustrating a conventional semiconductor device. [Figure 14] FIG. 1 is a diagram illustrating an example of a circuit of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, first to fourth embodiments of the present invention will be described with reference to Fig. 1 to Fig. 12. In the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0010] (First embodiment) A semiconductor device according to a first embodiment of the present invention will be described with reference to Figures 1 to 4. Figure 1 shows a side cross-sectional view of the semiconductor device, Figure 2 shows a bottom view of the device, Figure 3 shows a top view of the device, and Figure 4 shows a circuit diagram of the device. 《Device structure》 The structure of the semiconductor device according to this embodiment will be described with reference to FIG. 1. A plurality of electrode pads 1a are formed on the main surface of a semiconductor substrate 1, and these are electrically connected to an internal circuit (not shown). The internal circuit is monolithically formed on the semiconductor substrate 1 by a semiconductor process. An insulating film 2 is formed on the back surface of the main surface of the semiconductor substrate 1, and a printed circuit 3 is further formed on the front surface of the insulating film 2. The insulating film 2 is formed by applying, for example, epoxy resin, and this insulating film 2 maintains insulation between the semiconductor substrate 1 and the printed circuit 3. The printed circuit 3 is formed by screen printing a conductive paste such as silver paste. Furthermore, a chip capacitor 5a consisting of a chip component whose two poles are connected via a conductive adhesive 4 is mounted on the printed circuit 3.

[0011] The semiconductor substrate 1, which includes an insulating film 2, a printed circuit 3, and a chip capacitor 5a, is die-bonded onto a lead frame 6. The lead frame 6 is made of a conductive material such as 42 alloy, aluminum, or copper, and serves to maintain an appropriate distance (pitch) between terminals for mounting on a mounting substrate (not shown). In other words, it is a fan-out component that converts the narrow pitch of the electrode pads 1a to an appropriate pitch. The electrode pads 1a are electrically connected to the printed circuit 3 by bonding wires 10. In this case, leads 6a and 6b of the lead frame 6 are used to relay the electrical connection. The molding resin 11 is made of an epoxy resin and covers the entire device except for a portion of the leads 6a and 6b. The portions of the leads 6a and 6b not covered by the molding resin 11 are used as external connection portions for connection to a mounting board (not shown). In this embodiment, the portions of the leads 6a and 6b other than the external connection portions serve as internal connection portions with the semiconductor substrate 1 and the printed circuit 3. This structure, in which components such as capacitors are mounted on the back side of the semiconductor substrate 1, allows for the semiconductor substrate 1 to be prevented from becoming unnecessarily large, thereby saving space. This is because a low-pass filter that reduces noise at gigahertz-level frequencies requires a large-capacity capacitor, and forming this monolithically within the semiconductor substrate would increase the circuit size.

[0012] Next, the configuration of the back surface of the semiconductor device according to this embodiment will be described with reference to Fig. 2. Note that in this figure, the portion covered with resin 11 is shown in a see-through manner. As described above, an insulating film 2 is formed on the back surface of the semiconductor substrate 1, and a printed circuit 3 is formed on the insulating film 2. A part of this printed circuit 3 is a printed resistor RA formed with a meander structure. For ease of explanation, the other printed wiring portions of the printed circuit 3 are designated by the symbols 3a, 3b, and 3c. The combined resistance of these printed resistors RA and the printed wirings 3a and 3b forms a resistance component RA1, which will be described later, and the parasitic inductance of the printed resistor RA mainly forms an inductance component LA1, which will be described later, for the entire wiring. Lead 6a, which serves as the positive power supply terminal VCC, is connected to one end of printed resistor RA via printed wiring 3a. The other end of printed resistor RA is connected to lead 6b via printed wiring 3b, and to one end of chip capacitor 5a via conductive adhesive 4. The other end of chip capacitor 5a is connected to one end of printed wiring 3c via conductive adhesive 4. The other end of printed wiring 3c is connected to lead 6a, which serves as the negative power supply terminal VEE. These leads 6a and 6b are bonded to printed wiring 3a through 3c with conductive adhesive. Leads 6a and 6b that are not bonded to printed wiring 3a through 3c are bonded to lands (not shown) formed on insulating film 2. These lands are provided simultaneously with printed circuit 3 solely for bonding purposes and are not connected to any other electrodes or nodes. With this structure, leads 6a and 6b connect to insulating film 2 and printed circuit 3, supporting semiconductor substrate 1 from its backside.

[0013] FIG. 3 shows a bird's-eye view of the semiconductor device according to this embodiment, seen through the mold resin 11. An operational amplifier OP1 is monolithically formed on the semiconductor substrate 1 as an internal circuit. The positive bias terminal (not shown) of the operational amplifier OP1 is connected to a high-potential power rail at node H via a positive power line HBL, and the negative bias terminal (not shown) is connected to a low-potential power rail at node L via a negative power line LBL. The high-potential power rail is electrically connected to lead 6b via electrode pad 1a and bonding wire 10, and the low-potential power rail is electrically connected to lead 6a, which serves as a negative power terminal VEE, via electrode pad 1a and bonding wire 10. Although not shown, the operational amplifier OP1 is composed of two differential amplifier circuits, each with two channels, A and B, for input and output. For this purpose, input terminals INM (Ach), INM (Bch), INP (Ach), and INP (Bch) and output terminals OUT (Ach) and OUT (Bch) are assigned to leads 6a, 6a..., respectively. Also, a parasitic capacitance Cb0 exists between the power supply rails due to the PN junction of the transistors that make up the operational amplifier OP1. The above is the structure of the semiconductor device according to this embodiment.

[0014] 《Manufacturing method》 The following describes a method for manufacturing a semiconductor device according to this embodiment. First, a lead frame 6 without a die pad is prepared. The die pad's suspension lead is left as lead 6b, and the other leads are designated as lead 6a. Meanwhile, a semiconductor substrate 1 is prepared. After forming an operational amplifier OP1, metal wiring, a passivation film, and pad openings using a standard wafer process, electrode pads 1a are formed by aluminum deposition and patterning. After the wafer process, an insulating film 2 is formed by applying an epoxy resin or the like to the backside of the wafer. Furthermore, a wiring pattern and lands are formed on the surface by screen printing a conductive paste. These lands become the junctions with the leads 6a or 6b. After transferring the pattern using a squeegee, a heat treatment is performed to form the printed circuit 3 (printed wiring 3a to 3c and printed resistor RA). Next, the semiconductor substrate 1 is die-bonded onto the lead frame 6. Die-bonding is performed by applying a conductive adhesive to the inner end surfaces of all of the leads 6a and 6b, and then aligning and joining them with the printed wiring 3a to 3c and lands of the semiconductor substrate 1. Next, chip capacitor 5a is mounted on the back surface of semiconductor substrate 1. Mounting is performed by applying conductive adhesive 4 to the surface of insulating film 2 on the back surface of semiconductor substrate 1, then mounting chip capacitor 5a and curing conductive adhesive 4. Next, the semiconductor substrate 1 and the leads 6a and 6b are connected by bonding wires 10. At this time, a wire bonder is used, with the electrode pad 1a of the semiconductor substrate 1 being the first bonding point and the lead 6a or 6b being the second bonding point. Next, the assembly consisting of the lead frame 6, semiconductor substrate 1, and chip capacitor 5a is set in the mold of a resin molding machine, and molten resin is injected to perform transfer molding to form molded resin 11. At this time, in order to expose the back surfaces of the leads 6a and 6b from the molded resin 11, the back surfaces of these leads are butted against the lower mold. Finally, gates and burrs are removed, tie bars are cut, and leads are shaped to separate the individual semiconductor devices. Note that since the example shown is a leadless package, leads 6a and 6b can be cut using a cutting die to follow the outline of mold resin 11.

[0015] <Circuit configuration> The circuit configuration of a semiconductor device according to this embodiment will be described using an operational amplifier as an example, with reference to FIG. 4. In this embodiment, a low-pass filter is formed by the parasitic capacitance of the semiconductor substrate, the printed circuit, and the mounted components. That is, the low-pass filter LPF1 is formed by the inductance component LA1, the resistance component RA1, the capacitor CA1, and the parasitic capacitance Cb0 shown in FIG. 4. This low-pass filter LPF1 is provided between power rails and filters out noise components that are present on the power rails. The circuit layout on the back side of semiconductor substrate 1 is as described above using Figure 2, so the inductance component LA1 and resistance component RA1 of printed circuit 3 are arranged as a series circuit on the high-potential power rail. Capacitor CA1 is connected between the power rails. Meanwhile, the circuit layout on the main surface of semiconductor substrate 1 is as described above using Figure 3. Therefore, one end of the above series circuit is connected to the positive power supply terminal VCC, the other end is connected to one end of capacitor CA1, and the other end of capacitor CA1 is connected to the negative power supply terminal VEE, which, together with the parasitic capacitance Cb0 between the power rails, forms a low-pass filter LPF1. In addition to the above, the operational amplifier OP1 is provided with a feedback resistor, a phase compensation capacitor, and other circuits, but these are not shown in the figure as they are not related to the subject matter of the present invention. Because the circuit of the semiconductor device according to this embodiment has the above-described configuration, noise on the power supply rail is reduced by the low-pass filter LPF1. As a result, a voltage with little noise is applied to the positive bias terminal of the operational amplifier OP1 via node H and the positive power supply line HBL, thereby suppressing output voltage fluctuations due to high-frequency noise. The circuit constants of this low-pass filter LPF1 satisfy the condition shown in equation (1).

[0016]

number

[0017] (Second embodiment) A semiconductor device according to a second embodiment of the present invention will be described with reference to Figures 5 and 6. Figure 5 shows a side cross-sectional view of the semiconductor device, and Figure 6 shows a top view of the device. In this embodiment, a general-purpose semiconductor chip 7 having an internal circuit formed thereon is mounted on a semiconductor substrate 1 having a printed circuit formed on its back surface, forming a vertically stacked structure. In other words, the semiconductor substrate 1 is used as a relay chip for relaying the connection between the semiconductor chip 7 and the printed circuit and the connection between the semiconductor chip 7 and the lead frame 6. The semiconductor chip 7 and the semiconductor substrate 1 are electrically connected by connecting their electrode pads 7a and 1a with bonding wires 10. The electrode pads 1a of the semiconductor substrate 1 are electrically connected to the leads 6a and 6b of the lead frame 6 by bonding wires 10, as in the first embodiment. The electrode pads 1a electrically connected to the operational amplifier OP1, which is an internal circuit of the semiconductor chip 7, and the electrode pads 1a electrically connected to the leads 6a or 6b are connected by metal wiring 1b within the semiconductor substrate 1. Therefore, the number of electrode pads 1a is at least twice the number of electrode pads 7a. For example, if there are eight electrode pads 7a, the number of electrode pads 1a will be 16 or more. Similarly to the first embodiment, the low-pass filter LPF1 is composed of an inductance component LA1, a resistance component RA1, a capacitor CA1, and a parasitic capacitance Cb0. This completes the configuration of the second embodiment.

[0018] This configuration allows for the formation of a printed circuit of an appropriate size without being restricted by the small scale of the internal circuit. In the first embodiment, when the circuit scale of the operational amplifier OP1 is small, the size of the semiconductor substrate 1 is also small, limiting the area for constructing the filter on the back surface. The limited area for constructing the filter prevents the printed resistor RA from being large, causing the cutoff frequency fc to shift to the high-frequency side. As a result, high-frequency noise cannot be sufficiently attenuated. In this embodiment, by using the semiconductor substrate 1 as a relay chip, the area for constructing the printed resistor RA on the back surface of the chip can be secured. As a result, the resistance value of the printed resistor RA can be increased, and the cutoff frequency fc can be lowered. This increases the attenuation rate of high-frequency noise, enabling more effective high-frequency noise countermeasures. Furthermore, in the first embodiment, a semiconductor substrate containing two circuits is used, but instead, two semiconductor chips 7, 7 containing one circuit can be mounted on the semiconductor substrate 1 to configure the same circuit as in the first embodiment, thereby improving the degree of freedom in design. In other words, there is no need to prepare a dedicated semiconductor chip 7, and there is a cost advantage in that the construction period is shortened.

[0019] (Third embodiment) A semiconductor device according to a third embodiment of the present invention will be described with reference to Figures 7 to 9. Figure 7 shows a side cross-sectional view of the semiconductor device according to this embodiment, Figure 8 shows a top view of the device, and Figure 9 shows a circuit diagram of the device. In this embodiment, a comparator is formed as an internal circuit, and high-frequency noise countermeasures are taken for the comparator. As shown in Fig. 7, a semiconductor substrate 8 including an insulating film 2, a printed circuit 3, and a chip capacitor 5a is die-bonded onto a lead frame 6. The semiconductor substrate 8 is similar to the first embodiment except that a comparator CMP is formed as an internal circuit. In other words, it is the same as the first embodiment except that the semiconductor substrate 1 in Fig. 1 described above is replaced with the semiconductor substrate 8. 8 shows a bird's-eye view of the semiconductor device according to this embodiment, seen through the mold resin 11. The semiconductor device is the same as the first embodiment except that a comparator CMP is monolithically formed on the semiconductor substrate 8 as an internal circuit. In other words, it is the same as the semiconductor substrate 1 in FIG. 3 described above, but with the semiconductor substrate 8 replaced. As shown in the circuit diagram of Figure 9, a low-pass filter LPF2 is configured with an inductance component LA1, a resistance component RA1, a capacitor CA1, and a parasitic capacitance Cb0. This low-pass filter LPF2 is provided between the power rails and filters out noise components that are carried on the power rails. This example differs from the first example in that a comparator CMP is provided instead of the operational amplifier OP1, but the rest is the same as that shown in Figure 4 described above. The output of the comparator CMP is a binary logic that outputs either a voltage close to the negative power supply terminal VEE or a voltage close to the positive power supply terminal VCC. If high-frequency noise gets into the comparator and the output logic is reversed, the application in which the comparator is installed will malfunction. For this reason, it is considered that high-frequency noise countermeasures for comparators are more important than for operational amplifiers. In this embodiment, as in the previous embodiments, high frequency noise countermeasures are implemented by forming a printed circuit on the back surface of the semiconductor substrate 8. This has the advantage of reducing the chip area and power consumption.

[0020] (Fourth embodiment) A semiconductor device according to a fourth embodiment of the present invention will be described with reference to Figures 10 and 11. Figure 10 shows a side cross-sectional view of the semiconductor device according to this embodiment, and Figure 11 shows a top view of the device. The circuit configuration is the same as that described in the third embodiment with reference to Figure 9. In this embodiment, the semiconductor substrate 8 of the third embodiment is used as a relay chip, and the internal circuit is monolithically formed inside a general-purpose semiconductor chip 9, with both being vertically stacked as shown in FIG. The semiconductor substrate 8 does not have any active circuits such as amplifiers formed therein and is used solely for relaying, and is therefore the same as the semiconductor substrate 1 in the second embodiment. The internal circuit of the semiconductor chip 9 includes a comparator CMP as shown in Fig. 11. That is, it is the same as Fig. 6 described above, except that the operational amplifier OP1 is replaced with the comparator CMP. In this embodiment, by using the semiconductor substrate 8 as a relay chip, it is possible to provide a countermeasure against high frequency noise in a comparator with a small chip size.

[0021] Although the embodiments of the present invention have been described above, various modifications are possible without departing from the spirit of the present invention. For example, the printed circuit in the above embodiment may be a circuit formed by a plating pattern. In this case, the printed resistor can be replaced with a plated resistor formed as part of the plating pattern. Furthermore, as shown in FIG. 12, a chip resistor 5b can be used instead of the printed resistor or plated resistor. This chip resistor 5b can be mounted simultaneously with the chip capacitor 5a using conductive adhesive 4. In the second and fourth embodiments, the semiconductor substrate and the semiconductor chip may be connected by flip-chip bonding using bumps instead of wire bonding. In the above embodiment, a lead frame is used as a fan-out member to ensure sufficient distance between the external terminals of the semiconductor device and improve mounting reliability, but other fan-out members can also be used. For example, when using a chip carrier or interposer made of an organic substrate, through holes into which mounted components can be inserted may be provided, and the semiconductor substrate may be supported by the periphery of the through holes. In this case, the internal connection portion may be a metal pattern formed on the surface of the substrate, and the external connection portion may be a peripheral electrode obtained by dividing the through hole, or a land, bump, or pin formed on the back surface of the substrate, and these terminals are connected by a wiring pattern. Furthermore, while the above embodiment has been described using a leadless package as an example, the present invention is not limited to this, and packages in which both the front and back surfaces of the outer ends of the leads are exposed to the outside may also be used, such as in-line type leads or gull-wing type leads. In particular, for leads having bent portions formed in the leads, such as gull-wing type leads, the vertical distance between the surface of the inner end of the lead and the back surface of the outer end can be adjusted, and even if the mounted component is large, it can be incorporated into the device by making the vertical distance greater than the mounting height. In the above embodiment, an insulating film made of epoxy resin or the like is used to provide insulation between the semiconductor substrate and the printed circuit, but an insulating layer made of a ceramic substrate may be used instead of the insulating film. The ceramic substrate is attached to the back surface of the semiconductor substrate. When using a high voltage, the insulating layer must be thick, but an insulating layer made of a ceramic substrate can reduce the number of steps compared to an insulating film. Although silicon is assumed to be the material for the semiconductor substrate used in the above embodiment, it goes without saying that other semiconductor materials may also be used. If a semi-insulating substrate or a dielectrically isolated substrate such as SOI is used, the insulating film and ceramic substrate described above are not required. [Explanation of symbols]

[0022] 1,8 Semiconductor substrate 1a, 7a, 8a, 9a Electrode pads 1b,8b Metal wiring 2. Insulating film 3 Printed circuit 4. Conductive adhesive 5a chip capacitor 5b Chip resistor 6 Lead Frame 6a,6b lead 7,9 Semiconductor chips 10 Bonding Wire 11 Molding resin CA1 capacitor, capacitance value Cb0 parasitic capacitance LA1 inductance component, inductance value RA printed resistance RA1 Resistance component of the circuit, resistance value LPF1 Low-pass filter

Claims

1. a semiconductor substrate having a plurality of electrodes formed on a main surface, an internal circuit electrically connected to the plurality of electrodes, and a printed circuit formed on a surface opposite to the main surface; At least one component mounted on the printed circuit; a fan-out member that supports the semiconductor substrate from the back surface side, the fan-out member having a plurality of internal connection parts made of a conductive material and a plurality of external connection parts made of a conductive material that are electrically connected to at least some of the plurality of internal connection parts; a resin that covers the semiconductor substrate, the mounted components, and the fan-out member so that only the external connection portion of the fan-out member is exposed; At least some of the electrodes of the semiconductor substrate are electrically connected to the internal connection portion of the fan-out member; A semiconductor device characterized in that a portion of the printed circuit on the semiconductor substrate is electrically connected to the mounted component, and another portion is electrically connected to the internal connection portion of the fan-out member.

2. the fan-out member comprises a lead frame having a plurality of leads; the internal connection portion is a portion of the lead that is covered with the resin, 2. The semiconductor device according to claim 1, wherein the external connection portion is a portion of the lead that is not covered with the resin.

3. The lead has a bent portion formed therein, 3. The semiconductor device according to claim 2, wherein the bent portion makes the vertical distance between the surface of the inner end portion of the lead and the rear surface of the outer end portion larger than the mounting height of the mounted component.

4. the internal circuit on the semiconductor substrate is a monolithically formed operational amplifier, a parasitic capacitance between power rails that supply power to the operational amplifier; the mounted component is a capacitor, the printed circuit has an inductance component and a resistance component; 2. The semiconductor device according to claim 1, wherein a low-pass filter is formed by the parasitic capacitance of the semiconductor substrate, the printed circuit, and the mounted components.

5. the inductance component and the resistance component of the printed circuit form a series circuit, the series circuit being inserted into the power supply rail, one end of the series circuit being connected to a positive power supply terminal and the other end being connected to one end of the capacitor; the other end of the capacitor is connected to the negative power supply terminal of the power rail; 5. The semiconductor device according to claim 4, wherein when the capacitance value of the capacitor is CA1, the capacitance value of the parasitic capacitance is Cb0, the inductance value of the inductance component is LA1, and the resistance value of the resistance component is RA1, the relationship with the cutoff frequency fc of the low-pass filter satisfies equation (1). [Equation 1]

6. a semiconductor chip is mounted on the main surface of the semiconductor substrate; 6. The semiconductor device according to claim 5, wherein the internal circuit is monolithically formed within the semiconductor chip.

7. 7. The semiconductor device according to claim 1, wherein the printed circuit is replaced with a circuit made of a plating pattern.

8. 7. The semiconductor device according to claim 1, wherein the resistance component is replaced by a resistance part mounted on the printed circuit.

9. 7. The semiconductor device according to claim 4, wherein the operational amplifier is replaced with a comparator.

10. An insulating layer formed by bonding a ceramic substrate to the back surface of the semiconductor substrate is formed, 7. The semiconductor device according to claim 1, wherein the printed circuit is formed on the insulating layer.

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