Semiconductor device

Abstract

To provide a semiconductor device which improves wiring efficiency.SOLUTION: The semiconductor device includes a first die including an element that operates at a first voltage, and a second die including an element that operates at a second voltage lower than the first voltage, wherein the second die includes a wiring layer group including a plurality of stacked wiring layers, a high-voltage signal wiring that is provided in a specific wiring layer among the plurality of wiring layers and through which a signal of the first voltage is transmitted, and a low-voltage signal wiring that is provided in the specific wiring layer and through which a signal of the second voltage is transmitted, and the high-voltage signal wiring is provided linearly along a stacking direction of the wiring layer group.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The multi-die package disclosed in Patent Document 1 includes multiple dies (a first die and a second die). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-510512 Summary of the Invention [Problem to be solved by the invention]

[0004] When a high-voltage power supply is used for the first die and a low-voltage power supply is used for the second die, the high-voltage signals from the first die enter the signal area (wiring area) of the second die and pass from the upper layer to the lower layer that make up the second die. The number of high-voltage signal wirings that transmit high-voltage signals can be several hundred or more. The signal area (wiring area) of the second die also contains multiple low-voltage signal wirings that transmit low-voltage signals lower than the high-voltage signals from the first die. When high-voltage signal wiring is routed in this wiring area using place and route (P&R), the high-voltage signal wiring comes close to the low-voltage signal wiring, which can cause crosstalk between the high-voltage signal wiring and the low-voltage signal wiring. To prevent this, shield wiring is installed between the high-voltage and low-voltage signal wiring within the wiring layer. This requires a larger space between the wiring, which reduces wiring efficiency.

[0005] In view of the above circumstances, the present disclosure has an object to provide a semiconductor device that improves wiring efficiency. [Means for solving the problem]

[0006] In order to solve the above problem, the semiconductor device according to the present disclosure comprises a first die having elements that operate at a first voltage, and a second die having elements that operate at a second voltage that is lower than the first voltage, wherein the second die comprises a wiring layer group including a plurality of stacked wiring layers, and a high-voltage signal wiring that is provided in a specific wiring layer among the plurality of wiring layers and transmits a signal of the first voltage, and a low-voltage signal wiring that is provided in the specific wiring layer and transmits a signal of the second voltage, wherein the high-voltage signal wiring is provided in a straight line along the stacking direction of the wiring layer group. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram of a hardware configuration of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing a specific example of a circuit included in the semiconductor device 100 according to the embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing the cross-sectional structure of the second die 102. As shown in FIG. [Figure 5] FIG. 5 is a diagram showing the cross-sectional structure of the second die 102. As shown in FIG. [Figure 6A] FIG. 6A is a diagram showing wiring and the like provided in the second wiring layer 202 as viewed in a plane in the direction D1. [Figure 6B] FIG. 6B is a diagram showing the wiring and the like provided in the second wiring layer 202 as viewed in a plane in the direction D1. [Figure 7] FIG. 7 is a diagram for explaining a configuration example of a comparative example. [Figure 8] FIG. 8 is a diagram for explaining a configuration example of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0009] (Embodiment) FIG. 1 is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram of a hardware configuration of the semiconductor device 100 according to an embodiment of the present disclosure. FIG. 3 is a diagram showing a specific example of a circuit included in the semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a first die (DIE) 101 and a second die 102. The second die 102 is connected to the first die 101 via a plurality of signal lines SW and a plurality of buses (BUS). The first die 101 may be interpreted as a core die, and the second die 102 may be interpreted as a custom die. Each of the first die 101 and the second die 102 may be interpreted as a chiplet of a multi-chip package.

[0010] (1st die 101) 3, the first die 101 may include a bus 24 and a bus master 25. The bus master 25 may be interpreted as a CPU. The bus master 25 may receive or transmit signals for data to and from the second die 102.

[0011] (Bus 24) The bus 24 may transmit a signal of the data transmitted from the second die 102 to the bus master 25 .

[0012] (Second die 102) The second die 102 may include a bus 12 , a level shifter 13 , and a plurality of circuits 6 .

[0013] (Bus 12) The bus 12 may transmit a signal of the data transmitted from the first die 101 to the circuit 6. The bus 12 may transmit a signal of the data transmitted from the circuit 6 to the level shifter 13.

[0014] (Level Shifter 13) The level shifter 13 may convert the voltage level of the data signal transmitted from the first die 101 to a voltage level that can be handled by the second die 102 and transmit it to the bus 12. The level shifter 13 may convert the voltage level of the data signal transmitted from the bus 12 to a voltage level that can be handled by the first die 101 and transmit it.

[0015] Next, the cross-sectional structure of the second die 102 will be described with reference to Figures 4 to 6. Figures 4 and 5 are diagrams showing the cross-sectional structure of the second die 102.

[0016] The first die 101 is disposed so as to overlap the second die 102. For convenience of explanation, in FIG. 4, the first die 101 is disposed at a certain distance from the second die 102. The power supply voltage of the first die 101 may be interpreted as being higher than the power supply voltage of the second die 102. The operating voltage (first voltage) of the LV (Low Voltage) element of the first die 101 is higher than the operating voltage (second voltage) of the LV element of the second die 102. If the LV element of the first die 101 were directly connected to the LV element of the second die 102, the LV element of the second die 102 would be degraded or destroyed due to the voltage difference. Therefore, the LV element of the first die 101 cannot be directly connected to the LV element of the second die 102. Therefore, the LV element of the first die 101 must be connected to the second die 102 via the HV (High Voltage) element of the second die 102. The HV element of the second die 102 may be interpreted as an element to which a first voltage can be applied. In this disclosure, for convenience of explanation, an example configuration of a semiconductor device 100 including an LV element and an HV element is described, but the semiconductor device 100 may also include elements other than an LV element and an HV element (for example, an MV (Middle Voltage) element).

[0017] 4, the semiconductor device 100 of the present disclosure is characterized by the shapes of the wiring provided in the multiple wiring layers constituting the second die 102. Specifically, the semiconductor device 100 may include a wiring layer group 200, a first wiring 4, a second wiring 5, and a shield wiring 7 provided in a specific wiring layer. The first wiring 4 and the second wiring 5 may be interpreted as high-voltage signal wiring 3.

[0018] (wiring layer group 200) The wiring layer group 200 may include a plurality of wiring layers M1 to M9 stacked in the direction (direction D1) in which the second die 102 and the first die 101 are stacked. The plurality of wiring layers M1 to M9 may be interpreted as metal layers. For example, as disclosed in Japanese Patent Application Laid-Open No. 2001-339048, an interlayer insulating film may be provided between each of the plurality of wiring layers M1 to M9. The configuration of the wiring layer group 200 is well known, and therefore a detailed description thereof will be omitted.

[0019] The multiple wiring layers M1 to M9 are stacked in the following order in the direction D1: wiring layer M1, wiring layer M2, wiring layer M3, wiring layer M4, wiring layer M5, wiring layer M6, wiring layer M7, wiring layer M8, and wiring layer M9. The wiring layers M7, M8, and M9 may be interpreted as a first wiring layer 201. The wiring layers M3, M4, M5, and M6 may be interpreted as a second wiring layer 202. The wiring layer M1 and M2 may be interpreted as a third wiring layer 203. A polysilicon layer POLY may be provided below the third wiring layer 203. The second wiring layer 202 may be interpreted as a specific wiring layer of the present disclosure. Note that the second die 102 may include wiring layers other than the first wiring layer 201, the second wiring layer 202, and the third wiring layer 203, and the number of these wiring layers is not limited to the illustrated example and may be increased or decreased.

[0020] The first wiring layer 201 may be interpreted as a layer through which a signal of a first voltage is transmitted from the second die 102. The first wiring layer 201 may be provided with power supply wiring that supplies power to a plurality of functional blocks.

[0021] The second wiring layer 202 may be interpreted as a layer for coupling multiple functional blocks. Specifically, the second wiring layer 202 may be interpreted as a layer through which a signal of a first voltage and a signal of a second voltage lower than the first voltage from the second die 102 are transmitted. As shown in FIGS. 6A and 6B , the wiring layer M6 of the second wiring layer 202 includes a high-voltage signal wiring 3 (first wiring 4, second wiring 5), a shield wiring 7, and multiple low-voltage signal wirings 10 for coupling multiple functional blocks. The shape of the shield wiring 7 in a plan view in the direction D1 may be a ring surrounding the high-voltage signal wiring 3 as shown in FIG. 6A or a C-shape with a part of the circle cut off as shown in FIG. 6B. A high-voltage signal (a signal of a first voltage) is transmitted to the high-voltage signal wiring 3, and a low-voltage signal (a signal of a second voltage) lower than the first voltage is transmitted to the low-voltage signal wiring 10. The shield wiring 7 may be provided in each of the wiring layers M3, M4, M5, and M6 that form the second wiring layer 202 so as to surround the periphery of the high-voltage signal wiring 3.

[0022] The third wiring layer 203 may be interpreted as a layer in which a plurality of functional blocks (such as level shifters) are provided. Specifically, the third wiring layer 203 may be interpreted as a layer in which a circuit that converts a signal of a first voltage into a signal of a second voltage, a circuit that converts a signal of the second voltage into a signal of the first voltage, and the like are provided. An HV element may be provided in the polysilicon layer POLY. Hereinafter, each of the wiring layer M1, wiring layer M2, wiring layer M3, wiring layer M4, wiring layer M5, wiring layer M6, wiring layer M7, wiring layer M8, and wiring layer M9 may be simply referred to as a wiring layer.

[0023] The first wiring 4 may be interpreted as a pattern wiring extending from the first end 1 of each wiring layer toward the second end 2. The first wiring 4 may be interpreted as a wiring for transmitting signals.

[0024] The second wiring 5 may be connected to the first wiring 4. The second wiring 5 may be interpreted as a pattern wiring provided adjacent to the first wiring 4 in the direction D1. Like the first wiring 4, the second wiring 5 may be interpreted as a wiring for transmitting signals.

[0025] The first wiring 4 and the second wiring 5 may be linearly arranged along the direction D1. Specifically, among the multiple wiring layers provided on the second die 102, the first wiring 4 and the second wiring 5 provided in the first wiring layer 201 may be linearly arranged along the direction D1 with the first wiring 4 and the second wiring 5 provided in the second wiring layer 202 and the third wiring layer 203 other than the first wiring layer 201 among the multiple wiring layers. Adjacent first wirings 4 may be linearly arranged along the direction D1. Adjacent second wirings 5 ​​may be linearly arranged along the direction D1.

[0026] The term "linear" encompasses not only a geometrically strict straight line but also an arrangement of points that can be considered to be approximately linear. For example, as shown in FIG. 5, even if the center position of the first wiring 4 is slightly offset from the center position of the second wiring 5 in direction D2, the first wiring 4 and the second wiring 5 may be considered to be linearly arranged. In direction D3 (depth direction of the second die 102) perpendicular to directions D1 and D2, even if the center position of the first wiring 4 is slightly offset from the center position of the second wiring 5 in direction D2, the first wiring 4 and the second wiring 5 may be considered to be linearly arranged.

[0027] The shield wiring 7 may be provided in some of the wiring layers among the multiple wiring layers. Specifically, the first wiring layer 201 and the third wiring layer 203 provided in the second die 102 may not be provided with the shield wiring 7, but the second wiring layer 202 provided in the second die 102 may be provided with the shield wiring 7. As described above, a high-voltage signal (signal of a first voltage) from the first die 101 is transmitted to the high-voltage signal wiring 3 of the second wiring layer 202, and a low-voltage signal (signal of a second voltage) lower than the first voltage is transmitted to the multiple low-voltage signal wirings 10 of the second wiring layer 202. By providing the shield wiring 7, crosstalk caused by a potential difference between the first voltage and the second voltage, i.e., an effect on the low-voltage signal wiring 10 through which a signal of the second voltage is transmitted, can be suppressed. Furthermore, the amount of shield wiring 7 can be reduced compared to when the shield wiring 7 is provided in all wiring layers including the first wiring layer 201 and the third wiring layer 203.

[0028] In the present disclosure, the shield wiring 7 is provided only in the second wiring layer 202, but the shield wiring 7 may also be provided in other layers besides the second wiring layer 202, such as the first wiring layer 201 and the third wiring layer 203.

[0029] In the present disclosure, the second die 102 is provided with the first wiring 4 and the second wiring 5 on the signal input side, and the first wiring 4 and the second wiring 5 on the signal output side.

[0030] 7 and 8 are diagrams for explaining a configuration example of the comparative example. As shown in Fig. 7, a high-voltage signal wiring 3A is wired in a P&R manner on the wiring layer M6 of the second die 102A according to the comparative example, and a plurality of low-voltage signal wirings 10 are provided around the high-voltage signal wiring 3A. When the high-voltage signal wiring 3A is wired in a P&R manner, the high-voltage signal wiring 3A comes closer to the plurality of low-voltage signal wirings 10 in an increased area. Therefore, when a high first voltage is applied to the high-voltage signal wiring 3A, crosstalk due to coupling capacitance C is more likely to occur between the low-voltage signal wiring 10 and the high-voltage signal wiring 3A.

[0031] 8, if multiple shield wirings 40 for preventing crosstalk are provided between the low-voltage signal wiring 10 and the high-voltage signal wiring 3A, an extra mounting area is required, which reduces the wiring efficiency of the second die 102B. Furthermore, if the high-voltage signal wiring 3A is wired using P&R, the wiring distance becomes longer, which increases power consumption accordingly.

[0032] In the semiconductor device 100 of the present disclosure, the high-voltage signal wiring 3 is linearly arranged along the direction D1 as shown in FIG. 4 . This configuration prevents the high-voltage signal wiring 3 from being spread out in the planar directions (directions D2 and D3). Therefore, even if the low-voltage signal wiring 10 is arranged around the high-voltage signal wiring 3 when viewed in the D1 direction, the distance between the high-voltage signal wiring 3 and the low-voltage signal wiring 10 is not so close that crosstalk occurs in some parts of the high-voltage signal wiring 3. In other words, when the high-voltage signal wiring 3 is wired in a P&R manner on the second wiring layer 202, it is not necessary to design the distance between the high-voltage signal wiring 3 and the low-voltage signal wiring 10 to a distance that does not cause crosstalk, or to provide a shield between the high-voltage signal wiring 3 and the low-voltage signal wiring 10, taking into consideration the position where the high-voltage signal wiring 3 is closest to the low-voltage signal wiring 10. This eliminates the need for an extra mounting area, and reduces the reduction in wiring efficiency and power consumption.

[0033] By providing the shield wiring 7 surrounding the high-voltage signal wiring 3 in the second wiring layer 202, which is a specific wiring layer of the present disclosure, the influence of crosstalk is further reduced, and therefore the distance between the high-voltage signal wiring 3 and the low-voltage signal wiring 10 can be narrowed.

[0034] In addition, the following supplementary notes are provided in relation to the above description.

[0035] (Appendix 1) a first die having elements operating at a first voltage; a second die having elements operating at a second voltage lower than the first voltage; Equipped with The second die is a wiring layer group including a plurality of stacked wiring layers; a high-voltage signal wiring provided in a specific wiring layer among a plurality of wiring layers, through which a signal of the first voltage is transmitted; a low-voltage signal wiring provided in the specific wiring layer and through which a signal of the second voltage is transmitted; Including, The high-voltage signal wiring is provided linearly along the stacking direction of the wiring layer group.

[0036] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the specific wiring layer includes a shield wiring that surrounds a high-voltage signal wiring.

[0037] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the shield wiring has a ring shape.

[0038] (Appendix 4) 3. The semiconductor device according to claim 2, wherein the shield wiring has a C-shape with a portion of a circle cut off.

[0039] (Appendix 5) 2. The semiconductor device according to claim 1, wherein the specific wiring layer is provided between a layer through which a signal of the first voltage from the first die is transmitted and a layer including a circuit that converts a signal of the first voltage to a signal of the second voltage or a signal of the second voltage to a signal of the first voltage. [Explanation of symbols]

[0040] 1 First end 2 Second end 3 High voltage signal wiring 3A high voltage signal wiring 4 1st wiring 5 2nd wiring 6 circuits 7 Shielded wiring 10 Low voltage signal wiring 12 Bus 13 Level Shifter 24 Bus 25 Bus Master 30 Wiring 40 Shielded wiring 100 Semiconductor device 101 First Die 102 Second Die 102A Second Die 102B 2nd die 200 Wiring Layers 201 Wiring layer 202 Wiring layer 203 Wiring layer

Claims

1. a first die having elements operating at a first voltage; a second die having elements operating at a second voltage lower than the first voltage; Equipped with The second die is a wiring layer group including a plurality of stacked wiring layers; a high-voltage signal wiring provided in a specific wiring layer among a plurality of wiring layers, through which a signal of the first voltage is transmitted; a low-voltage signal wiring provided in the specific wiring layer and through which a signal of the second voltage is transmitted; Including, The high-voltage signal wiring is provided linearly along the stacking direction of the wiring layer group.

2. 2. The semiconductor device according to claim 1, wherein said specific wiring layer includes a shield wiring surrounding a high-voltage signal wiring.

3. The semiconductor device according to claim 2 , wherein the shield wiring has a ring shape.

4. 3. The semiconductor device according to claim 2, wherein the shield wiring has a C-shape with a part of the circle cut off.

5. 2. The semiconductor device according to claim 1, wherein the specific wiring layer is provided between a layer through which a signal of the first voltage from the first die is transmitted and a layer including a circuit that converts a signal of the first voltage to a signal of the second voltage or a signal of the second voltage to a signal of the first voltage.

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