Programmable logic device and FPGA using the same

Abstract

To provide a programmable logic circuit capable of performing advanced control while securing area efficiency and flexibility.SOLUTION: The FPGA and the logic block 10 of the FPGA using the programmable logic circuit have a plurality of lanes 11 and 12 sequentially connected in a direction in which an input signal of the programmable logic circuit flows, each of the plurality of lanes has one or two or more logic cells 13, an input signal to the lane is input to each logic cell through input side selector circuits 16 and 17 which can be program-controlled, and an output signal from each logic cell is output as an input signal to the next sequential lane connected to the lane or / and output as an output signal of the programmable logic circuit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a programmable logic circuit device suitable for incorporation into an application specific integrated circuit (ASIC) such as an SoC, and to an FPGA using this programmable logic circuit. [Background technology]

[0002] There are IC products called ASICs (Application Specific Integrated Circuits) that are custom designed, manufactured, and provided for specific applications. ASICs are semiconductor integrated circuits that are designed and manufactured to combine the necessary logic functions for a specific device or application, but the logic functions installed cannot be changed after manufacturing.

[0003] However, in recent years, as ASICs have become larger and more expensive, there have been an increasing number of cases where logic needs to be modified due to defects discovered after manufacturing, or new functions need to be added. Therefore, a method has been adopted in which programmable logic circuit blocks such as FPGA (Field Programmable Gate Array) devices are installed in ASICs, making it possible to fix defects and add functions. Here, the FPGA portion installed in ASICs is called "embedded FPGA (eFPGA)."

[0004] The logic cells of eFPGAs use LUTs (Look-Up Tables), which directly represent truth tables. While standard FPGAs not designed for ASICs use SRAM for the memory used in LUTs, it is not easy to design large amounts of small SRAM memory in ASICs. For this reason, eFPGAs within ASICs use FFs (Flip-Flops). However, FFs generally require several times (e.g., 6 to 10 times) the area of ​​SRAM. Furthermore, when using a multi-output LUT (e.g., a 4-input, 3-output LUT), FFs are attached to all outputs (a total of three for a 4-input, 3-output LUT). As a result, the area of ​​a logic cell capable of implementing the same amount of logic in an eFPGA is several times larger than that of a standard FPGA. This poses certain problems in terms of implementation logic density.

[0005] In addition, the wiring and connection structure of eFPGAs, known as the island style, consists of programmable logic blocks (LBs) arranged in a grid, with the grid-like logic blocks connected by connection boxes (CBs) and switch boxes (SBs). Each logic block contains multiple logic cells, which are interconnected by local connection blocks (LCBs). While logic cells within a logic block typically have M-output, N-input look-up tables (LUTs), most LCB connections use a "full crossbar" connection, connecting the outputs of all logic cells to the inputs of all logic cells. This requires a large number of multiplexers and configuration memories for wiring switching. This is another reason why the logic density of eFPGAs cannot be increased. Summary of the Invention [Problem to be solved by the invention]

[0006] As explained above, conventional eFPGAs face the challenge of improving the implementation logic density, and there is a demand for programmable logic circuits with new structures that can solve this problem.

[0007] The present invention has been made in view of the above circumstances, and aims to provide a programmable logic circuit with a novel structure that can solve the above-mentioned problems, an FPGA that uses this programmable logic circuit, and a logic block of the FPGA. [Means for solving the problem]

[0008] In order to solve the above problems, the inventors of the present invention came up with the idea that by focusing on the structure of a netlist, which is a representation format of the logic circuit to be implemented, it would be possible to provide a wiring architecture that is different from conventional ones, and completed the programmable logic circuit of the present invention, as well as an FPGA and a logic block of an FPGA that uses this programmable logic circuit.

[0009] According to the present invention, the following inventions are provided.

[0010] (1) A programmable logic circuit, The programmable logic circuit has a plurality of lanes connected sequentially in a direction in which an input signal of the programmable logic circuit flows, Each of the plurality of lanes has one or more logic cells, and an input signal to the lane is input to each logic cell through a programmable input side selector circuit, and an output signal from each logic cell is output as an input signal to the next sequential lane connected to the lane and / or as an output signal of the programmable logic circuit, The logic cell comprises: having basic logic cells that constitute nodes of a gate-level netlist; This basic logic cell is a programmable circuit that is configured by adding a programmable NOT circuit to the input and output of a basic logic operation element. 1. A programmable logic circuit comprising: (2) In the programmable logic circuit according to (1), The input signals of each lane include the input signals of this programmable logic circuit. 1. A programmable logic circuit comprising: (3) In the programmable logic circuit according to (2), At least one of the lanes receives an input signal of the programmable logic circuit from the preceding sequential lane to which it is connected. 1. A programmable logic circuit comprising: (4) In the programmable logic circuit according to (1), At least one of the lanes has a wiring that feeds back an output signal from the logic cell to the preceding sequential lane to which the lane is connected or as an input signal to the lane. 1. A programmable logic circuit comprising: (5) In the programmable logic circuit according to (1), At least one of the lanes has a wiring that feeds forward an output signal from the logic cell as an input signal to a subsequent lane after the lane to which it is connected. 1. A programmable logic circuit comprising: (6) In the programmable logic circuit according to (1), At least one of the lanes has a wiring that skips and outputs an output signal from a logic cell as an input signal to another programmable logic circuit. 1. A programmable logic circuit comprising: (7) In the programmable logic circuit according to (1), Each lane is The nodes constituting the netlist at the logic cell level are mapped to each logic cell provided in each lane according to the hierarchy along the direction from the input side to the output side on the netlist. 1. A programmable logic circuit comprising: (8) In the programmable logic circuit according to (7), The node mapping is performed on each logic cell provided in each lane according to the sequential number of connections of the lane in the programmable logic circuit. 1. A programmable logic circuit comprising: (9) In the programmable logic circuit according to (1), A flip-flop (FF) is provided on the output side of the logic cell provided in each lane. 1. A programmable logic circuit comprising: (10) In the programmable logic circuit according to (1), An output selector circuit is provided on the output side of the logic cell previously provided in each lane. 1. A programmable logic circuit comprising: (11) In the programmable logic circuit according to (1), The logic cell comprises: The input / output of the basic logic cell is programmable to be switched depending on the connection relationship of the nodes in the netlist. 1. A programmable logic circuit comprising: (12) In the programmable logic circuit according to (11), The logic cell comprises: a combinational logic cell formed by combining a plurality of the basic logic cells; This combinational logic cell has a plurality of basic logic cells that cover a plurality of nodes that make up the graph of the netlist. 1. A programmable logic circuit comprising: (13) In the programmable logic circuit according to (12), When the number of basic logic cells to be combined is n, an integer of 2 or more, and the number of inputs of each basic logic cell is m, an integer of 2 or more, The combinational logic cell comprises: It is an (m-1) x n+1 input n output logic cell in which n basic logic cells are connected by switching input signals in order to express two or more patterns of node connection. 1. A programmable logic circuit comprising: (14) In the programmable logic circuit according to (12), the combinational logic cell has a plurality of outputs; one or more selectors each configured to receive at least two or more output signals from the combinational logic cell and to output a selected signal; a flip-flop (FF) provided to receive the output signal from the selector; 1. A programmable logic circuit comprising: (15) The basic logic element according to (14), The one or more selectors are further configured to receive a constant signal. Programmable logic circuits. (16) The programmable logic circuit according to (1), This programmable logic circuit is the logic block of the FPGA. 1. A programmable logic circuit comprising: (17) An FPGA in which the programmable logic circuit described in (1) above is implemented as a logic block. (18) A programmable logic circuit implemented in a logic block (LB) that constitutes an FPGA. This programmable logic circuit is a combinational logic cell (PAE) which is formed by combining a plurality of basic logic cells (PAs) and is programmed to switch inputs and outputs of the basic logic cells in accordance with the connection relationships of the nodes in a netlist, and which outputs a plurality of output signals; one or more selectors each configured to receive at least two or more output signals from the combinational logic cell and to output a selected signal; a flip-flop (FF) provided to receive the output signal from the selector; A programmable logic circuit having:

[0011] With this configuration, nodes on the netlist (nodes that configure the netlist according to the number of levels along the flow direction from the input side to the output side) can be mapped to each logic cell provided in multiple lanes according to the number of levels of the lane. This eliminates the need for a "full crossbar connection" that connects the outputs of all logic cells provided in the programmable logic circuit to the inputs of all logic cells, thereby reducing the amount of setting memory required for the program.

[0012] Other aspects of the present invention and other configurations will be described in the following embodiments and shown in the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] Figure 1 is a schematic diagram showing the routing architecture of an island-style FPGA.

[0014] [Figure 2] FIG. 2 is a schematic diagram showing a logic cell having a fully crossbar-connected LCB.

[0015] [Figure 3] FIG. 3 is a schematic diagram showing a netlist of a logic cell.

[0016] [Figure 4] FIG. 4 is a schematic diagram showing a logic cell according to one embodiment of the present invention.

[0017] [Figure 5] FIG. 5 is an explanatory diagram showing the mapping of logic cells.

[0018] [Figure 6] FIG. 6 is a schematic diagram showing lanes in a logic cell according to a first modification of the embodiment.

[0019] [Figure 7] FIG. 7 is a schematic diagram showing a logic cell according to the first modification.

[0020] [Figure 8] FIG. 8 is a schematic diagram showing a logic cell according to the first modification.

[0021] [Figure 9] FIG. 9 is a schematic diagram showing a logic cell according to a second modification of the embodiment.

[0022] [Figure 10] FIG. 10 is a schematic diagram showing the configuration of a PAE.

[0023] [Figure 11] Figure 11 is a schematic diagram that also explains the technology mapping of PAE.

[0024] [Figure 12] Figure 12 is a schematic diagram that also explains the technology mapping of PAE.

[0025] [Figure 13] FIG. 13 is a schematic diagram showing the configuration of a PAE.

[0026] [Figure 14] FIG. 14 is a schematic diagram showing a modified example of the PAE.

[0027] [Figure 15] FIG. 15 is a schematic diagram showing a modified example of the PAE.

[0028] [Figure 16] FIG. 16 is a schematic diagram showing a modified example of the PAE.

[0029] [Figure 17] FIG. 17 is a schematic diagram showing a modified example of the PAE.

[0030] [Figure 18] FIG. 18 is a schematic diagram showing a modified example of the logic cell.

[0031] [Figure 19] FIG. 19 is a schematic diagram showing a modified example of the logic cell.

[0032] [Figure 20] FIG. 20 is a schematic diagram showing a modified example of the wiring of the logic cell.

[0033] [Figure 21] FIG. 21 is a schematic diagram showing a modified example of the wiring of the logic cell.

[0034] [Figure 22] FIG. 22 is a schematic diagram showing a modified example of the wiring of the logic cell.

[0035] [Figure 23] FIG. 23 is a schematic diagram showing a modified example of the wiring of the logic cell.

[0036] [Figure 24] FIG. 24 is a schematic diagram showing a modified example of the wiring of the logic cell.

[0037] [Figure 25] FIG. 25 is a schematic diagram showing a modified example of the wiring of the logic cell.

[0038] [Figure 26] FIG. 26 is a schematic diagram showing a modified example of the wiring of the logic cell. DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0040] First, the basic concept of the present invention will be explained while comparing it with a conventional configuration.

[0041] (Basic concept) As mentioned above, the full crossbar connection of logic cells within a conventional LCB was primarily intended for LUTs with interchangeable inputs, and while it provided a high degree of freedom in wiring, it required an extra number of wires and configuration memories to switch between them, which limited the reduction in packaging density.

[0042] In response to this, the inventors came up with the idea that by considering the flow of signals from input to output in the netlist, it is possible to significantly reduce the number of wires and configuration memories compared to the conventional full crossbar connection, and thus completed this invention.

[0043] (Island-style FPGA routing architecture) FIG. 1 is a schematic diagram showing a conventional island-style FPGA 1, and FIG. 2 is a conceptual diagram showing the wiring architecture within a logic block 2 arranged in this FPGA 1.

[0044] In this island-style FPGA 1, as shown in Figure 1, logic blocks (LB) 2 are arranged in a two-dimensional matrix, and these logic blocks 2 are connected via programmable wiring such as switch blocks (SB) 3 and connection blocks (CB) 4. As shown in Figure 2, each logic block 2 has multiple 4-input LUTs (look-up tables) 5 as logic cells, and these multiple LUTs 5 are locally interconnected through a crossbar connection using local connection blocks (LCB) 6. This crossbar connection adopts a wiring architecture that connects all outputs of any LUT 5 to all inputs of any logic cell, taking into account flexibility in logic circuit design. For this reason, it is called a "full crossbar connection."

[0045] In the case of this full crossbar connection, the number of configuration memories required for wiring within logic block 2 is calculated as follows: For example, if the LUT (logic cell) 5 implemented in this logic block is a 4-input, 3-output LUT, and four of these 4-input, 3-output LUTs are fully crossbar connected in parallel, the number of outputs of LCB 6 providing this full crossbar connection will be 16 (= 4 inputs x 4), a total for the four logic cells, since each logic cell has four inputs. On the other hand, the number of inputs will be 22, consisting of 10 inputs from outside and 12 feedback lines (= 3 x 4) from each logic cell.

[0046] Therefore, in the case of LCB6, the number of configuration memories required to switch the internal wiring of logic block 2 is calculated using the following formula, which is 80 bits.

[0047] 4×4×ceil(log2(22))=16×5=80bit Also, in the case of a 22-input, 16-output LCB6, there are 16 22-input, 1-output multiplexers (MUX), which means that 16 sets of 21 2-input, 1-output (2-to-1) multiplexers are required. Therefore, this LCB6 requires a total of 336 (=21 x 16) 2-input, 1-output multiplexers.

[0048] (The wiring architecture of the present invention) In contrast to the conventional wiring architecture using LCB6 as described above, the present invention focuses on netlists and provides a new wiring architecture that takes into account the signal flow from input to output that is generally considered in netlists.

[0049] In Figure 3, the reference numeral 8 denotes a netlist in which a gate-level netlist is replaced with a 4-input, 3-output logic cell during logic synthesis. In such a netlist 8, signals resulting from calculations generally flow from inputs (i0 to i8) to outputs (P0[0] to P0[2]). Therefore, when designing a wiring architecture based on such a netlist 8, it is not necessary to connect all outputs of any logic cell to all inputs of any logic cell, as in a full crossbar connection.

[0050] Based on this knowledge, the logic blocks in the FPGA of this invention do not connect all logic cells in a full crossbar configuration, but rather use a group of multiple logic cells (lane) as the basic unit, arrange multiple lanes in order, and provide a wiring architecture that prioritizes connecting the outputs and inputs between adjacent lanes.

[0051] 4 shows a logic block 10 of an FPGA according to a first embodiment of the present invention. This logic block 10 has first lanes 11 (order level 1) connected sequentially from the input side to the output side of the logic block 10, and second lanes 12 (order level 2) arranged on the output side. In this logic block 10, four logic cells 13 are implemented, two in each of the first lanes 11 and two in each of the second lanes 12.

[0052] Ten external input signals 14 are provided to this logic block 10, and four of the ten external input signals are selected by an input selector circuit (MUX: multiplexer) 16 and input to each logic cell 13 provided in the first lane 11. In addition to the ten external input signals, a total of six internal input signals output from each logic cell 13 in the first lane 11 are selected by an input selector circuit (MUX) 17 and four input signals are input to each logic cell 13 provided in the second lane 12.

[0053] The output signals 15 of this logic block 10 are output via output selector circuits 18, 19 provided on the output side of each logic cell 13, and the number of signals is 12 in total: 6 signals from the first lane 11 and 6 signals from the second lane 12.

[0054] Although not shown in this figure, additional wiring can be provided. For example, wiring (skip wiring) that skip connects specific wiring of the first lane 11 to other wiring blocks may be provided through optional flip-flops (FFs) as needed. Also, the output of the logic cell 13 in the lane can be routed through FFs 21 and 22 as shown in this example. In this case, output selector circuits (MUX) 18 and 19 can be added to suppress output signals that would increase the amount of wiring.

[0055] Furthermore, although not shown in this figure, it is also possible to eliminate unnecessary wiring. For example, each input selector circuit 17 of each logic cell 13 in the second lane 12 can eliminate some of the 10 external input signals and some of the 6 signals from the first lane 11, allowing selection from fewer wiring.

[0056] In the case of this logic block 10, the required number of configuration memories is calculated as follows:

[0057] That is, of the four 4-input 3-output logic cells 13 implemented in this logic block 10, two logic cells 13 are arranged in the first lane 11 and two logic cells 13 are arranged in the second lane 12. In this case, the number of configuration memories for selecting the input signals of each logic cell 13 in the first lane 11 is calculated by the following formula and is 32 bits.

[0058] 4×2×ceil(log2(10))=8×4=32 Next, the number of configuration memories for selecting the input signals of each logic cell 13 in the second lane 12 is 32 bits, as calculated by the following formula since the number of inputs is 16.

[0059] 4×2×ceil(log2(16))=8×4=32 Therefore, the total number of configuration memories required to switch the internal wiring of this logic block is 64 bits (= 32 + 32), which is a 20 percent reduction in the number of configuration memories compared to 80 bits for a full crossbar connection.

[0060] In this connection architecture, each of the two logic cells 13 in the first lane has four 10-input input multiplexers, for a total of eight. When this is converted into two-input, one-output (2-to-1) multiplexers, the number is 10-1=9, so the total number of two-input, one-output multiplexers in the first lane is 2x4x9=72.

[0061] Next, if we calculate similarly for the second lane, we find that there are eight 16-input multiplexers, which are equivalent to 15 two-input, one-output multiplexers, so the number of two-input, one-output multiplexers in the second lane is 8 x 15 = 120.

[0062] This means that a total of 192 (=72+120) multiplexers are required in this logic block.

[0063] Therefore, the size of the multiplexers can be reduced by at least 43% compared to the conventional 336 multiplexers.

[0064] (Netlist-based clustering) Next, a method for clustering a netlist using the logic block (considered as one cluster) of this invention will be explained using as an example a netlist 8 using a 4-input, 3-output logic cell shown in Fig. 3. In the following, the first lane 11 and the second lane 12 may be referred to as degree level 1, degree level 2, and degree level N, respectively, depending on the hierarchy (depth) of the netlist.

[0065] First, the logic block 10 of this first embodiment is described under the following conditions for the purpose of clustering.

[0066] Number of logical cells in a cluster = 4 Number of lanes in the cluster (lane order) = 2 Maximum number of input signals: 10 Maximum number of logic cells in the first lane (level 1) = 2 Maximum number of logic cells in the second lane (level 2) = 2 In the clustering, among the nodes constituting the netlist (black circles in the netlist in FIG. 3), nodes that satisfy the above conditions, that is, logic cells 13, are identified as candidates for clustering.

[0067] First, in step 1, the degree of the lanes in the logic block 10 is determined. In this embodiment, the degree is "2" because it consists of degree level 1 and degree level 2. If the degree is "2", this logic block 10 can be mapped to cover two specific hierarchical levels of the netlist. Note that mapping within one hierarchical level is also possible.

[0068] Next, in step 2, starting from the hierarchy located closest to the input side of the netlist, a combination of logic cells (nodes) that satisfy the above level conditions is selected.The selected candidates are then added to the selection candidate list as candidate logic cells.

[0069] Furthermore, in step 3, clustering is performed by finally selecting a logical cell that satisfies all other conditions from the combination of logical cells added to the selection candidates, and finally, in step 4, the selected (clustered) logical cell is deleted from the candidates.

[0070] Then, repeat steps 2 to 4 above to fill each cluster with the maximum number of logical cells according to the above conditions. When the process can no longer proceed, start clustering again from step 1 for the unmapped nodes.

[0071] In the case of the above example netlist, it can be clustered into two logical clusters as shown by C1 and C2 in Fig. 5. These clusters C1 and C2 each correspond to the above logical block 10.

[0072] As a result, when a specific netlist is mapped using the logic block 10 of this embodiment, the area of ​​the selector circuit used for the internal wiring of the logic block 10 can be reduced by at least 43%, and the number of memory components of the selector circuit used for the internal wiring can be reduced by at least 20%, compared to when the same number of logic cells are mapped using the logic block 2 having the conventional full crossbar-connected LCBs 6.

[0073] This configuration provides a programmable logic circuit with a novel structure that solves the problem of improving the packaging logic density that existed in conventional eFPGAs, as well as an FPGA and a logic block of the FPGA that use this programmable logic circuit. Note that when configuring an FPGA using the logic block 10 of the above embodiment, the configuration is achieved by replacing the logic block 2 shown in Figure 1 with the logic block 10 of this embodiment, but the wiring scheme and number of wires between the logic blocks are not limited to those shown in Figure 1.

[0074] (Variation 1) The logic block 10 in the above embodiment has two lanes 11 and 12 and a total of four logic cells 13, two of which are distributed in each lane, but this is not limited to this. It is possible to customize the lane order, the number of logic cells 13 in a lane, the number of inputs and input signals of the selector circuits 16 and 17, depending on the target netlist.

[0075] In other words, in the present invention, the total number of inputs and outputs, the number of logic cells 13, the number of inputs and connection methods of the input selector circuits 16 and 17, the number of output selector circuits 18 and 19, the number of inputs and connection methods of the output selector circuits 18 and 19, the lanes to which they are connected, and whether or not output flip-flops (FFs) 21 and 22 are included are not limited to those in the above embodiment.

[0076] 6, four logic cells are arranged in one lane 23. Also, in this example, one output selector circuit 18 is shared between two output terminals of the logic cell 13. Furthermore, in this example, wiring and a signal selector 25 (multiplexer) are provided to extract a signal to be skipped (a signal going to a lane other than the next lane).

[0077] The two signal selectors 25 shown in this diagram connect the output of the logic cell 13 in this lane 23 to the input selector circuits of lanes other than the next lane. For example, it can be connected to the input selector circuit X of the logic cell of the lane before the nth degree level (including itself (n=0)) (feedback wiring), or it can be connected to the input selector circuit of the lane after the mth degree level (feedforward wiring). Also, although this diagram shows two skip signal selectors 25, the number and how the inputs are connected can be freely set. Also, in this figure, a portion of all outputs of the logic cells in the lane (total 3x4=12) are thinned out and connected to the output selector 25, but the method of thinning out is not limited to this, and it is also possible to connect all outputs.

[0078] In the example of Figure 6, four logic cells are arranged in parallel, just like the conventional example of crossbar connection shown in Figure 2. For convenience, the number of configuration memories required in this example can be calculated as follows:

[0079] That is, four 4-input, 3-output logic cells 13 are implemented in this lane 23. In this case, the number of configuration memories for selecting the input signals of each logic cell 13 in the first lane 23 is calculated by the following formula, assuming that the number of inputs to the input multiplexer is 16, and is 64 bits.

[0080] 4×4×ceil(log2(16))=16×4=64 In addition, in this configuration, each of the four logic cells 13 in the first lane has four 10-input input multiplexers, for a total of 16. If this is converted into 2-input 1-output (2-to-1) multiplexers, the number is 10-1=9, so the total number of 2-input 1-output multiplexers in the first lane is 4x4x9=144.

[0081] On the other hand, in this example, as described above, one output selector circuit 18 is shared between two output terminals of logic cell 13. Also, one output selector circuit is shared between two logic cells. In the example shown in this figure, there are eight FFs and eight output multiplexers. This is compared to the twelve in the above embodiment, so the configuration is simplified accordingly. The addition of output selector circuit 18 increases the configuration memory by 6x1 = 6 bits, and the addition of output selector circuit 25 increases it by 2x2 = 4 bits, for a total of 10 bits. However, compared to the embodiment of Figure 2, the number of feedback lines can be reduced, allowing for an overall reduction in the configuration memory.

[0082] 7 is an example of a logic block having two lanes 23 as shown in FIG. 6, and FIG. 8 is a diagram showing three lanes 23 provided in one logic block 10 and wiring between different logic blocks 10. This example has twice the number of logic cells compared to the examples in FIGS. 2 and 4, and although a direct comparison with the above-mentioned prior art is not possible, it is possible to reduce the number of logic memories considerably compared to a crossbar-connected logic block having the same number of logic cells.

[0083] (Regarding logic cells) Furthermore, in the above embodiment, it is possible to use a conventionally used LUT as a logic cell, but by using a "PAE circuit (combinational logic cell)" which can reduce the number of constituent memories of the logic cell itself compared to a conventional LUT, it is possible to reduce the number of constituent memories required for the above wiring and further improve packaging density.

[0084] FIG. 9 shows an example of a logic block 10″ having three levels of lanes, each lane having three 4-input, 3-output PAE circuits 26 arranged as logic cells. This PAE circuit 26 has three PA circuits (programmable AND circuits: basic logic cells) 27 switchably connected, as shown in FIGS. 10(a) and 10(b). Each PA circuit 26 is a programmable circuit configured by adding a programmable NOT circuit 29 to a basic logic operation element (AND gate, OR gate, NOT gate, etc.) 28, and is programmable to switch the input / output of the basic logic cell 27 according to the connection relationship of the nodes in the netlist.

[0085] The number of configuration memories used by this PAE circuit 26 is 16 bits in the case of a conventional 4-input LUT (4LUT) logic cell, but the 4-input PAE circuit 26 of this embodiment uses 8 bits, which is half the number.

[0086] In one embodiment, the effect of reducing the number of memory components can be obtained simply by replacing the normal 4-input 3-output LUT as the logic cell of the first embodiment with a 4-input 3-output PAE, but if technology mapping using PAE is performed as follows, it is possible to further improve the actual packaging density.

[0087] That is, in this case, the gate level netlist (AIG) shown in FIG. 11 is used.

[0088] (1) Matching with one of the node graphs (a), (b), and (c) in Figure 12 (node ​​graphs showing PAE circuits) from the AIG. (2) Mapping to logical cells, (3) Return to (1) until all nodes are covered. (4) Once all nodes have been mapped, the process is complete.

[0089] When the netlist shown in FIG. 11 is mapped using a 4-input, 3-output PAE, it can be covered as shown by the lasso in the figure. When mapping to the PAE circuit of this embodiment, outputs from nodes within the covered range can be used, so there is no overlapping of target nodes. As a result, in this example, eight 4-input, 3-output combinational logic cells (configuration memory count: 8 bits) can be mapped, resulting in a configuration memory capacity of 8 bits x 8 = 64 bits. In the case of a 4-LUT, 14 cells are required as a result of technology mapping, resulting in 16 bits x 14 = 224 bits. As a result, the configuration memory capacity of the PAE circuit is less than one-third of that when an LUT is used.

[0090] Furthermore, the average coverage rate of the netlist in this embodiment is 2.52 nodes, exceeding the 2.43 nodes of the LUT. As a result, in an evaluation using 29 types of benchmark circuits in this embodiment, the average configuration memory reduction rate reached 51.6%, halving the configuration memory. Furthermore, the maximum configuration memory reduction rate was 66.5%, and the minimum configuration memory reduction rate was 23.0%, achieving a reduction in memory compared to conventional LUTs.

[0091] According to the example described above, a programmable logic circuit (PAE and combinations thereof) is provided, which is a logic cell for an embedded FPGA mounted on an ASIC, and has a basic logic cell (PX circuit) that constitutes a node of a gate-level netlist, and this basic logic cell is a programmable circuit configured by adding a programmable NOT circuit to a basic logic operation element, and is programmable to switch the input / output of the basic logic cell depending on the connection relationship of the nodes in the netlist.

[0092] Although the PAE circuit 26 described above has four inputs and three outputs, it is not limited to this, just as the number of inputs to a basic logical operation element is not limited to two.

[0093] According to this embodiment, when a combinational logic cell is configured by combining two or more types of graphs, each of which connects n basic logic cells with m inputs, the number of inputs is (m-1) x n+1 and the number of outputs is n. m and n can be any number equal to or greater than 2.

[0094] FIG. 13 is an enlarged view of the PAE circuit 26 shown in FIG. 10(b). Also, in this figure, the basic logic cell 27, which was labeled PA in FIG. 10(b), is labeled PX. This example shows the PAE circuit 26 when the number of inputs m of the basic logic cell (PX) 27 is two and the number of connected cells n is three. The number of inputs to this PAE circuit 26 is (m-1)×n+1=(2-1)×3+1=4, and the number of outputs is n, i.e., 3. The number of inputs m of the basic logic cells 27 is two, and n=3 of them are connected. The graphs with three connections result in three patterns, as shown in FIGS. 12(a) to 12(c) (circles indicate basic logic cells). To achieve these multiple node connections, the PAE circuit 26 has a function (indicated by reference numeral 30 in FIG. 13) for switching the connections of the internal logic nodes using a multiplexer or an equivalent circuit. The PAE circuit 15 has a memory (shown by reference numeral 31 in FIG. 13) that stores switching information for multiplexers and the like for switching connections, and is capable of setting the memory 31 inside the PAE circuit 26 in accordance with the connection shape of the nodes that make up the netlist.

[0095] In addition, in the case of connecting n=4 basic logic cells 27 with m=2 inputs, the number of graphs becomes seven patterns (not shown), and a combination logic cell with (2-1)×4+1=5 inputs and 4 outputs created by combining two types of graphs from these seven patterns is shown in, for example, Figures 14 to 17.

[0096] In these examples, the connection relationship between two types of basic logic cells (nodes) is realized by one combinational logic cell, but it is also possible to realize more than two types of node connection relationships by one combinational logic cell.

[0097] Furthermore, the above example shows a case where the number of included basic logic cells is four, but the number n included is also arbitrary.

[0098] The programmable NOT circuit 29 of the PA circuit 27 shown in Fig. 10(b) may be realized by a NOT gate and a multiplexer as shown in Fig. 18(a), or by an XOR gate as shown in Fig. 18(b).Furthermore, the basic logic element 28 may be configured using a NAND gate or a NOR gate in addition to an AND gate or an OR gate as shown in Fig. 19.

[0099] In the above example, a programmable NOT circuit is placed at one input of the basic logic operation element, but it may be placed at both inputs as shown in Figure 20(a). Also, the number of inputs to the basic logic cell is not limited to two as shown in Figure 20(b). (Comparison of memory configurations) The table below shows a comparison of the number of memory components when there are four logic cells, as explained above. JPEG2026015242000002.jpg108167

[0100] The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the present invention.

[0101] For example, in the above embodiment (FIG. 4), each input selector circuit 17 of each logic cell 13 of the second lane 12 selects from 10 external input signals to the second lane 12 and 6 from the first lane 11, but this is not limited to this, and it is possible to remove some wiring.

[0102] For example, the left logic cell 13 of the second lane 12 selects the four left outputs of the six outputs from the two logic cells 13 of the first lane 11, and similarly, the right logic cell of the second lane 12 selects the four right outputs of the six outputs from the two logic cells 13 of the first lane 11. Furthermore, the second lane 12 selects four different signals from each of the ten external input signals. With this configuration, each input selector circuit 17 of the second lane 12 can select from eight wires.

[0103] As another example, the logic cell 13 of the second lane 12 may be configured so that only the leftmost input signal of the four input signals is selected from 16 signals, while the other three input signals are each selected from the six output signals of the first lane 11 and two different signals from the external input signals. This allows the logic cell 13 of the second lane 12 to select from 16 wires for only the leftmost input, and to select from eight wires for the other three inputs.

[0104] As yet another example, in each lane of this embodiment, it is also possible to arrange the wiring as shown in FIGS.

[0105] In the example of FIG. 21, the input selector 18 of the logic cell 13 has four inputs. In contrast, in another example shown in FIG. 22, the input selector 18 of the logic cell 13 has two inputs. The input wiring of the input selector 18 of FIG. 21 can be selected from the line of the external input signal, the wiring from the first lane, or the wiring to be skip-connected. On the other hand, the input selector 18 of the logic cell 13 of FIG. 22 reduces the number of inputs to half. In this case, it is preferable to shift the selected wiring as shown in FIG. 22. In this example, the shift amount is 1, but the shift method is not limited to this, and the shift amount may be n, or any two wirings may be selected.

[0106] In this example, the number of inputs to the input selector is reduced from four to two, but the original number of inputs may be reduced. For example, if the original number of inputs is 20 (external input, first lane, skip wiring), this may be reduced to eight inputs. In this case, the 20 inputs may be arranged in an appropriate order, and eight input wirings may be selected from the 20 by shifting them by one.

[0107] Also, as shown in FIG. 23, the logic cell 13 of FIG. 21 and the logic cell 13 of FIG. 22 may be arranged side by side in one lane and connected by wiring.

[0108] Furthermore, as shown in FIG. 24, within one lane, a wiring 28 may be provided that connects the output of a logic cell 13 to the input selector 18 of another logic cell 13 (in this example, the adjacent logic cell).

[0109] In addition, although FFs are connected to all outputs of the logic cell 13 in the example shown in Fig. 4, FFs may be connected to only some of the outputs, rather than all of the outputs, as shown in Fig. 25. In this example, an FF is connected to only one of the three outputs.

[0110] FIG. 26 shows a modified example of the example shown in FIG. 6. In this example, as in the example shown in FIG. 9, four logic cells are arranged in one lane 23. Furthermore, one output selector circuit 18 is shared between two output terminals of the logic cell 13, and wiring and a signal selector 25 (multiplexer) are provided for extracting a skip signal (a signal going to a lane other than the next lane). However, in this example, each selector 18, 25 is provided with an input that provides a constant (0 or 1) from a memory provided in the logic block or an external input, so that not only the output value from the logic selector but also the constant can be selected and output. In this example, constant inputs are provided not only to the output selectors 18, 25 but also to the input selector 16 and output FF 19 of the logic cell 13. Note that, in the case of lanes configured as shown in FIGS. 21 to 26, even a logic block 10 configured without two or more lanes can achieve certain effects in terms of reducing configuration memory and packaging area.

[0111] Furthermore, in the above embodiment, the logic cells are assumed to be LUTs and PAEs, but they may be used in combination. For example, a single lane may contain a combination of LUTs and PAEs as logic cells, or each lane may contain an LUT and a PAE. Also, a single FPGA may contain a combination of programmable logic circuits that use only LUTs as logic cells and programmable logic circuits that use only PAEs.

[0112] Furthermore, in the above embodiment, the first lane and the second lane use the same number of logic cells, but the number of logic cells used may be different between the lanes.

[0113] Furthermore, in the above embodiment, the programmable logic circuits (PA, PX, and PAE circuits) of the present invention are incorporated into the logic blocks of an FPGA, but they can also be applied to reconfigurable logic devices other than FPGAs. That is, the most direct application example of this BLE is eFPGA (embedded FPGA). When providing a reconfigurable logic area inside an SoC (System-on-Chip) or ASIC (Application Specific Integrated Circuit), incorporating the programmable logic circuit of this invention can enable advanced control while ensuring area efficiency and flexibility. [Explanation of symbols]

[0114] 1...FPGA 2...Logical block 3...Switch Block 4...Connection block 5...LUT 6...Local connection block 8...Netlist 10...Logical block 11...First lane 12...Second lane 13...Logic cell 16, 17...Input selector circuit 18, 19...Output selector circuit 21, 22...Output Flip-Flop 23...Lane 25...Signal selector 26…PAE circuit 27…PA circuit

Claims

1. 1. A programmable logic circuit comprising: The programmable logic circuit has a plurality of lanes connected sequentially in a direction in which an input signal of the programmable logic circuit flows, Each of the plurality of lanes has one or more logic cells, and an input signal to the lane is input to each logic cell through a programmable input side selector circuit, and an output signal from each logic cell is output as an input signal to the next sequential lane connected to the lane and / or as an output signal of the programmable logic circuit, The logic cell comprises: having basic logic cells that constitute nodes of a gate-level netlist; This basic logic cell is a programmable circuit that is configured by adding a programmable NOT circuit to the input and output of a basic logic operation element.

1. A programmable logic circuit comprising:

2. 2. The programmable logic circuit of claim 1, The input signals of each lane include the input signals of this programmable logic circuit.

1. A programmable logic circuit comprising:

3. 3. The programmable logic circuit of claim 2, At least one of the lanes receives an input signal of the programmable logic circuit from the preceding sequential lane to which it is connected.

1. A programmable logic circuit comprising:

4. 2. The programmable logic circuit of claim 1, At least one of the lanes has a wiring that feeds back an output signal from the logic cell to the preceding sequential lane to which the lane is connected or as an input signal to the lane.

1. A programmable logic circuit comprising:

5. 2. The programmable logic circuit of claim 1, At least one of the lanes has wiring that feeds forward an output signal from the logic cell as an input signal to a subsequent lane after the lane to which it is connected.

1. A programmable logic circuit comprising:

6. 2. The programmable logic circuit of claim 1, At least one of the lanes has a wiring that skips and outputs an output signal from a logic cell as an input signal to another programmable logic circuit.

1. A programmable logic circuit comprising:

7. 2. The programmable logic circuit of claim 1, Each lane is The nodes constituting the netlist at the logic cell level are mapped to each logic cell provided in each lane according to the hierarchy along the direction from the input side to the output side on the netlist.

1. A programmable logic circuit comprising:

8. 8. The programmable logic circuit of claim 7, The node mapping is performed on each logic cell provided in each lane according to the sequential number of connections of the lane in the programmable logic circuit.

1. A programmable logic circuit comprising:

9. 2. The programmable logic circuit of claim 1, A flip-flop (FF) is provided on the output side of the logic cell provided in each lane.

1. A programmable logic circuit comprising:

10. 2. The programmable logic circuit of claim 1, An output selector circuit is provided on the output side of the logic cell previously provided in each lane.

1. A programmable logic circuit comprising:

11. 2. The programmable logic circuit of claim 1, The logic cell comprises: The input / output of the basic logic cell is programmable to be switched depending on the connection relationship of the nodes in the netlist.

1. A programmable logic circuit comprising:

12. 12. The programmable logic circuit of claim 11, The logic cell comprises: a combinational logic cell formed by combining a plurality of the basic logic cells; This combinational logic cell has a plurality of basic logic cells that cover a plurality of nodes that make up the graph of the netlist.

1. A programmable logic circuit comprising:

13. 13. The programmable logic circuit of claim 12, When the number of basic logic cells to be combined is n, an integer of 2 or more, and the number of inputs of each basic logic cell is m, an integer of 2 or more, The combinational logic cell comprises: It is an (m-1) x n+1 input n output logic cell in which n basic logic cells are connected by combining input signals in a switchable manner to express two or more patterns of node connection.

1. A programmable logic circuit comprising:

14. 13. The programmable logic circuit of claim 12, the combinational logic cell has a plurality of outputs; one or more selectors each configured to receive at least two or more output signals from the combinational logic cell and to output a selected signal; a flip-flop (FF) provided to receive the output signal from the selector; 1. A programmable logic circuit comprising:

15. 15. A basic logic element according to claim 14, comprising: The one or more selectors are further configured to receive a constant signal. Programmable logic circuits.

16. 2. The programmable logic circuit of claim 1, This programmable logic circuit is a logic block of an FPGA.

1. A programmable logic circuit comprising:

17. 10. An FPGA in which the programmable logic circuit according to claim 1 is implemented as a logic block.

18. A programmable logic circuit implemented in a logic block (LB) that constitutes an FPGA, This programmable logic circuit is a combinational logic cell (PAE) which is formed by combining a plurality of basic logic cells (PA) and is programmed to switch inputs and outputs of the basic logic cells in accordance with the connection relationships of the nodes in a netlist, and which outputs a plurality of output signals; one or more selectors each configured to receive at least two or more output signals from the combinational logic cell and to output a selected signal; A programmable logic circuit having:

19. 20. The programmable logic circuit of claim 18, Furthermore, a flip-flop (FF) is provided in the subsequent stage of the selector so as to receive the output signal from the selector. A programmable logic circuit having:

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