System and method for validating components of a storage device

Abstract

To provide a system and a method for verifying whether a storage device or a processor device forming a part of a computing storage device is an authenticated component through hardware.SOLUTION: A verification module 200a, 200b for performing hardware verification of modular components of a computing storage device, the verification module 204a, 204b further comprising a multiplexer LA, LA, wherein an output of the multiplexer is coupled to the reserved pin 208 of the connector, and wherein the reset pin 206 controls the multiplexer so that the output of the hardware verification logic 202 is selected during a reset period when the reset pin is asserted. When the reset pin is de-asserted, the multiplexer transmits the type of chassis via the reserved pin 208. The hardware verification logic initiates a verification cycle in response to a reset by the host processor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a storage device, and more particularly to a system and method for verifying whether components of a storage device are authorized and / or verified components. [Background technology]

[0002] For various data processing tasks, it is preferable to use computational storage devices (e.g., field programmable gate arrays (FPGAs) or solid state drives (SSDs) with embedded processors), which help provide efficient and cost-effective data processing solutions. For example, the computational storage device provides a platform for performing at least some of the data processing functions that would otherwise be performed by a host CPU processor, whether provided within the storage device itself. Therefore, it would be desirable to have a system and method for quickly determining whether one or more components of a computing storage device are verified components. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2015 / 0095712 [Patent Document 2] US Patent Application Publication No. 2016 / 0293274 [Patent Document 3] US Patent Application Publication No. 2017 / 0220499 [Patent Document 4] US Patent Application Publication No. 2018 / 0196103 [Patent Document 5] US Patent Application Publication No. 2018 / 0373664 [Patent Document 6] US Patent Application Publication No. 2019 / 0129882 [Patent Document 7] U.S. Patent Application Publication No. 2019 / 0155519 [Patent Document 8] U.S. Patent No. 6,484,128 [Patent Document 9] U.S. Patent No. 7,845,016 [Patent Document 10] U.S. Patent No. 8,875,280 [Patent Document 11] U.S. Patent No. 9,524,108 [Non-patent literature]

[0004] [Non-Patent Document 1] Moorison,Paul,How New Storage Technologies Get a Boost from Hardware Emulation,Veloce Insights Blog,https: / / blogs.mentor.com / emulation / blog / 2017 / 09 / 26 / how-new-storage-technologies-get-a-boost-from-hardware-emulation / ,6pages [Non-patent document 2] Moorthy, T., Gopalakrishnan, S. IO and data management for infrastructure as a service FPGA accelerators.J Cloud Comp6,20(2017).https: / / doi.org / 10.1186 / s13677-017-0089-9,23pages Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned prior art, and an object of the present invention is to provide a system and method for verifying, via hardware, whether a storage device or a processor device forming part of a computing storage device is an authenticated component. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, one aspect of the present invention provides a computing system for verifying components of a storage device, comprising: a first component including a connector having a first connection; and a second component coupled to the first component via the connector, wherein the first component is configured to generate a first signal to be transmitted via the first connection of the connector based on the second connection being in a first state; the second component is configured to receive the first signal via the first connection of the connector; the first connection is configured to transmit a second signal based on the second connection being in a second state; the second component is configured to compare the first signal with a third signal in response to receiving the first signal and generate a result; the second component is configured to transmit a signal to perform an action based on the result; and the second connection is configured to cause the first component to enter the first state in response to connection to the second component.

[0007] The first component may include at least one of a field gate programmable array (FPGA) or an application-specific integrated circuit (ASIC), and the second component may include non-volatile memory. The third signal may be associated with an identifier stored in a memory of the second component. The connector may be configured to support the Peripheral Component Interconnect Express (PCIe) protocol. The second connection may be configured to assume the first state in response to a reset of at least a portion of the system. The first connection portion may include a preset pin. The result may include an indication of a match between the first signal and the third signal, and the action may include activating a function of the system. The result may include an indication of a discrepancy between the first signal and the third signal, and the action may include deactivating a function of the system. The result may include an indication of a discrepancy between the first signal and the third signal, and the action may include displaying a notification on a display device. The second component may be coupled to the device via a second connector.

[0008] In order to achieve the above object, one aspect of the present invention provides a method for verifying components of a storage device using a computing system, the method comprising: generating a first signal by a first component including a connector having a first connection based on a second connection being in a first state; transmitting the first signal through the first connection of the connector; receiving the first signal by a second component; and comparing the first signal with a third signal by the second component in response to receiving the first signal to generate a result, wherein the first connection is configured to transmit the second signal based on the second connection being in a second state, the second component is coupled to the first component via the connector, the computing system is configured to perform an action in response to the result, and the second connection is configured so that the first component is in the first state in response to connection to the second component.

[0009] As one skilled in the art will appreciate, the present invention provides a mechanism for quickly determining whether one or more components of a computing storage device are verified components, which can, for example, help prevent unexpected device behavior or errors resulting from the use of unverified components. [Effects of the Invention]

[0010] According to the present invention, verification is performed through hardware verification logic included in the processor device and the storage device, and the hardware verification logic is configured to use reserved pins of a connector connecting the storage device to the processor device, thereby enabling rapid verification of whether one or more components of the computing storage device are verified components. [Brief explanation of the drawings]

[0011] [Figure 1A] FIG. 1 is a block diagram of a first example of a computing storage device having modular components, according to one embodiment. [Figure 1B] FIG. 10 is a block diagram of a second example computing storage device having modular components according to one embodiment. [Figure 1C] FIG. 10 is a block diagram of a third example computing storage device having modular components according to one embodiment. [Figure 2] FIG. 2 is a block diagram of a validation module for performing hardware validation of modular components of a computing storage device according to one embodiment. [Figure 3] 1B is a block diagram of the computing storage device of FIG. 1A configured with the verification module of FIG. 2. [Figure 4] 10 is a signaling diagram of a verification module according to one embodiment. [Figure 5]1 is a flowchart of a hardware verification processor according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Specific examples of embodiments of the present invention will now be described in detail with reference to the drawings. Herein, like reference numerals refer to like elements throughout. However, the present invention may be embodied in a variety of different forms and should not be construed as being limited to only the embodiments exemplified herein. Rather, these embodiments are provided as examples so that the present invention will be thorough and complete and will fully convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for those skilled in the art to fully understand the aspects and features of the present invention may not be described. Unless otherwise specified, like reference numerals refer to like elements throughout the drawings and description set forth herein, and therefore, descriptions thereof may not be repeated. Note that in the drawings, the relative sizes of elements, layers, and regions may be exaggerated and / or simplified for clarity.

[0013] Computational storage devices are sometimes modular in design or construction. In such cases, the computing storage device is composed of different removable components, including, for example, storage components (e.g., solid state memory) and processing components (e.g., field programmable gate arrays (FPGAs)). The modular components of a computing storage device may be obtained from other vendors. Thus, it is possible to attempt to configure a computing storage device from an unauthorized / unqualified vendor, which may compromise the quality of the configured computing storage device.

[0014] Generally, the present invention relates to a method and system for detecting, via hardware, whether a storage device (e.g., SSD) or processing device (e.g., FPGA) forming part of a computing storage device is an authenticated component. The verification process is performed, for example, during a full or partial reset of the computing storage device. The verification process is performed, for example, to verify whether such device has an authenticated component before downloading an image and / or bitfile that configures the FPGA to operate in a predetermined manner.

[0015] In one embodiment, the validation process is performed via hardware validation logic included in the processor device and the storage device. The hardware validation logic is configured to use reserved pins on a connector (e.g., a U.2 connector) that couples the storage device to the processor device. In one embodiment, the reserved pins include pin E6 of the U.2 connector.

[0016] According to one embodiment, hardware verification by the initiator of the target occurs during a reset period. The initiator is an initiator as described by the NVMe standard, but embodiments of the present invention are not limited thereto. The initiator may be a processor device that turns the target into a storage device, or vice versa. For example, a reset period occurs when these devices are inserted into a slot in a computer system without halting or shutting down the system, or when the entire computer system is rebooted. During the reset period, the initiator is configured to monitor reserved pins to determine whether traffic is sensed via the pins. In one embodiment, an authorized target drives a reserved pin with a verification ID (also referred to as a verification signal) that notifies the initiator that the target is an authorized device. For example, the verification ID includes a predefined waveform pattern / signal. In response to verifying that the target is an authorized device, the initiator activates certain functions of the device that would not be activated without such verification. For example, capabilities may include downloading proprietary bit files and / or activating certain acceleration features.

[0017] 1A-1C are block diagrams of various examples of computing storage devices (100a, 100b, 100c) (collectively referred to as 100) having modular components according to one embodiment. The various modular components described herein are also referred to as hardware components.

[0018] 1A includes a modular storage component 102 that is removably coupled to one or more processor components (104a, 104b). The modular storage component 102 may be, for example, an SSD including a storage controller 106 and various flash drives 108. For example, the SSD may be a Non-Volatile Memory Express (NVMe) SSD, an NVMe-oF (NVMe over Fabrics) compatible eSSD (Ethernet SSD), or any other suitable persistent (non-volatile) memory device.

[0019] For example, one or more of the processor components (104a, 104b) may include one or more FPGAs (110a, 110b). In some embodiments, a graphics processing unit (GPU), a tensor processing unit (TPU), and / or an application-specific integrated circuit (ASIC) as are conventional in the art may be used in addition to or instead of the FPGA.

[0020] 1A, modular storage component 102 couples to a host device via connector 111a, which may be, for example, a small-form-factor-technology-affiliate-100x (SFF-TA-100x) connector (where x is an integer value such as 2, 6, 7, 8, etc.). A user can create a computational storage device of choice by adding one or more processor components (104a, 104b) to storage component 102 as needed.

[0021] In one embodiment, the modular storage component 102 is coupled to one or more processor components (104a, 104b) via connectors (112a, 112b). For example, the connectors (112a, 112b) may be standard connectors such as U.2, M.2, Next Generation Small Form Factor (NF1), or Enterprise & Data Center SSD Form Factor (EDSFF) connectors. For example, communication between the storage component 102 and one or more processor components (104a, 104b) occurs via PCIe links (114a, 114b) through the connectors (112a, 112b).

[0022] In the example of FIG. 1B, computing storage device 100b includes a modular processor component 120 that is removably coupled to one or more modular storage components (122a-122d) (collectively referred to as 122) via connectors (124a-124d). The processor device of modular processor component 120 may be, for example, an FPGA, and one or more modular storage components 122 may be, for example, an SSD. In the example of FIG. 1B, processor component 120 is coupled to a host device via connector 111b. A user can create a selective computing storage device by adding one or more modular storage components 122 to processor component 120 as needed.

[0023] The computing storage device 100c of FIG. 1C is similar to (but not necessarily identical to) the computing storage device 100a of FIG. 1A, except that dual processor components (130a, 130b) are coupled to a storage component 132 via a connector 134 having a dual-port configuration. For example, the connector may be a U.2 connector or a PCIe interface. In the example of FIG. 1C, the processor components (130a, 130b) are coupled to a host device via connector 111c. A user can design a selective computing storage device by adding optional modular storage components 132 to the processor components (130a, 130b) as needed.

[0024] 1A-1C, with the modular configuration of computing storage device 100, for example, certain modular components may be acquired from unauthorized / unqualified vendors, which may compromise the product quality (e.g., performance) of the computing storage device. Therefore, it is preferable to have a method and system for determining whether one or more components of the computing storage device are verified components. If the added modular components are verified as approved components, certain acceleration features, such as compression and / or encryption functions, of the computing storage device are activated.

[0025] In one embodiment, if the added modular component cannot be verified, the computing storage device is configured to download or receive a standard FPGA bitfile, for example, without downloading a proprietary FPGA bitfile. For example, this means allowing the computing storage device to operate normally, but without acceleration capabilities. Such a device preferably additionally transmits a message informing the user or application that the added device is unauthorized.

[0026] 2 is a block diagram of validation modules (200a, 200b) (collectively referred to as 200) for performing hardware validation of modular components of a computing storage device according to one embodiment. In one embodiment, validation modules 200 are located in an initiator component and a target component. Validation modules 200 each include hardware validation logic (202a, 202b) (collectively referred to as 202), which may be described, for example, as state machines.

[0027] In one embodiment, validation module 200 further includes multiplexers (204a, 204b) (collectively referred to as 204). The input to a particular one of multiplexers 204 is provided by corresponding hardware validation logic 202 and reserved pin 208. In one embodiment, reserved pin 208 is a reserved pin of connector 210 (similar to connectors (112, 124, 134)). If the connector is implemented as a U.2 connector, reserved pin 208 is the "E6" pin, which is defined as a reserved (RSVD) pin (or any other suitable pin). While a U.2 connector is used as an example of a connector for coupling a processor module to a storage module, those skilled in the art should recognize that the connector could also be an M.2 or NF1 connector having one or more reserved pins.

[0028] The outputs of the multiplexers (204a, 204b) are coupled to reserved pins 208 of connector 210. A reset pin 206 controls the multiplexers (204a, 204b) so that when the reset pin 206 is asserted (e.g., asserted low), the output of the hardware validation logic 202 is selected during the reset period. When the reset pin 206 is de-asserted, the multiplexer transmits the chassis type via the reserved pin 208.

[0029] In one embodiment, the hardware verification logic 202 of the initiator and target devices begins a verification cycle in response to a reset by the host processor, which in one embodiment drives the reset pin 206 to be asserted low, causing the multiplexer 204 to select the hardware verification logic 202 to communicate over the reserved pin 208 of the connector 210 during the reset.

[0030] In one embodiment, an initiator is a device initially installed in a host computer for validation of a target, which is a modular component added later. A processor component or a storage component can be an initiator or a target. In one example, the initiator is the processor component (120, 130) of FIGS. 1B and 1C, and the target is the storage component (122, 132) of FIGS. 1B and 1C. In another example, the initiator is the storage component 102 of FIG. 1A, and the target is the processor component 110 of FIG. 1A.

[0031] For purposes of explanation, assuming the initiator is an FPGA and the target is an SSD, the initiator executes hardware verification logic 202a, including, for example, a verification identifier (ID), from a non-volatile memory device upon a reset. For example, the non-volatile memory device is an EEPROM (electrically erasable programmable read-only memory). A download can occur because a reset erases any logic programmed into the FPGA.

[0032] In one embodiment, the initiator's hardware validation logic 202a monitors the reserved pin 208 during the reset period for activity on the pin. Monitoring continues until the reserved pin 208 is no longer asserted low.

[0033] Turning now to the target, like the initiator, multiplexer 204b selects the SSD's hardware verification logic 202b to communicate with the FPGA via connector 210 in response to reset pin 206 being asserted low. In one embodiment, if the target is a device to be verified, hardware verification logic 202b drives reserved pins 208 of connector 210 with a verification ID during the reset period. In one embodiment, the target's hardware verification logic 202b receives the verification ID transmitted via reserved pins 208 from the FPGA, a host processor, or the like.

[0034] The FPGA's hardware verification logic 202a detects the verification ID on the monitored reserved pin 208 and compares the received verification ID with the expected verification ID downloaded from the memory device. If the verification IDs do not match, verification of the target SSD fails. The FPGA's hardware verification logic 202a records the result of a failed verification process in a defined register location. For example, a result of "not verified" is recorded in a defined register location. However, if the verification is successful, the FPGA's hardware verification logic 202a is configured to record a "verified" status in a defined register location.

[0035] In one embodiment, the FPGA checks the results of the verification at a defined register location before performing certain operations. For example, such operations may include downloading or not downloading proprietary bitfiles in addition to standard bitfiles in the boot sequence, and / or activating or deactivating certain acceleration features of the FPGA, including compression, encryption, etc. Other acceleration features that may be activated or deactivated based on the verification results include, for example, activating / deactivating double data rate fourth generation synchronous dynamic random-access (DDR4) channels (if supported), activating / deactivating high bandwidth memory (HBM) (if present), etc.

[0036] Figure 3 is a block diagram of the computing storage device of Figure 1A configured with the validation modules (200a, 200b) of Figure 2. The hardware validation logic 202a executed by the storage component 102 is integrated into the initialization logic performed by the storage controller during cold reboots. The hardware validation logic 202a executed by the processor component 104 is stored in non-volatile memory such as an EEPROM and loaded into the FPGA 110 upon reset.

[0037] In this embodiment, the multiplexers (204a, 204b) are integrated into the storage component 102 and the processor component 104, respectively. In some embodiments, the multiplexers (204a, 204b) are external to the storage and / or processor components.

[0038] 4 is a signaling diagram of the verification module 200 according to one embodiment. At the rising edge of a particular clock cycle 400, the reset pin 206 is asserted low 402 to initiate a reset period. For example, the reset period may last for several seconds. In one embodiment, no activity on the rebooted device occurs during the reset period, and the lack of activity is used to perform verification by the target device initiator. In one embodiment, the target device's hardware verification logic 202b drives the reserved pin 208 from a low state 404 to a high state 406 as many times as necessary based on a predetermined pattern dictated by the verification ID. In one embodiment, the minimum requirement is that the pin be driven from a low state to a high state for at least one clock cycle and from a high state to a low state for at least another clock cycle.

[0039] The initiator, monitoring the reserved pin 208 during the reset period, receives the verification ID. In one embodiment, a fixed counter is invoked by the initiator when a first signal is received on the reserved pin 208. When the fixed counter reaches a certain value corresponding to the size of the expected verification ID, the initiator concludes that all verification IDs have been received. Note that the initiator causes the reserved pin 208 (not shown) to be driven to a low state 408. For example, this occurs before the expiration of the reset period. The initiator compares the received verification ID with the expected verification ID to determine a match.

[0040] In one embodiment, when the reset pin 206 is no longer asserted 410 (e.g., upon expiration of the reset period), the reserved pin 208 serves to provide the chassis type. For example, a low reserved pin 208 indicates an NVMe chassis type, and a high reserved pin 208 indicates an NVMe-oF chassis type.

[0041] 5 is a flowchart of a hardware verification process according to one embodiment. It should be understood that the order of the steps in the process is not fixed and may be changed to any desired order as recognized by one skilled in the art.

[0042] At step 500, a reset is asserted by the host processor for a particular slot (eg, in response to host insertion of a device into the slot) or for the entire system.

[0043] At step 502, the initiator and target hardware validation logic (202a, 202b) is initiated in response to a reset. In one embodiment, the determination of which modular components of the computing storage device are initiators and which modular components are targets depends on the device first coupling to the host device. In one embodiment, the module or configuration as an initiator or target is via programmable pins.

[0044] In step 504, the initiator's hardware verification logic 202a monitors the reserved pin 208 to determine if the target is an authorized target. In one embodiment, the initiator's hardware verification logic 202a compares the signal received via the reserved pin 208 with the verification ID expected by the initiator. If the received signal matches the expected verification ID, the target is considered authorized, and the "verified" status is stored in a specific register.

[0045] In step 506, in response to verifying the target, the initiator performs one or more operations permitted to be performed with the approved target. For example, such operations may include downloading a proprietary FPGA bitfile of the FPGA vendor (in addition to the standard FPGA bitfile) during the boot sequence and continuing a PCIe link training sequence to establish a high-speed I / O connection between the initiator and the target device. Other operations may include activating acceleration features of the processor component, activating DDR4 channels, and / or activating high bandwidth memory (HBM).

[0046] Referring back to step 504, if the initiator's hardware verification logic 202a is unable to verify the target (e.g., due to a mismatch between the received verification ID and the expected verification ID), the hardware verification logic 202a stores a "not verified" status in a specific register in step 508.

[0047] In step 510, the initiator performs one or more actions in response to the target component failing verification. For example, such actions may include proceeding through a boot sequence by downloading a standard FPGA bitfile rather than a proprietary FPGA bitfile, deactivating certain acceleration features of the FPGA (e.g., compression, encryption, etc.), deactivating DDR4 channels, and deactivating HBM, if present. In this manner, a computing storage device with an unverified target component present can perform its functions, but with limited capabilities.

[0048] In one embodiment, a notification is sent in step 512 to inform the user that the target device is not an approved device. The notification may be displayed to the user, for example, as part of a Basic Input Output System (BIOS) function.

[0049] It should be understood that terms such as "first," "second," and "third" are used herein to describe various elements, components, regions, layers, and / or sections. These elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed herein could be termed a second element, component, region, layer, or section without departing from the spirit and scope of the inventive concepts.

[0050] The terms used herein are intended to describe specific embodiments and are not intended to limit the concept of the present invention. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not of degree, and are intended to account for the inherent deviation in measured or calculated values ​​recognized by those skilled in the art.

[0051] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. As used herein, the terms "comprises" and / or "comprising" will be further understood to specify the presence of the stated features, integers, steps, operations, elements, and / or components, but not to exclude the addition or presence of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Phrases such as "at least one," when preceding a list of elements, modify the entire list of elements, and not individual elements of the list. Furthermore, when describing embodiments of the present invention, the use of "may" refers to "one or more embodiments of the present invention." Additionally, the term "exemplary" is intended to indicate an example or illustration. As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0052] When an element or layer is said to be "present on," "connected," "bonded," or "adjacent to" another element or layer, it will be understood as being directly present on, directly connected to, directly bonded to, or directly adjacent to the other element or layer, or that one or more intermediate elements or layers are present. In contrast, when an element or layer is said to be "directly present on," "directly connected," "directly bonded," or "directly adjacent to" another element or layer, there are no intermediate elements or layers present.

[0053] Any numerical range recited herein is intended to include all subranges of the same numerical precision subsumed within the recited range. For example, a range of "1.0 to 10.0" includes all subranges between the recited minimum of 1.0 and the recited maximum of 10.0, i.e., including minimums of 1.0 or greater and maximums of 10.0 or less, such as 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited herein is intended to include all higher numerical limitations subsumed therein.

[0054] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0055] 100, 100a, 100b, 100c computing storage device 102 (Modular) Storage Components 104, 104a, 104b processor components 106 Storage Controller 108 flash drive 110, 110a, 110b FPGAs 111a, 111b, 111c (SFF-TA-100x) connectors 112, 112a, 112b (U.2, M.2, NF1, or EDSFF) connector 114, 114a, 114b PCIe links 120 (Modular) Processor Components 122, 122a-122d Modular storage components 124, 124a~124d connectors 130a, 130b (dual) processor components 132 (Selective Modular) Storage Components 134 (U.2 or PCIe interface) connector 200, 200a, 200b Verification Modules 202, 202a, 202b (hardware) verification logic 204, 204a, 204b multiplexers 206 Reset pin 208 reserved pin ("E6") 210 (U.2 or NF1) connector

Claims

1. 1. A computing system for validating components of a storage device, comprising: a first component including a connector having a first connection portion; a second component coupled to the first component via the connector; the first component is configured to generate a first signal transmitted through the first connection of the connector based on the second connection being in a first state; the second component is configured to receive the first signal via a first connection of the connector; the first connection portion is configured to transmit a second signal based on the second connection portion being in a second state; the second component is configured to compare the first signal with a third signal in response to receiving the first signal and generate a result; the second component is configured to send a signal to perform an action based on the result; The system, wherein the second connection is configured to cause the first component to enter the first state in response to connection to the second component.

2. the first component includes at least one of a field gate programmable array (FPGA) or an application-specific integrated circuit (ASIC); The system of claim 1 , wherein the second component comprises a non-volatile memory.

3. 10. The system of claim 1, wherein the third signal is associated with an identifier stored in a memory of the second component.

4. 10. The system of claim 1, wherein the connector is configured to support a Peripheral Component Interconnect Express (PCIe) protocol.

5. 2. The system of claim 1, wherein the second connection is configured to assume the first state in response to a reset of at least a portion of the system.

6. 10. The system of claim 1, wherein the first connection includes a preset pin.

7. the result includes an indication of a match between the first signal and the third signal; The system of claim 1 , wherein the action includes activating a function of the system.

8. the result includes an indication of a discrepancy between the first signal and the third signal; 2. The system of claim 1, wherein the action includes deactivating a function of the system.

9. the result includes an indication of a discrepancy between the first signal and the third signal; The system of claim 1 , wherein the action includes displaying a notification on a display device.

10. The system of claim 1 , wherein the second component is coupled to the device via a second connector.

11. the first component includes a selector device; 2. The system of claim 1, wherein the second connection in a first state is configured to provide an input to the selector device for selecting the first signal and transmitting the first signal over the first connection.

12. 12. The system of claim 11, wherein the selector device comprises a multiplexer.

13. 1. A method for validating components of a storage device by a computing system, comprising: generating, by a first component including a connector having a first connection, a first signal based on the second connection being in a first state; transmitting a first signal via a first connection of the connector; receiving, by a second component, the first signal; and comparing, by the second component, the first signal with a third signal in response to receiving the first signal to generate a result; the first connection portion is configured to transmit a second signal based on the second connection portion being in a second state; the second component is coupled to the first component via the connector; the computing system is configured to perform an action in response to the result; The method, wherein the second connection is configured to cause the first component to enter the first state in response to the connection to the second component.

14. the first component includes at least one of a field gate programmable array (FPGA) or an application-specific integrated circuit (ASIC); The method of claim 13 , wherein the second component comprises non-volatile memory.

15. 14. The method of claim 13, wherein the third signal is associated with an identifier stored in a memory of the second component.

16. 14. The method of claim 13, wherein the connector is configured to support a Peripheral Component Interconnect Express (PCIe) protocol.

17. 14. The method of claim 13, wherein the second connection is configured to assume the first state in response to a reset of at least a portion of the computing system.

18. 14. The method of claim 13, wherein the first connection comprises a preset pin.

19. the result includes an indication of a match between the first signal and the third signal; The method of claim 13, wherein the action includes activating a function of the computing system.

20. the result includes an indication of a discrepancy between the first signal and the third signal; The method of claim 13, wherein the action includes deactivating functionality of the computing system.

21. the result includes an indication of a discrepancy between the first signal and the third signal; 14. The method of claim 13, wherein the action includes displaying a notification on a display device.

22. The method of claim 13 , wherein the second component is coupled to the device via a second connector.

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