Analog multiplier

Abstract

To provide an analog multiplier which is hardly affected by odd-order harmonics of a local oscillation signal and can be realized at a low cost.SOLUTION: An analog multiplier according to an embodiment of the present invention includes a weighting circuit unit configured to generate a plurality of weighted input signals obtained by applying a plurality of different weights to an input signal, an analog switch unit configured to connect any of a plurality of selection terminals and a common terminal based on a switching signal, the weighted input signals generated by the weighting circuit unit being input to the plurality of selection terminals, a reference signal oscillator configured to output a reference signal having a frequency that is a rational number multiple of a predetermined local oscillation frequency, and a switching signal generator configured to generate, from the reference signal, a switching signal that defines a selection terminal to be connected to the common terminal for each of divided sections obtained by dividing one cycle of the local oscillation frequency by an integer. The analog multiplier is characterized in that the weighting circuit unit generates a plurality of weighted input signals weighted in accordance with the normalized integration value for each of the divided sections of the sine wave of the local oscillation frequency.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multiplier that handles transmitted and received signals as analog signals (hereinafter referred to as an "analog multiplier"), and more particularly to a weighted analog switch type multiplier. [Background technology]

[0002] Conventionally, a simple analog switch-type frequency multiplier has been used in a simple synchronous detection circuit 20, as shown in Fig. 1, in which a received signal is passed through a band-pass filter (BPF) 21 and a receiving amplifier 22, and a switching signal that is coherent with a local oscillation signal output by a local oscillator 25 is generated in a quadrature synchronization signal generator 26 using an analog switch 23, and frequency multiplication is performed by switching the polarity of the signal using this switching signal (see, for example, Patent Document 1). In such a synchronous detection circuit 20, a low-pass filter (LPF) is provided after the analog switch 23, and the output of this filter becomes the final output in the receiving circuit of the detection circuit 20. Note that the synchronous detection circuit 20 may also include a transmitting circuit consisting of a transmitting amplifier 27, a driver 28, etc., in addition to the receiving circuit described above.

[0003] 2, there is also a synchronous detection circuit 30 that uses a method in which a received signal that has passed through a band-pass filter 31 and a receiving amplifier 32 is converted into a digital signal by an AD converter 33 and then digitally processed. In this method, a digital signal synchronized with a local oscillation signal output by a local oscillator 35 is generated by a numerically controlled oscillator (NCO) 341, and is multiplied by the output of the AD converter 33 by a numerical mixer 342. Further, a digital filter 343 performs low-pass filtering and the like, and the resulting signal becomes the final output from the receiving circuit of the detection circuit 30. Note that the synchronous detection circuit 30 may also include a transmitting circuit that includes a DA converter 39, a transmitting amplifier 37, a driver 38, etc., in addition to the receiving circuit described above. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 10-093430 Summary of the Invention [Problem to be solved by the invention]

[0005] In a simple analog switch type frequency multiplier, aliases are generated even for odd harmonics (frequencies 3f, 5f, 7f, ...) of the clock signal (frequency f), so to reduce this effect, the bandpass filter applied to the received signal must be narrow-band. For this reason, although the switch section is inexpensive and consumes little power, there are significant constraints on the cost and number of components of the analog circuit that realizes the bandpass filter.

[0006] On the other hand, in the case of a method using digital signal processing, although the input BPF can be simplified by oversampling, the size and power consumption of the logic circuits used for analog-to-digital conversion and digital signal processing restrict the cost and commercialization.

[0007] In view of the above problems, an object of the present invention is to provide an analog multiplier that is less susceptible to the effects of odd-order harmonics of a local oscillation signal and can be realized at low cost. [Means for solving the problem]

[0008] In order to solve the above problem, an analog multiplier according to one embodiment of the present invention includes a weighting circuit unit that generates a plurality of weighted input signals by applying a plurality of different weights to an input signal, an analog switch unit that connects one of a plurality of selection terminals to a common terminal based on a switching signal, wherein the weighted input signals generated by the weighting circuit unit are input to the plurality of selection terminals, a reference signal oscillator that outputs a reference signal having a frequency that is a rational multiple of a predetermined local oscillation frequency, and a switching signal generator that generates, from the reference signal, a switching signal that specifies which selection terminal is to be connected to the common terminal for each division interval obtained by integer-dividing one cycle of the local oscillation frequency.The weighting circuit unit generates a plurality of weighted input signals with weights corresponding to normalized integral values ​​for each division interval of a sine wave of the local oscillation frequency.

[0009] In the present invention, the weighting circuit section may function as part of a filter provided in the subsequent stage of the analog multiplier.

[0010] In the present invention, it is preferable that the signal source impedance viewed from the output end of the analog switch section is constant regardless of which selection terminal is connected to the common terminal. [Effects of the Invention]

[0011] According to the present invention, it is possible to realize an analog multiplier that is less susceptible to the effects of odd-order harmonics of a local oscillation signal and can be realized at low cost. [Brief explanation of the drawings]

[0012] [Figure 1] 1 shows the configuration of a conventional synchronous detection circuit having a simple analog switch type frequency multiplier. [Figure 2] 1 shows the configuration of a conventional synchronous detection circuit using a digital signal processing method. [Figure 3] 1 shows a configuration of a detection circuit including an analog multiplier according to an embodiment of the present invention. [Figure 4] FIG. 10 is a diagram illustrating an example of a waveform of a pseudo-sine wave. [Figure 5]10A and 10B are diagrams illustrating an example of frequency components of a pseudo sine wave and a square wave. DETAILED DESCRIPTION OF THE INVENTION

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0014] FIG. 3 is a circuit block diagram showing the configuration of a synchronous detection circuit 1 to which an analog multiplier 10 according to an embodiment of the present invention is applied.

[0015] 3, the synchronous detection circuit 1 includes a band-pass filter 11, a receiving amplifier 12, a weighted analog switch 13, a low-pass filter 14, a reference oscillator 15, and a switching signal generator 16. Of these, the weighted analog switch 13, the reference oscillator 15, and the switching signal generator 16 constitute an analog multiplier 10, as shown in FIG.

[0016] Bandpass filter 11 passes only a predetermined pass frequency band in the input received signal and blocks signals of frequencies outside the pass frequency band. Bandpass filter 11 is configured to pass the frequency of the local oscillation signal and block odd-order harmonics that are not canceled in the pseudo-sine wave described below (11th and higher harmonics when the pseudo-sine wave is realized by six-value weighting switching, as exemplified below). Receiving amplifier 12 is an amplifier that separates the output and input of bandpass filter 11 and amplifies them appropriately. It is preferable that the output impedance of receiving amplifier 12 is sufficiently low.

[0017] The weighted analog switch 13 receives the output of the receiving amplifier 12 as an input signal, and outputs a signal obtained by multiplying the input signal by a weight (amplification coefficient or attenuation coefficient) corresponding to the selected terminal. The function of outputting a signal obtained by multiplying the input signal by a weight (amplification coefficient or attenuation coefficient) corresponding to the selected terminal is hereinafter referred to as "weighting switching." The low-pass filter 14 passes only predetermined low-frequency signals and blocks high-frequency signals from the signals output by the weighted analog switch 13. The output of the low-pass filter 14 is the final output from the receiving circuit of the synchronous detection circuit 1.

[0018] Reference oscillator 15 outputs a reference oscillation signal that has a frequency that is a rational multiple of the carrier wave in the received signal and is in phase with the carrier wave, i.e., in a so-called coherent relationship. The signal to be multiplied by the received signal is called a local oscillation signal, and the frequency of the local oscillation signal is called the local oscillation frequency. Reference oscillator 15 provides a reference signal to switching signal generator 16 to generate a switching signal with the same period as the local oscillation frequency. When switching signal generator 16 divides one period of the local oscillation signal into a predetermined number n of intervals and changes the switching signal for each divided interval, as described below, it is preferable to set the frequency of the reference signal to n times the frequency of the local oscillation signal, as this facilitates generation of the switching signal. The reference signal output by reference oscillator 15 may also be used to generate a quadrature synchronization signal in a transmission circuit including transmission amplifier 17, driver 18, etc.

[0019] Based on the reference signal output by reference oscillator 15, switching signal generator 16 generates and outputs a multi-value switching signal having the same period as the local oscillation frequency to weighted analog switch 13. The switching signal is a signal that specifies which selection terminal 132A in analog switch unit 132 is connected to common terminal 132B for each division interval obtained by dividing the period of the local oscillation signal by an integer number. Switching signal generator 16 changes the switching signal so as to switch which selection terminal 132A is connected to common terminal 132B for each interval obtained by dividing one period of the local oscillation signal into a predetermined number n of intervals.

[0020] The configuration and operation of the weighted analog switch 13 will be described in more detail. The weighted analog switch 13 is composed of a weighting circuit section 131 and an analog switch section 132. Note that the weighting circuit section 131 may be configured to include the impedance of the switches of the analog switch section 132.

[0021] The weighting circuit unit 131 generates a plurality of weighted input signals by applying a plurality of different weights (i.e., multiplying the signals by different amplification coefficients or attenuation coefficients) to the input signal from the receiving amplifier 12. The weighting can be realized by a resistance value or a voltage division ratio using a resistor, a transfer ratio of a current mirror, charge redistribution using a switched capacitor, or weighting on the time axis such as pulse width modulation.

[0022] The analog switch section 132 has a plurality of selection terminals 132A, a common terminal 132B, and a control terminal 132C. One of a plurality of weighted input signals is input to each of the plurality of selection terminals 132A. The common terminal 132B serves as the output terminal of the weighted analog switch 13. A switching signal from the switching signal generation section 16 is input to the control terminal 132C. The analog switch section 132 connects one of the plurality of selection terminals 132A to the common terminal 132B based on the switching signal input to the control terminal 132C, and outputs the weighted input signal input to the connected selection terminal 132A as the output of the weighted analog switch 13. A commercially available, inexpensive CMOS analog multiplexer can be used for the analog switch section 132.

[0023] The weighting circuit unit 131 generates a plurality of weighted input signals, each weighted with a weight corresponding to the normalized integral value of the sine wave of the local oscillation frequency for each of n division intervals obtained by integer-dividing the period of the local oscillation signal. Using such weighted input signals and a switching signal, it is possible to realize analog multiplication in which the received signal is multiplied by a pseudo-sine wave that approximates the sine wave of the frequency of the local oscillation signal using a weighted combination of rectangular waves.

[0024] For example, if one cycle of a local oscillation signal is divided into 12 sections (n=12) as shown in Figure 4, a pseudo sine wave can be realized by combining six weights for each section. That is, due to the symmetry of a sine wave, the absolute values ​​of the values ​​for each section are the following three (a1 to a3). a1=(2-√3) / 2 a2=(√3-1) / 2 a3=1 / 2

[0025] If we normalize a3 so that the largest absolute value is 1, the approximate values ​​of a1 / a3 and a2 / a3 are as follows: a1 / a3 ≒ 0.268 a2 / a3 ≒ 0.732 Taking into account the difference in sign, a pseudo-sine wave can be realized by combining six weights: -1, -0.732, -2.68, 2.68, 0.732, and 1.

[0026] Specifically, if the weights are set to 0.268 for the first and sixth sections, 0.732 for the second and fifth sections, 1.000 for the third and fourth sections, -0.268 for the seventh and twelfth sections, -0.732 for the eighth and eleventh sections, and -1.000 for the ninth and tenth sections, a pseudo-sine wave can be realized by combining six different weights.

[0027] Note that the number of intervals, n, into which the period of the local oscillation signal is divided is preferably an even number, from the viewpoint of limiting the number of types of absolute values ​​of the weights to be provided. That is, if n is an even number, the number of types of absolute values ​​of the weights in each interval can be n / 4 due to the symmetry of the pseudo sine wave (in the above example, there are three types of absolute values ​​of the weights for n=12). In contrast, if n is an odd number, (n+1) / 2 types of absolute values ​​of the weights are required, which complicates the circuit and goes against the spirit of the present invention. Furthermore, if n is an odd number, one interval in one period will have a weight of 0, and the energy or information of a 1 / n interval of the multiplicand signal will be lost, which may be disadvantageous in terms of the signal-to-noise ratio, etc. Therefore, it is preferable to set n to an even number in this respect as well.

[0028] It is known that the frequency component Fs of a square wave contains odd-order harmonics due to Fourier transform. A quasi-sine wave can cancel these odd-order harmonics by combining weighted square waves. Figure 5 shows the spectrum of a quasi-sine wave generated by switching between six weighting levels, which divides one cycle of the local oscillator signal shown in Figure 4 into 12 sections, along with the spectrum of a square wave with the same cycle as the quasi-sine wave. In Figure 5, the black circle markers indicate the spectrum of the quasi-sine wave, and the white square markers indicate the spectrum of the square wave. As shown in Figure 5, the quasi-sine wave can cancel the 3rd, 5th, 7th, and 9th harmonics. As a result, since bandpass filter 11 only needs to deal with aliases of 11th and higher harmonics (i.e., sufficiently reduce them), compared to the countermeasures for 3rd and higher harmonics required in conventional simple analog switch type frequency multipliers, if the attenuation of, for example, the 11th harmonic is sufficient, the order of bandpass filter 11 can be reduced to one-third or less, simplifying the configuration. In some cases, bandpass filter 11 may even be omitted.

[0029] When weighting in the weighting circuit unit 131 is achieved using resistors and capacitors, it is advisable to use Thevenin's theorem to determine the values ​​of the resistors and capacitors so that the signal source impedance seen from the output terminal of the weighting circuit unit 131 is constant, regardless of which selection terminal 132A is connected to the common terminal 132B in the analog switch unit 132. With this configuration, the signal source impedance seen from the output terminal of the weighted analog switch 13 is constant regardless of the operation of the analog switch unit 132 (i.e., regardless of which selection terminal 132A is connected to the common terminal 132B), thereby reducing the effects of switch characteristics and signal amplitude. In addition, the operating points of the analog switches can be made equal. Therefore, it is also possible to compensate for the effects of charge injection, which is the injection of electric charge from the switching signal of the analog switch into the signal path, thereby significantly improving characteristics with a simple configuration.

[0030] Even when the weighting circuit 131, which makes the signal source impedance constant as described above, is approximated by a simple integer ratio for a real circuit, it is possible to suppress low-order harmonics such as the third and fifth harmonics by 80 dB or more relative to the fundamental wave. Therefore, this can be easily achieved even with elements with values ​​such as the E24 series that are available on the market.

[0031] The weighting circuit unit 131 may function as part of an element constituting the low-pass filter 14 provided in the subsequent stage. The configuration of the weighting circuit unit 131 in which the signal source impedance is constant as described above is preferable because it simplifies the circuit and the characteristics of the low-pass filter 14 do not change depending on which selection terminal 132A is connected to the common terminal 132B of the analog switch unit 132. Furthermore, using an active filter whose operating point does not change due to factors such as ground potential as the low-pass filter 14 is also preferable because it reduces changes in the operating point of the analog switch unit 132. When the low-pass filter 14 is an active filter of the type that receives signals from a capacitor, the charge due to charge injection is redistributed to the capacitor, reducing the effects of charge injection and maintaining a certain degree of consistency regardless of the signal amplitude, thereby reducing secondary distortion and harmonics due to switch characteristics. This is particularly preferable.

[0032] In the analog multiplier according to the present invention described above, a sine wave at a local oscillation frequency is approximated as a weighted combination of square waves, and the weighting is normalized by the integral value of the sine wave in the division section. Due to the superposition nature of the Fourier transform of a square wave, when the number of divisions is, for example, n (n>2) and m (m≧1), harmonics other than mn±1 are essentially eliminated, thereby enabling the suppression of low-order harmonics with a simple circuit configuration. The examples shown in Figures 4 and 5 are for n=12. In this case, harmonics are generated at the 11th and 13th orders when m=1, at the 23rd and 25th orders when m=2, and at the 35th and 37th orders when m=3. However, Figure 5 confirms that harmonics other than mn±1 are not generated.

[0033] Furthermore, when compared with conventional digital frequency multipliers, if the required performance is not too high, the analog multiplier according to the present invention does not require high-performance AD ​​converters and DA converters for oversampling, processors and memories for digital signal processing, or dedicated power supply circuits for these. Instead, it can be realized at low cost using relatively slow baseband operational amplifiers, AD converters, simple power supply circuits, etc.

[0034] [Modification of the embodiment] The present invention is not limited to the above-described embodiments, and includes modifications and improvements within the scope of achieving the object of the present invention. Furthermore, those skilled in the art who appropriately add, delete, or modify components of the above-described embodiments, as well as those who appropriately combine the features of the respective embodiments, are also included within the scope of the present invention as long as they include the gist of the present invention. [Explanation of symbols]

[0035] 1 Synchronous detection circuit 10 Analog Multiplier 11 Bandpass Filter 12 Receiving amplifier 13 Weighted Analog Switch 14 Low-pass filter 15 Reference Oscillator 16 Switching signal generator 17 Transmitting amplifier 18 Drivers

Claims

1. a weighting circuit unit that generates a plurality of weighted input signals by applying a plurality of different weights to an input signal; an analog switch section that connects any one of a plurality of selection terminals to a common terminal based on a switching signal, and the weighted input signals generated by the weighting circuit section are input to the plurality of selection terminals; a reference signal oscillator that outputs a reference signal having a frequency that is a rational multiple of a predetermined local oscillation frequency; a switching signal generating unit that generates, from the reference signal, the switching signal that defines a selection terminal to be connected to a common terminal for each divided section obtained by dividing one period of the local oscillation frequency into integer sections; An analog multiplier comprising: an analog multiplier, wherein the weighting circuit generates a plurality of weighted input signals weighted according to normalized integral values ​​of a sine wave of a local oscillation frequency for each of the divided sections;

2. 2. The analog multiplier according to claim 1, wherein the weighting circuit section functions as a part of a filter provided in a subsequent stage of the analog multiplier.

3. 3. The analog multiplier according to claim 1, wherein the signal source impedance seen from the output terminal of the analog switch unit is constant regardless of which of the selection terminals is connected to the common terminal.

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