Semiconductor device and communication system

Abstract

To provide a semiconductor device capable of effectively constructing a communication system together with a device of a communication system different from that of itself.SOLUTION: In the semiconductor memory device (1), the first reception unit (11) and the first transmission unit (12) are configured to through-output data (DDT) for the first memory (10) included in the reception data (RX) from the second output terminal (1C) when the bridge selection data (BR) included in the reception data (RX) indicates ON of through-output in which bit data is outputted as it is. The second transmission unit (14) fixes a signal level of the first bus (BS1) so that a signal of the first bus (1B) through which the first transmission / reception device (40) receives the reception data from the transmission device (20) is recessive when the through-output is performed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-224946

[0005] [overview] In some applications, a communication system may be constructed using a semiconductor device that performs serial communication using a protocol different from that of the semiconductor device itself, in addition to the semiconductor device itself.

[0006] A semiconductor device according to one aspect of the present disclosure is a semiconductor device connectable to an external transmitter via a first transceiver capable of communication using a differential voltage system, and connectable to an external first device via a second transceiver capable of communication using a differential voltage system, a first input terminal configured to be connectable to a first received data output terminal of the first transceiver; a first output terminal configured to be connectable to a first transmission data input terminal of the first transceiver; a second output terminal configured to be connectable to a second transmission data input terminal of the second transceiver; a second input terminal configured to be connectable to a second received data output terminal of the second transceiver; a first receiving unit configured to receive reception data, which is serial data, from the transmitting device via the first input terminal; a first transmitting unit connected to the second output terminal; a second receiving unit connected to the second input terminal; a second transmitting unit connected to the first output terminal; Equipped with the first receiving unit and the first transmitting unit are configured to, when bridge selection data included in the received data indicates on of a through output that outputs bit data as is, through-output the data for the first device included in the received data from the second output terminal; The second transmitting unit is configured to fix the signal level of the first output terminal so that, when the through output is being performed, the signal of the first bus through which the first transceiver receives the received data from the transmitting device becomes inferior. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a communication system according to a comparative example. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 5 is a table showing an example of bridge mode information. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a CAN transceiver. [Figure 7] FIG. 7 is a diagram showing the data structure of received data RX when writing or reading is performed with the semiconductor device 1 as the target device. [Figure 8] FIG. 8 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the data structure of received data RX when writing or reading is performed with the device 10 as the target device. [Figure 10] FIG. 10 is a timing chart showing a write process to the device 10. In FIG. [Figure 11] FIG. 11 is a diagram showing the configuration of a transmission unit in the semiconductor device 1. As shown in FIG. [Figure 12] FIG. 12 is a diagram showing the configuration of the signal output unit. [Figure 13] FIG. 13 is a timing chart showing a read process for the device 10. In FIG. [Figure 14] FIG. 14 is an external view showing an example of a vehicle.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <1. Communication Systems> 1 is a diagram showing the configuration of a communication system 501 according to a comparative example for comparison with an embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, a semiconductor device 1, and n (n is an integer equal to or greater than 1) devices 10. The communication system 501 is, as an example, for use in a vehicle, and the same applies to the other communication systems described below.

[0010] Communication between the MCU 20 and the CAN transceiver 30 is performed using UART (Universal Asynchronous Receiver / Transmitter). UART is a format for exchanging serial data between two devices. With UART, bidirectional communication is performed between the sender and receiver using two lines.

[0011] Communication between the CAN transceivers 30 and 40 is performed via a CAN bus BS1. CAN is a serial communication protocol standardized by international standards such as ISO11898. CAN uses a differential voltage method for transmitting data based on the level of the voltage difference generated between two communication lines. Communication between the CAN transceiver 40 and the semiconductor device 1 and the n devices 10 is performed via UART.

[0012] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and an RXD (receive data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus BS1, and outputs data input from the CAN bus BS1 from the RXD terminal 30B.

[0013] The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus BS1, and outputs data input from the CAN bus BS1 from the RXD terminal 40A.

[0014] The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC. The n devices 10 are ICs in which circuits with predetermined functions are integrated, and are configured as, for example, matrix switch ICs.

[0015] The semiconductor device 1 has an RX (receive data input) terminal 1A and a TX (transmit data output) terminal 1B. The device 10 has an RX terminal 10A and a TX terminal 10B. The RX terminal 1A and the n RX terminals 10A are commonly connected to an RXD terminal 40A. The TX terminal 1B and the n TX terminals 10B are commonly connected to a TXD terminal 40B.

[0016] 1, the semiconductor device 1 and the n devices 10 support the same protocol, so the semiconductor device 1 and the n devices 10 can be commonly connected to the same CAN transceiver 40. Received data RX output from the RXD terminal 40A is input to the RX terminal 1A and the n RX terminals 10A. The received data RX specifies the device address of one of the semiconductor device 1 and the n devices 10. Transmitted data TX output from the TX terminal 1B and the n TX terminals 10B is input to the TXD terminal 40B.

[0017] However, if the semiconductor device 1 and the n devices 10 support different protocols, it would be difficult to accommodate the configuration of the comparative example shown in Figure 1. Therefore, an embodiment of the present disclosure is implemented as described below. Figure 2 is a diagram showing the configuration of a communication system 50 according to an exemplary embodiment of the present disclosure. In the communication system 50, CAN transceivers 35 and 45 are provided between the semiconductor device 1 and the n devices 10.

[0018] In the configuration shown in FIG. 2, UART communication is performed between the CAN transceiver 40 and the semiconductor device 1, between the semiconductor device 1 and the CAN transceiver 45, and between the CAN transceiver 35 and the device 10. The semiconductor device 1 has an RXD (receive data output) terminal 1C and a TXD (transmit data input) terminal 1D in addition to an RX terminal 1A and a TX terminal 1B. The RX terminal 1A is connected to the RXD terminal 40A of the CAN transceiver 40. The TX terminal 1B is connected to the TXD terminal 40B of the CAN transceiver 40. The receive data RX output from the RXD terminal 40A is input to the RX terminal 1A. The transmit data TX output from the TX terminal 1B is input to the TXD terminal 40B. The receive data RX and the transmit data TX are serial data.

[0019] The CAN transceiver 45 has an RXD terminal 45A and a TXD terminal 45B. Received data BRX output from the RXD terminal 1C is input to the TXD terminal 45B. Transmitted data BTX output from the RXD terminal 45A is input to the TXD terminal 1D. The received data BRX and transmitted data BTX are serial data.

[0020] Communication is performed between the CAN transceiver 45 and the CAN transceiver 35 via a CAN bus BS2. The CAN transceiver 35 has an RXD terminal 35A and a TXD terminal 35B. The RX terminals 10A of the devices 10 are commonly connected to the RXD terminal 35A. The TX terminals 10B of the devices 10 are commonly connected to the TXD terminal 35B.

[0021] The received data BRX is output as received data RX from the RXD terminal 35A via the CAN bus BS2 and input to the RX terminal 10A of each device 10. The transmitted data TX output from the TX terminal 10B of the device 10 is output as transmitted data BTX from the RXD terminal 45A via the CAN bus BS2 and input to the TXD terminal 1D.

[0022] In the configuration according to the embodiment of the present disclosure shown in FIG. 2, the semiconductor device 1 and the n devices 10 support different protocols. When the MCU 20 writes or reads to the semiconductor device 1 via the CAN transceivers 30 and 40, the received data RX output from the RXD terminal 40A to the RX terminal 1A consists only of data that supports the protocol of the semiconductor device 1. Note that "write" refers to the process of writing data to the target device, and "read" refers to the process of reading data from the target device. In the case of a read, the semiconductor device 1 receives the received data RX and then outputs the transmitted data TX from the TX terminal 1B to the TXD terminal 40B.

[0023] On the other hand, when the MCU 20 writes to or reads from the device 10, the receive data RX output from the RXD terminal 40A to the RX terminal 1A includes data corresponding to the protocol of the device 10. At this time, the semiconductor device 1 turns on the bridge function and through-outputs the data included in the receive data RX and corresponding to the protocol of the device 10 as receive data BRX from the RXD terminal 1C. Through-output means outputting bit data as is. The device address of the device 10 is specified in the receive data BRX.

[0024] In the case of a read, the device 10, which is the target device (the device specified by the device address), outputs transmission data TX from the TX terminal 10B. The transmission data TX is input as transmission data BTX to the semiconductor device 1. Since the bridge function of the semiconductor device 1 is on, the transmission data BTX is output as transmission data TX from the TX terminal 1B.

[0025] As described above, according to the embodiment of the present disclosure, even if the protocols of the semiconductor device 1 and the device 10 are different, the CAN transceiver 40 can write and read to and from the semiconductor device 1 and the device 10, respectively.

[0026] Note that this embodiment is not limited to the configuration in which a CAN transceiver is provided between the semiconductor device 1 and the device 10 as described above, and may also be configured without a CAN transceiver as shown in Fig. 3. That is, in this case, the RX terminals 10A of the devices 10 are commonly connected to the RXD terminal 1C, and the TX terminals 10B of the devices 10 are commonly connected to the TXD terminal 1D. As a result, receive data BRX output from the RXD terminal 1C is input to the RX terminal 10A of each device 10, and transmit data BTX output from the TX terminal 10B of the device 10 is input to the TXD terminal 1D.

[0027] <2. Configuration of semiconductor device> 4 is a block diagram of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes functional blocks including a first receiving unit 11, a first transmitting unit 12, a second receiving unit 13, a second transmitting unit 14, and a control unit 15. Note that FIG. 4 illustrates only functional blocks related to communication functions, and other functional blocks may also be included. For example, if the semiconductor device 1 is an LED driver, it includes functional blocks related to LED driving.

[0028] The first receiver 11 receives reception data RX via an RX terminal 1A. The first transmitter 12 outputs reception data BRX via an RXD terminal 1C. The second receiver 13 receives transmission data BTX via a TXD terminal 1D. The second transmitter 14 outputs transmission data TX via a TX terminal 1B.

[0029] The control unit 15 controls the first receiving unit 11, the first transmitting unit 12, the second receiving unit 13, and the second transmitting unit 14. The control unit 15 includes a register 151.

[0030] In this embodiment, it is possible to set whether or not a CAN transceiver is provided between the semiconductor device 1 and the device 10 as described above. Specifically, this can be set by the bridge mode information BRMODE. The bridge mode information BRMODE is set in the register 151. FIG. 5 shows an example of the bridge mode information BRMODE. In the example of FIG. 5, when BRMODE=0, a configuration (FIG. 3) in which a CAN transceiver is not provided between the semiconductor device 1 and the device 10 is set, and when BRMODE=1, a configuration (FIG. 2) in which a CAN transceiver is provided between the semiconductor device 1 and the device 10 is set.

[0031] <3. CAN transceiver configuration> 6 is a diagram showing the configuration of CAN transceiver 40. Note that the configuration of CAN transceiver 45 is similar to that of CAN transceiver 40, and therefore CAN transceiver 40 will be representatively described here.

[0032] The CAN transceiver 40 includes a driver control unit 41, a driver 42, a receiver 43, and an output unit 44. The CAN transceiver 40 also includes a TXD terminal 40B, an RXD terminal 40A, a CANH terminal, and a CANL terminal.

[0033] The CANH and CANL terminals are connected to the respective lines of the CAN bus BS1. Termination resistors R1 and R2 are connected in series between the CANH and CANL terminals. The resistance value of the termination resistors is specified by ISO 11898, and each termination resistor R1 and R2 is configured with a 60 Ω resistor. One end of a capacitor C1 is connected to a connection node N1 where the resistors R1 and R2 are connected.

[0034] The driver 42 has a PMOS transistor (P-channel metal-oxide-semiconductor field-effect transistor (MOSFET)) 42A, a diode 42B, an NMOS transistor (N-channel MOSFET) 42C, and a diode 42D. The source of the PMOS transistor 42A is connected to the application terminal of the power supply voltage VCC. The drain of the PMOS transistor 42A is connected to the anode of the diode 42B. The cathode of the diode 42B is connected to the CANH terminal. The source of the NMOS transistor 42C is connected to the ground terminal. The drain of the NMOS transistor 42C is connected to the cathode of the diode 42D. The anode of the diode 42D is connected to the CANL terminal. The diodes 42B and 42D are used to prevent backflow when a surge occurs.

[0035] The driver control unit 41 controls the on / off of the PMOS transistor 42A and the NMOS transistor 42C based on transmission data TX input from the outside via the TXD terminal 40B.

[0036] More specifically, when the PMOS transistor 42A and the NMOS transistor 42C are turned on, the current flowing through the termination resistors R1 and R2 is the same, so the voltage drops across the termination resistors R1 and R2 are the same, and the high-side signal CANH generated at the CANH terminal is a voltage higher than the voltage at the connection node N1 (=midpoint voltage) by the voltage drop, while the low-side signal CANL generated at the CANL terminal is a voltage lower than the voltage at the connection node N1 (=midpoint voltage) by the voltage drop. In this case, the high-side signal CANH is at a high level, and the low-side signal CANL is at a low level.

[0037] Here, the CANH terminal and the CANL terminal are connected to the application terminal of the power supply voltage VCC2 via resistors R41 and R42, respectively. When the PMOS transistor 42A and the NMOS transistor 42C are turned off, the voltage of the connection node N1 gradually approaches the second power supply voltage VCC2 due to the action of the resistors R41 and R42, which have relatively high resistance values. The second power supply voltage VCC2 is the low level of the high-side signal CANH and the high level of the low-side signal CANL, and is the same voltage as the intermediate voltage.

[0038] In this way, the transmission data TX input to the TXD terminal 40B is output from the CANH terminal and the CANL terminal to the CAN bus BS1.

[0039] On the other hand, the output section 44 has a PMOS transistor 44A and an NMOS transistor 44B. The source of the PMOS transistor 44A is connected to the terminal to which the power supply voltage VCC is applied. The drain of the PMOS transistor 44A is connected to the drain of the NMOS transistor 44B at a node N42. The source of the NMOS transistor 44B is connected to the ground terminal. The voltages at the CANH terminal and the CANL terminal are input to the receiver 43. The output terminal of the receiver 43 is connected to a node N41 to which the gates of the PMOS transistor 44A and NMOS transistor 44B are connected. The node N42 is connected to the RXD terminal 40A.

[0040] The receiver 43 applies a high-level or low-level signal to the node N41 according to the difference in the input voltage. Therefore, the output unit 44 outputs a signal that is the logical inversion of the output of the receiver 43 from the RXD terminal 40A to the outside as received data RX. In this way, the data input from the CAN bus BS1 is output from the RXD terminal 40A.

[0041] When the high-side signal CANH is high and the low-side signal CANL is low, it is called "dominant." When the high-side signal CANH is low and the low-side signal CANL is high, it is called "recessive." Dominant signals take priority over recessive signals.

[0042] When the transmit data TX is at a high level, the driver 42 sets the signals at the CANH and CANL terminals to recessive, and when the transmit data TX is at a low level, the driver 42 sets the signals at the CANH and CANL terminals to dominant. The TXD terminal 40B is pulled up by a pull-up resistor RP inside the CAN transceiver 40. As a result, when the transmit data TX is set to high impedance (Hi-z), the TXD terminal 40B goes to a high level and the signals at the CANH and CANL terminals are set to recessive.

[0043] In the case of the CAN transceiver 45, receive data BRX is input to a TXD terminal 45B corresponding to the TXD terminal 40B, and transmit data BTX is output from an RXD terminal 45A corresponding to the RXD terminal 40A. The CANH and CANL terminals are connected to the CAN bus BS2.

[0044] <4. Structure of received data> 7 is a diagram showing the data structure of received data RX when writing or reading is performed using the semiconductor device 1 as the target device. The received data RX shown in FIG.

[0045] In UART, communication is carried out in data units called frames. As shown in Figure 7, a frame FR is made up of bit data from a start bit S to a stop bit P. The start bit S is at low level, and the stop bit P is at high level. A predetermined number of bits of bit data are placed between the start bit S and the stop bit P. In the example of Figure 7, 8 bits of bit data are placed. In other words, the frame FR is made up of 10 bits of bit data.

[0046] As shown in FIG. 7, the received data RX includes, from the beginning, a synchronization frame SYN, a read / write etc. frame RWD, a data number frame ND, a register address frame AD, a data frame DT, and CRC (Cyclic Redundancy Check) frames CR1 and CR2.

[0047] The synchronization frame SYN is bit data for setting the baud rate in the semiconductor device 1 .

[0048] The Read / Write etc. frame RWD includes a device address DA, a bridge bit BR, a broadcast / parity bit B / PA, and a Read / Write bit RW. The device address DA is bit data indicating the address of the target device (semiconductor device 1) (5-bit data in the example of Figure 7). The bridge bit BR is bit data indicating the on / off of the bridge function of the semiconductor device 1. The broadcast / parity bit B / PA is bit data indicating the on / off of the broadcast of the semiconductor device 1 or the parity of the device address DA. The Read / Write bit RW is bit data indicating Read or Write.

[0049] Here, the bridge bit BR=0 indicates that the bridge function is off, i.e., normal mode (the bridge function is off in the received data RX shown in Figure 7). In this case, the broadcast / parity bit B / PA indicates whether broadcast is on or off. When the broadcast / parity bit B / PA=0, it indicates that broadcast is off, and when the broadcast / parity bit B / PA=1, it indicates that broadcast is on.

[0050] When broadcasting the semiconductor device 1, multiple semiconductor devices 1 are connected to a CAN transceiver 40 as shown in Fig. 8. A device 10 is connected to each semiconductor device 1. When broadcasting is on, all of the multiple semiconductor devices 1 become target devices.

[0051] The bridge bit BR=1 indicates that the bridge function is on (the bridge function is on in the received data RX shown in FIG. 9, which will be described later). In this case, the broadcast / parity bit B / PA becomes the parity of the device address DA. This makes it possible to detect errors in the device address DA. In the configuration shown in FIG. 8, if the protocols differ for each group of devices 10 connected to each of the multiple semiconductor devices 1, turning on the broadcast of the semiconductor device 1 will result in the same received data RX being sent as received data BRX to devices 10 with different protocols, making the protocols incompatible with some of the devices 10. Therefore, when the bridge function is turned on, broadcasting is not performed.

[0052] The data number frame ND is bit data that indicates the number of frames in the data frame DT. do.

[0053] The register address frame AD is bit data indicating an address in the register 151. The data frame DT is bit data indicating the data body (data to be written to the register 151) to be transmitted by the received data RX. In the case of a read, the data frame DT is not included in the received data RX.

[0054] The CRC frames CR1 and CR2 are bit data indicating an error detection code added to the frames RWD, ND, AD, and DT for error detection. The 16-bit CRC data is divided into two frames: CR1 (lower 8 bits) and CR2 (upper 8 bits). Note that although the data frame DT is one frame in the example of FIG. 6, two or more frames may be included in the received data RX. In this case, the CRC frames CR1 and CR2 follow two or more data frames DT.

[0055] 9 is a diagram showing the data structure of received data RX when writing or reading is performed with the device 10 as the target device. The synchronization frame SYN and the read / write etc. frame RWD in the received data RX shown in FIG. 9 are as described above.

[0056] 9, a read / write etc. frame RWD is followed by a first data number frame ND1 and a second data number frame ND2. The first data number frame ND1 is bit data indicating the total number of frames. The second data number frame ND2 is bit data indicating the number of frames of write data for the target device (device 10 when the bridge function is used). In the case of a write process for the target device, the number of frames indicated by the second data number frame ND2 matches the number of frames indicated by the first data number frame ND1. In the case of a read process for the target device, the number of frames obtained by subtracting the number of frames indicated by the second data number frame ND2 from the number of frames indicated by the first data number frame ND1 is the number of frames of data (read data) returned from the target device to the semiconductor device 1.

[0057] In the received data RX shown in FIG. 9, device data DDT follows the second data count frame ND2. The device data DDT is data corresponding to the protocol of device 10 and is the target to be output through as received data BRX. The device data DDT includes a device address BDA. The device address BDA indicates the address of device 10 which is the target device. The position where the device address BDA is arranged in the device data DDT is a position according to the protocol of device 10.

[0058] <5. Through Output Control> Here, the through output control by the semiconductor device 1, that is, the control when the bridge function is on, will be described.

[0059] <<In the Case of Write>> FIG. 10 shows a timing chart during the Write process for device 10. In FIG. 10 (and FIG. 13 during the Read process described later), the received data RX, received data BRX, transmitted data BTX, and transmitted data TX are shown in order from the top. Also, in FIG. 10 (and FIG. 13 during the Read process described later), it is assumed that CAN transceivers 45, 35 are provided between the semiconductor device 1 and device 10 (FIG. 2, BRMODE = 1).

[0060] When the synchronization frame SYN in the received data RX is received, the baud rate is set by the first receiving unit 11, and thereafter, the frame is sampled based on the set baud rate. Thereby, the bit value (0 or 1) of the bit data is obtained.

[0061] Subsequently, a Read / Write etc. frame RWD is received. In the Read / Write etc. frame RWD, the on of the bridge function is set in the bridge bit BR, and Write is set in the Read / Write bit RW.

[0062] Next, the first data number frame ND1 and the second data number frame ND2 are received. During a write process, the number of frames indicated by the first data number frame ND1 matches the number of frames indicated by the second data number frame ND2.

[0063] Subsequently, the number of frames (number of frames for Write) indicated by the second data number frame ND2 (i.e., data SPDT) is output as received data BRX. At this time, the transmitted data BRX is input to the TXD terminal 45B of the CAN transceiver 45.

[0064] 11 is a diagram showing the configuration of the transmitters 12 and 14 in the semiconductor device 1. The first transmitter 12 of the semiconductor device 1 has a signal output section 121.

[0065] The signal output unit 121 has a push-pull configuration as shown in Fig. 12. Specifically, the push-pull configuration is configured by connecting a PMOS transistor (P-channel MOSFET) 121A and an NMOS transistor (N-channel MOSFET) 121B in series between an application terminal of a power supply voltage VCC and an application terminal of a ground potential. The source of the PMOS transistor 121A is connected to the application terminal of the power supply voltage VCC, and the drain of the PMOS transistor 121A is connected to the drain of the NMOS transistor 121B at a node Nd. The source of the NMOS transistor 121B is connected to the application terminal of the ground potential. An RXD terminal 1C is connected to the node Nd. By turning on and off the PMOS transistor 121A and the NMOS transistor 121B, high-level or low-level reception data BRX is output from the RXD terminal 1C.

[0066] When the receive data BRX is input to the TXD terminal 45B of the CAN transceiver 45, the CAN bus BS2 is recessive on the CAN transceiver 35 side, so that signals at the CANH and CANL terminals corresponding to the receive data BRX are transmitted to the CAN transceiver 35 side. At this time, the signals at the CANH and CANL terminals are input to the receiver (corresponding to the receiver 43 in FIG. 6) in the CAN transceiver 45, so that the receive data BRX is mirrored and output as transmit data BTX from the RXD terminal 45A via the receiver and output unit (corresponding to the output unit 44 in FIG. 6) (FIG. 10).

[0067] The transmission data BTX is input to the second receiving unit 13. Here, as shown in Fig. 11, the second transmitting unit 14 has a signal output unit 141. The signal output unit 141 has a push-pull configuration similar to the signal output unit 121. The signal output unit 141 outputs the transmission data TX.

[0068] Let us now assume that the second transmitter 14 outputs the transmission data BTX as the transmission data TX. In this case, the transmission data TX output from the signal output unit 141 is input to the TXD terminal 40B of the CAN transceiver 40 (FIG. 6). At this time, the reception data RX is sent from the CAN transceiver 30 to the CAN bus BS1, resulting in a conflict between the transmission data TX and the reception data RX. In other words, if the reception data RX on the CAN bus BS1 is recessive, the transmission data TX may cause the signals at the CANH and CANL terminals to become dominant, potentially changing the reception data RX.

[0069] Therefore, in this embodiment, the transmission data TX output from the second transmission unit 14 (signal output unit 141) is fixed to high impedance (FIG. 10). That is, both the PMOS transistor and the NMOS transistor in the signal output unit 141 are in the off state. Since the TXD terminal 40B is pulled up by the pull-up resistor RP (FIG. 6), the TXD terminal 40B is fixed to the high level, and the signals of the CANH and CANL terminals are fixed to receptive. Therefore, conflict with the reception data RX sent from the CAN transceiver 30 side can be avoided.

[0070] Note that, even in the case of the configuration (FIG. 3) where no CAN transceiver is provided between the semiconductor device 1 and the device 10, when the reception data RX is through-output, the transmission data TX is fixed to high impedance.

[0071] [[ID=,8]]Also, when the TXD terminal 40B is not pulled up, the transmission data TX may be fixed to the high level by the second transmission unit 14 (signal output unit 141).

[0072] <<In the case of Read>> FIG. 13 shows a timing chart during the Read process for the device 10. In this case, until the reception data RX is through-output, it is the same as in the Write process. In the case of the Read process, after the reception data RX is through-output, the data read from the device 10 is output as the transmission data TX. The transmission data TX is input to the semiconductor device 1 as the transmission data BTX via the CAN transceivers 35 and 45.

[0073] Here, because the bridge function is on, the second reception unit 13 and the second transmission unit 14 through-output the transmission data BTX as the transmission data TX. The through-output of the transmission data BTX is performed for the number of frames obtained by subtracting the number of frames indicated by the second data number frame ND2 from the number of frames indicated by the first data number frame ND1.

[0074] At this time, the transmit data TX is input to the TXD terminal 40B of the CAN transceiver 40 (FIG. 6), but because the CAN bus BS1 is recessive on the CAN transceiver 30 side, signals at the CANH and CANL terminals corresponding to the transmit data TX are transmitted to the CAN transceiver 30 side. At this time, the signals at the CANH and CANL terminals are input to the receiver 43, so the transmit data TX is mirrored and output as receive data RX from the RXD terminal 40A via the receiver 43 and output unit 44.

[0075] Let's assume that the first transmitter 12 directly outputs the received data RX as received data BRX. In this case, the received data BRX directly output from the signal output unit 121 is input to the TXD terminal 45B of the CAN transceiver 45. At this time, because the transmitted data BTX is being sent from the CAN transceiver 35 to the CAN bus BS2, a conflict occurs between the received data BRX and the transmitted data BTX. In other words, if the transmitted data BTX on the CAN bus BS2 is recessive, the received data BRX may cause the signals at the CANH and CANL terminals to become dominant, potentially changing the transmitted data BTX.

[0076] Therefore, in this embodiment, the reception data BRX output from the first transmission unit 12 (signal output unit 121) is fixed to high impedance (FIG. 13). That is, both the PMOS transistor 121A and the NMOS transistor 121B in the signal output unit 121 are turned off. Because the TXD terminal 45B is pulled up by a pull-up resistor, the TXD terminal 45B is fixed to a high level, and the signals at the CANH and CANL terminals are fixed to recessive levels. This makes it possible to avoid conflicts with the transmission data BTX sent from the CAN transceiver 35.

[0077] If the TXD terminal 45B of the CAN transceiver 45 is not pulled up, the first transmitting unit 12 (signal output unit 121) may fix the received data BRX to a high level.

[0078] <6. Vehicles> Fig. 14 is an external view showing one configuration example of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving power supply from a battery (not shown). Note that the installation positions of the electronic devices X11 to X18 in Fig. 14 may differ from the actual positions for convenience of illustration.

[0079] The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

[0080] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0081] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0082] The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0083] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and other devices.

[0084] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0085] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0086] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0087] The communication system including the semiconductor device 1 and the device 10 described above may be applied to any of the electronic devices X11 to X18.

[0088] <7.Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0089] <8. Notes> As described above, the semiconductor device (1) according to one aspect of the present disclosure is a semiconductor device connectable to an external transmitter (20) via a first transceiver (40) capable of communication using a differential voltage system, and connectable to an external first device (10) via a second transceiver (45) capable of communication using a differential voltage system, a first input terminal (1A) configured to be connectable to a first reception data output terminal (40A) of the first transmission / reception device; a first output terminal (1B) configured to be connectable to a first transmission data input terminal (40B) of the first transmission / reception device; a second output terminal (1C) configured to be connectable to a second transmission data input terminal (45B) of the second transmission / reception device; a second input terminal (1D) configured to be connectable to a second reception data output terminal (45A) of the second transmission / reception device; a first receiving unit (11) configured to be able to receive received data (RX), which is serial data, from the transmitting device via the first input terminal; a first transmitting unit (12) connected to the second output terminal; a second receiving unit (13) connected to the second input terminal; a second transmitting unit (14) connected to the first output terminal; Equipped with the first receiving unit and the first transmitting unit are configured to, when bridge selection data (BR) included in the received data indicates on of a through output that outputs bit data as is, through output the data for the first device (DDT) included in the received data from the second output terminal; The second transmitting unit is configured to fix the signal level of the first output terminal so that the signal of the first bus (BS1) through which the first transceiver device receives the received data from the transmitting device becomes recessive when the through output is being performed (first configuration).

[0090] With this configuration, when data for the first device is through-output, it is possible to avoid a conflict with the received data by the first transceiver, thereby providing a semiconductor device that can effectively build a communication system with a device that uses a communication method different from its own.

[0091] Also, in the above first configuration, the first transmission data input terminal may be pulled up, and the second transmission unit may be configured to fix the first output terminal to high impedance when the through output is being performed (second configuration).

[0092] Also, in the above first configuration, the first transmission data input terminal may not be pulled up, and the second transmission unit may be configured to fix the first output terminal to a high level when the through output is being performed (third configuration).

[0093] In any one of the first to third configurations, after the data for the first device is through-output, transmission data (BTX) transmitted from the first device via the second transmission / reception device is input to the second input terminal, and the second receiving unit and the second transmitting unit through-output the transmission data from the first output terminal; The first transmitting unit may be configured to fix the signal level of the second output terminal so that the signal of a second bus (BS2) through which the second transmitting / receiving device receives the transmission data from the first device is recessive when the transmission data is being output through (fourth configuration).

[0094] Also, in the above fourth configuration, the second transmission data input terminal may be pulled up, and the first transmission unit may be configured to fix the second output terminal to high impedance when the through output is being performed (fifth configuration).

[0095] Also, in the above fourth configuration, the second transmission data input terminal may not be pulled up, and the first transmission unit may be configured to fix the second output terminal to a high level when the through output is being performed (sixth configuration).

[0096] In addition, in any one of the first to sixth configurations, it may be possible to configure whether or not the second transmitting / receiving device is provided between the semiconductor device and the first device (seventh configuration).

[0097] In any one of the first to seventh configurations, the first transmitting / receiving device and the second transmitting / receiving device may be configured as CAN transceivers (eighth configuration).

[0098] In addition, in any of the above first to eighth configurations, communication between the first transceiver and the semiconductor device, and communication between the second transceiver and the semiconductor device may be performed by UART (ninth configuration).

[0099] Furthermore, a communication system (50) according to one embodiment of the present disclosure includes a semiconductor device of any one of the first to ninth configurations, the transmitting device, the first transceiver device, the second transceiver device, and the first device (tenth configuration).

[0100] The communication system of the tenth configuration may be mountable on a vehicle (eleventh configuration). [Industrial Applicability]

[0101] The present disclosure can be used, for example, in communication systems for various applications. [Explanation of symbols]

[0102] 1. Semiconductor device 1A RX terminal 1B TX terminal 1C RXD terminal 1D TXD terminal 10 devices 10A RX terminal 10B TX terminal 11 First receiving unit 12 First transmission unit 13 Second receiving unit 14 Second transmission unit 15 Control Unit 30 CAN transceivers 30A TXD terminal 30B RXD terminal 35 CAN transceiver 35A RXD terminal 35B TXD terminal 40 CAN transceivers 40A RXD terminal 40B TXD terminal 41 Driver control unit 42 Drivers 42A PMOS transistor 42B Diode 42C NMOS transistor 42D Diode 43 Receiver 44 Output section 44A PMOS transistor 44B NMOS transistor 45 CAN transceiver 45A RXD terminal 45B TXD terminal 50 Communication Systems 121 Signal output section 121A PMOS transistor 121B NMOS transistor 141 Signal output section 151 registers 501 Communication Systems BS1, BS2 CAN bus C1 capacitor N1, N41, N42 connection nodes Nd node R1, R2 terminating resistor R41, R42 resistors RP pull-up resistor X vehicle X11~X18 Electronic equipment

Claims

1. A semiconductor device connectable to an external transmitter via a first transceiver capable of communication using a differential voltage system, and connectable to an external first device via a second transceiver capable of communication using a differential voltage system, a first input terminal configured to be connectable to a first received data output terminal of the first transceiver; a first output terminal configured to be connectable to a first transmission data input terminal of the first transceiver; a second output terminal configured to be connectable to a second transmission data input terminal of the second transceiver; a second input terminal configured to be connectable to a second received data output terminal of the second transceiver; a first receiving unit configured to receive reception data, which is serial data, from the transmitting device via the first input terminal; a first transmitting unit connected to the second output terminal; a second receiving unit connected to the second input terminal; a second transmitting unit connected to the first output terminal; Equipped with the first receiving unit and the first transmitting unit are configured to, when bridge selection data included in the received data indicates an on state of through output for outputting bit data as is, through output the data for the first device included in the received data from the second output terminal; The semiconductor device, wherein the second transmitting unit fixes the signal level of the first output terminal so that, when the through output is being performed, the signal of the first bus through which the first transceiver receives the received data from the transmitting device becomes inferior.

2. the first transmission data input terminal is pulled up; 2. The semiconductor device according to claim 1, wherein said second transmitting section fixes said first output terminal to a high impedance when said through output is being performed.

3. the first transmission data input terminal is not pulled up, 2. The semiconductor device according to claim 1, wherein said second transmitting section fixes said first output terminal to a high level when said through output is being performed.

4. After the data for the first device is through-output, transmission data to be transmitted from the first device via the second transmission / reception device is input to the second input terminal, and the second receiving unit and the second transmitting unit through-output the transmission data from the first output terminal; 2. The semiconductor device according to claim 1, wherein the first transmitting unit fixes the signal level of the second output terminal so that, when the transmission data is being through-output, the signal of a second bus through which the second transmitting / receiving device receives the transmission data from the first device becomes inferior.

5. the second transmission data input terminal is pulled up; 5. The semiconductor device according to claim 4, wherein said first transmitting section fixes said second output terminal to a high impedance when said through output is being performed.

6. the second transmission data input terminal is not pulled up, 5. The semiconductor device according to claim 4, wherein said first transmitting section fixes said second output terminal to a high level when said through output is being performed.

7. The semiconductor device according to claim 1 , wherein whether or not the second transmitting / receiving device is provided between the semiconductor device and the first device can be set.

8. The semiconductor device according to claim 1 , wherein the first transceiver and the second transceiver are configured as CAN transceivers.

9. 2. The semiconductor device according to claim 1, wherein communication between said first transmitting / receiving device and said semiconductor device and communication between said second transmitting / receiving device and said semiconductor device are performed by UART.

10. 10. A communication system comprising: the semiconductor device according to claim 1; the transmitting device; the first transmitting / receiving device; the second transmitting / receiving device; and the first device.

11. The communication system according to claim 10, which is mountable in a vehicle.

Images