Semiconductor device and switching device

Abstract

To suppress input of an excessive voltage to a target transistor.SOLUTION: In the target transistor (MO), the first conductive electrodes, the second conductive electrodes, and the control electrodes are connected to the first, second, and third wirings (WR1, WR2, WR3), respectively. The control circuit (1210, DRV) controls the target transistor to be turned on or off by supplying a high-side voltage (VCC2) or a low-side voltage (VEE2) to the third wiring according to input control signals (Din, Dout). When the low-side voltage is lower than the voltage of the second wiring by a predetermined threshold voltage or more, an overvoltage signal (S _ UVLO) in an asserted state is output. When the overvoltage signal in the asserted state is output, the control circuit supplies the low-side voltage to the third wiring regardless of the input control signal, and the protection switching element (1230) provided between the second wiring and the fourth wiring to which the low-side voltage is applied is set to ON.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices and switching devices. [Background technology]

[0002] Semiconductor devices for controlling the state of a target transistor are widely used. An example of this type of semiconductor device is sometimes called a gate driver (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-14549

[0004] [overview] In this type of semiconductor device, it is essential to properly adjust the voltage supplied to the target transistor.

[0005] A semiconductor device according to one aspect of the present disclosure is a semiconductor device configured to control a state of a target transistor having a first conduction electrode, a second conduction electrode, and a control electrode, the target transistor being configured so that the first conduction electrode is connected to a first wiring, the second conduction electrode is connected to a second wiring, and the control electrode is connected to a third wiring, and the semiconductor device controls the target transistor to be on by supplying a high-side voltage higher than a voltage of the second wiring to the third wiring in response to an input control signal, or controls the target transistor to be on by supplying a low-side voltage lower than the high-side voltage to the third wiring. The device comprises: a control circuit configured to control the target transistor to be turned off; an overvoltage detection circuit configured to output an overvoltage signal in an asserted state when the low-side voltage is lower than the voltage of the second wiring by a predetermined threshold voltage or more; and a protection switching element provided between the second wiring and a fourth wiring to which the low-side voltage is applied, wherein when the overvoltage detection circuit outputs the overvoltage signal in the asserted state, the control circuit performs an operation of supplying the low-side voltage to the third wiring regardless of the input control signal, and the protection switching element is set on by the overvoltage detection circuit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a configuration diagram of a signal transmission device according to an application configuration. [Figure 11] FIG. 11 is a diagram showing the overall configuration of a system having a signal transmission device according to an application configuration. [Figure 12] FIG. 12 is a perspective view of the external appearance of the signal transmission device of FIG. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of the resistor circuit of FIG. [Figure 14] FIG. 14 is a diagram showing another example of the configuration of the resistor circuit of FIG. [Figure 15] FIG. 15 is a diagram showing an example of the configuration of the negative voltage generating circuit of FIG. [Figure 16] FIG. 16 is a diagram showing the relationship between the primary side control signal and the secondary side control signal in the signal transmission device of FIG. [Figure 17] FIG. 17 is an explanatory diagram of the operation of the secondary side circuit in the signal transmission device of FIG. 11 during the period in which the overvoltage signal is maintained in the negated state. [Figure 18] FIG. 18 is an explanatory diagram of the VEE2_OVLO function in the signal transmission device of FIG. [Figure 19] FIG. 19 is a timing chart for explaining the operation of the signal transmission device of FIG. 11 when a negative voltage abnormality is detected. [Figure 20] FIG. 20 is a diagram showing an example of the configuration of a protection switching element in the signal transmission device of FIG. [Figure 21] FIG. 21 is a diagram showing another example of the configuration of the protection switching element in the signal transmission device of FIG. [Figure 22] FIG. 22 is a configuration diagram of a system including a switching device according to an embodiment of the present disclosure.

[0007] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0008] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0009] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0010] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0011] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0012] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0013] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0014] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0015] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0016] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0017] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0018] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0019] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0020] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0021] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0022] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0023] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0024] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0025] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0026] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0027] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0028] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0029] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0030] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0031] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0032] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0033] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0034] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0035] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0036] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0037] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0038] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0039] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0040] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0041] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0042] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0043] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0044] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0045] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0046] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0047] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0048] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0049] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0050] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0051] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0052] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0053] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0054] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0055] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0056] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0057] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0058] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0059] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0060] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0061] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0062] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0063] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0064] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0065] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0066] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0067] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0068] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0069] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0070] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0071] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0072] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0073] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0074] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0075] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0076] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0077] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0078] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0079] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0080] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0081] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0082] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0083] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0084] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0085] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0086] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0087] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0088] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation breakdown voltage to be achieved.

[0089] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0090] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0091] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0092] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0093] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0094] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0095] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0096] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0097] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0098] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0099] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0100] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0101] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0102] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0103] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0104] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0105] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0106] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0107] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0108] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0109] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0110] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0111] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0112] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0113] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0114] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0115] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0116] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0117] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0118] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0119] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0120] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0121] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0122] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0123] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0124] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0125] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0126] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0127] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0128] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0129] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0130] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0131] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0132] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0133] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0134] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0135] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0136] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0137] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0138] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0139] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0140] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0141] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0142] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0143] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0144] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0145] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminal of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0146] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0147] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0148] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0149] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0150] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0151] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0152] <Signal transmission device (application configuration)> 10 shows a configuration diagram of a signal transmission device 1000. The signal transmission device 1000 is a signal transmission device according to an application configuration, and may be formed by utilizing the configuration of the above-described signal transmission device 200 (see FIG. 1, etc.). The signal transmission device 1000 may be considered to be one form of the signal transmission device 200.

[0153] In this specification, for the sake of simplicity, a symbol or sign referring to information, a signal, a physical quantity, a functional unit, a circuit, an element, a component, etc. may be used, and the name of the information, signal, physical quantity, functional unit, circuit, element, component, etc. corresponding to the symbol or sign may be omitted or abbreviated. For example, the first signal processing circuit referred to by "1110" (see FIG. 11) described below may be written as first signal processing circuit 1110 or may be abbreviated as signal processing circuit 1110, but they all refer to the same thing.

[0154] Some terms and expressions will be explained. A level refers to the level (height) of electric potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal or voltage of interest, a switch from a low level to a high level may be called a rising edge, and a switch from a high level to a low level may be called a falling edge.

[0155] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs (such as IGBTs). Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source. Hereinafter, the on and off states of any transistor may be simply referred to as on and off. Furthermore, for any transistor, the period in which the transistor is in the on state is referred to as the on period, and the period in which the transistor is in the off state is referred to as the off period.

[0156] For any signal having a high-level or low-level signal level, the period during which the level of the signal is the high level is referred to as the high-level period, and the period during which the level of the signal is the low level is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0157] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0158] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0159] As shown in FIG. 10, the signal transmission device 1000 includes a primary circuit 1100 and a secondary circuit 1200. An insulating circuit 1300 having a plurality of insulating elements is provided in the signal transmission device 1000. The primary circuit 1100 and the secondary circuit 1200 are insulated from each other. Each insulating element in the insulating circuit 1300 is provided between the primary circuit 1100 and the secondary circuit 1200. The insulating circuit 1300 is a circuit for transmitting a signal in the primary circuit 1100 to the secondary circuit 1200 while insulating the primary circuit 1100 and the secondary circuit 1200 from each other in a direct current manner. The power supply source for the transmission is the primary circuit 1100. Therefore, specifically, each insulating element in the insulating circuit 1300 is driven by the primary circuit 1100, and thus the signal in the primary circuit 1100 is transmitted to the secondary circuit 1200.

[0160] The primary side circuit 1100 and the secondary side circuit 1200 correspond to the primary circuit system 200p and the secondary circuit system 200s in FIG. 1, respectively. The primary side circuit 1100 can be considered to be one form of the primary circuit system 200p, and the secondary side circuit 1200 can be considered to be one form of the secondary circuit system 200s. The primary side circuit 1100 can be formed by a controller chip 210 (see FIG. 1, etc.), and the secondary side circuit 1200 can be formed by a driver chip 220 (see FIG. 1, etc.). The isolation circuit 1300 can be formed by a transformer chip 230 (see FIG. 1, etc.).

[0161] The ground in the primary side circuit 1100 is referred to as ground GND1. Ground GND1 has a reference potential in the primary side circuit 1100. The conductor portion in the primary side circuit 1100 that has the reference potential is ground GND1. With respect to the primary side circuit 1100, voltages shown without a particular reference represent potentials as seen from ground GND1. A power supply voltage VCC1 (see also Figure 1) is supplied to the primary side circuit 1100. The primary side circuit 1100 operates based on the power supply voltage VCC1 with the potential of ground GND1 as the reference.

[0162] The ground in the secondary side circuit 1200 is referred to as ground GND2. Ground GND2 has a reference potential in the secondary side circuit 1200. The conductor portion in the secondary side circuit 1200 having the reference potential is ground GND2. With respect to the secondary side circuit 1200, voltages shown without a particular reference represent potentials seen from ground GND2. A power supply voltage VCC2 (see also FIG. 1) is supplied to the secondary side circuit 1200. The secondary side circuit 1200 is driven based on the power supply voltage VCC2, with the potential of ground GND2 as the reference. Grounds GND1 and GND2 are insulated from each other.

[0163] FIG. 11 shows the overall configuration of a system SYS including a signal transmission device 1000. In addition to the signal transmission device 1000, the system SYS includes an MPU (Micro Processor Unit) 1400, a resistor circuit 1500, a negative voltage generating circuit 1600, a target transistor MO, a load LD, and a voltage source VS. The target transistor MO is an N-channel insulated gate bipolar transistor (IGBT). However, an N-channel MOSFET may also be used as the target transistor MO. Because the signal transmission device 1000 has the function of driving the gate of the target transistor MO, it can also be referred to as a gate driver (insulated gate driver). The MPU 1400 is an example of an external device provided outside the signal transmission device 1000. The signal transmission device 1000 is disposed between the MPU 1400 and the target transistor MO.

[0164] FIG. 12 is an external perspective view of the signal transmission device 1000. The signal transmission device 1000 is an electronic component (semiconductor device) including multiple semiconductor chips, a housing (package) that houses the multiple semiconductor chips, and multiple external terminals that are exposed to the outside of the signal transmission device 1000 from the housing. The signal transmission device 1000 is formed by encapsulating the multiple semiconductor chips in a housing (package) made of resin. Note that the number of external terminals of the signal transmission device 1000 and the type of housing of the signal transmission device 1000 shown in FIG. 12 are merely examples and can be designed as desired. FIG. 11 shows power supply terminals PIN1 and PIN2, a signal input terminal SIN, ground terminals GNDa and GNDb, an output terminal OUT, and a negative power supply terminal NEG as some of the multiple external terminals provided in the signal transmission device 1000. Other external terminals are also provided in the signal transmission device 1000.

[0165] 11, a power supply voltage VCC1 is supplied to a power supply terminal PIN1 from an external voltage source not shown. A power supply voltage VCC2 is supplied to a power supply terminal PIN2 from another external voltage source not shown. A ground terminal GNDa is connected to a ground GND1. A ground terminal GNDb is connected to a ground GND2. The MPU1400 operates based on the power supply voltage VCC1 with respect to ground GND1.

[0166] The external configuration of the signal transmission device 1000 will be described. The output terminal OUT and the gate of the target transistor MO are connected to a wiring WR3 and are connected to each other through the wiring WR3. A resistor circuit 1500 is inserted in series on the wiring WR3, which is disposed between the output terminal OUT and the gate of the target transistor MO. The resistor circuit 1500 has a resistance component that functions as a gate resistor of the target transistor MO. For example, the resistor circuit 1500 may be the resistor circuit 1510 shown in FIG. 13. The resistor circuit 1510 is composed of a single resistor 1511. When the resistor circuit 1500 is the resistor circuit 1510, a first terminal of the resistor 1511 is connected to the output terminal OUT, and a second terminal of the resistor 1512 is connected to the gate of the target transistor MO. Alternatively, for example, the resistor circuit 1500 may be the resistor circuit 1520 shown in FIG. 14. The resistor circuit 1520 includes resistors 1521 and 1522 and diodes 1523 and 1524. When the resistor circuit 1500 is the resistor circuit 1520, the output terminal OUT is connected to the anode of the diode 1523 and the cathode of the diode 1524, the cathode of the diode 1523 is connected to the first end of the resistor 1521, the second end of the resistor 1521 is connected to the gate of the target transistor MO, the anode of the diode 1524 is connected to the first end of the resistor 1522, and the second end of the resistor 1522 is connected to the gate of the target transistor MO.

[0167] A load LD is inserted between the application terminal of the power supply voltage VPWR and the target transistor MO. In the configuration example of FIG. 11, a first terminal of the load LD is connected to the application terminal of the power supply voltage VPWR, and a second terminal of the load LD is connected to the collector of the target transistor MO. The emitter of the target transistor MO is connected to ground GND2. The wiring to which the collector of the target transistor MO is connected is called wiring WR1, and the wiring to which the emitter of the target transistor MO is connected is called wiring WR2. The wiring WR2 has the potential of ground GND2. The power supply voltage VPWR has a potential higher than ground GND2 by a predetermined amount. A current loop is formed through a voltage source VS that generates the power supply voltage VPWR based on the potential of ground GND2, the load LD, the target transistor MO, and ground GND2. During the on-period of the target transistor MO, a current based on the power supply voltage VPWR flows through the load LD and the target transistor MO (current flows in the current loop). During the off-period of the target transistor MO, no current is generated through the load LD and the target transistor MO (current does not flow in the current loop). The ground terminal GNDb is connected to the source of the target transistor MO.

[0168] The negative voltage generating circuit 1600 is connected to the wiring WR4 and to the ground GND2 (and is therefore connected to the wiring WR2 and the ground terminal GNDb). The negative power supply terminal NEG is also connected to the wiring WR4. The voltage on the wiring WR4 is referred to as the voltage VEE2. The negative voltage generating circuit 1600 generates a voltage VEE2 on the wiring WR4 that is lower than the potential of the wiring WR2, with the potential of the wiring WR2 as the reference, assuming that the protection switching element 1230 (described later) is off.

[0169] FIG. 15 shows a negative voltage generating circuit 1610, which is an example of the negative voltage generating circuit 1600. The negative voltage generating circuit 1610 includes a Zener diode 1611 and a resistor 1612. The voltage source VS2 shown in FIG. 15 is an external voltage source provided outside the signal transmission device 1000, and has a negative terminal connected to ground GND2 and a positive terminal connected to power supply terminal PIN2. The voltage source VS2 outputs a power supply voltage VCC2 from the positive terminal based on the potential of the negative terminal. When the negative voltage generating circuit 1600 is the negative voltage generating circuit 1610, the anode of the Zener diode 1611 is connected to the negative power supply terminal NEG (and therefore connected to wiring WR4), the cathode of the Zener diode 1611 and a first end of the resistor 1612 are commonly connected to ground terminal GNDb (and therefore commonly connected to wiring WR2), and the second end of the resistor 1612 is connected to the power supply terminal PIN2. As a result, if the protection switching element 1230, which will be described later, is off, a voltage that is lower than the potential of ground GND2 by the Zener voltage of the Zener diode 1611 is applied to the negative terminal NEG as the voltage VEE2. Note that a current loop is formed that runs from the positive terminal of the voltage source VS2 through the resistor 1612, the Zener diode 1611, and the negative terminal NEG, and then through the secondary circuit 1200 and the ground terminal GNDb to the negative terminal of the voltage source VS2, and a negative voltage VEE2 is generated when a current flows through this current loop.

[0170] The internal configuration of the signal transmission device 1000 in Fig. 11 will be described. The signal transmission device 1000 includes a first signal processing circuit 1110 as a component of the primary side circuit 1100, a second signal processing circuit 1210, an overvoltage detection circuit 1220, a protective switching element 1230, and a driver DRV as components of the secondary side circuit 1200, and transformers 1310 and 1320 as components of the isolation circuit 1300.

[0171] The first signal processing circuit 1110 is driven based on a power supply voltage VCC1 with respect to the potential of ground GND1. The MPU 1400 supplies a control signal Din to a signal input terminal SIN, and the control signal Din from the MPU 1400 is received by the first signal processing circuit 1110 through the signal input terminal SIN. The control signal Din is a control signal within the primary side circuit 1100, and has a high level or a low level. The high level of the control signal Din has the potential of the power supply voltage VCC1, and the low level has the potential of ground GND1. A waveform shaping circuit such as a Schmitt buffer may be provided between the signal input terminal SIN and the first signal processing circuit 1110. The MPU 1400 and the first signal processing circuit 1110 may be connected to each other in a manner that allows bidirectional communication. The bidirectional communication between the MPU 1400 and the first signal processing circuit 1110 may be serial communication using SPI (Serial Peripheral Interface). Alternatively, in this bidirectional communication, I 2 An interface based on C (Inter-Integrated Circuit) or Microwire may also be used.

[0172] The first signal processing circuit 1110 has a transmitting circuit 1111. The transmitting circuit 1111 is connected to each primary coil of the transformers 1310 and 1320. The second signal processing circuit 1210 has a receiving circuit 1211. The receiving circuit 1211 is connected to each secondary coil of the transformers 1310 and 1320. A control signal Din is transmitted from the transmitting circuit 1111 to the receiving circuit 1211 in an isolated manner using the transformers 1310 and 1320. That is, the transmitting circuit 1111 supplies a transmitting pulse signal to each primary coil of the transformers 1310 and 1320 in response to the control signal Din, and the receiving circuit 1211 restores the control signal Din based on a receiving pulse signal generated across both ends of each secondary coil of the transformers 1310 and 1320. The restored control signal Din is referred to as a control signal Dout. The control signals Din and Dout are examples of a primary control signal and a secondary control signal, respectively. Control signal Dout is a control signal within secondary-side circuit 1200 and has a high level or a low level. The high level of control signal Dout has the potential of power supply voltage VCC2, and the low level has the potential of ground GND2. Transformers 1310 and 1320 have the same structures as the above-mentioned transformers 231 and 232 (see FIG. 1, etc.), respectively. Transformer 1310 can be considered to be transformer 231 itself, and transformer 1320 can be considered to be transformer 232 itself.

[0173] Although not specifically shown, signals may also be transmitted in an isolated manner from the second signal processing circuit 1210 to the first signal processing circuit 1110. That is, a secondary-side transmitting circuit having a configuration equivalent to that of the transmitting circuit 1111 may be provided in the second signal processing circuit 1210, while a primary-side receiving circuit having a configuration equivalent to that of the receiving circuit 1211 may be provided in the first signal processing circuit 1110, and another transformer for transmitting signals from the secondary-side transmitting circuit to the primary-side receiving circuit in an isolated manner may be provided in the isolation circuit 130. When some abnormality (e.g., a negative voltage abnormality, which will be described later) is detected in the secondary-side circuit 1200, an abnormality detection signal indicating that the abnormality has been detected can be transmitted from the secondary-side transmitting circuit to the primary-side receiving circuit via the other transformer, and when the first signal processing circuit 1110 receives the abnormality detection signal, it can transmit a predetermined error signal to the MPU 1400.

[0174] FIG. 16 shows the relationship between the control signals Din and Dout. In the initial state, the control signals Din and Dout are at low levels. The transmitter circuit 1111 generates a received pulse signal (electromotive force) across the secondary coil of the transformer 1310 by supplying a transmission pulse signal (pulse-shaped current) to the primary coil of the transformer 1310 in response to a rising edge in the control signal Din. The receiver circuit 1211 generates a rising edge in the control signal Dout based on the received pulse signal in the secondary coil of the transformer 1310. The transmitter circuit 1111 generates a received pulse signal (electromotive force) across the secondary coil of the transformer 1320 by supplying a transmission pulse signal (pulse-shaped current) to the primary coil of the transformer 1320 in response to a falling edge in the control signal Din. The relationship between the level of the control signal Din and the level of the control signal Dout may be reversed from that described above, but here, it is assumed that the receiving circuit 1211 is configured so that the control signal Dout has a high level during the high level period of the control signal Din and so that the control signal Dout has a low level during the low level period of the control signal Din (for the sake of simplicity, signal delay is ignored).

[0175] The isolation circuit 1300 may have any configuration as long as it can transmit the control signal Din to the secondary side circuit 1200 in an isolated manner and obtain the above-mentioned control signal Dout in the secondary side circuit 1200. Therefore, the isolation element in the isolation circuit 1300 may be a capacitor.

[0176] The second signal processing circuit 1210 drives the gate of the target transistor MO by controlling the state of the driver DRV in response to the control signal Dout. Driving the gate of the target transistor MO controls the gate voltage of the target transistor MO, thereby setting the state of the target transistor MO to on or off. The driver DRV has transistors MH and ML connected in series. The transistor MH is a high-side transistor made of a P-channel MOSFET, and the transistor ML is a low-side transistor made of an N-channel MOSFET. The source of the transistor MH is connected to the application terminal of the power supply voltage VCC2. The drains of the transistors MH and ML are commonly connected to the output terminal OUT. The source of the transistor ML is connected to the negative power supply terminal NEG. Therefore, the voltage at the source of the transistor ML is the voltage VEE2.

[0177] The second signal processing circuit 1210 is connected to the gates of the transistors MH and ML, and controls the gate voltages of the transistors MH and ML individually to turn the transistors MH and ML on or off individually. The second signal processing circuit 1210 is driven based on a power supply voltage VCC2 with respect to the potential of the ground GND2. However, the second signal processing circuit 1210 is connected not only to the power supply terminal PIN2 and the ground terminal GNDb but also to the negative power supply terminal NEG, and can properly turn off the transistor ML by supplying the voltage VEE2 at the negative power supply terminal NEG to the gate of the transistor ML.

[0178] The second signal processing circuit 1210 sets the state of the driver DRV to an output high state, an output low state, or a both-off state (Hi-Z state) based on the control signal Dout and a signal (described in detail later) supplied from the overvoltage detection circuit 1220. When the driver DRV is in the output high state, the transistor MH is on and the transistor ML is off. When the driver DRV is in the output low state, the transistor MH is off and the transistor ML is on. When the driver DRV is in the both-off state, both the transistors MH and ML are off.

[0179] When the driver DRV is in the output high state, positive charge is supplied from the application terminal of the power supply voltage VCC2 via the transistor MH and the output terminal OUT and through the wiring WR3 to the gate of the target transistor MO, thereby raising the gate voltage of the target transistor MO to the power supply voltage VCC2. When the driver DRV is in the output low state, positive charge is drawn from the gate of the target transistor MO through the wiring WR3 to the output terminal OUT and the transistor ML toward the negative power supply terminal NEG, thereby lowering the gate voltage of the target transistor MO to the voltage VEE2. In this way, the driver DRV drives the gate of the target transistor MO (controls the gate voltage) by inputting and outputting charge to and from the gate of the target transistor MO through the output terminal OUT and the wiring WR3. When the driver DRV is in the both-off state, no current is generated between the driver DRV and the gate of the target transistor MO.

[0180] When the gate voltage of the target transistor MO is equal to the power supply voltage VCC2, the target transistor MO is in an ON state. When the gate voltage of the target transistor MO is equal to the voltage VEE2, the target transistor MO is in an OFF state. That is, in response to the control signal Dout, the second signal processing circuit 1210 controls the target transistor MO to be ON by supplying a power supply voltage VCC2 (high-side voltage) higher than the potential of ground GND2 to the wiring WR3 using the driver DRV, and controls the target transistor MO to be OFF by supplying a voltage VEE2 (low-side voltage) lower than the power supply voltage VCC2 (high-side voltage) to the wiring WR3. However, when the driver DRV switches from the output low state to the output high state, the state of the target transistor MO switches from the OFF state to the ON state during the period in which the gate voltage of the target transistor MO rises from voltage VEE2 to the power supply voltage VCC2. Similarly, when the state of the driver DRV switches from the output high state to the output low state, the state of the target transistor MO switches from the on state to the off state during the period in which the gate voltage of the target transistor MO drops from the power supply voltage VCC2 to the voltage VEE2. In order to obtain the desired off characteristics in the target transistor MO during the period in which the target transistor MO should be controlled to be off, or to quickly turn the target transistor MO from the on state to the off state when the target transistor MO should be switched from the on state to the off state, the system of FIG. 11 introduces a negative voltage VEE2.

[0181] The overvoltage detection circuit 1220 is connected to the ground terminal GNDb and the negative power supply terminal NEG and detects whether an abnormality (hereinafter referred to as a negative voltage abnormality) has occurred in which the voltage VEE2 becomes excessively low relative to the potential of ground GND2. The overvoltage detection circuit 1220 outputs an overvoltage signal S_OVLO indicating the detection result of whether a negative voltage abnormality has occurred to the second signal processing circuit 1210, and controls the state of the protection switching element 1230 based on the detection result of whether a negative voltage abnormality has occurred. The overvoltage signal S_OVLO is a binary signal having a high level or a low level. The high-level overvoltage signal S_OVLO may have the potential of the power supply voltage VCC2, and the low-level overvoltage signal S_OVLO may have the potential of ground GND2. Of the high level and the low level of the overvoltage signal S_OVLO, one is assigned to an asserted state (active state), and the other is assigned to a negated state (inactive state). Here, it is assumed that the low-level overvoltage signal S_OVLO is in an asserted state, and the high-level overvoltage signal S_OVLO is in a negated state (however, the reverse may also be true).

[0182] The overvoltage detection circuit 1220 compares the differential voltage V_DIF between the voltage of ground GND2 and the voltage VEE2 with a threshold voltage Vth_OVLO. Here, the differential voltage V_DIF is assumed to have positive polarity when the voltage VEE2 is lower than the potential of ground GND2. The absolute value of the difference between the voltage of ground GND2 and the voltage VEE2 can be considered to be the differential voltage V_DIF. The threshold voltage Vth_OVLO has a predetermined positive voltage value (e.g., 8 V). In principle, the overvoltage detection circuit 1220 sets the overvoltage signal S_OVLO to a high level (negates it) and maintains the overvoltage signal S_OVLO at a high level if the differential voltage V_DIF is maintained below the threshold voltage Vth_OVLO. However, if the overvoltage detection circuit 1220 detects that the differential voltage V_DIF is equal to or greater than the threshold voltage Vth_OVLO, it outputs an asserted overvoltage signal S_OVLO (i.e., a low-level overvoltage signal S_OVLO). The difference voltage V_DIF being equal to or greater than the threshold voltage Vth_OVLO corresponds to the voltage VEE being lower than the voltage of the wiring WR2 by the threshold voltage Vth_OVLO or more, and the state in which the difference voltage V_DIF is equal to or greater than the threshold voltage Vth_OVLO is the above-mentioned negative voltage abnormality.

[0183] 17, the second signal processing circuit 1210 supplies the power supply voltage VCC2 to the wiring WR3 (to the gate of the target transistor MO) by setting the driver DRV to an output high state during a high-level period of the control signal Dout, on the condition that the overvoltage signal S_OVLO is in a negated state, thereby controlling the target transistor MO to be on. The second signal processing circuit 1210 supplies the voltage VEE2 to the wiring WR3 (to the gate of the target transistor MO) by setting the driver DRV to an output low state during a low-level period of the control signal Dout, on the condition that the overvoltage signal S_OVLO is in a negated state, thereby controlling the target transistor MO to be off. In other words, the second signal processing circuit 1210 switches the state of the driver DRV between an output high state and an output low state in response to the control signal Dout, on the condition that the overvoltage signal S_OVLO is in a negated state, thereby switching the target transistor MO between on and off. However, switching between the output high state and the output low state is a concept that includes setting the state of the driver DRV to both off states for a short dead time in order to prevent the occurrence of through current during the switching process, and a circuit that inserts the dead time may be included in the second signal processing circuit 1210.

[0184] The differential voltage V_DIF should normally be within the voltage range (e.g., 5 volts or less) defined by the specifications of the signal transmission device 1000. However, the differential voltage V_DIF may become excessively large due to an abnormality in the negative voltage generation circuit 1600 or an abnormality in another circuit that affects the differential voltage V_DIF. When a circuit abnormality occurs, it is undesirable to turn on the target transistor MO and supply current to the load LD. Taking this into consideration, the signal voltage transmission device 1000 is provided with a VEE2_OVLO function. The VEE2_OVLO function supplies the voltage VEE2 to the gate of the target transistor MO by setting the driver DRV to an output low state regardless of the control signal Dout (and therefore regardless of the control signal Din) when it is detected that the differential voltage V_DIF is equal to or greater than the threshold voltage Vth_OVLO. The VEE2_OVLO function is implemented by the second signal processing circuit 1210 in response to the overvoltage signal S_OVLO from the overvoltage detection circuit 1220. That is, as shown in FIG. 18, when an asserted overvoltage signal S_OVLO (low-level overvoltage signal S_OVLO) is output from the overvoltage detection circuit 1220, the second signal processing circuit 1210 sets the driver DRV to an output low state regardless of the control signal Dout, thereby supplying the voltage VEE2 to the wiring WR3 (and therefore to the gate of the target transistor MO) and performing a protection operation to set the target transistor MO to off.

[0185] The VEE2_OVLO function is useful for protecting the load LD when a negative voltage abnormality occurs. However, if the voltage VEE2 is supplied to the gate of the target transistor MO when the differential voltage V_DIF is considerably large, there is a concern that the voltage between the gate and emitter of the target transistor MO may exceed its withstand voltage. In consideration of this, the signal voltage supply device 1000 is provided with a protection switching element 1230. As shown in FIG. 11, the protection switching element 1230 is provided between the ground terminal GNDb and the negative power supply terminal NEG (in other words, between the wirings WR2 and WR4).

[0186] The overvoltage detection circuit 1220 supplies a signal SW_CNT to the protection switching element 1230 to set the protection switching element 1230 on or off. The signal SW_CNT has a value of "1" or "0", and the level of the signal SW_CNT having a value of "1" is different from the level of the signal SW_CNT having a value of "0". When the signal SW_CNT has a value of "1", the protection switching element 1230 is on, and when the signal SW_CNT has a value of "0", the protection switching element 1230 is off.

[0187] Only when the protection switching element 1230 is on, conduction occurs between the ground terminal GNDb and the negative power supply terminal NEG through the protection switching element 1230. During the on period of the protection switching element 1230, the magnitude of the voltage between the ground terminal GNDb and the negative power supply terminal NEG (i.e., the differential voltage V_DIF) is maintained at a voltage sufficiently lower than the threshold voltage Vth_OVLO. During the off period of the protection switching element 1230, the protection switching element 1230 has no effect on the voltage between the ground terminal GNDb and the negative power supply terminal NEG.

[0188] FIG. 19 is a timing chart illustrating operation upon detection of a voltage abnormality. From top to bottom, FIG. 19 shows the waveform of the voltage VEE2, the waveform of the differential voltage V_DIF, the waveform of the overvoltage signal S_OVLO, changes in the value of the signal SW_CNT, changes in the state of the protection switching element 1230, changes in the state of the driver DRV, and changes in the state of the target transistor MO. As shown in FIG. 19, during a high-level period of the overvoltage signal S_OVLO (i.e., during a period in which the overvoltage signal S_OVLO is negated), the overvoltage detection circuit 1220 supplies the signal SW_CNT having a value of “0” to the protection switching element 1230, thereby turning the protection switching element 1230 off. During a low-level period of the overvoltage signal S_OVLO (i.e., during a period in which the overvoltage signal S_OVLO is asserted), the overvoltage detection circuit 1220 supplies the signal SW_CNT having a value of “1” to the protection switching element 1230, thereby turning the protection switching element 1230 on. Figure 19 shows how the differential voltage V_DIF starts from a state in which it is maintained below the threshold voltage Vth_OVLO, and then increases until it reaches the threshold voltage Vth_OVLO, causing the overvoltage signal S_OVLO to switch from a negated state to an asserted state.

[0189] 20, a protection transistor 1231, which is a P-channel MOSFET, can be used as the protection switching element 1230. In this case, the source of the protection transistor 1231 is connected to the ground terminal GNDb, the drain of the protection transistor 1231 is connected to the negative power supply terminal NEG, and a signal SW_CNT1 is supplied as the signal SW_CNT to the gate of the protection transistor 1231. When the protection transistor 1231 is the protection switching element 1230, the protection transistor 1231 is turned off by supplying a high-level signal SW_CNT1 to the gate of the protection transistor 1231 as the signal SW_CNT having a value of "0", and the protection transistor 1231 is turned on by supplying a low-level signal SW_CNT1 to the gate of the protection transistor 1231 as the signal SW_CNT having a value of "1".

[0190] Here, the high-level signal SW_CNT1 has a potential equal to or higher than the potential of ground GND2. The potential of the low-level signal SW_CNT1 is lower than the potential of ground GND2, and the difference between the potentials of the low-level signal SW_CNT1 and ground GND2 is greater than the absolute value of the gate threshold voltage of the protection transistor 1231. The low-level signal SW_CNT1 may have a potential of voltage VEE2. In this case, the gate and drain of the protection transistor 1231 are shorted during the low-level period of the overvoltage signal S_OVLO. This leaves a voltage equal to the absolute value of the gate threshold voltage of the protection transistor 1231 between the ground terminal GNDb and the negative power supply voltage NEG. As a result, a voltage equal to the absolute value of the gate threshold voltage of the protection transistor 1231 is applied between the gate and emitter of the target transistor MO. However, this does not pose a problem because the magnitude of the gate threshold voltage of the protection transistor 1231 is sufficiently smaller than the threshold voltage Vth_OVLO and the breakdown voltage between the gate and emitter of the target transistor MO.

[0191] 21, a protection transistor 1232 which is an N-channel MOSFET may be used as the protection switching element 1230. In this case, the drain of the protection transistor 1232 is connected to the ground terminal GNDb, the source of the protection transistor 1232 is connected to the negative power supply terminal NEG, and a signal SW_CNT2 is supplied to the gate of the protection transistor 1232 as the signal SW_CNT. When the protection transistor 1232 is the protection switching element 1230, the protection transistor 1232 is turned off by supplying a low-level signal SW_CNT2 to the gate of the protection transistor 1232 as the signal SW_CNT having a value of "0", and the protection transistor 1232 is turned on by supplying a high-level signal SW_CNT2 to the gate of the protection transistor 1232 as the signal SW_CNT having a value of "1".

[0192] Here, the low-level signal SW_CNT2 has the potential of the voltage VEE2, and the high-level signal SW_CNT2 has the potential of the power supply voltage VCC2. The high-level signal SW_CNT2 may have the potential of the ground GND2. When the high-level signal SW_CNT2 has the potential of the ground GND2, during the low-level period of the overvoltage signal S_OVLO, the gate and drain of the protection transistor 1232 are short-circuited. As a result, a voltage corresponding to the gate threshold voltage of the protection transistor 1232 remains between the ground terminal GNDb and the negative power supply voltage NEG. Consequently, a voltage corresponding to the gate threshold voltage of the protection transistor 1232 is applied between the gate and emitter of the target transistor MO. However, since the gate threshold voltage of the protection transistor 1232 is sufficiently smaller than the threshold voltage Vth_OVLO and the breakdown voltage between the gate and emitter of the target transistor MO, no problem occurs.

[0193] In the example of FIG. 19, after the period during which the negative overvoltage signal S_OVLO is output from the overvoltage detection circuit 1220, at time t A it transitions from the state where "V_DIF < Vth_OVLO" holds to the state where "V_DIF ≥ Vth_OVLO" holds. In response to this transition, the overvoltage detection circuit 1220 switches the state of the overvoltage signal S_OVLO from the negative state to the assert state. After switching the state of the overvoltage signal S_OVLO from the negative state to the assert state, the overvoltage detection circuit 1220 continues to output the assert-state overvoltage signal S_OVLO until a predetermined release condition is satisfied, and when the release condition is satisfied, it returns the state of the overvoltage signal S_OVLO to the negative state. If the overvoltage signal S_OVLO is in the assert state, the protection switching element 1230 is maintained in the on state. When the overvoltage detection circuit 1220 returns the overvoltage signal S_OVLO to the negative state, it returns the value of the signal SW_CNT from "1" to "0" to return the state of the protection switching element 1230 from the on state to the off state.

[0194] For example, the release condition may be satisfied when a rising edge occurs in the control signal Dout. In this case, at time t AAfter the state of the overvoltage signal S_OVLO is switched from the negated state to the asserted state at time t, the overvoltage signal S_OVLO is maintained in the asserted state and the protection switching element 1230 is maintained in the on state until a rising edge occurs in the control signal Dout. A After that, when a rising edge occurs in the control signal Dout, the overvoltage signal S_OVLO is switched from the asserted state to the negated state, and the protection switching element 1230 is switched from the on state to the off state. A signal indicating that a rising edge has occurred in the control signal Dout is transmitted from the second signal processing circuit 1210 to the overvoltage detection circuit 1220.

[0195] When the release condition is met by the occurrence of a rising edge in the control signal Dout, A If the negative voltage abnormality is resolved after time t, the MPU 1400 can subsequently supply the signal transmission device 1000 with a control signal Din that transitions between high and low levels to turn on and off the target transistor MO. A If the negative voltage abnormality continues to occur after that, the overvoltage signal S_OVLO is immediately set to the asserted state.

[0196] Alternatively, the release condition may be any other condition. The release condition may be satisfied by inputting a predetermined release signal to a specific external terminal provided on the signal transmission device 1000. Alternatively, the release condition may be satisfied by inputting a predetermined release command signal from the MPU 1400 to the signal transmission device 1000.

[0197] According to the signal transmission device 1000 shown in FIG. 11, the VEE2_OVLO function is realized, while the application of an excessive voltage to the gate-emitter voltage of the target transistor MO is suppressed.

[0198] <<Deformation, etc.>> The following describes application techniques, modifications, or supplements to the above-described system SYS or signal transmission device 1000.

[0199] 11, the second signal processing circuit 1210 and the driver DRV can be considered to form a control circuit. In this case, the control signal Din or Dout can be considered to be an input control signal. The control circuit (1210, DRV) controls the target transistor MO to be on by supplying a power supply voltage VCC2 (high-side voltage) to the wiring WR3 in response to the input control signal (Din, Dout), or controls the target transistor MO to be off by supplying a voltage VEE2 (low-side voltage) lower than the power supply voltage VCC2 to the wiring WR3.

[0200] 22, the system SYS includes a switching device 2000. The switching device 2000 can be understood as a device obtained by removing the MPU 1400, the load LD, and the voltage source VS from the system SYS in FIG. 11, and therefore has at least the signal transmission device 1000, the target transistor MO, the resistor circuit 1500, and the negative voltage generation circuit 1600 as components. However, the negative voltage generation circuit 1600 may also be understood as being provided outside the switching device 2000 and connected to the switching device 2000.

[0201] Two sets of switching devices 2000 may be provided, and a half-bridge circuit may be formed by connecting the target transistor MO in the first set of switching devices 2000 in series with the target transistor MO in the second set of switching devices 2000. In this case, the MPU 1400 connected to each set of signal transmission devices 1000 may be the same. The source potential of the target transistor MO in the i-th set of switching devices 2000 functions as the ground GND2 in the i-th set of switching devices 2000 (where i is 1 or 2).

[0202] A motor drive system having six sets of switching devices 2000 may be formed to drive a three-phase motor. In this case, the target transistors MO in the first and second sets of switching devices 2000 may be used as the upper and lower arms of the U phase, the target transistors MO in the third and fourth sets of switching devices 2000 may be used as the upper and lower arms of the V phase, and the target transistors MO in the fifth and sixth sets of switching devices 2000 may be used as the upper and lower arms of the W phase. Then, by controlling the on / off of the six sets of target transistors MO, the currents supplied to the U-, V-, and W-phase coils of the three-phase motor may be controlled. In this motor drive system, the MPU 1400 connected to each set of signal transmission devices 1000 may be the same. The source potential of the target transistor MO in the i-th set of switching devices 2000 functions as the ground GND2 of the i-th set of switching devices 2000 (where i is an integer between 1 and 6).

[0203] 11 or any system including the system SYS (such as the motor drive system described above) can be mounted in any electrical device. The electrical device may be an electrical component mounted in a vehicle such as an automobile, a computer device, a home appliance, or an industrial device.

[0204] Although the technology related to the VEE2_OVLO function has been described for the signal transmission device 1000 having the configuration shown in Fig. 11, this technology may be applied to any semiconductor device. For example, a semiconductor device (hereinafter referred to as a modified semiconductor device) may be formed by excluding the primary side circuit 1100 and the isolation circuit 1300 from the signal transmission device 1000 of Fig. 11. In this modified semiconductor device, the control signal Din from the MPU 1400 itself becomes the control signal Dout.

[0205] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0206] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0207] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first conduction electrode, a second conduction electrode, and a control electrode. In an FET, one of the first and second conduction electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second conduction electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second conduction electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0208] When an N-channel MOSFET is used as the target transistor MO, the drain of the target transistor MO is connected to a wiring WR1, the source of the target transistor MO is connected to a wiring WR2, and the gate of the target transistor MO is connected to a wiring WR3, whether the target transistor MO is an IGBT or a MOSFET.

[0209] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0210] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0211] A semiconductor device according to one aspect of the present disclosure (see FIG. 11) is a semiconductor device (1100) configured to control the state of a target transistor (MO) having a first conduction electrode, a second conduction electrode, and a control electrode, wherein the target transistor is configured so that the first conduction electrode is connected to a first wiring (WR1), the second conduction electrode is connected to a second wiring (WR2), and the control electrode is connected to a third wiring (WR3), and the semiconductor device controls the target transistor to be on by supplying a high-side voltage (VCC2) higher than the voltage of the second wiring to the third wiring in response to input control signals (Din, Dout), or controls the target transistor to be on by supplying a low-side voltage (VEE2) lower than the high-side voltage to the third wiring. The first configuration comprises a control circuit (1210, DRV) configured to control a target transistor to be turned off, an overvoltage detection circuit (1220) configured to output an overvoltage signal (S_OVLO) in an asserted state when the low-side voltage is lower than the voltage of the second wiring by a predetermined threshold voltage (Vth_OVLO) or more, and a protection switching element (1230) provided between the second wiring and a fourth wiring (WR4) to which the low-side voltage is applied, wherein when the overvoltage detection circuit outputs the overvoltage signal in an asserted state, the control circuit performs an operation of supplying the low-side voltage to the third wiring regardless of the input control signal, and the protection switching element is set on by the overvoltage detection circuit.

[0212] This provides the function of shutting off the target transistor when the low-side voltage is excessively low compared to the voltage of the second wiring, while preventing excessive voltage from being applied between the control electrode and second conduction electrode of the target transistor, thereby protecting the target transistor.

[0213] In the semiconductor device according to the first configuration (see FIGS. 11 and 19), the overvoltage detection circuit outputs the overvoltage signal in the asserted state or the negated state according to the difference (V_DIF) between the voltage of the second wiring and the low-side voltage, and after a period in which the overvoltage signal in the negated state is output from the overvoltage detection circuit, when the difference between the voltage of the second wiring and the low-side voltage transitions from a state in which it is less than the threshold voltage to a state in which the low-side voltage is lower than the voltage of the second wiring by the threshold voltage or more (time t A ), the overvoltage detection circuit may be configured to switch the state of the overvoltage signal to the asserted state (second configuration).

[0214] In the semiconductor device according to the second configuration, the overvoltage detection circuit may be configured (third configuration) to continue outputting the asserted overvoltage signal after switching the state of the overvoltage signal to the asserted state until a predetermined release condition is met.

[0215] In the semiconductor device according to the third configuration, the control circuit may be configured (fourth configuration) such that, during a period in which the overcurrent signal is in the negated state, the control circuit controls the target transistor to be on by supplying the high-side voltage to the third wiring when the input control signal has a first level, and controls the target transistor to be off by supplying the low-side voltage to the third wiring when the input control signal has a second level, and the release condition is met when the input control signal switches from the second level to the first level.

[0216] In the semiconductor device according to any of the first to fourth configurations (see FIG. 11), the control circuit may be configured (fifth configuration) to include a driver (DRV) having a high-side transistor (MH) provided between the application terminal of the high-side voltage and the third wiring and a low-side transistor (ML) provided between the third wiring and the fourth wiring, and to supply the high-side voltage to the third wiring by setting the high-side transistor on and the low-side transistor off, and to supply the low-side voltage to the third wiring by setting the high-side transistor off and the low-side transistor on.

[0217] In the semiconductor device according to any one of the first to fifth configurations, the target transistor may be an insulated gate bipolar transistor, and the first conduction electrode, the second conduction electrode, and the control electrode may be a collector, an emitter, and a gate, respectively (sixth configuration).

[0218] In the semiconductor device according to any one of the first to fifth configurations, the target transistor may be a field effect transistor, and the first conduction electrode, the second conduction electrode and the control electrode may be a drain, a source and a gate, respectively (seventh configuration).

[0219] A semiconductor device according to any of the first to seventh configurations may be a signal transmission device (1000) provided between an external device (1400) and the target transistor, comprising a primary circuit (1100) configured to receive a primary control signal (Din) from the external device, a secondary circuit (1200) configured to drive a control electrode of the target transistor, and an isolation circuit (1300) configured to transmit the primary control signal to the secondary circuit as a secondary control signal while providing DC insulation between the primary circuit and the secondary circuit, wherein the control circuit, the overvoltage detection circuit, and the protection switching element are provided in the secondary circuit, and the primary control signal or the secondary control signal is the input control signal (eighth configuration).

[0220] A switching device according to one aspect of the present disclosure has a configuration (ninth configuration) including the semiconductor device according to any one of the first to eighth configurations and the target transistor. [Explanation of symbols]

[0221] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias 1000 Signal Transmission Device 1100 Primary circuit 1110 First signal processing circuit 1111 Transmitting circuit 1200 Secondary circuit 1210 Second signal processing circuit 1211 receiving circuit 1220 Overvoltage detection circuit 1230 Protection Switching Element 1231, 1232 Protection transistors DRV driver MH, ML transistors 1300 Isolated Circuit 1310, 1320 transformer 1400 MPU 1500, 1510, 1520 resistance circuit 1511, 1521, 1522 Resistors 1523, 1524 Diodes 1600, 1610 Negative voltage generator circuit 1611 Zener diode 1612 Resistance MO target transistor LD load VCC1, VCC2, VPWR power supply voltage VEE2 voltage VS, VS2 voltage source PIN1, PIN2 power terminals GNDa, GNDb Ground terminals SIN signal input terminal OUT output terminal Din, Dout control signals S_OVLO Overvoltage signal WR1~WR4 wiring 2000 Switching Device

Claims

1. A semiconductor device configured to control a state of a target transistor having a first conduction electrode, a second conduction electrode, and a control electrode, the target transistor being configured such that the first conduction electrode is connected to a first wiring, the second conduction electrode is connected to a second wiring, and the control electrode is connected to a third wiring, the semiconductor device comprising: a control circuit configured to control the target transistor to be turned on by supplying a high-side voltage higher than a voltage of the second wiring to the third wiring in response to an input control signal, or to control the target transistor to be turned off by supplying a low-side voltage lower than the high-side voltage to the third wiring; an overvoltage detection circuit configured to output an overvoltage signal in an asserted state when the low-side voltage is lower than the voltage of the second wiring by a predetermined threshold voltage or more; a protection switching element provided between the second wiring and a fourth wiring to which the low-side voltage is applied, When the overvoltage signal in the asserted state is output from the overvoltage detection circuit, the control circuit executes an operation of supplying the low-side voltage to the third wiring regardless of the input control signal, and the protection switching element is set to ON by the overvoltage detection circuit. , semiconductor device.

2. the overvoltage detection circuit outputs the overvoltage signal in the asserted state or the negated state according to a difference between the voltage of the second line and the low-side voltage; After a period in which the overvoltage signal in the negated state is output from the overvoltage detection circuit, when the difference between the voltage of the second line and the voltage of the low side transitions from a state in which it is less than the threshold voltage to a state in which the voltage of the low side is lower than the voltage of the second line by at least the threshold voltage, the overvoltage detection circuit switches the state of the overvoltage signal to the asserted state. The semiconductor device according to claim 1 .

3. After switching the state of the overvoltage signal to the asserted state, the overvoltage detection circuit continues to output the overvoltage signal in the asserted state until a predetermined release condition is met. The semiconductor device according to claim 2 .

4. the control circuit controls the target transistor to be turned on by supplying the high-side voltage to the third wiring when the input control signal has a first level during a period in which the overcurrent signal is in the negated state, and controls the target transistor to be turned off by supplying the low-side voltage to the third wiring when the input control signal has a second level; The release condition is met when the input control signal switches from the second level to the first level. The semiconductor device according to claim 3 .

5. The control circuit includes a driver having a high-side transistor provided between an application terminal of the high-side voltage and the third wiring and a low-side transistor provided between the third wiring and the fourth wiring, and supplies the high-side voltage to the third wiring by setting the high-side transistor on and the low-side transistor off, and supplies the low-side voltage to the third wiring by setting the high-side transistor off and the low-side transistor on.

5. The semiconductor device according to claim 1.

6. The target transistor is an insulated gate bipolar transistor, and the first conduction electrode, the second conduction electrode, and the control electrode are a collector, an emitter, and a gate, respectively.

5. The semiconductor device according to claim 1.

7. The target transistor is a field effect transistor, and the first conductive electrode, the second conductive electrode, and the control electrode are a drain, a source, and a gate, respectively.

5. The semiconductor device according to claim 1.

8. The semiconductor device is a signal transmission device provided between an external device and the target transistor, a primary side circuit configured to receive a primary side control signal from the external device; a secondary-side circuit configured to drive a control electrode of the target transistor; an isolation circuit configured to transmit the primary side control signal to the secondary side circuit as a secondary side control signal while providing DC insulation between the primary side circuit and the secondary side circuit, The control circuit, the overvoltage detection circuit, and the protection switching element are provided in the secondary side circuit, and the primary side control signal or the secondary side control signal is the input control signal.

5. The semiconductor device according to claim 1.

9. A semiconductor device according to any one of claims 1 to 4, the target transistor; , switching device.

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