Quantum computation support method, and information processing apparatus

Abstract

To suppress prolongation of an execution time of a phase rotation gate.SOLUTION: An information processor 10 sets each of a plurality of partial areas 3a, 3b in an available area 4 where a physical quantum bit available for phase rotation of a first rotation angle of a state of a logical quantum bit 2 is disposed as an operation object. The information processor 10 causes the quantum computer 1 to execute a generation operation of a first auxiliary state used for phase rotation by a first rotation angle for each of the plurality of partial regions 3a and 3b. Then, the information processing apparatus 10 causes the quantum computer 1 to perform a phase rotation operation on the logical qubit 2 using the first auxiliary state indicated by the first partial region in which the first auxiliary state has been successfully generated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a quantum computing assistance program, a quantum computing assistance method, and an information processing device. [Background technology]

[0002] In calculations using a quantum computer, quantum calculations are performed according to quantum circuits by performing gate operations on quantum bits. A quantum bit is the smallest unit of information used in calculations, and is equivalent to a bit (classical bit) in a classical computer. However, unlike classical bits, quantum bits can also be in a superposition state of "0" and "1."

[0003] The information in quantum bits can be corrupted (errors can occur) due to interactions with the environment, errors in gate operation, etc. There are two ways to deal with errors: quantum error correction and quantum error mitigation.

[0004] Quantum error correction is a process of detecting and correcting errors by combining and encoding (redundant) multiple quantum bits. Hereafter, unencoded quantum bits are referred to as physical quantum bits, and a set of encoded quantum bits is referred to as logical quantum bits. Quantum error mitigation is a process of proceeding with calculations while including errors, and mitigating the effects of errors by modifying quantum circuits or extrapolating measurement results.

[0005] A quantum computer that performs quantum computations while performing quantum error correction on logical qubits is called a fault-tolerant quantum computer (FTQC). In an FTQC, any quantum computation can be performed by combining certain basic gates. Examples of certain basic gates are the H gate, CNOT gate, S gate, and T gate. The H gate, CNOT gate, and S gate are quantum gates that perform Clifford operations, and the T gate is a quantum gate that performs non-Clifford operations. A set of these basic gates is called Clifford+T.

[0006] Among the basic gates of Clifford+T, the T gate uses a large number of physical qubits for error correction, which makes it difficult to realize FTQC using Clifford+T.

[0007] As a technology to reduce the number of physical qubits used for error correction, a highly efficient phase rotation gate quantum computing architecture called STAR (Space-Time Efficient Analog Rotation quantum computing) architecture has been proposed. Also, a method called lattice surgery has been proposed as a method for applying gate operations to logical qubits. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Yutaro Akahoshi, Kazunori Maruyama, Hirotaka Oshima, Shintaro Sato, and Keisuke Fujii, "Partially Fault-tolerant Quantum Computing Architecture with Error-corrected Clifford Gates and Space-time Efficient Analog Rotations", PRX Quantum 5, 010337, 5 March 2024 [Non-patent document 2] Dominic Horsman, Austin G Fowler, Simon Devitt and Rodney Van Meter, "Surface code quantum computing by lattice surgery", New Journal of Physics, 7 December 2012, Volume 14 [Non-patent document 3] Daniel Litinski, "A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery", Quantum, 2019-03-05, volume 3, page 128 Summary of the Invention [Problem to be solved by the invention]

[0009] In the STAR architecture, a phase rotation gate is used instead of the T gate of Clifford+T. The phase rotation gate is realized using the logical qubit of the auxiliary state. Therefore, the execution time of the phase rotation gate is affected by the time required to generate the auxiliary state. If the physical error of the physical qubit used to generate the auxiliary state is large, or if the code distance of the logical qubit representing the auxiliary state is large, the probability of failure in the generation process of the auxiliary state becomes very high. If the generation of the auxiliary state fails multiple times and the generation process of the auxiliary state is repeated, the execution time of the phase rotation gate becomes long.

[0010] In one aspect, the present invention aims to prevent the execution time of a phase rotation gate from becoming long. [Means for solving the problem]

[0011] In one proposal, a quantum computing assistance program is provided that causes a computer to perform the following processes. The computer causes the quantum computer to perform an operation to generate a first auxiliary state to be used for the phase rotation by the first rotation angle, with each of a plurality of partial regions in the available region in which physical quantum bits that can be used for the phase rotation of the state of the logical quantum bit by the first rotation angle being the operation target.The computer then causes the quantum computer to perform a phase rotation operation using the first auxiliary state indicated in the first partial region in which the generation of the first auxiliary state was successful, with the logical quantum bit being the operation target. [Effects of the Invention]

[0012] According to one aspect, it is possible to prevent the execution time of the phase rotation gate from becoming longer. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of a quantum computing assistance method according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of a quantum computing system. [Figure 3] FIG. 1 is a diagram illustrating an example of hardware of a quantum computing system. [Figure 4] FIG. 1 illustrates the characteristics of a quantum bit. [Figure 5] FIG. 1 illustrates an example of quantum error correction. [Figure 6] FIG. 1 is a diagram illustrating an example of a basic gate used in error-tolerant quantum computing. [Figure 7] FIG. 1 is a diagram illustrating an example of a quantum circuit that performs gate operations for phase rotation. [Figure 8] FIG. 10 is a diagram showing an example of injection. [Figure 9] FIG. 10 is a diagram showing an example of enlarging to a surface code. [Figure 10] FIG. 10 is a diagram illustrating an example of an injection failure probability. [Figure 11] FIG. 10 is a diagram illustrating the relationship between logical quantum bits and patches. [Figure 12] FIG. 1 is a diagram showing an example of joining and separating, which are basic operations of lattice surgery. [Figure 13] FIG. 1 is a diagram showing an example of deformation, which is a basic operation of lattice surgery. [Figure 14] FIG. 1 is a diagram illustrating an example of logic gate operation by lattice surgery. [Figure 15] FIG. 10 is a diagram showing an example of logic CNOT gate operation by lattice surgery. [Figure 16] FIG. 1 is a diagram illustrating an example of an arrangement of logical quantum bits. [Figure 17]FIG. 10 is a diagram illustrating an example of a method for realizing a phase rotation gate using lattice surgery. [Figure 18] FIG. 10 is a diagram illustrating an example of parallel injection. [Figure 19] FIG. 10 is a diagram illustrating an example of pre-injection. [Figure 20] FIG. 10 is a diagram illustrating an example of the execution process of a phase rotation gate with parallel injection and pre-injection. [Figure 21] FIG. 10 is a diagram illustrating an example of a real-time update process of an injection region. [Figure 22] FIG. 10 is a diagram illustrating an example of a method for allocating free space. [Figure 23] FIG. 10 is a diagram illustrating an example of a connection between a patch that has been successfully injected and a patch that is a target of operation. [Figure 24] FIG. 1 is a block diagram showing an example of functions for quantum computing in a quantum computing system. [Figure 25] FIG. 10 is a diagram illustrating an example of functions of a phase rotation control unit. [Figure 26] FIG. 10 is a diagram illustrating an example of functions of an injection region determination unit. [Figure 27] FIG. 2 is a diagram illustrating an example of functions of an RUS execution control unit. [Figure 28] 1 is a flowchart illustrating an example of a procedure for quantum computing assisted processing on a classical computer. [Figure 29] 10 is a flowchart illustrating an example of a procedure for quantum circuit execution processing. [Figure 30] 10 is a flowchart illustrating an example of a procedure for phase rotation processing. [Figure 31] 10 is a flowchart (1 / 2) showing an example of the procedure of the injection and logical ZZ measurement process. [Figure 32] 10 is a flowchart (2 / 2) showing an example of the procedure of the injection and logical ZZ measurement process. [Figure 33] 10 is a flowchart illustrating an example of a procedure for an injection region update process. [Figure 34] FIG. 10 is a diagram showing a first example of verification results of the gate operation time of a phase rotation gate. [Figure 35] FIG. 10 is a diagram showing a second example of verification results of the gate operation time of the phase rotation gate. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented in combination with a plurality of other embodiments within a range that does not contradict each other. [First embodiment] The first embodiment is a quantum computing assistance method for preventing the execution time of a logic gate operation of a phase rotation gate on a logical quantum bit from increasing.

[0015] Fig. 1 is a diagram illustrating an example of a quantum computing assisted method according to a first embodiment. Fig. 1 illustrates an information processing device 10 for implementing the quantum computing method. The information processing device 10 can implement the quantum computing assisted method by, for example, executing a quantum computing assisted program.

[0016] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device included in the information processing device 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10.

[0017] The storage unit 11 stores the quantum circuit 5, which indicates the procedure of quantum computation. The quantum circuit 5 is, for example, a quantum circuit that combines a Clifford gate and a phase rotation gate 5a. The processing unit 12 controls the quantum computer 1 to realize quantum computation in accordance with the quantum circuit 5. The processing unit 12 causes the quantum computer 1 to execute the gate operations of the quantum gates indicated in the quantum circuit 5. When it is the turn to execute the phase rotation gate 5a, the processing unit 12 causes the quantum computer 1 to execute the phase rotation in the following procedure. Note that the rotation angle "θ" of the phase rotation gate 5a is defined as the first rotation angle.

[0018] Processing unit 12 identifies available region 4 in which physical quantum bits that can be used for phase rotation of the state of logical quantum bit 2 by the first rotation angle "θ" are arranged. For example, among the regions in which physical quantum bits are arranged, available region 4 is set to be an empty region (a region in which physical quantum bits that are not used in other calculations are arranged) adjacent to logical quantum bit 2 that is the target of the phase rotation operation.

[0019] In the region where the physical quantum bits are arranged, for example, a blank calculation region is provided that is not allocated to quantum bits included as operation targets in quantum circuit 5. The blank calculation region is managed by dividing it into subregions 3a to 3c, each having a size corresponding to the code distance of logical quantum bit 2. The identification number of subregion 3a is "0", the identification number of subregion 3b is "1", and the identification number of subregion 3c is "2".

[0020] In the example of Figure 1, subregion 3c is being used for a logical quantum gate operation other than that of phase rotation gate 5a to be executed. Therefore, subregions 3a and 3b, which are consecutive free regions adjacent to the region representing logical quantum bit 2 that is the target of operation of phase rotation gate 5a, become available region 4.

[0021] The processing unit 12 sets each of the plurality of partial areas 3 a and 3 b in the available area 4 as an operation target, and calculates a first auxiliary state (|m θ > L ) for each of the plurality of partial regions 3a and 3b. θ > L ) can be generated in parallel. θ > L The generation operation of the first auxiliary state (|m θ > L The success or failure of the generation operation of ) depends on, for example, the first auxiliary state (|m θ > L This can be determined by running an error detection circuit on the code representing

[0022] In the example of FIG. 1, in the subregion 3a, the first auxiliary state (|m θ > L ) is successfully generated, but in subregion 3b, the first auxiliary state (|m θ > L The processing unit 12 fails to generate the first auxiliary state (|m θ > L ) has been successfully generated.

[0023] Therefore, the processing unit 12 operates on the logical quantum bit 2 to generate the first auxiliary state (|m θ > L The first auxiliary state (|m θ > L ) is made to execute a phase rotation operation using quantum computer 1.

[0024] In this way, the first auxiliary state (|m θ > L ) are generated in parallel, the first auxiliary state (|m θ > L ) can be generated early. As a result, the first auxiliary state (|m θ > L This prevents the phase rotation operation from being prolonged due to repeated failures in generating the phase.

[0025] For the logical quantum gate operation of phase rotation, a phase rotation circuit can be used that stochastically applies either a phase rotation in a desired rotation direction or a phase rotation in a direction opposite to the desired rotation direction to the logical quantum bit 2. When a phase rotation in the opposite direction occurs by executing such a phase rotation circuit, the processing unit 12 changes the rotation angle to twice that of the second auxiliary state (|m 2θ > L ) and its second auxiliary state (|m 2θ > L) to perform the phase rotation operation again. This type of phase rotation circuit has a short calculation time per operation, so even if the phase rotation must be repeated several times, the time required to achieve the desired phase rotation can be shortened.

[0026] When a phase rotation circuit in which the rotation direction is probabilistic is used, the processing unit 12 anticipates that the rotation will be reversed and pre-registers the second auxiliary state (|m 2θ > L For example, the processing unit 12 can generate a first auxiliary state (|m θ > L If the generation of the logical quantum bit 2 is successful, the quantum computer 1 is caused to execute a phase rotation circuit in which the direction of rotation is probabilistic and the logical quantum bit 2 is the object of operation.

[0027] Next, while the quantum computer 1 is executing the phase rotation circuit, the processing unit 12 identifies a second partial region (partial region 3b) that is not used by the phase rotation circuit among the multiple partial regions 3a and 3b in the available region 4. The processing unit 12 operates on the identified second partial region as an operation target, and generates a second auxiliary state (|m 2θ > L ) is generated by the quantum computer 1.

[0028] When the phase rotation circuit executes a reverse phase rotation, the processing unit 12 operates on the logical quantum bit 2 as the operation target, and converts the logical quantum bit 2 into the second auxiliary state (|m 2θ > L ) as an input to the quantum computer 1. In the example of FIG. 1, the second auxiliary state (|m 2θ > L ) is expanded to the sub-region 3a adjacent to the logical qubit 2 to be operated. Then, the second auxiliary state (|m 2θ > L ) is used to perform the phase rotation operation.

[0029] In this way, the second auxiliary state (|m 2θ > L ), when the phase rotation is reversed, the next translation rotation operation becomes possible immediately. As a result, phase rotation can be efficiently performed when using a phase rotation circuit in which the rotation direction is probabilistic.

[0030] The operation of generating the auxiliary state can be performed in a shorter time than the gate operation of the phase rotation circuit, in which the rotation direction is probabilistic. Therefore, the processing unit 12 generates the second auxiliary state (|m 2θ > L ) is successfully generated, the second auxiliary state (|m 2θ > L ) may be repeatedly generated by the quantum computer 1. By this means, the second auxiliary state (|m 2θ > L ) is more likely to be successfully generated.

[0031] The processing unit 12 determines the second auxiliary state (|m 2θ > L ), the phase rotation is assumed to be reversed, and the rotation angle is further doubled to create the third auxiliary state (|m 4θ > L In this case, if there is an area that has become vacant during the previous phase rotation operation, the processing unit 12 can dynamically update the available area 4.

[0032] For example, the processing unit 12 updates the range of the available region 4 in accordance with the usage status of the physical quantum bits outside the available region 4 while the quantum computer 1 is performing the gate operation of the phase rotation circuit. In the example of FIG. 1, during the first phase rotation operation, the calculation using the subregion 3c is completed, and the subregion 3c is now free. Therefore, the processing unit 12 expands the range of the available region 4 to a range that includes the subregion 3c. This results in the second auxiliary state (|m 2θ > L) during the second phase rotation operation (the third auxiliary state (|m 4θ > L ) can be generated using the subdomain 3c. 4θ > L ) can be generated in advance, so that even if the second phase rotation operation fails, the third phase rotation operation can be performed quickly.

[0033] In the example of Figure 1, the second auxiliary state (|m 2θ > L ) is successful, and the state of logical quantum bit 2 is a state in which the phase has been rotated by the first rotation angle from the original state. Processing unit 12 detects the success of the phase rotation and terminates the logic gate operation of phase rotation gate 5a.

[0034] It should be noted that, among the quantum gates shown in the quantum circuit 5, if the quantum bits to be operated do not overlap, multiple quantum gates can be executed in parallel. Therefore, multiple phase rotation gates 5a may be executed in parallel by the quantum computer 1. In this case, the processing unit 12 may allocate the free space so that the size of the available space of each of the multiple phase rotation gates 5a is as equal as possible.

[0035] For example, when there are multiple logical quantum bits 2 to be operated on, the processing unit 12 allocates areas that can be allocated to two or more of the available areas 4 corresponding to each of the multiple logical quantum bits 2 to the smaller available area of ​​the allocatable available area 4. This equalizes the sizes of the available areas 4. If there is a phase rotation gate whose available area 4 is smaller than the others, the logical gate operation of that phase rotation gate alone may be prolonged, which may result in a longer execution time for the quantum circuit 5. By equalizing the sizes of the available areas 4, it is possible to prevent such an increase in execution time.

[0036] Second Embodiment The second embodiment is a quantum computing system that can prevent the execution time of a phase rotation gate from increasing in quantum computing using the STAR architecture.

[0037] 2 is a diagram showing an example of the configuration of a quantum computing system. The quantum computing system 300 is a computer system that performs calculations using, for example, the principles of quantum mechanics. The quantum computing system 300 includes a classical computer 100 and a quantum computer 200. The classical computer 100 is a von Neumann computer. The quantum computer 200 is a non-von Neumann computer that performs quantum calculations by applying quantum gates to quantum bits.

[0038] A terminal device 30 is connected to the classical computer 100 via a network 20. The terminal device 30 is a computer used by a user who requests quantum computing by the quantum computing system 300. The classical computer 100 receives a quantum computing request, including a quantum circuit, from, for example, the terminal device 30. A quantum circuit indicates the order of gate operations on quantum bits by arranging elements such as quantum gates. A quantum bit is a bit that can represent a superposition state between the "0" state and the "1" state.

[0039] The classical computer 100 instructs the quantum computer 200 to perform a gate operation on a quantum bit in accordance with a quantum computation request received from the terminal device 30. In addition, the classical computer 100 obtains the measurement results of each quantum bit from the quantum computer 200.

[0040] The quantum computer 200 performs gate operations on quantum bits in accordance with instructions from the classical computer 100. The quantum computer 200 also measures the state of the quantum gate and transmits the measurement results to the classical computer 100.

[0041] FIG. 3 is a diagram illustrating an example of hardware for a quantum computing system. A classical computer 100 is entirely controlled by a processor 101. A memory 102 and multiple peripheral devices are connected to the processor 101 via a bus 109. The processor 101 may be a multiprocessor. The processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or a DSP (Digital Signal Processor). At least some of the functions realized by the processor 101 executing a program may be realized by an electronic circuit such as an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device).

[0042] The memory 102 is used as a main storage device of the classical computer 100. The memory 102 temporarily stores at least a portion of the OS (Operating System) program and application programs to be executed by the processor 101. The memory 102 also stores various data used in processing by the processor 101. As the memory 102, for example, a volatile semiconductor storage device such as a RAM (Random Access Memory) is used.

[0043] The peripheral devices connected to the bus 109 include a storage device 103, a GPU (Graphics Processing Unit) 104, an input interface 105, an optical drive device 106, a device connection interface 107, and a network interface 108.

[0044] The storage device 103 writes and reads data electrically or magnetically to and from a built-in recording medium. The storage device 103 is used as an auxiliary storage device for the classical computer 100. The storage device 103 stores the OS program, application programs, and various data. Note that the storage device 103 may be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0045] The GPU 104 is an arithmetic unit that performs image processing. The GPU 104 is an example of a graphics controller. The GPU 104 is connected to a monitor 21. The GPU 104 displays an image on the screen of the monitor 21 in accordance with an instruction from the processor 101. The monitor 21 may be a display device using organic EL (Electro Luminescence) or a liquid crystal display device.

[0046] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 and the mouse 23 to the processor 101. The mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0047] The optical drive device 106 uses a laser beam or the like to read data recorded on an optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded so that it can be read by reflected light. The optical disc 24 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (Rewritable), and the like.

[0048] The device connection interface 107 is a communication interface for connecting peripheral devices to the classical computer 100. For example, a memory device 25 or a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 26 is a device for writing data to the memory card 27 or reading data from the memory card 27. The memory card 27 is a card-type recording medium.

[0049] The network interface 108 is connected to the network 20. The network interface 108 transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108 is a wired communication interface connected by a cable to a wired communication device such as a switch or a router. The network interface 108 may also be a wireless communication interface connected by radio waves to a wireless communication device such as a base station or an access point.

[0050] The quantum computer 200 shares a bus 109 with the classical computer 100. The quantum computer 200 can communicate information with each element in the classical computer 100 via the bus 109.

[0051] Quantum computer 200 has quantum processing unit 201 connected to bus 109. Quantum processing unit 201 performs gate operations on quantum bits according to quantum gates shown in the quantum circuit and measures the states of the quantum bits. Quantum processing unit 201 has quantum bit device 202 and quantum bit control signal generator 203. Quantum bit device 202 holds the states of multiple quantum bits and performs gate operations on those quantum bits. Quantum bit control signal generator 203 generates control signals that instruct gate operations or measurements on the quantum bits.

[0052] The quantum computing system 300 can realize the processing functions of the second embodiment by using the hardware described above. Note that the information processing device 10 shown in the first embodiment can also be realized by using hardware similar to that of the classical computer 100 shown in FIG.

[0053] The classical computer 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the classical computer 100 can be recorded on various recording media. For example, the program to be executed by the classical computer 100 can be stored in a storage device 103. The processor 101 loads at least a portion of the program in the storage device 103 into the memory 102 and executes the program. The program to be executed by the classical computer 100 can also be recorded on a portable recording medium such as an optical disk 24, a memory device 25, or a memory card 27. The program stored on the portable recording medium becomes executable after being installed on the storage device 103, for example, under the control of the processor 101. The processor 101 can also read and execute the program directly from the portable recording medium.

[0054] Next, we will provide an overview of error correction in quantum computing and explain the usefulness of the STAR architecture. FIG. 4 is a diagram showing the characteristics of a quantum bit. A quantum bit 41, which is the smallest unit of information in a quantum computer 200, can be in the state "|0>" and the state "|1>", and can also be in a superposition state between these. In the superposition state, whether the value obtained by measuring the quantum bit 41 is "|0>" or "|1>" is determined probabilistically. For example, if the probability of "|0>" and the probability of "|1>" are the same, the superposition state of the quantum bit 41 is "2>". -1 / 2 (|0>+|1>)".

[0055] The information held by such a quantum bit 41 can be corrupted (an error occurs) due to interactions with the environment or operational errors. For example, if an error destroys the superposition state, the state of the quantum bit 41 changes to a state like "|0>". To improve calculation accuracy, it is necessary to detect quantum bits in which an error has occurred and correct the state of the quantum bit to the correct state.

[0056] Therefore, a technology called quantum error correction has been proposed. In quantum error correction, a quantum bit is encoded using multiple quantum bits. When encoded, the state of one or multiple logical quantum bits is represented by the multiple physical quantum bits used for encoding. The quantum bit in which an error has occurred is detected and corrected based on the overall state of the multiple encoded quantum bits.

[0057] FIG. 5 is a diagram illustrating an example of quantum error correction. As shown in FIG. 5, a logical quantum bit 42 is defined by a plurality of physical quantum bits 42a, 42b, . . . , 42n. In the example of FIG. 5, when the states of the plurality of physical quantum bits 42a, 42b, . . . , 42n are all "|0>", an error occurs, and the state of physical quantum bit 42b is inverted to "|1>". In such a case, the error is detected based on information obtained from the respective states of the plurality of physical quantum bits 42a, 42b, . . . , 42n. Then, the physical quantum bit 42b in which the error occurred is identified, and the state of that physical quantum bit 42b is corrected.

[0058] By performing quantum error correction appropriately in this way, even if errors occur in the physical qubits, as long as the number of errors is within an allowable range, the logical qubit 42 will remain in a correct state. Quantum computation with quantum error correction for logical qubits can be realized by combining predetermined basic gates.

[0059] FIG. 6 shows an example of a basic gate used in error-tolerant quantum computing. The basic gates used in quantum computing with quantum error correction are an H gate 43a, a CNOT gate 43b, an S gate 43c, and a T gate 43d. The H gate 43a is called a Hadamard gate and is a quantum gate that rotates a state by 180 degrees around an axis tilted at 45 degrees between the Z axis and the X axis. The CNOT gate 43b is a quantum gate that leaves the state of the target bit unchanged if the state of the control bit is "|0>" and inverts the state of the target quantum bit if the state of the control bit is "|1>". The S gate 43c is a quantum gate that rotates the state by π / 2 around the Z axis. The T gate 43d is a quantum gate that rotates the state by π / 4 around the Z axis.

[0060] Of these, the H gate 43a, CNOT gate 43b, and S gate 43c are called Clifford operators. In contrast, the T gate is called a non-Clifford operator. These basic gates are collectively called Clifford+T. Clifford+T in calculations on the quantum computer 200 corresponds to AND, XOR, and NOT in the classical computer 100. In other words, by combining Clifford+T quantum gates, it is possible to perform any quantum calculation.

[0061] Here, in Clifford+T fault-tolerant quantum computing, typically more than one million physical qubits are used to perform useful calculations. A large proportion (e.g., more than 90%) of the large number of physical qubits is used to rotate the logical qubit by an arbitrary angle. Rotation by an arbitrary angle involves gate operations using a large number of T gates 43d. A large number of physical qubits are used for error correction of the T gates 43d (the error correction cost is high). This is a major factor in increasing the number of physical qubits required to realize FTQC.

[0062] Moreover, in order to realize a rotation operation of an arbitrary angle, in most cases, the gate operation of the T gate 43d must be repeated several tens of times. Therefore, realizing rotation of an arbitrary angle using the T gate 43d leads to a decrease in the execution efficiency of the quantum circuit.

[0063] Therefore, in the STAR architecture, a phase rotation gate 43e is used as a basic gate instead of the T gate 43d of Clifford+T. The phase rotation gate 43e in the STAR architecture is a gate that rotates a predetermined auxiliary state "|m θ > L This can be implemented using a phase rotation circuit using the ". The auxiliary states are sometimes called resource states.

[0064] Status "|m θ >" is "|m θ >=R Z (θ)|+>=2 -1 / 2 (e -iθ / 2 |0>+e +iθ / 2 |1>)". θ is an arbitrary rotation angle. Auxiliary state "|m θ > L The subscript L in " indicates that the state is represented by a redundant logical qubit. Similarly, hereafter, the subscript L will be added to the state of a logical qubit.

[0065] 7 is a diagram showing an example of a quantum circuit that performs gate operations for phase rotation. The phase rotation circuit 50 performs a phase rotation (R Z The phase rotation circuit 50 is a quantum circuit that realizes the state of the object to be manipulated, "|ψ> L " is input, and the second qubit is given the auxiliary state "|m θ > L " is entered.

[0066] In the phase rotation circuit 50, first, a logical ZZ measurement (M ZZ ) 50a is then taken. Then, the logical X measurement (M XIf the measurement result of logical X measurement 50b is "-1", a gate operation of Z gate 50c is performed on the first quantum bit.

[0067] If the result of the logical ZZ measurement is "+1", then the state of the first qubit is "R Z (θ)|ψ> L If the result of the logical ZZ measurement is "-1", the state of the first qubit is "R Z (-θ)|ψ> L " In this way, after the gate operation of the phase rotation by the phase rotation circuit 50, "R Z (θ)|ψ> L " or "R Z (-θ)|ψ> L " is obtained. In other words, the output state is probabilistically reversed. If the output state is "R Z (θ)|ψ> L " and "R Z (-θ)|ψ> L The probability of each being "1 / 2".

[0068] Since the output state of the phase rotation circuit 50 will stochastically result in the desired rotation (forward rotation) or reverse rotation, the quantum computing system 300 repeatedly executes the same gate operation until the desired rotation is successful.

[0069] For example, if a gating operation for a rotation of the desired angle θ fails, resulting in a reverse rotation (-θ), the quantum computing system 300 will perform a rotation of angle 2θ in the next gating operation for the rotation. If a gating operation for a rotation of angle 2θ also fails, resulting in a reverse rotation (-2θ), the sum of the two rotation operations will be -3θ. In this case, the quantum computing system 300 will perform a rotation of angle 4θ in the next gating operation for the rotation. Note that by performing processing using 2π periodicity, it is possible to ensure that the rotation angle always falls within [-π,π].

[0070] If the probability of a successful spin and the probability of an unsuccessful spin are 1 / 2, then the average number of times until a spin is successful is 1×(1 / 2)+2×(1 / 4)+=Σ n n2 -n=2". That is, the quantum computing system 300 can achieve phase rotation by executing the gate operation of the phase rotation circuit 50 an average of two times.

[0071] Hereinafter, the process of repeating stochastic phase rotation using the phase rotation circuit 50 until a target rotation angle is achieved will be referred to as Repeat-Until-Success (RUS). The phase rotation circuit 50 in the RUS receives the auxiliary state "|m θ > L Therefore, before the phase rotation, the auxiliary state "|m θ > L " is generated. This auxiliary state "|m θ > L The efficiency of generating the auxiliary state "|m" to realize the gate operation of the phase rotation affects the efficiency of the execution of the phase rotation gate operation. θ > L The preparation process for " is called "injection".

[0072] The injection can be performed using an auxiliary state generator circuit. 8 is a diagram showing an example of injection. The auxiliary state "|m θ > L " can be generated by applying an error-detecting code called the [[4,1,1,2]] code 52.

[0073] In general, when written as a [[n,k,r,d]] code, the numbers have the following meanings: n: Number of physical qubits used for encoding k: the number of logical qubits the code has r: the number of gauge qubits the code has d: Code distance of the code A gauge qubit is a quantum state that is independent of logical qubits and exhibits gauge degrees of freedom that are not used (redundant) in calculations.

[0074] The [[4,1,1,2]] code 52 is a code with one logical qubit and one gauge qubit. Note that the logical qubit and gauge qubit are sometimes written together as the [[4,2,2]] code.

[0075] The input states of the four physical quantum bits in the auxiliary state generation circuit 51 are all "|0>". In the auxiliary state generation circuit 51, first, gate operations of H gates 51a and 51b are performed on the second and fourth physical quantum bits of the four physical quantum bits. Next, gate operations of CNOT gate 51c are performed with the second physical quantum bit as the control quantum bit and the first physical quantum bit as the target quantum bit. At the same time, gate operations of CNOT gate 51d are performed with the fourth physical quantum bit as the control quantum bit and the third physical quantum bit as the target quantum bit. Then, a two-qubit rotation gate 51e around the Z axis is executed on the first physical quantum bit and the third physical quantum bit.

[0076] The operation of the two-qubit rotation gate 51e is "R Z0Z2 (θ)=e -i(1 / 2)θZ0Z2 " (The number following Z is a subscript of Z indicating the quantum bit to be operated). The operation of the two-qubit rotation gate 51e can be expressed as a matrix as shown in equation (1) (the subscript indicating the quantum bit to be operated is omitted).

[0077]

number

[0078] The two-qubit rotation gate 51e shown in equation (1) can be easily implemented in the quantum computer 200. For example, in the case of an ion trap type quantum computer, the two-qubit rotation gate 51e can be implemented as an XX rotation gate R XX (θ) and an H gate. In addition, the two-qubit rotation gate 51e can be implemented using, for example, a cross resonant gate R ZX(θ) and H gates. Even if these cannot be used, the two-qubit rotation gate 51e can be implemented using the CNOT gate and the RZ gate (R Z (θ)) can be combined. The output of the auxiliary state generating circuit 51 is the auxiliary state "|m θ > L " (The state of the gauge qubit is omitted.)

[0079] The generated auxiliary state is subjected to error detection using the [[4,1,1,2]] code 52. If no error is detected, the generated auxiliary state is used to gate the coded phase rotation while remaining in its coded state. This allows the phase rotation to be achieved without passing through a decoded state, thereby preventing an increase in the error rate due to passing through a decoded state.

[0080] If an error is detected in the generated auxiliary state, the auxiliary state is discarded and the auxiliary state generation process is executed again by the auxiliary state generation circuit 51. This makes it possible to generate an auxiliary state with as few errors as possible.

[0081] The probability that the generated auxiliary state will result in an error and that the generation process will have to be redone is affected by the error rate of the physical quantum bit used in the auxiliary state generation circuit 51. In addition, the auxiliary state generated by the [[4,1,1,2]] code 52 is extended to a code with the code distance required for the logical quantum bit used as input to the phase rotation circuit 50.

[0082] FIG. 9 is a diagram showing an example of extension to a surface code. The surface code 52a is obtained by extending the [[4,1,1,2]] code 52 to a code distance of "5" (d=5). The state prepared in the [[4,1,1,2]] code 52 is set at the top left of the surface code 52a. The other physical quantum bits are initialized to "|0>" or "|+>". In the surface code 52a, the shaded circles are physical quantum bits initialized to "|0>", and the double circles are physical quantum bits initialized to "|+>". As a result of the initialization, the state of the surface code 52a is the auxiliary state "|m θ >L " represents the

[0083] The quantum computing system 300 performs stabilizer measurements on such a surface code 52a. Based on the information obtained by measuring the stabilizer, the location of the error can be estimated. The quantum computing system 300 performs error detection based on the stabilizer measurement results, and if an error is detected, discards the generated auxiliary state and redoes the auxiliary state generation process. This makes it possible to generate an auxiliary state with as few errors as possible.

[0084] If no error is detected in the surface code 52 a representing the auxiliary state, that auxiliary state is used as the auxiliary state of the phase rotation circuit 50 . The process of extending the [[4,1,1,2]] code 52 to the surface code 52a can also cause a failure in generating the auxiliary state. Therefore, when the code distance of the surface code 52a is large, the probability that the generation of the auxiliary state will fail (injection failure probability) increases.

[0085] Figure 10 shows an example of the injection failure probability. Graph 53 shows the relationship between the physical error rate and the injection failure probability when an injection is performed using a single [[4,1,1,2]] code and the result is extended to a surface code of a predetermined code distance. The horizontal axis of graph 53 is the physical error rate p, and the vertical axis is the injection failure probability.

[0086] The multiple polygonal lines 53a to 53d in the graph 53 represent the change in the injection failure probability as the physical error rate p increases. The polygonal line 53a is for the case where the code distance is "3" (d=3). The polygonal line 53b is for the case where the code distance is "5" (d=5). The polygonal line 53c is for the case where the code distance is "7" (d=7). The polygonal line 53d is for the case where the code distance is "9" (d=9).

[0087] As shown by the broken lines 53a to 53d, the higher the physical error rate, the higher the injection failure probability. The longer the code distance, the higher the injection failure probability. When the injection failure probability is high, it takes time to supply the auxiliary state, which results in a slower execution time for the phase rotation gate.

[0088] Therefore, in the quantum computing system 300 according to the second embodiment, in the execution of a phase rotation gate using the RUS of the STAR architecture, the execution time is reduced by performing the generation of auxiliary states in parallel.

[0089] In quantum computing system 300, basic logic gates that act on logical quantum bits are executed by a method called lattice surgery. In lattice surgery, logical quantum bits to be operated on are handled in units called patches.

[0090] 11 is a diagram showing the relationship between logical qubits and patches. A logical qubit 60 is represented by a surface code at a predetermined code distance. Of the rectangular area that constitutes the logical qubit 60, the left and right sides are X boundaries 61, and the top and bottom sides are Z boundaries. Multiple physical qubits aligned on the X boundaries become logical X operators. Multiple physical qubits aligned on the Z boundaries become logical Z operators.

[0091] One such logical quantum bit 60 is represented by one patch 63. The X boundary of the patch 63 is represented by a dashed line, and the Z boundary is represented by a solid line. Lattice surgery involves several basic operations, and various logic gates can be implemented by combining these operations.

[0092] Figure 12 shows an example of merging and separation, which are basic operations of lattice surgery. Merging is an operation that converts two logical qubits 60a and 60b into one logical qubit 60c by measuring the stabilizer operator 64 between them. The logical gate operation of merging is expressed by replacing two patches 63a and 63b with one merged patch 63c.

[0093] Splitting is an operation that splits logical qubit 60c into two by measuring the states of multiple physical qubits aligned at split point 65 of coupled logical qubit 60c. The splitting logic gate operation is represented by replacing coupled patch 63c with two patches 63a and 63b.

[0094] 13 is a diagram showing an example of deformation, which is a basic operation of lattice surgery. The logical gate operation of deformation can be divided into expansion and contraction. The expansion is an operation of initializing the physical qubits in the region in the direction of expansion (expansion region 66) and measuring the stabilizer operator in expansion region 66. This generates an expanded logical qubit 60e. The logical gate operation of expansion is represented by replacing patch 63d with expanded patch 63e that includes expansion region 66.

[0095] Shrinking is an operation that measures the physical qubits within a shrinking region (shrinking region 67). This causes, for example, enlarged logical qubit 60e to shrink to the original size of logical qubit 60d. The logic gate operation of shrinking is represented by replacing enlarged patch 63e with a patch of the reduced size 63d.

[0096] Figure 14 shows an example of logic gate operation using lattice surgery. For example, using basic logic gates, gate operation of logic X x logic X measurement (X is an X inside a circle) can be performed. Hereinafter, logic X x logic X measurement (X is an X inside a circle) will be referred to as logic XX measurement.

[0097] First, patch 68a and patch 68b are coupled by initializing the physical qubit between them to "|0>". A coupled patch 68c is generated by a coupling logic gate operation. A logical XX measurement is indirectly performed by the X stabilizer measurement (the measurement is the product of the X stabilizer measurements) during coupling.

[0098] The combined patch 68c has become a single code, so it is returned to the two patches 68a and 68b by a separation logic gate operation. At this time, the correct logical XX measurement result can be obtained by applying an appropriate Pauli operator depending on the measurement result of the physical quantum bit included in the separation point.

[0099] The state of patch 68a before the combination and separation is defined as "|ψ> L " and the state of patch 68b is "|φ> L If the code distance is set to "3", the state of the patches 68a and 68b before joining and separating is set to "|ψ> L |φ> L The logic XX measurement results in the state of each of the patches 68a and 68b being "(1+(-1) M X L ×X L )|ψ> L |φ> L " (× is an × inside a circle) is obtained. M indicates the measurement result and is either "0" or "1".

[0100] In this way, logic XX measurement is realized. Logic Z x logic Z measurement (x is an x ​​inside a circle) can also be realized by performing logic gate operations for coupling and separation at Z boundaries. Hereafter, logic Z x logic Z measurement (x is an x ​​inside a circle) will be referred to as logic ZZ measurement.

[0101] If the code distance is "3", in the case of the logical ZZ measurement, the state of the patches 68a and 68b before combining and separating is "|ψ> L |φ> L By the logical ZZ measurement, the state of each of the patches 68a and 68b is "(1 + (-1) MZ L ×Z L )|ψ> L |φ> L ” (× is an × inside a circle) is obtained.

[0102] 15 is a diagram showing an example of logical CNOT gate operation using lattice surgery. For example, consider a logical CNOT gate 69 in which the logical qubit in state "|C>" is the control qubit and the logical qubit in state "|T>" is the target qubit.

[0103] The state of the control qubit is prepared in patch 69a. The state of the target qubit is prepared in patch 69b. First, patch 69a is expanded with the expansion region on the top side to become expanded patch 69c. After expanding patch 69c is separated, the expansion region is combined with patch 69b to generate combined patch 69d. When combined patch 69d is separated, the state of patch 69b becomes the state after applying logic CNOT gate 69.

[0104] The logical CNOT gate 69 utilizes an extra calculation area (auxiliary patch) other than the patches 69a and 69b corresponding to the logical quantum bits to be operated. The logical qubits used in quantum computing are arranged in a suitable arrangement within qubit device 202.

[0105] FIG. 16 is a diagram showing an example of an arrangement of logical quantum bits. For example, assume that the area in which quantum bits are arranged in quantum bit device 202 is divided into 16 patches. Each of the 16 patches is assigned a number from "0 to 15." The four patches in the upper horizontal row, numbered "0 to 3," are used as logical quantum bit area 202a. The four patches in the lower horizontal row, numbered "12 to 15," are used as logical quantum bit area 202b. Each patch in logical quantum bit areas 202a and 202b is used as a logical quantum bit to be operated on in quantum computation.

[0106] The area between logical quantum bit areas 202a and 202b is a blank calculation area 202c. Eight patches "4 to 11" in blank calculation area 202c are used in the calculation process of gate operations on the logical quantum bits.

[0107] When performing logic gate operations of a phase rotation gate by lattice surgery, an auxiliary state is generated in the patch within the computational margin area 202c. 17 is a diagram showing an example of a method for realizing a phase rotation gate by lattice surgery. The phase rotation gate is realized by performing a gate operation of a phase rotation circuit 50 on a logical quantum bit to be gated.

[0108] For example, the state "|ψ>" generated using the patch 71 in the logical qubit regions 202a and 202b L When performing a phase rotation gate logic gate operation on the patch 71, the patch 72 adjacent to the patch 71 is used as an auxiliary patch, and an auxiliary state is generated in the patch 72.

[0109] If the auxiliary state is successfully generated, a logic ZZ measurement is performed between patch 71 and patch 72. The logic ZZ measurement involves logic gate operations of coupling and isolation, which are the basic operations of lattice surgery. Then, a logic X measurement is performed on patch 72.

[0110] In the example of Figure 17, an auxiliary state is generated using one patch 72. In this case, if the generation of the auxiliary state fails, the generation of the auxiliary state is repeated in patch 72. The higher the probability of failure in the generation of the auxiliary state, the more times the auxiliary state generation process is repeated, and the longer it takes to complete the preparation (injection) of the auxiliary state. Therefore, in the quantum computing system 300, multiple patches are used to perform injection in parallel.

[0111] FIG. 18 is a diagram showing an example of parallel injection. For example, suppose a logical gate operation of a phase rotation gate is performed on a logical quantum bit represented by patch 73. In this case, a patch that satisfies a predetermined condition is detected from the calculation margin area. For example, a patch that satisfies the following condition is detected. - Not in use The phase rotation gate must be positioned so that it can be connected to the target patch. In the example of Figure 18, the patches painted in black are in use. There are five unused patches 74a to 74e. The positional relationship that can be connected to the target patch 73 on which the phase rotation gate is to be applied is a positional relationship that can be reached by tracing only the unused patches vertically or horizontally from the patch 74a adjacent to the patch 73.

[0112] Patches 74a to 74d satisfy predetermined conditions and are therefore detected as the injection region 74. Patch 74e is not in use, but is not detected because it is not in a position that allows it to be connected to patch 73.

[0113] In the quantum computing system 300, injections are performed in parallel using the patches 74a to 74d in the injection region 74. In the example of Fig. 18, injections are performed in four parallel increments.

[0114] If at least one of the injections executed in parallel succeeds in generating an auxiliary state, a logical ZZ measurement is performed using that auxiliary state. During the logical ZZ measurement, a pre-injection can be performed, for example, using an unused patch assigned to the operation of that phase rotation gate. Pre-injection is a process that performs an injection for the next phase rotation in advance, assuming that RUS will fail (resulting in a reverse rotation).

[0115] FIG. 19 is a diagram showing an example of a pre-injection. For example, assume that a logical ZZ measurement is being performed between patch 73 and patch 74a. Meanwhile, in preparation for a case where RUS fails, an injection of the auxiliary state of the next rotation angle "2θ" is performed in advance using the remaining injection area 74-1. In the example of FIG. 19, three patches worth of patches 74b to 74d are available, so the auxiliary state "|m 2θ > L " is generated by three parallel injections.

[0116] 20 is a diagram showing an example of the execution process of a phase rotation gate involving parallel injection and pre-injection. For example, the state of the logical quantum bit to be acted upon is prepared in patch 75a. At this time, four patches 75b to 75e are unused, and patches 75b to 75e are included in the injection region.

[0117] In this case, parallel injection is performed in four parallel increments using patches 75b to 75e. In the example of FIG. 20, injection is successful only in patch 75b. Therefore, logical ZZ measurement is performed using patches 75a and 75b, and pre-injection is performed using other free patches 75c to 75e. Here, it is assumed that RUS using logical ZZ measurement has failed (reverse rotation). It is also assumed that pre-injection was successful only in patch 75d. In this case, the state of patch 75d is "m 2θ > L " is expanded in the direction of patch 75b using the basic operation of lattice surgery.

[0118] Next, the state of the enlarged patch (the area including patch 75b and patch 75d) is 2θ > L ” and pre-injection using other empty patches 75c and 75e. Here, it is assumed that RUS using the logical ZZ measurement is successful (forward rotation). As a result, the state of the logical qubit represented by patch 75a becomes “R Z (θ)|ψ>L "

[0119] Note that while parallel injection and pre-injection are repeated, the calculation in the area being used may be completed and the area may be released. If the released patch satisfies the conditions for being an injection area, the patch can be added to the injection area. Furthermore, when a new area is added to the injection area, a patch with a newly connected path to the target patch can also be added to the injection area.

[0120] 21 is a diagram showing an example of real-time update processing of the injection area. For example, in the initial stage, patch 74e is not connected to the target patch 73 via an unused patch. Therefore, patch 74e is not included in the injection area 74.

[0121] After that, it is assumed that the calculations performed using patches 74f and 74g while performing the logical ZZ measurement, etc., are completed. Patches 74f and 74g are positioned so that they can be connected to the target patch. Patch 74e is also positioned so that it can be connected to the target patch. As a result, injection region 74 is expanded to injection region 74-2, which includes patches 74e to 74g.

[0122] In quantum computing, in order to reduce computation time, multiple gate operations that are not dependent on each other can be executed in parallel. Therefore, logic gate operations of multiple phase rotation gates may be performed in parallel. When multiple phase rotation gates are executed in parallel, it is important to allocate unused areas fairly to the multiple phase rotation gate operations.

[0123] FIG. 22 is a diagram showing an example of a method for allocating free areas. For example, assume that four patches 76a to 76d are the targets of operation of a phase rotation gate. The patches adjacent to each of the patches 76a to 76d are allocated as injection areas. The injection area of ​​patch 76a is "area 1," the injection area of ​​patch 76b is "area 2," the injection area of ​​patch 76c is "area 3," and the injection area of ​​patch 76d is "area 4." In FIG. 22, the black areas are areas currently being used for calculation.

[0124] Now, let's assume that the calculation in the area in use has finished and the area has become free. This free area has the size of four patches. First, each injection area is expanded by one patch into the adjacent free area. In Figure 22, the arrow indicates the patch to which it will be expanded.

[0125] At this time, if there is a patch that is simultaneously reached from multiple injection regions, it is determined that a collision has occurred at that patch. In Figure 22, the patch where a collision has occurred is indicated by a white circle.

[0126] If there are no collisions in the destination patch, each injection region is further expanded into adjacent free space by one patch, and this operation is repeated until there are no more adjacent free spaces.

[0127] Patches without collisions are included in the injection region that is expanded to include them. For patches with collisions, the sizes of the colliding injection regions are compared and the patch is included in the smaller injection region.

[0128] For example, consider a patch where "Area 1" and "Area 3" collide. "Area 1" is the size of one patch, and "Area 3" is the size of two patches. Comparing the sizes of "Area 1" and "Area 3," "Area 1" is smaller. Therefore, the patch where the collision occurred is included in "Area 1."

[0129] Next, consider the patch where "Area 2" and "Area 4" collide. "Area 2" is the size of one patch, and "Area 4" is the size of two patches. Comparing the sizes of "Area 2" and "Area 4," "Area 2" is smaller. Therefore, the patch where the collision occurred is included in "Area 2."

[0130] Finally, the size of each injection region is the size of two patches. As a result, the injection regions used by multiple phase rotation gates executed in parallel are allocated fairly to the multiple phase rotation gates.

[0131] When parallel injection or pre-injection is performed, injection may be successful in multiple patches. In that case, one patch is selected from the successful injection patches and connected to the target patch.

[0132] 23 is a diagram showing an example of the connection between a patch that has been successfully injected and a patch that is the target of operation. For example, suppose two patches 77a and 77b are the targets of a phase rotation gate operation. Injection region 77c is assigned to the phase rotation gate operation on the logical quantum bit represented by patch 77a. Injection region 77d is assigned to the phase rotation gate operation on the logical quantum bit represented by patch 77b.

[0133] Each of the injection regions 77c and 77d contains four patches. Parallel injections are performed using the patches in the injection regions 77c and 77d. In the example shown in Figure 23, injection was successful in patch 77e in injection region 77c. Furthermore, injection was successful in patch 77f in injection region 77d.

[0134] 23, injection is successful for one patch 77e in the injection area 77c, and for one patch 77f in the injection area 77d, but injection may be successful for multiple patches in one injection area. In this case, the patch closest to the target patch is connected to the target patch by shortest path search.

[0135] The path search between the target patch and the successfully injected patch can be performed using, for example, the A* algorithm. The A* algorithm is an improved version of the Dijkstra algorithm. The A* algorithm can find the shortest distance more efficiently when the distance to the end point can be estimated.

[0136] Among the successfully injected patches, the patch closest to the target patch is connected to the target patch via the shortest path, and the logical ZZ measurement is performed. At this time, the patch on the connection path is used as an auxiliary patch.

[0137] In the example of Figure 23, patch 77a to be operated and patch 77e in injection area 77c that was successfully injected are connected, and logical ZZ measurement is performed. Also, patch 77b to be operated and patch 77f in injection area 77d are connected, and logical ZZ measurement is performed. By connecting via the shortest path, the number of auxiliary patches used can be minimized, and more patches can be used for the next pre-injection.

[0138] Next, the quantum computing function of quantum computing system 300 for efficiently performing phase rotation in the STAR architecture will be described. 24 is a block diagram showing an example of functions for quantum computation in a quantum computing system. The classical computer 100 has a quantum computation request accepting unit 110, a quantum circuit execution control unit 120, a Clifford computation control unit 130, and a phase rotation control unit 140.

[0139] The quantum computing request receiving unit 110 receives a quantum computing request from the terminal device 30. The quantum computing request includes, for example, a quantum circuit corresponding to the problem to be solved. The quantum computing request receiving unit 110 transmits an execution command for the quantum circuit corresponding to the problem to be solved, which is indicated in the quantum computing request, to the quantum circuit execution control unit 120. Furthermore, upon receiving the result of the quantum computing by the quantum circuit from the quantum circuit execution control unit 120, the quantum computing request receiving unit 110 transmits the calculation result to the terminal device 30.

[0140] The quantum circuit execution control unit 120 transmits quantum gate execution commands to the Clifford arithmetic control unit 130 or the phase rotation control unit 140 in the order indicated in the quantum circuit acquired as the execution target, based on the quantum circuit corresponding to the problem to be solved. When the quantum circuit execution control unit 120 receives measurement results indicating the state of the quantum bits after gate operations corresponding to the quantum circuit from the Clifford arithmetic control unit 130, it calculates a solution to the problem to be solved based on the measurement results. The quantum circuit execution control unit 120 then transmits the solution to the problem to be solved to the quantum computation request receiving unit 110 as the result of the quantum computation.

[0141] The quantum circuit execution control unit 120 also manages patches that are in use for calculations in the quantum bit device 202 and patches that are free. For example, the quantum circuit execution control unit 120 sets a patch that is assigned for a quantum gate operation of the quantum circuit that is the target of calculation as being in use. The quantum circuit execution control unit 120 also changes a patch that was assigned to a quantum gate operation for which calculation has been completed to a free state.

[0142] The Clifford operation control unit 130 instructs the quantum computer 200 to perform a Clifford operation or a measurement operation on a logical quantum bit. In accordance with the instruction from the Clifford operation control unit 130, the quantum computer 200 performs a gate operation of the Clifford operation or a measurement. Then, the quantum computer 200 transmits information indicating the completion of the gate operation or the measurement result to the Clifford operation control unit 130. When the gate operation is completed, the Clifford operation control unit 130 transmits a notification to that effect to the quantum circuit execution control unit 120. Furthermore, when the Clifford operation control unit 130 receives a measurement result, it transmits the received measurement result to the quantum circuit execution control unit 120.

[0143] The phase rotation control unit 140 instructs the quantum computer 200 to execute a series of operations to realize phase rotation for the logical quantum bit. The quantum computer 200 performs gate operations for phase rotation in accordance with the instructions from the phase rotation control unit 140. Then, the quantum computer 200 transmits information indicating completion of the gate operations to the phase rotation control unit 140.

[0144] Note that error detection is performed during the phase rotation gate operation. The quantum computer 200 transmits the error detection result to the phase rotation control unit 140. Based on the error detection result, the phase rotation control unit 140 determines subsequent instructions to the quantum computer 200 (e.g., the next rotation angle, the position of the patch where injection is to be performed), and instructs the quantum computer 200 to perform the gate operation.

[0145] When the gate operation for phase rotation is completed, the phase rotation control unit 140 transmits information indicating the completion of phase rotation to the quantum circuit execution control unit 120. The function of each element shown in FIG. 24 can be realized by, for example, having the processor 101 execute a program module corresponding to that element.

[0146] 25 is a diagram showing an example of the functions of the phase rotation control unit. Upon receiving a phase rotation command from the quantum circuit execution control unit 120, the phase rotation control unit 140 controls the quantum computer 200 to cause the quantum computer 200 to perform a logic gate operation of a phase rotation gate. The phase rotation command indicates a patch to be operated on for phase rotation and a rotation angle.

[0147] In order to cause the quantum computer 200 to perform phase rotation, the phase rotation control unit 140 has an injection region determination unit 141 , an RUS execution control unit 142 , an injection success / failure determination unit 143 , and a phase rotation success / failure determination unit 144 .

[0148] The injection region determination unit 141 acquires quantum gate execution status information from the quantum circuit execution control unit 120 and allocates an injection region for the logic gate operation of the phase rotation gate for the target patch. After allocating the injection region, the injection region determination unit 141 transmits an RUS execution command to the RUS execution control unit 142. The RUS execution command includes information indicating the allocated injection region. The RUS execution command is a command to instruct the execution of parallel injection using the allocated injection region, or logical ZZ measurement & pre-injection.

[0149] In response to the RUS execution command, the RUS execution control unit 142 controls the quantum computer 200 to perform a logic gate operation of a phase rotation gate on the target patch. For example, the RUS execution control unit 142 controls the execution of phase rotation based on the STAR architecture.

[0150] The RUS execution control unit 142 causes the quantum computer 200 to execute parallel injections in the injection region. The RUS execution control unit 142 acquires information indicating patches for which injections were successful from the injection success / failure determination unit 143, and controls the quantum computer 200 to connect the patches to be manipulated. The RUS execution control unit 142 then causes the quantum computer 200 to execute logical ZZ measurements and pre-injection.

[0151] The RUS execution control unit 142 obtains the result of the phase rotation success / failure determination for the patch on which the logical ZZ measurement was performed from the phase rotation success / failure determination unit 144. If the phase rotation fails, the RUS execution control unit 142 obtains information indicating the patch on which the pre-injection was successful from the injection success / failure determination unit 143, and controls the quantum computer 200 to connect that patch to the patch to be manipulated. The RUS execution control unit 142 then causes the quantum computer 200 to perform the logical ZZ measurement and pre-injection again.

[0152] The injection success / failure determination unit 143 acquires the execution result of the error detection circuit for each patch that has been injected. The injection success / failure determination unit 143 determines the success / failure of the injection based on the value indicated by the execution result of the error detection circuit, and transmits the determination result to the RUS execution control unit 142.

[0153] The phase rotation success / failure determination unit 144 determines whether the phase rotation of the logical quantum bit indicated by the target patch has been successful, based on the measurement results obtained when the quantum computer 200 executes the phase rotation circuit. For example, if the result of the logical ZZ measurement is "+1", the phase rotation success / failure determination unit 144 determines that the phase rotation has been successful (rotated in the intended direction), and if the result of the logical ZZ measurement is "-1", it determines that the phase rotation has failed (rotated in the opposite direction to the intended direction). If the phase rotation has been rotated in the intended direction, the phase rotation success / failure determination unit 144 transmits information indicating the completion of the phase rotation to the quantum circuit execution control unit 120. If the phase rotation has been rotated in the opposite direction, the phase rotation success / failure determination unit 144 transmits information indicating the failure of the phase rotation to the RUS execution control unit 142.

[0154] Next, the function of the injection region determination unit 141 will be described in detail. 26 is a diagram showing an example of functions of the injection region determination unit 141. The injection region determination unit 141 has a calculation margin region management unit 141a, an RUS execution management unit 141b, and an injection region update unit 141c.

[0155] The computational margin area manager 141a manages whether or not patches in the computational margin area are used based on the quantum gate execution status information. The computational margin area manager 141a transmits free space information indicating free space in the computational margin area to the RUS execution manager 141b.

[0156] The RUS execution management unit 141b determines an injection region corresponding to the logic gate operation of the phase rotation gate of the target patch based on the free region information, and then transmits an RUS execution command specifying the injection region to the RUS execution control unit 142.

[0157] Furthermore, if the free area information is updated before the phase rotation is completed, the RUS execution management unit 141b transmits a reallocation command to the injection area update unit 141c to instruct reallocation of the injection area.

[0158] The injection region update unit 141c updates the injection region based on the updated free region information. The injection region update unit 141c transmits the injection region information indicating the updated injection region to the RUS execution control unit 142.

[0159] 27 is a diagram showing an example of functions of the RUS execution control unit 142. The RUS execution control unit 142 includes a logical ZZ measurement region specifying unit 142a, an injection execution management unit 142b, a quantum operation execution management unit 142c, an injection execution control unit 142d, and a logical ZZ measurement execution control unit 142e.

[0160] The logical ZZ measurement area specifying unit 142a specifies an area to be measured by the logical ZZ measurement in response to the RUS execution command. For example, the logical ZZ measurement area specifying unit 142a specifies a patch to be operated on by phase rotation and a patch (auxiliary patch) in the calculation reserved area adjacent to that patch as an area to be measured by the logical ZZ measurement. The logical ZZ measurement area specifying unit 142a transmits utilization area information indicating the area to be measured by the logical ZZ measurement to the injection execution management unit 142b.

[0161] The injection execution management unit 142b manages the patches and rotation angles for which injection is performed. For example, in the first injection, the injection execution management unit 142b targets all patches within the injection region as injection targets. In addition, in the first injection, the injection execution management unit 142b sets the rotation angle specified by the phase rotation gate as the rotation angle for injection.

[0162] After the injection of any patch is successful, the injection execution management unit 142b targets patches in the injection region other than the patch used for the logical ZZ measurement as the injection target for the pre-injection. In this case, the injection execution management unit 142b sets the injection angle to twice the angle of the previous injection. The injection execution management unit 142b sends an injection command indicating the patch to be injected and the rotation angle of the injection to the quantum operation execution management unit 142c. The injection command is a command to execute parallel injection or a command to execute pre-injection and logical ZZ measurement.

[0163] The quantum operation execution management unit 142c manages the execution of quantum operations for the RUS. For example, when the quantum operation execution management unit 142c receives an injection command instructing the execution of parallel injection, it sends a parallel injection execution command specifying the patch to be used for injection to the injection execution control unit 142d. Furthermore, when the quantum operation execution management unit 142c receives an execution command for pre-injection & logical ZZ measurement, it sends a pre-injection execution command to the injection execution control unit 142d. Furthermore, the quantum operation execution management unit 142c sends a logical ZZ measurement execution command to the logical ZZ measurement execution control unit 142e.

[0164] The injection execution control unit 142d specifies a patch to be injected in parallel or in advance and transmits a quantum operation instruction to the quantum computer 200 to execute the injection. The injection execution control unit 142d transmits, for example, quantum operation instructions to the quantum computer 200, for executing the auxiliary state generation circuit 51 using the [[4,1,1,2]] code 52 and for executing the error detection circuit for the [[4,1,1,4]] code 52. The injection execution control unit 142d also transmits, to the quantum computer 200, a quantum operation instruction for extending the [[4,1,1,2]] code 52, from which the auxiliary state has been generated, to the surface code. The injection execution control unit 142d also transmits, to the quantum computer 200, a quantum operation instruction for executing the error detection circuit in the surface code.

[0165] The logical ZZ measurement execution control unit 142e transmits quantum operation instructions to the quantum computer 200 for connecting the patch that has been successfully injected with the patch that is the target of phase rotation operation, and for executing the logical ZZ measurement and the logical X measurement.

[0166] Next, quantum computation assistance processing of the classical computer 100 when executing a quantum circuit including a phase rotation gate will be described in detail. 28 is a flowchart showing an example of the procedure of quantum computing assisted processing on a classical computer. The processing shown in FIG. 28 will be explained below in order of step number.

[0167] [Step S101] When the quantum computing request receiving unit 110 receives a quantum computing request from the terminal device 30, it decomposes the quantum gates (e.g., 3-qubit gates) in the quantum circuit to be computed and converts them into a quantum circuit that combines quantum gates of "Clifford + φ (phase rotation)".

[0168] [Step S102] The quantum circuit execution control unit 120 performs initialization processing on the logical quantum bits. For example, the quantum circuit execution control unit 120 identifies the physical quantum bits to be used in executing the quantum circuit, and transmits initialization instructions for those physical quantum bits to the quantum computer 200. The quantum computer 200 initializes the states of the physical quantum bits to predetermined states in accordance with the initialization instructions.

[0169] [Step S103] The quantum circuit execution control unit 120 performs quantum circuit execution processing upon receiving a response indicating the completion of initialization from the quantum computer 200. The quantum circuit execution processing will be described in detail later (see FIG. 29).

[0170] [Step S104] When the quantum circuit execution control unit 120 completes execution of the quantum circuit and acquires the measurement result of the final logical qubit state, it calculates a solution to the problem to be solved based on the measurement result. The quantum circuit execution control unit 120 then transmits the calculation result to the quantum computing request receiving unit 110. The quantum computing request receiving unit 110 transmits the calculation result to the terminal device 30.

[0171] In this way, quantum computation using the quantum circuit is performed. Next, the quantum circuit execution process will be described in detail. 29 is a flowchart showing an example of the procedure of the quantum circuit execution process. The process shown in FIG. 29 will be explained below in order of step number.

[0172] [Step S201] The quantum circuit execution control unit 120 selects the next operation (gate operation or measurement) to be executed from the quantum circuit. [Step S202] The quantum circuit execution control unit 120 determines whether the selected operation is a gate operation of a phase rotation quantum gate. If the selected operation is a gate operation of a Clifford gate or a measurement, the quantum circuit execution control unit 120 proceeds to step S203. If the selected operation is a phase rotation quantum gate, the quantum circuit execution control unit 120 proceeds to step S204.

[0173] [Step S203] The quantum circuit execution control unit 120 transmits an execution command for the next Clifford gate operation or measurement to the Clifford operation control unit 130. If the transmitted command is a Clifford gate operation execution command, the Clifford operation control unit 130 transmits a quantum operation command for the Clifford gate operation on the logical quantum bit to the quantum computer 200. If the transmitted command is a measurement execution command, the Clifford operation control unit 130 transmits a quantum operation command for measuring the state of the logical quantum bit to the quantum computer 200. When the Clifford operation control unit 130 acquires the measurement result from the quantum computer 200, it transmits the measurement result to the quantum circuit execution control unit 120. The quantum circuit execution control unit 120 then proceeds to step S205.

[0174] [Step S204] The phase rotation control unit 140 performs phase rotation processing, the details of which will be described later (see FIG. 30). [Step S205] The quantum circuit execution control unit 120 determines whether the final operation of the quantum circuit has been completed. If the final operation of the quantum circuit has been completed, the quantum circuit execution control unit 120 terminates the quantum circuit execution process. If there is an unprocessed operation, the quantum circuit execution control unit 120 proceeds to step S201.

[0175] Next, the phase rotation process will be described in detail. 30 is a flowchart showing an example of a procedure for phase rotation processing. The processing shown in FIG. 30 will be explained below in order of step number.

[0176] [Step S301] When the phase rotation control unit 140 receives a phase rotation command, it first identifies an initial injection region. For example, the injection region determination unit 141 in the phase rotation control unit 140 identifies an empty patch in the calculation margin region 202c that can be connected to the patch to be operated. The injection region determination unit 141 determines the region including the measured patch as the initial injection region.

[0177] Furthermore, when multiple phase rotations are performed simultaneously, the injection region determination unit 141 allocates injection regions so that injection regions of approximately the same size are allocated to the logic gate operations of each of the multiple phase rotation gates.

[0178] [Step S302] The phase rotation control unit 140 repeats the processes of steps S303 to S305 until RUS for all phase rotations is completed. Note that the processes of steps S303 to S305 can be executed in parallel for each logic gate operation of the phase rotation gate.

[0179] [Step S303] The phase rotation control unit 140 executes injection and logical ZZ measurement processing, which will be described in detail later (see FIGS. 31 and 32).

[0180] [Step S304] The phase rotation control unit 140 determines whether an empty area has occurred. For example, if there is a completed quantum computation in the quantum gate execution status, the injection region determination unit 141 of the phase rotation control unit 140 determines that the patch used in that quantum computation has become an empty area. If an empty area has occurred, the phase rotation control unit 140 proceeds to step S305. If an empty area has not occurred, the phase rotation control unit 140 proceeds to step S306.

[0181] [Step S305] The phase rotation control unit 140 performs an injection region update process, which will be described in detail later (see FIG. 33). [Step S306] When the RUS for all phase rotations has been completed, the phase rotation control unit 140 ends the phase rotation process.

[0182] Next, the injection and logical ZZ measurement process will be explained in detail. 31 is a flowchart (1 / 2) showing an example of the procedure for the injection and logical ZZ measurement process. The process shown in FIG. 31 will be explained below in order of step number.

[0183] [Step S401] The phase rotation control unit 140 acquires successful injection patch information. For example, the phase rotation control unit 140 stores information about patches that have been successfully injected as a result of the injection success / failure determination in the memory 102. Then, at the execution timing of step S401, the phase rotation control unit 140 acquires information about patches that have been successfully injected from the memory 102.

[0184] Before the first parallel injection in the phase rotation process, the successful injection patch information (initial state) indicates that there are no successful patches. [Step S402] The phase rotation control unit 140 determines whether there is a patch that has been successfully injected. If there is at least one patch that has been successfully injected, the phase rotation control unit 140 proceeds to step S404. If there is no patch that has been successfully injected, the phase rotation control unit 140 proceeds to step S403.

[0185] [Step S403] The phase rotation control unit 140 instructs the quantum computer 200 to perform parallel injection. For example, the phase rotation control unit 140 transmits to the quantum computer 200 quantum operation instructions for performing injection on each patch in the injection region. If the parallel injection is successful in injecting any patch, the successful injection patch information is updated. After updating the successful injection patch information in accordance with the parallel injection, the phase rotation control unit 140 proceeds to step S401.

[0186] [Step S404] The phase rotation control unit 140 executes the process of step S405 for all patches that have been successfully injected. [Step S405] The phase rotation control unit 140 identifies the shortest connection path for the logical ZZ measurement between the successful patch and the patch to be operated by the phase rotation gate.

[0187] [Step S406] If the process of step S405 has been completed for all patches that have been successfully injected, the phase rotation control unit 140 proceeds to step S407.

[0188] [Step S407] The phase rotation control unit 140 identifies the patch with the shortest connection path from among the patches that have been successfully injected. [Step S408] The phase rotation control unit 140 instructs the quantum computer 200 to perform a logical ZZ measurement using the auxiliary state indicated in the identified patch. For example, the phase rotation control unit 140 transmits to the quantum computer 200 quantum operation instructions for connecting the identified patch with the patch to be operated, and for performing a logical ZZ measurement and a logical X measurement. After performing the operation in accordance with the instructions, the quantum computer 200 transmits information indicating the direction of the phase rotation (forward or reverse rotation) to the classical computer 100 as the operation result.

[0189] After issuing the instruction to perform the logical ZZ measurement, the phase rotation control unit 140 advances the process to step S409 without waiting for the operation result from the quantum computer 200. [Step S409] The phase rotation control unit 140 identifies an area available for pre-injection. For example, the phase rotation control unit 140 identifies an area including patches in the injection area excluding patches used for logical ZZ measurement as an area available for pre-injection.

[0190] [Step S410] The phase rotation control unit 140 determines the rotation angle of the pre-injection. For example, the phase rotation control unit 140 determines the pre-injection rotation angle to be twice the rotation angle of the patch injection used in the logical ZZ measurement in step S408. The phase rotation control unit 140 then proceeds to step S421 (see FIG. 32).

[0191] 32 is a flowchart (2 / 2) showing an example of the procedure for the injection and logical ZZ measurement process. The process shown in FIG. 32 will be explained below in order of step number. [Step S421] The phase rotation control unit 140 repeats the process of step S422 until the logical ZZ measurement is completed.

[0192] [Step S422] The phase rotation control unit 140 instructs the quantum computer 200 to perform pre-injection. For example, the phase rotation control unit 140 specifies a patch within the identified pre-injection region and transmits a quantum operation command to the quantum computer 200 to perform injection at the specified patch. Note that in the repetition of pre-injection in step S422, the phase rotation control unit 140 excludes patches that have been successfully injected from the targets of pre-injection in the next and subsequent runs.

[0193] [Step S423] If the logical ZZ measurement is completed, the phase rotation control unit 140 advances the process to step S424. [Step S424] The phase rotation control unit 140 determines whether the RUS based on the logical ZZ measurement was successful. For example, the phase rotation control unit 140 determines that the RUS was successful if the phase rotation was forward. On the other hand, the phase rotation control unit 140 determines that the RUS was unsuccessful if the phase rotation was reverse. If the RUS was successful, the phase rotation control unit 140 proceeds to step S425. If the RUS was unsuccessful, the phase rotation control unit 140 proceeds to step S426.

[0194] [Step S425] The phase rotation control unit 140 outputs a signal indicating completion of phase rotation, and ends the RUS for the patch that is the target of the operation. [Step S426] The phase rotation control unit 140 determines whether any pre-injection was successful. If the injection was successful in at least one patch, the phase rotation control unit 140 proceeds to step S427. If the injection failed in all pre-injected patches, the phase rotation control unit 140 determines that the RUS is incomplete and ends the current injection and logical ZZ measurement process.

[0195] [Step S427] The phase rotation control unit 140 stores information about the patches that were successfully injected. Then, the phase rotation control unit 140 determines that the RUS is incomplete and ends the current injection and logical ZZ measurement process.

[0196] If RUS is not complete, the injection and logical ZZ measurement process is repeated while updating the injection region. If RUS is complete, the quantum computation of the transition is performed using the state of the logical qubit indicated by the patch being manipulated.

[0197] Next, the injection area update process will be described in detail. 33 is a flowchart showing an example of the procedure for the injection region update process. The process shown in FIG. 33 will be described below in order of step number.

[0198] [Step S501] The phase rotation control unit 140 acquires free area information indicating unused patches in the calculation margin area 202c. [Step S502] The phase rotation control unit 140 acquires the current injection region of each patch that is the target of the phase rotation operation.

[0199] [Step S503] The phase rotation control unit 140 repeats the processes of steps S504 to S505 for all patches in the free area until they are assigned to any injection area or included in the collision list.

[0200] [Step S504] The phase rotation control unit 140 attempts to expand the injection region to an adjacent free patch (one patch), and if no collision occurs, assigns the expanded patch to the injection region. The assigned patch becomes part of the injection region to which it is assigned. As a result, the injection region is expanded.

[0201] [Step S505] The phase rotation control unit 140 updates the collision patch list. For example, the phase rotation control unit 140 registers, in the collision patch list, a collision patch in which multiple injection regions collide when attempting to expand an injection region.

[0202] [Step S506] If all the patches in the free area are assigned to any of the injection areas or included in the collision list, the phase rotation control unit 140 proceeds to step S507.

[0203] [Step S507] The phase rotation control unit 140 executes the processes of steps S508 to S511 for all collision patches. [Step S508] The phase rotation control unit 140 calculates the size of each of the two colliding injection regions A and B in the collision patch. The phase rotation control unit 140 calculates the size of injection region A as "S A" and the size of injection area B is "S B "

[0204] [Step S509] The phase rotation control unit 140 determines the size of the injection area A, "S A " and the size of injection area B "S B The phase rotation control unit 140 compares the size of the injection area A, "S A If " is larger than (S A >S B ) processing proceeds to step S510. A ” is the size of injection area B “S B " or less (S A ≦S B ) The process proceeds to step S511.

[0205] [Step S510] The phase rotation control unit 140 assigns the collision patch to the injection region B. The phase rotation control unit 140 then proceeds to step S512. [Step S511] The phase rotation control unit 140 assigns a collision patch to the injection region A.

[0206] [Step S512] If the processes of steps S508 to S511 have been completed for all collision patches, the phase rotation control unit 140 advances the process to step S513. [Step S513] The phase rotation control unit 140 updates the injection region information.

[0207] As described above, when a quantum circuit includes a phase rotation gate, the auxiliary states used for phase rotation by the STAR architecture are efficiently generated by parallel injection and pre-injection. As a result, the time required to generate the auxiliary states is reduced, preventing the operation of the phase rotation gate from being prolonged.

[0208] Also, if the free space increases while performing the logical ZZ measurement, the free space is also used for pre-injection. This increases the chances that the pre-injection will be successful with one of the patches.

[0209] Below, we will explain the results of verifying the operation time of the phase rotation gate when injection generation efficiency improvement processing (parallel injection, pre-injection, and real-time update of the injection region) is applied, with reference to Figures 34 and 35. The following verification compares the calculation time when the injection generation efficiency improvement processing is applied and when it is not applied, when the phase rotation gate is executed simultaneously on 32 logical qubits.

[0210] If the injection generation efficiency improvement process is not applied, the injection area is fixed to one patch, and even if free space occurs, it is not allocated to the injection area.

[0211] 34 is a diagram showing a first example of the verification results of the gate operation time of a phase rotation gate. The example in FIG. 34 is an example in which the injection failure probability is relatively large. The results of simulating the logic gate operation of 32 parallel phase rotation gates 1000 times are shown in a histogram in graph 81.

[0212] In graph 81, the horizontal axis represents the time required to complete the logic gate operation of the phase rotation gate, and the vertical axis represents the number of samples out of 1000 that completed at that time. Histogram 81a shows the simulation results when the injection generation efficiency improvement process was applied. Histogram 81b shows the simulation results when the injection generation efficiency improvement process was not applied.

[0213] The black area 81c is the overlapping portion of histogram 81a and histogram 81b. The vertical line 81d indicates the average execution time when the time required for injection is fixed as a unit time.

[0214] The average time required for 1000 phase rotation gates without injection efficiency improvement is 160.822250. In contrast, the average time required for 1000 phase rotation gates with injection efficiency improvement is 26.627250.

[0215] As can be seen from graph 81, when the injection generation efficiency improvement process is not applied, there are many cases where the logic gate operation of the phase rotation gate takes a long time. This is because the injection failures continue, and it takes time to operate the logic gate of the phase rotation gate.

[0216] When the injection generation efficiency improvement process is applied, for the logic gate operation of the phase rotation gate that took time to generate the injection, the injection region used for the logic gate operation of the completed phase rotation gate can be used. Therefore, the longer the injection generation takes, the wider the injection region becomes, and the failure probability is exponentially suppressed.

[0217] Figure 35 shows a second example of the verification results for the gate operation time of a phase rotation gate. The example in Figure 35 is an example where the injection failure probability is relatively small. The results of simulating the logic gate operation of 32 parallel phase rotation gates 1000 times are shown in a histogram in graph 82.

[0218] In graph 82, the horizontal axis represents the time required to complete the logic gate operation of the phase rotation gate, and the vertical axis represents the number of samples out of 1000 that completed at that time. Histogram 82a shows the simulation results when the injection generation efficiency improvement process was applied. Histogram 82b shows the simulation results when the injection generation efficiency improvement process was not applied.

[0219] The black area 82c is the overlapping portion of the histogram 82a and the histogram 82b. The vertical line 82d indicates the average execution time when the time required for injection is fixed as a unit time.

[0220] The average time required for 1000 phase rotation gates without injection efficiency improvement processing is 11.912500. In contrast, the average time required for 1000 phase rotation gates with injection efficiency improvement processing is 7.952000.

[0221] As shown in graph 82, since the failure probability is small, the logic gate operation of the phase rotation gate can be executed at high speed even without injection generation efficiency processing. Even in such a case, if injection generation efficiency processing is performed, the logic gate operation of the phase rotation gate can be further accelerated. This is because the overhead of injection processing is suppressed by pre-injection during logic ZZ measurement.

[0222] Other Embodiments In the second embodiment, a phase rotation circuit 50 (see FIG. 7) using logical ZZ measurement is used for the logic gate operation of the phase rotation gate, but the logic gate operation of the phase rotation gate can also be performed using other quantum circuits. For example, the logic gate operation of the phase rotation gate can also be performed using the gate teleportation circuit shown in the aforementioned Non-Patent Document 1.

[0223] Although the embodiments have been described above, the configuration of each part shown in the embodiments can be replaced with other parts having similar functions. Also, any other components or processes may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0224] 1. Quantum computers 2 logical qubits 3a,3b,3c partial area 4 Available area 5 Quantum circuit 5a Phase rotation gate 10. Information processing equipment 11 Storage section 12 Processing section

Claims

1. causing a quantum computer to perform an operation of generating a first auxiliary state to be used for a phase rotation of a state of a logical quantum bit by a first rotation angle, with each of a plurality of partial regions within an available region in which physical quantum bits that can be used for the phase rotation of the state of the logical quantum bit by the first rotation angle being the operation target; causing the quantum computer to perform a phase rotation operation using the first auxiliary state indicated in a first partial region in which the generation of the first auxiliary state has been successful, with the logical quantum bit as an operation target; A quantum computing support program that causes a computer to perform processing.

2. In the process of causing the quantum computer to perform the phase rotation operation, a phase rotation circuit is caused to operate on the quantum computer, which stochastically applies either a phase rotation in a target rotation direction or a phase rotation in a direction opposite to the target rotation direction to the logical quantum bit; While the quantum computer is executing the phase rotation circuit, a second partial region among the plurality of partial regions within the available region that is unused by the phase rotation circuit is targeted for operation, and the quantum computer is caused to execute an operation of generating a second auxiliary state to be used for phase rotation by a second rotation angle that is twice the first rotation angle; when the phase rotation in the opposite direction occurs as a result of the execution of the phase rotation circuit, causing the quantum computer to execute a gate operation of the phase rotation circuit using the second auxiliary state shown in the second partial region as an input, with the logical quantum bit as an operation target; The quantum computing support program according to claim 1.

3. In the process of causing the quantum computer to execute the operation of generating the second auxiliary state, while the quantum computer is executing the gate operation of the phase rotation circuit, the quantum computer is repeatedly caused to execute the generation of the second auxiliary state using the second partial region until the generation of the second auxiliary state in the second partial region is successful. The quantum computing support program according to claim 2.

4. In the process of causing the quantum computer to execute the operation of generating the second auxiliary state, the range of the available area is updated according to the usage status of physical quantum bits outside the available area while the quantum computer is executing the gate operation of the phase rotation circuit. The quantum computing support program according to claim 2.

5. When there are a plurality of logical quantum bits to be operated on, areas that can be allocated to two or more of the available areas corresponding to each of the plurality of logical quantum bits are allocated to an available area having a smaller size among the allocatable available areas. The quantum computing support program according to claim 1, further causing a computer to execute a process.

6. The computer causing a quantum computer to perform an operation of generating a first auxiliary state to be used for a phase rotation of a state of a logical quantum bit by a first rotation angle, with each of a plurality of partial regions within an available region in which physical quantum bits that can be used for the phase rotation of the state of the logical quantum bit by the first rotation angle being the operation target; causing the quantum computer to perform a phase rotation operation using the first auxiliary state indicated in a first partial region in which the generation of the first auxiliary state has been successful, with the logical quantum bit as an operation target; Quantum computing support method.

7. a processing unit that causes a quantum computer to perform an operation of generating a first auxiliary state to be used for phase rotation of a state of a logical quantum bit by a first rotation angle, with each of a plurality of partial regions within an available region in which physical quantum bits that can be used for phase rotation of the state of the logical quantum bit by the first rotation angle being set as operation targets, and that causes the quantum computer to perform a phase rotation operation using the first auxiliary state indicated in a first partial region in which generation of the first auxiliary state has been successful, with the logical quantum bit being set as the operation target; An information processing device having the above.

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