Semiconductor device

Abstract

To provide a semiconductor device capable of reducing the amount of change in voltage with respect to time when the voltage sharply changes during turn-off.SOLUTION: The first surface side region of the semiconductor portion has a second semiconductor layer of the second conductivity type facing the first gate electrode and a third semiconductor layer of the first conductivity type in contact with the first electrode. The second surface side region of the semiconductor part has a fourth semiconductor layer of the second conductivity type in contact with the second electrode, a fifth semiconductor layer of the first conductivity type in contact with the second electrode, a sixth semiconductor layer of the first conductivity type having a first conductivity-type impurity concentration lower than that of the fifth semiconductor layer, and a seventh semiconductor layer of the second conductivity type facing the second gate electrode and located between the fifth semiconductor layer and the sixth semiconductor layer. The semiconductor part further includes an eighth semiconductor layer of the second conductivity type provided at a position facing at least the sixth semiconductor layer in the first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] An IGBT (Insulated Gate Bipolar Transistor) with a double-sided gate structure in which gate electrodes are provided on both the front and back sides of a semiconductor layer has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-49610 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a semiconductor device that can reduce the amount of change in voltage over time when the voltage changes abruptly during turn-off. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a first semiconductor layer of a first conductivity type; a first-surface side region located between the first electrode and the first semiconductor layer in the first direction; and a second-surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first-surface side region; a plurality of first insulating films provided between the first-surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes facing the second-surface side region in the first direction; and a plurality of second insulating films provided between the second-surface side region and the plurality of second gate electrodes, wherein the first-surface side region includes a second semiconductor layer of a second conductivity type facing the first gate electrode via the first insulating film; and a third semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode, the second surface side region having a fourth semiconductor layer of the second conductivity type in contact with the second electrode, a fifth semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the second electrode, a sixth semiconductor layer of the first conductivity type having a lower first conductivity type impurity concentration than the fifth semiconductor layer, and a seventh semiconductor layer of the second conductivity type facing the second gate electrode via the second insulating film and positioned between the fifth semiconductor layer and the sixth semiconductor layer, the semiconductor section further having an eighth semiconductor layer of the second conductivity type provided at a position facing at least the sixth semiconductor layer in the first direction, and the distance in the first direction between the eighth semiconductor layer and the second electrode is shorter than the distance in the first direction between the eighth semiconductor layer and the first electrode. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 2 is a schematic plan view of a second surface side region in the semiconductor device of the embodiment. FIG. [Figure 3] 3A and 3B are schematic cross-sectional views of a second surface side region in a semiconductor device according to an embodiment. [Figure 4]3A and 3B are schematic cross-sectional views of a second surface side region in a semiconductor device according to an embodiment. [Figure 5] 3A and 3B are schematic plan views of a second surface side region in the semiconductor device of the embodiment. [Figure 6] 3A and 3B are schematic plan views of a second surface side region in the semiconductor device of the embodiment. [Figure 7] 10 is a graph showing a simulation result. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, identical or similar elements are given the same reference numerals.

[0008] FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment.

[0009] The semiconductor device 1 includes a first electrode 51, a second electrode 52, a semiconductor portion 10, a plurality of first gate electrodes 61, a plurality of first insulating films 71, a plurality of second gate electrodes 62, and a plurality of second insulating films 72. The semiconductor device 1 is an IGBT, and the first electrode 51 is an emitter electrode and the second electrode 52 is a collector electrode.

[0010] The semiconductor portion 10 is located between the first electrode 51 and the second electrode 52 in the first direction Z. Two directions perpendicular to the first direction Z are defined as the second direction X and the third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0011] The material of the semiconductor portion 10 is, for example, silicon. Alternatively, the material of the semiconductor portion 10 may be silicon carbide, gallium nitride, or the like. In this specification, the first conductivity type of the semiconductor portion 10 is described as n-type, and the second conductivity type is described as p-type. The first conductivity type may also be p-type, and the second conductivity type may also be n-type.

[0012] The semiconductor part 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in the first direction Z. The first electrode 51 faces the first surface 10A in the first direction Z, and the second electrode 52 faces the second surface 10B in the first direction Z.

[0013] The semiconductor unit 10 has an n-type first semiconductor layer 21, a first surface side region 11 located between the first electrode 51 and the first semiconductor layer 21 in the first direction Z, and a second surface side region 12 located between the second electrode 52 and the first semiconductor layer 21 in the first direction Z. The first semiconductor layer 21 is a drift layer in the IGBT. The first surface side region 11 includes a first surface 10A of the semiconductor unit 10 and a portion between the first surface 10A and the first semiconductor layer 21. The second surface side region 12 includes a second surface 10B of the semiconductor unit 10 and a portion between the second surface 10B and the first semiconductor layer 21.

[0014] The first gate electrode 61 faces the first-surface side region 11 of the semiconductor portion 10 via a first insulating film 71. The first insulating film 71 is provided between the first-surface side region 11 and the first gate electrode 61, and between the first semiconductor layer 21 and the first gate electrode 61. The first gate electrode 61 has, for example, a trench gate structure and is provided in a trench extending from the first surface 10A in the first direction Z and penetrating the first-surface side region 11 via the first insulating film 71. A plurality of first gate electrodes 61, each extending in the third direction Y, are aligned in the second direction X. A portion of the first semiconductor layer 21 is located between adjacent first gate electrodes 61 in the second direction X. An insulating layer 73 is provided between the first gate electrode 61 and the first electrode 51 in the first direction Z, and the first gate electrode 61 is not in contact with the first electrode 51. The first gate electrode 61 may have a planar gate structure.

[0015] The plurality of first gate electrodes 61 may include first gate electrodes 61A of a first system and first gate electrodes 61B of a second system. The first gate electrodes 61A of the first system are electrically connected to a first gate drive circuit 91, and the gate voltage of the first gate electrodes 61A of the first system is controlled by the first gate drive circuit 91. The first gate electrodes 61B of the second system are electrically connected to a second gate drive circuit 92, and the gate voltage of the first gate electrodes 61B of the second system is controlled by the second gate drive circuit 92. The gate voltage of the first gate electrodes 61A of the first system and the gate voltage of the first gate electrodes 61B of the second system are controlled independently of each other. Pairs of first gate electrodes 61 of the same system are adjacent to each other in the second direction X, sandwiching the second semiconductor layer 22 and the third semiconductor layer 23 therebetween.

[0016] The first surface side region 11 has a p-type second semiconductor layer 22 and an n-type third semiconductor layer 23. The second semiconductor layer 22 is a base layer of the IGBT. The third semiconductor layer 23 is an emitter layer of the IGBT.

[0017] The second semiconductor layer 22 is located on the first semiconductor layer 21 in the first direction Z and is in contact with the first semiconductor layer 21. The second semiconductor layer 22 is located between the first gate electrodes 61 adjacent to each other in the second direction X. A side surface of the second semiconductor layer 22 faces the first gate electrode 61 in the second direction X, with the first insulating film 71 interposed therebetween. The first gate electrode 61 faces the second semiconductor layer 22 in the second direction X, with the first insulating film 71 interposed therebetween. The second semiconductor layer 22 is in contact with the first insulating film 71.

[0018] The n-type impurity concentration of the third semiconductor layer 23 is higher than the n-type impurity concentration of the first semiconductor layer 21. The third semiconductor layer 23 is located on the second semiconductor layer 22 in the first direction Z and is in contact with the second semiconductor layer 22. The third semiconductor layer 23 is in contact with the first electrode 51 and is electrically connected to the first electrode 51. Two third semiconductor layers 23 are provided between first gate electrodes 61 adjacent to each other in the second direction X and spaced apart from each other in the second direction X. A portion 22A of the second semiconductor layer 22 is located between the two third semiconductor layers 23. The portion 22A of the second semiconductor layer 22 is in contact with the first electrode 51. The p-type impurity concentration of the portion 22A of the second semiconductor layer 22 is higher than the p-type impurity concentration of the second semiconductor layer 22 other than the portion 22A. The third semiconductor layer 23 is in contact with the first insulating film 71.

[0019] The first-surface side region 11 may further include a p-type tenth semiconductor layer 30. The tenth semiconductor layer 30 is located between adjacent first gate electrodes 61 in the second direction X. The depth of the tenth semiconductor layer 30 from the first surface 10A is deeper than the depth of the second semiconductor layer 22 from the first surface 10A. The depth of the tenth semiconductor layer 30 from the first surface 10A is shallower than the depth of the first gate electrode 61 from the first surface 10A. An insulating layer 73 is provided between the tenth semiconductor layer 30 and the first electrode 51 in the first direction Z, and the tenth semiconductor layer 30 is not in contact with the first electrode 51. The tenth semiconductor layer 30 is not in contact with any electrode in the semiconductor device 1 and is in an electrically floating state.

[0020] The third semiconductor layer 23 is not disposed in the tenth semiconductor layer 30. One of both side surfaces of the first gate electrode 61 in the second direction X is adjacent to the third semiconductor layer 23, the second semiconductor layer 22, and a part of the first semiconductor layer 11 located below the second semiconductor layer 22, via the first insulating film 71. The other of both side surfaces of the first gate electrode 61 in the second direction X is adjacent to the tenth semiconductor layer 30, via the first insulating film 71.

[0021] The second gate electrode 62 has a planar gate structure and faces the second-surface side region 12 in the first direction Z. The second insulating film 72 is provided between the second-surface side region 12 and the second gate electrode 62. The second gate electrode 62 is located within the second electrode 52, and the second insulating film 72 is provided between the second gate electrode 62 and the second electrode 52. The second insulating film 72 surrounds the upper surface, lower surface, and side surfaces of the second gate electrode 62. The second gate electrode 62 is not in contact with the second electrode 52.

[0022] The second surface side region 12 has a p-type fourth semiconductor layer 24, an n-type fifth semiconductor layer 25, an n-type sixth semiconductor layer 26, and a p-type seventh semiconductor layer 27.

[0023] The p-type impurity concentration of the fourth semiconductor layer 24 is higher than the p-type impurity concentration of the second semiconductor layer 22 and the p-type impurity concentration of the seventh semiconductor layer 27. The fourth semiconductor layer 24 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The fourth semiconductor layer 24 is a collector layer of the IGBT. The fourth semiconductor layer 24 is located between the second electrode 52 and the seventh semiconductor layer 27 in the first direction Z.

[0024] The n-type impurity concentration of the fifth semiconductor layer 25 is higher than the n-type impurity concentration of the first semiconductor layer 21. A portion of the fifth semiconductor layer 25 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. Another portion of the fifth semiconductor layer 25 is in contact with the second insulating film 72. The fifth semiconductor layer 25 is located between the second electrode 52 and the seventh semiconductor layer 27 in the first direction Z. A portion of the fifth semiconductor layer 25 is located between the second insulating film 72 and the seventh semiconductor layer 27 in the first direction Z. The fifth semiconductor layer 25 is in contact with the fourth semiconductor layer 24 in the second direction X. A portion of the fifth semiconductor layer 25 is in contact with the second insulating film 72.

[0025] The n-type impurity concentration of the sixth semiconductor layer 26 is lower than the n-type impurity concentration of the fifth semiconductor layer 25 and is equivalent to the n-type impurity concentration of the first semiconductor layer 21. The sixth semiconductor layer 26 faces the second gate electrode 62 in the first direction Z via the second insulating film 72. The sixth semiconductor layer 26 is in contact with the second insulating film 72 in the first direction Z. The sixth semiconductor layer 26 is in contact with the seventh semiconductor layer 27 in the second direction X.

[0026] The seventh semiconductor layer 27 has a channel portion 27A that faces the second gate electrode 62 in the first direction Z, with the second insulating film 72 interposed therebetween. The channel portion 27A is located between the fifth semiconductor layer 25 and the sixth semiconductor layer 26 in the second direction X, and is in contact with the fifth semiconductor layer 25 and the sixth semiconductor layer 26. The seventh semiconductor layer 27 is located between the first semiconductor layer 21 and the fourth semiconductor layer 24 and between the first semiconductor layer 21 and the fifth semiconductor layer 25 in the first direction Z, and is in contact with the fourth semiconductor layer 24 and the fifth semiconductor layer 25. The p-type impurity concentration of the seventh semiconductor layer 27 is lower than the p-type impurity concentration of the fourth semiconductor layer 24.

[0027] The second-surface side region 12 may further include an n-type ninth semiconductor layer 29. The ninth semiconductor layer 29 is located between the first semiconductor layer 21 and the seventh semiconductor layer 27 and between the first semiconductor layer 21 and the sixth semiconductor layer 26 in the first direction Z, and is in contact with the first semiconductor layer 21, the seventh semiconductor layer 27, and the sixth semiconductor layer 26. The n-type impurity concentration of the ninth semiconductor layer 29 is higher than the n-type impurity concentration of the first semiconductor layer 21. The ninth semiconductor layer 29 is a buffer layer in the IGBT. By providing the ninth semiconductor layer 29, the expansion of the depletion layer can be stopped by the ninth semiconductor layer 29 when the semiconductor device 1 is in the off state, and the thickness of the first semiconductor layer 21 (thickness in the first direction Z) can be made thinner than when the ninth semiconductor layer 29 is not provided.

[0028] The fourth semiconductor layer 24, the fifth semiconductor layer 25, and the seventh semiconductor layer 27 are arranged symmetrically in the first direction X, with the sixth semiconductor layer 26 sandwiched between them. In the semiconductor device 1, the configuration shown in the cross section of FIG. 1 is repeated in the second direction X. The sixth semiconductor layer 26 is located between two channel portions 27A adjacent to each other in the second direction X. The components of the first-surface side region 11 and the components of the second-surface side region 12 are arranged independently of each other. For example, the shape and arrangement intervals of the multiple first gate electrodes 61 and the shape and arrangement intervals of the multiple second gate electrodes 62 are configured independently of each other.

[0029] 2 is a schematic plan view showing an example of the arrangement of each layer in the second-surface side region 12. For example, the channel portion 27A extends in the third direction Y between the fifth semiconductor layer 25 and the sixth semiconductor layer 26.

[0030] As shown in FIG. 1, the semiconductor portion 10 further includes a p-type eighth semiconductor layer 28 provided at a position facing at least the sixth semiconductor layer 26 in the first direction Z. The direction from a portion of the eighth semiconductor layer 28 toward a portion of the sixth semiconductor layer 26 is along the first direction Z. In the example shown in FIG. 1, the eighth semiconductor layer 28 faces the channel portion 27A and the second gate electrode 62 in the first direction Z. The direction from a portion of the eighth semiconductor layer 28 toward a portion of the channel portion 27A is along the first direction Z. The direction from a portion of the eighth semiconductor layer 28 toward a portion of the second gate electrode 62 is along the first direction Z.

[0031] The p-type impurity concentration of the eighth semiconductor layer 28 is lower than the p-type impurity concentration of the fourth semiconductor layer 24. The eighth semiconductor layer 28 is not in contact with any electrode in the semiconductor device 1 and is in an electrically floating state. The distance (shortest distance) in the first direction Z between the eighth semiconductor layer 28 and the second electrode 52 is shorter than the distance (shortest distance) in the first direction Z between the eighth semiconductor layer 28 and the first electrode 51. The eighth semiconductor layer 28 is provided in the semiconductor section 10 at a position closer to the interface between the semiconductor section 10 and the second electrode 52 than to the interface between the semiconductor section 10 and the first electrode 51.

[0032] 2, the eighth semiconductor layer 28 is represented by a dot pattern. Note that the eighth semiconductor layer 28 is also represented by a dot pattern in FIGS. 5(a) to 6(b), which will be described later. As shown in FIG. 2, in a plan view, the eighth semiconductor layer 28 overlaps at least the sixth semiconductor layer 26. In the example shown in FIG. 2, in a plan view, the eighth semiconductor layer 28 overlaps the channel portion 27A.

[0033] 1, the eighth semiconductor layer 28 is located at the boundary between the first semiconductor layer 21 and the ninth semiconductor layer 29, and is in contact with the first semiconductor layer 21 and the ninth semiconductor layer 29. In the example shown in FIG. 1, the eighth semiconductor layer 28 is separated from the sixth semiconductor layer 26 and the seventh semiconductor layer 27 and is not in contact with them.

[0034] When a positive voltage is applied to the second electrode 52 and the first electrode 51 is set to 0 V, a gate voltage higher than the first threshold voltage is applied to the first gate electrode 61, whereby an n-type first channel (inversion layer) is formed in a portion of the second semiconductor layer 22 (base layer) facing the first gate electrode 61, and the semiconductor device 1 enters an on-state. In the on-state, an electron current flows between the first electrode 51 and the second electrode 52 through the third semiconductor layer 23 (emitter layer), the first channel, the first semiconductor layer 21 (drift layer), the ninth semiconductor layer 29 (buffer layer), the fourth semiconductor layer 24 (collector layer), and the fifth semiconductor layer 25. In the on-state, holes are supplied from the fourth semiconductor layer 24 and the seventh semiconductor layer 27 to the first semiconductor layer 21, creating a high density of electrons and holes in the first semiconductor layer 21, resulting in a low on-resistance.

[0035] The semiconductor device 1 is turned off by applying a gate voltage lower than the first threshold voltage to the first gate electrode 61. At the timing of turn-off when the gate voltage of the first gate electrode 61 is made lower than the first threshold voltage, the gate voltage of the second gate electrode 62 is turned on to a voltage higher than the second threshold voltage. Just before, just after, or simultaneously with the turn-off of the gate voltage of the first gate electrode 61, the gate voltage of the second gate electrode 62 is turned on.

[0036] 1, the first gate electrode 61B of the second system is turned off before the first gate electrode 61A of the first system, thereby narrowing down the amount of electrons injected into the first semiconductor layer 21 and reducing turn-off loss. During the period from when the first gate electrode 61A of the first system is turned on to when it is turned off, the on period of the first gate electrode 61B of the second system is shorter than the on period of the first gate electrode 61A of the first system.

[0037] When the gate voltage of the second gate electrode 62 is turned on, an n-type second channel (inversion layer) is formed in the channel portion 27A of the seventh semiconductor layer 27, and electrons in the first semiconductor layer 21 are discharged to the second electrode 52 via the ninth semiconductor layer 29, the sixth semiconductor layer 26, the second channel, and the fifth semiconductor layer 25. When the semiconductor device 1 is turned off, electrons in the first semiconductor layer 21 are discharged to the second electrode 52 via a path that does not pass through the p-type semiconductor layer, thereby suppressing injection of holes from the fourth semiconductor layer 24 and the seventh semiconductor layer 27 into the first semiconductor layer 21 and reducing turn-off switching loss. The gate voltage of the second gate electrode 62 is turned off before the gate voltage of the first gate electrode 61 is turned on.

[0038] In addition, when the semiconductor device 1 of the embodiment is in a mode in which a return current flows from the first electrode 51 (emitter electrode) to the second electrode 52 (collector electrode), it does not incorporate a commutation diode connected in parallel with the IGBT and does not have a reverse conduction function.

[0039] FIG. 7 is a graph showing the results of simulation calculations of the collector-emitter voltage Vce, collector current density Jc, and dVce / dt for the IGBTs of the example and the comparative example. dVce / dt is the amount of change in Vce with time when Vce changes sharply during turn-off. The example is a model that mimics the semiconductor device 1 of the above embodiment, and the results are shown by the solid line in FIG. 7. The comparative example differs from the example in that it does not have the eighth semiconductor layer 28, and the results are shown by the dashed line in FIG. 7. Note that on the time axis (horizontal axis), the time when all of the first gate electrodes 61 have been turned off is set to 0 seconds.

[0040] In both the example and the comparative example, at time -50 μs, the first gate electrode 61B of the second system was turned off and the second gate electrode 62 was turned on. A gate voltage of 15 V was applied to the second gate electrode 62. The n-type impurity concentration of the first semiconductor layer 21 (drift layer) was 2.0×10 13 cm -3 In this example, the p-type impurity concentration of the eighth semiconductor layer 28 in the first direction Z was 2.0×10 16 cm -3 The p-type impurity concentration of the eighth semiconductor layer 28 is constant in the second direction X. In the example, the eighth semiconductor layer 28 is located at the boundary between the first semiconductor layer 21 and the ninth semiconductor layer 29, as shown in FIG. 1. In the example, the eighth semiconductor layer 28 extends 10 μm on both sides in the second direction X from the center of the sixth semiconductor layer 26 in the second direction X. The width of the sixth semiconductor layer 26 in the second direction X is 4 μm.

[0041] In the comparative example, dVce / dt jumps during turn-off, which can cause problems such as surges. The maximum value of dVce / dt during turn-off in the comparative example was 40 kV / μs. The jump in dVce / dt during turn-off is thought to be caused by punch-through in a partial region of the depletion layer spreading in the drift layer (above the MOSFET on the second surface 10B side of the semiconductor portion 10). Punch-through occurred above the back surface MOSFET on the second surface 10B side, but did not occur in an end region away from the back surface MOSFET in the second direction X.

[0042] According to the embodiment, as shown in FIG. 1, by providing a p-type eighth semiconductor layer 28 at a position facing at least the sixth semiconductor layer 26, it is possible to suppress excessive emission of electrons e to the second electrode 52 in the region facing the sixth semiconductor layer 26 during turn-off. Furthermore, when the depletion layer reaches the eighth semiconductor layer 28, carriers are generated on the upper surface of the eighth semiconductor layer 28, preventing a localized rapid decrease in carriers. This makes it possible to reduce dVce / dt during turn-off. In the embodiment, the maximum value of dVce / dt during turn-off was 7.6 kV / μs.

[0043] Furthermore, the breakdown voltage, turn-off loss, and Jc=80 A / cm in the examples and comparative examples 2 The on-state voltage was simulated at this time. The breakdown voltage of the comparative example was 3807 V, and the breakdown voltage of the example was 3822 V. The turn-off loss of the comparative example was 99 mJ / cm 2 The turn-off loss in the example is 96 mJ / cm 2 The on-voltage of the comparative example was 2.16 V, and the on-voltage of the example was 2.10 V. Therefore, according to this embodiment, dVce / dt can be reduced without impairing other characteristics (breakdown voltage, turn-off loss, on-voltage).

[0044] If the eighth semiconductor layer 28 is too far from the second-surface side region 12 in the first direction Z, punch-through may occur in the first semiconductor layer 21 below the eighth semiconductor layer 28. Therefore, it is preferable that the eighth semiconductor layer 28 be located in a region within 10 μm on the first semiconductor layer 21 side in the first direction Z from the boundary between the first semiconductor layer 21 and the ninth semiconductor layer 29.

[0045] The p-type impurity concentration of the eighth semiconductor layer 28 is 1×10 14 cm -3 More than 1×10 17 cm -3 It is preferable that:

[0046] As shown in FIG. 3(a), the eighth semiconductor layer 28 may be continuously connected in the second direction X. In this case, as shown in FIG. 5(a), the eighth semiconductor layer 28 does not extend continuously in the third direction Y in a plan view. That is, the eighth semiconductor layer 28 does not extend over the entire surface of the semiconductor section 10 in a plane perpendicular to the first direction Z (the XY plane). In a plan view of the XY plane, the eighth semiconductor layer 28 extends in a direction intersecting the third direction Y. This ensures a path for discharging electrons in the first semiconductor layer 21 to the second electrode 52 during turn-off, thereby reducing turn-off switching loss.

[0047] 3(b), the eighth semiconductor layer 28 does not have to be in contact with the ninth semiconductor layer 29. In this case, the eighth semiconductor layer 28 is preferably located in a region within 10 μm on the first semiconductor layer 21 side in the first direction Z from the boundary between the first semiconductor layer 21 and the ninth semiconductor layer 29.

[0048] 4(a), the eighth semiconductor layer 28 may be divided into a plurality of layers and arranged in the first direction Z. At least one eighth semiconductor layer 28 is preferably located in a region within 10 μm on the first semiconductor layer 21 side in the first direction Z from the boundary between the first semiconductor layer 21 and the ninth semiconductor layer 29.

[0049] 4(b), the eighth semiconductor layer 28 may be arranged in a plurality of separate layers in the second direction X. The direction from at least one eighth semiconductor layer 28 toward a part of the sixth semiconductor layer 26 is along the first direction Z.

[0050] As shown in FIG. 5(b), the eighth semiconductor layer 28 may be disposed to extend in the third direction Y in a region overlapping with the sixth semiconductor layer 26 in a plan view.

[0051] 6(a), the eighth semiconductor layer 28 may be arranged in a plurality of separate layers in the third direction Y. The plurality of eighth semiconductor layers 28 are aligned in the third direction Y and spaced apart from each other.

[0052] As shown in FIG. 6( b), the eighth semiconductor layers 28 may be arranged in a checkerboard pattern in a plan view. A portion of the plurality of eighth semiconductor layers 28 and another portion of the plurality of eighth semiconductor layers 28 are aligned in the third direction Y and spaced apart from each other. A direction from one portion of the plurality of eighth semiconductor layers 28 toward a certain channel portion 27A and a direction from one portion of the plurality of eighth semiconductor layers 28 toward a certain sixth semiconductor layer 26 are aligned along the first direction Z. A direction from one portion of the plurality of eighth semiconductor layers 28 toward another channel portion 27A and a direction from one portion of the plurality of eighth semiconductor layers 28 toward a certain sixth semiconductor layer 26 are aligned along the third direction Y and spaced apart from each other. In the third direction Y, the eighth semiconductor layers 28 included in a part of the plurality of eighth semiconductor layers 28 and the eighth semiconductor layers 28 included in another part of the plurality of eighth semiconductor layers 28 are arranged alternately.

[0053] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0054] 1...semiconductor device, 10...semiconductor portion, 10A...first surface, 10B...second surface, 11...first surface side region, 12...second surface side region, 21...first semiconductor layer, 22...second semiconductor layer, 23...third semiconductor layer, 24...fourth semiconductor layer, 25...fifth semiconductor layer, 26...sixth semiconductor layer, 27...seventh semiconductor layer, 27A...channel portion, 28...eighth semiconductor layer, 29...ninth semiconductor layer, 30...tenth semiconductor layer, 51...first electrode, 52...second electrode, 61...first gate electrode, 61A...first gate electrode of first system, 61B...first gate electrode of second system, 62...second gate electrode, 71...first insulating film, 72...second insulating film, 73...insulating layer

Claims

1. A first electrode; A second electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a first semiconductor layer of a first conductivity type, a first surface side region located between the first electrode and the first semiconductor layer in the first direction, and a second surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first surface side region; a plurality of first insulating films provided between the first surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes facing the second surface region in the first direction; a plurality of second insulating films provided between the second surface side region and the plurality of second gate electrodes; Equipped with The first surface side region is a second semiconductor layer of a second conductivity type facing the first gate electrode via the first insulating film; a third semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode; and The second surface side region is a fourth semiconductor layer of the second conductivity type in contact with the second electrode; a fifth semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the second electrode; a sixth semiconductor layer of the first conductivity type having a lower first conductivity type impurity concentration than the fifth semiconductor layer; a seventh semiconductor layer of the second conductivity type facing the second gate electrode via the second insulating film and positioned between the fifth semiconductor layer and the sixth semiconductor layer; and the semiconductor portion further includes an eighth semiconductor layer of a second conductivity type provided at a position facing at least the sixth semiconductor layer in the first direction, a distance in the first direction between the eighth semiconductor layer and the second electrode being shorter than a distance in the first direction between the eighth semiconductor layer and the first electrode;

2. 2. The semiconductor device according to claim 1, wherein a concentration of the second conductivity type impurity in said fourth semiconductor layer is higher than a concentration of the second conductivity type impurity in said seventh semiconductor layer.

3. 3. The semiconductor device according to claim 1, wherein the second surface side region further includes a ninth semiconductor layer of the first conductivity type located between the first semiconductor layer and the seventh semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer.

4. The semiconductor device according to claim 3 , wherein the eighth semiconductor layer is in contact with the ninth semiconductor layer.

5. 4. The semiconductor device according to claim 3, wherein the eighth semiconductor layer is located within 10 [mu]m from a boundary between the first semiconductor layer and the ninth semiconductor layer toward the first semiconductor layer in the first direction.

6. The semiconductor device according to claim 1 , wherein the eighth semiconductor layer does not extend over the entire surface of the semiconductor portion perpendicular to the first direction.

7. The second conductivity type impurity concentration of the eighth semiconductor layer is 1×10 １４ cm －３ 1x10 or more １７ cm －３ 3. The semiconductor device according to claim 1, wherein:

8. The semiconductor device according to claim 1 , wherein the eighth semiconductor layer is separated from the sixth semiconductor layer and the seventh semiconductor layer.

9. The semiconductor device according to claim 1 , wherein the eighth semiconductor layer is divided into a plurality of layers and arranged in the first direction.

10. The semiconductor device according to claim 1 , wherein the eighth semiconductor layer is divided into a plurality of layers and arranged in a second direction perpendicular to the first direction.

11. 3. The semiconductor device according to claim 1, wherein the plurality of first gate electrodes include first gate electrodes of a first system and first gate electrodes of a second system, and wherein gate voltages of the first gate electrodes of the first system and the first gate electrodes of the second system are controlled independently of each other.

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