Circuit module

Abstract

To suppress an increase in circuit scale in a module having a plurality of dies.SOLUTION: The module substrate 50 forms the power supply circuit, the first functional part, and the first slave circuit 12 in the first die 10, sets the time information of the first functional part power mode designation command in the first power mode setting register, and forms the second functional part and the second slave circuit 21 in the second die 20. Setting information in the second power mode setting register at the time of the second functional section power mode designation command, forming the second sub-slave circuit in the first die, setting information in the second power mode setting sub-register at the time of the second functional section power mode designation command, and forming, in the power supply circuit, the first power supply wiring 18 that supplies power to the first functional section and the second power supply wiring 28 that connects the first and second dies and supplies power to the second functional section; The first and second functional sections include an active mode and a low power mode, and operate the power supply circuit when one of the first and second power mode setting sub-registers is in the active mode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit module. [Background technology]

[0002] In a high-frequency communication module, a technology for performing data communication between a master device and multiple slave circuits via a serial bus is known (see Patent Document 1). A slave ID for identification is assigned to each of the multiple slave circuits. When the master device transmits a command via the serial bus in which a slave ID specifying one of the multiple slave circuits is set, the slave circuit having the slave ID set in the command executes processing according to the command. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0242057 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, multiple slave circuits are formed on different dies. Furthermore, each of the multiple dies is equipped with a power supply circuit (voltage regulator) for operating the functional units. If a power supply circuit is equipped on each of the multiple dies, the circuit size of each die increases. An object of the present invention is to provide a circuit module that can suppress an increase in circuit size in a module having multiple dies. [Means for solving the problem]

[0005] According to one aspect of the present invention, a power supply circuit formed on the first die; a first functional portion formed on the first die; a first slave circuit formed on the first die, receiving a command specifying a first slave ID, and setting information specifying a power mode of the first functional unit in a first power mode setting register when the received command is a command specifying a power mode of the first functional unit; a second functional portion formed on a second die different from the first die; a second slave circuit formed on the second die, receiving a command specifying a second slave ID, and setting information specifying a power mode of the second functional unit in a second power mode setting register when the received command is a command specifying a power mode of the second functional unit; a second sub-slave circuit formed on the first die, receiving a command specifying the second slave ID, and setting information specifying a power mode of the second functional unit in a second power mode setting sub-register when the received command is a command specifying a power mode of the second functional unit; a first power supply wiring formed on the first die and supplying power from the power supply circuit to the first functional unit; a second power supply wiring that connects the first die and the second die and supplies power from the power supply circuit to the second function unit; a power supply control circuit that operates the power supply circuit when at least one of the first power mode setting register and the second power mode setting sub-register is set to the active mode; and A circuit module is provided. [Effects of the Invention]

[0006] A power supply circuit formed on the first die supplies power to a second functional unit formed on the second die. Since there is no need to form a power supply circuit for the second functional unit on the second die, an increase in circuit size can be suppressed. Information specifying the power mode of the second functional unit on the second die is set in a second power mode setting sub-register formed on the first die. Therefore, the power supply control circuit on the first die can control the power supply circuit without referring to the second power mode setting register on the second die, thereby suppressing an increase in the number of signal lines between the first die and the second die. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a circuit module according to a first embodiment. [Figure 2] FIG. 2 is a table showing the relationship between the setting values ​​of the first power mode setting register 11P, the setting values ​​of the second power mode setting sub-register 12P, and the operating state of the power supply circuit 14. In FIG. [Figure 3] FIG. 3 is a block diagram of the first slave circuit 11 and the second slave circuit 21. As shown in FIG. [Figure 4] FIG. 4 is a flowchart showing a processing procedure executed by the second sub-serial interface unit 12A of the first die 10 (FIG. 1). [Figure 5] 5 is a table showing whether the second sub-serial interface unit 12A and the second serial interface unit 21A read out the register value when they receive a command addressed to them requesting the reading out of the register value. [Figure 6] FIG. 6 is a block diagram of a circuit module according to the second embodiment. [Figure 7] FIG. 7 is a table showing the relationship between the setting values ​​of the first power mode setting register 11P, the setting values ​​of the second power mode setting sub-register 12P, and the operating states of the main power supply circuit 16, the bias circuit 17, and the power supply circuit 14. [Figure 8] FIG. 8 is a diagram showing the individual registers included in the first register 11B, the second sub-register 12B, and the second register 21B (FIG. 3). DETAILED DESCRIPTION OF THE INVENTION

[0008] [First Example] A circuit module according to a first embodiment will be described with reference to FIGS. 1 to 5. FIG. 1 is a block diagram of a circuit module according to a first embodiment. The circuit module according to the first embodiment includes a first die 10 and a second die 20. The first die 10 and the second die 20 are mounted on a module substrate 50, for example.

[0009] A first slave circuit 11, a second sub-slave circuit 12, a power supply control circuit 13, a power supply circuit 14, and a first functional unit 15 are formed on a first die 10. A second slave circuit 21 and a second functional unit 25 are formed on a second die 20.

[0010] The first slave circuit 11 includes a first serial interface unit 11A and a first power mode setting register 11P. The second sub-slave circuit 12 includes a second sub-serial interface unit 12A and a second power mode setting sub-register 12P. The second slave circuit 21 includes a second serial interface unit 21A and a second power mode setting register 21P. A clock signal SCLK is supplied to the first serial interface unit 11A, the second sub-serial interface unit 12A, and the second serial interface unit 21A via a clock line 41, and serial data SDATA is transmitted from a master device (not shown) via a serial bus 40. The serial data SDATA includes, for example, commands for the functional units of each die.

[0011] Information specifying the power mode of the first functional unit 15 is set in the first power mode setting register 11P. Information specifying the power mode of the second functional unit 25 is set in the second power mode setting register 21P and the second power mode setting sub-register 12P. The first slave circuit 11 includes a plurality of individual registers in addition to the first power mode setting register 11P, and the second sub-slave circuit 12 includes a plurality of individual registers in addition to the second power mode setting sub-register 12P. The second slave circuit 21 includes a plurality of individual registers in addition to the second power mode setting register 21P.

[0012] A first slave ID is set in the first slave circuit 11, and a second slave ID is set in the second sub-slave circuit 12 and the second slave circuit 21. The first serial interface unit 11A receives a command in which the first slave ID is set. When the received command is a command specifying the power mode of the first functional unit 15, information specifying the power mode of the first functional unit 15 is set in the first power mode setting register 11P.

[0013] Both the second serial interface unit 21A and the second sub-serial interface unit 12A receive a command specifying a second slave ID. When the received command specifies the power mode of the second functional unit 25, the second serial interface unit 21A sets information specifying the power mode of the second functional unit 25 in the second power mode setting register 21P, and the second sub-serial interface unit 12A sets information specifying the power mode of the second functional unit 25 in the second power mode setting sub-register 12P.

[0014] The power supply circuit 14 receives a battery voltage Vb from the module substrate 50 and stabilizes the voltage. A first power supply wiring 18 is formed on the first die 10. Power is supplied from the power supply circuit 14 to the first functional unit 15 via the first power supply wiring 18. A second power supply wiring 28 connects the first die 10 and the second die 20. More specifically, the second power supply wiring 28 includes wiring connected to the power supply circuit 14 of the first die 10, wiring formed on the module substrate 50, and wiring connected to the second functional unit 25 of the second die 20. Power is supplied from the power supply circuit 14 to the second functional unit 25 via the second power supply wiring 28.

[0015] Either the active mode or the low power mode is selected as the power mode of the first functional unit 15 and the second functional unit 25. Either the "active mode" or the "low power mode" is set in the first power mode setting register 11P, the second power mode setting sub-register 12P, and the second power mode setting register 21P.

[0016] Next, the control of the power supply by the power supply control circuit 13 (FIG. 1) will be described with reference to Fig. 2. Fig. 2 is a diagram showing the relationship between the setting value of the first power mode setting register 11P, the setting value of the second power mode setting sub-register 12P, and the operating state of the power supply circuit 14.

[0017] When at least one of the first power mode setting register 11P and the second power mode setting sub-register 12P is set to the active mode, the power supply control circuit 13 (FIG. 1) sets the power supply circuit 14 to the on state. This causes power to be supplied to the first functional unit 15 and the second functional unit 25. When both the first power mode setting register 11P and the second power mode setting sub-register 12P are set to the low power mode, the power supply control circuit 13 sets the power supply circuit 14 to the off state. This causes power supply to the first functional unit 15 and the second functional unit 25 to stop.

[0018] Next, the detailed configurations and functions of the first slave circuit 11, the second sub-slave circuit 12, and the second slave circuit 21 will be described with reference to FIG.

[0019] 3 is a block diagram of the first slave circuit 11, the second sub-slave circuit 12, and the second slave circuit 21. First, the function of the second serial interface unit 21A of the second slave circuit 21 will be described. The data receiving unit 21A1 receives a command transmitted over the serial bus 40. The error detecting unit 21A2 detects errors in the received command. For example, the command is provided with an error detecting code such as a parity bit, and the error detecting unit 21A2 detects a reception error in the command based on the error detecting code and provides the error detection result to the register write control unit 21A7.

[0020] The initial value of its own second slave ID is stored in ID initial value storage unit 21A4. When second slave circuit 21 is reset, the initial value of the second slave ID is set in slave ID storage unit 21A5. If no error is detected in the received command, the command is a command to update the slave ID, and the destination of the command is its own current slave ID, slave ID update unit 21A3 updates the value of the slave ID stored in slave ID storage unit 21A5 to the value specified in the command. From the next command, the slave ID of the destination of the command is compared with the updated slave ID.

[0021] The ID comparison unit 21A6 compares the value of the slave ID set in the command received by the data receiving unit 21A1 with the value of the slave ID stored in the slave ID storage unit 21A5, and provides the comparison result to the register write control unit 21A7.

[0022] The second register 21B includes a plurality of individual registers. The second power mode setting register 21P (FIG. 1) is one of the individual registers of the second register 21B. The register address holding unit 21A8 stores address information specifying an individual register of the second register 21B. When the received command is a command to rewrite the value of a register, the data receiving unit 21A1 stores the address of the target register of the second register 21B in the register address holding unit 21A8 based on the content of the received command. Furthermore, the data receiving unit 21A1 stores the value (data) to be set in the write data holding unit 21A9 based on the content of the command.

[0023] If the error detection unit 21A2 does not detect an error and the comparison result by the ID comparison unit 21A6 is "match," the register write control unit 21A7 writes the data stored in the write data holding unit 21A9 to the register specified by the address stored in the register address holding unit 21A8. If the error detection unit 21A2 detects an error or the comparison result by the ID comparison unit 21A6 is "mismatch," the register write control unit 21A7 does not write data to the second register 21B. In other words, the register value setting process is not executed.

[0024] Next, the configurations and functions of the first slave circuit 11 and the second sub-slave circuit 12 will be described. The first slave circuit 11 includes a first serial interface unit 11A and a first register 11B. The first register 11B includes a first power mode setting register 11P (FIG. 1) as one individual register. The second sub-slave circuit 12 includes a second sub-serial interface unit 12A and a second sub-register 12B. The second sub-register 12B includes a second power mode setting sub-register 12P (FIG. 1) as one individual register.

[0025] Next, we will explain the functions of the first serial interface unit 11A and the second sub-serial interface unit 12A of the first slave circuit 11. The second sub-serial interface unit 12A includes a data receiving unit 12A1, an error detecting unit 12A2, a slave ID updating unit 12A3, an ID initial value storage unit 12A4, an ID comparing unit 12A5, a slave ID storage unit 12A6, a register write control unit 12A7, a register address holding unit 12A8, and a write data holding unit 12A9. The functions of these blocks are the same as the functions of the corresponding blocks of the second serial interface unit 21A.

[0026] The initial ID value stored in the ID initial value storage unit 12A4 of the second sub-serial interface unit 12A is the same as the initial ID value stored in the ID initial value storage unit 21A4 of the second serial interface unit 21A. A command to update the slave ID is received by both the second serial interface unit 21A and the second sub-serial interface unit 12A, and the values ​​in the slave ID storage unit 21A5 of the second serial interface unit 21A and the slave ID storage unit 12A6 of the second sub-serial interface unit 12A are updated simultaneously. Therefore, the value in the slave ID storage unit 21A5 of the second serial interface unit 21A and the value in the slave ID storage unit 12A6 of the second sub-serial interface unit 12A are always the same.

[0027] The function of the first serial interface unit 11A is the same as the function of the second serial interface unit 21A, so a detailed description will be omitted. Note that the initial value of the slave ID of the first serial interface unit 11A is different from the initial value of the slave ID of the second serial interface unit 21A.

[0028] Next, a processing procedure executed by the second sub-serial interface unit 12A (FIG. 1) of the first die 10 will be described with reference to Fig. 4. Fig. 4 is a flowchart showing a processing procedure executed by the second sub-serial interface unit 12A (FIG. 1) of the first die 10. Upon receiving a command addressed to the second slave circuit 21 (step S1), the second sub-serial interface unit 12A decodes the command (step S2).

[0029] If the received command is a command to read a register value, the command reception process ends without executing the register value read process. Note that the second serial interface unit 21A of the second slave circuit 21, which is assigned the same slave ID as the slave ID of the second sub-serial interface unit 12A, also receives the same command. In response to the received command, the second serial interface unit 21A reads the register value and transmits a reply message to the master device.

[0030] If the command received by the second sub-serial interface unit 12A is other than a command for reading a register value, the second sub-serial interface unit 12A performs an operation according to the content of the command (step S4). When the reception process of one command is completed, the processing procedure shown in Fig. 4 is resumed, and the detection process of the next command is executed.

[0031] Next, a method for reading the contents of the second sub-register 12B (FIG. 3) will be described with reference to FIG. 5. The second slave circuit 21 and the second sub-slave circuit 12 (FIG. 1) have an operation mode and a test mode as operation modes. The operation mode is set when the second serial interface unit 21A and the second sub-serial interface unit 12A receive a command addressed to the second slave circuit 21.

[0032] FIG. 5 is a table showing whether the second sub-serial interface unit 12A and the second serial interface unit 21A read the register value when they receive a command addressed to them requesting the reading of the register value.

[0033] When the operating mode is the operation mode, upon receiving a command requesting the reading of a register value, the second slave circuit 21 reads the register value and returns a message to the master device. At this time, the second sub-slave circuit 12 also receives the same command, but the second sub-slave circuit 12 does not read the register value or return a message to the master device. When the operating mode is the test mode, it is possible to set the second slave circuit 21 not to read register values, or the second sub-slave circuit 12 not to read register values. When the second slave circuit 21 is set not to read register values, the second slave circuit 21 does not return a message to the master device. Instead, the second sub-slave circuit 12 reads the register value and returns a message to the master device.

[0034] When the master device sets the slave ID of the second slave circuit 21 and sends a command requesting the reading of a register value, only one of the second slave circuit 21 and the second sub-slave circuit 12 returns a message, thereby avoiding conflicts in return messages.

[0035] Next, the excellent effects of the first embodiment will be described. In the first embodiment, power is supplied to the second functional unit 25 (FIG. 1) of the second die 20 from the power supply circuit 14 of the first die 10. Since there is no need to provide a power supply circuit on the second die 20, an increase in the circuit scale of the second die 20 can be suppressed compared to a configuration in which a power supply circuit is provided on the second die 20.

[0036] In order for the power supply circuit 14 of the first die 10 to supply power to the second functional unit 25, the power supply control circuit 13 must obtain information specifying the power mode of the second functional unit 25 of the second die 20. In the first embodiment, information specifying the power mode of the second functional unit 25 is set in the second power mode setting sub-register 12P (FIG. 1) of the second sub-slave circuit 12 formed on the first die 10. Therefore, the power supply control circuit 13 can control the on / off of the power supply circuit 14 without referring to this information from the second die 20. In other words, there is no need to provide a signal line for notifying the first die 10 of the information specifying the power mode of the second functional unit 25 from the second die 20.

[0037] To provide these signal lines, space for the signal lines must be secured on the module substrate 50 (FIG. 1). In the first embodiment, there is no need to secure space for these signal lines, so an increase in the size of the circuit module can be suppressed.

[0038] When the second serial interface unit 21A of the second slave circuit 21 receives a command to update the slave ID, it updates its own slave ID. This command is also received by the second sub-serial interface unit 12A, and the second sub-serial interface unit 12A updates its own slave ID. Therefore, there is no mismatch in the slave ID values ​​between the second serial interface unit 21A and the second sub-serial interface unit 12A.

[0039] If an error is contained in a command transmitted over the serial bus 40 and addressed to the second slave circuit 21, the error is detected in the second slave circuit 21, and the register rewrite process corresponding to the command is not executed. In the first embodiment, the error detection unit 12A2 (FIG. 3) of the second sub-serial interface unit 12A has the same function of detecting command reception errors as the error detection unit 21A2 (FIG. 3) of the second serial interface unit 21A.

[0040] Therefore, if an error is contained in a command transmitted over the serial bus 40 and addressed to the second slave circuit 21, the error is also detected in the second sub-serial interface unit 12A, and the register rewrite process corresponding to the command is not executed. This prevents a mismatch between the register value in the second register 21B and the register value in the second sub-register 12B. This makes it possible to maintain the consistency of operation between the power supply circuit 14 of the first die 10 and the second functional unit 25 of the second die 20.

[0041] In the first embodiment, even if the second sub-serial interface unit 12A (FIG. 1) receives a command to read the value of a register, it does not execute the register read process (step S3 in FIG. 4). This avoids a conflict in which both the second serial interface unit 21A (FIG. 1) and the second sub-serial interface unit 12A (FIG. 1) respond to a read command for the second register 21B.

[0042] In the first embodiment, by setting the operation mode of the second sub-slave circuit 12 to the test mode (FIG. 5), the master device can read the value of the second sub-register 12B (FIG. 3) of the second sub-slave circuit 12. This makes it easier to test and debug the communication module.

[0043] [Second Example] Next, a circuit module according to a second embodiment will be described with reference to Figures 6, 7, and 8. Below, a description of the configuration common to the circuit module according to the first embodiment described with reference to Figures 1 to 5 will be omitted.

[0044] 6 is a block diagram of a circuit module according to the second embodiment. In the second embodiment, a band selection switch 15A and an antenna switch 25A are used as the first functional unit 15 and the second functional unit 25 (FIG. 1) of the first embodiment, respectively. An antenna terminal 51 of a module substrate 50 is connected to an antenna 36.

[0045] In addition to a first slave circuit 11, a second sub-slave circuit 12, a power control circuit 13, a power circuit 14, and a band selection switch 15A, a main power circuit 16 and a bias circuit 17 are formed on the first die 10. In addition to the first die 10 and the second die 20, a transmitter circuit 30 and a plurality of filters 35 are mounted on the module substrate 50. The transmitter circuit 30 includes a high-frequency amplifier formed of a heterojunction bipolar transistor or the like, and amplifies a high-frequency signal RFin. The plurality of filters 35 are bandpass filters that pass high-frequency signals in each frequency band of communication standards such as the fifth-generation mobile communication system (5G).

[0046] The main power supply circuit 16 stabilizes the battery voltage Vbatt supplied from an external source and supplies power to the power supply circuit 14 and bias circuit 17 in the first die 10 via a power supply wiring 19. The main power supply circuit 16 is controlled to be turned on and off by commands from the power supply control circuit 13. The bias circuit 17 supplies bias to the amplifier of the transmission circuit 30 based on commands from the first slave circuit 11. The power supply circuit 14 supplies power to the band selection switch 15A and the antenna switch 25A, as in the first embodiment (FIG. 1).

[0047] The band selection switch 15A selects one filter 35 from the plurality of filters 35 based on a command from the first slave circuit 11, and connects the selected filter 35 to the transmission circuit 30. The antenna switch 25A selects one filter 35 from the plurality of filters 35 based on a command from the second slave circuit 21, and connects the selected filter 35 to the antenna terminal 51. The high-frequency signal amplified by the transmission circuit 30 is supplied to the antenna 36 via the band selection switch 15A, the selected one filter 35, the antenna switch 25A, and the antenna terminal 51.

[0048] 7 is a diagram showing the relationship between the setting values ​​of the first power mode setting register 11P, the setting values ​​of the second power mode setting sub-register 12P, and the operating states of the main power supply circuit 16, the bias circuit 17, and the power supply circuit 14. When the setting value of at least one of the first power mode setting register 11P and the second power mode setting sub-register 12P is the active mode, the power supply control circuit 13 sets both the main power supply circuit 16 and the power supply circuit 14 to the on state. When the setting values ​​of both the first power mode setting register 11P and the second power mode setting sub-register 12P are the low power mode, the power supply control circuit 13 sets both the main power supply circuit 16 and the power supply circuit 14 to the off state.

[0049] When the first power mode setting register 11P is in the low power mode, the first slave circuit 11 sets the bias circuit 17 to the off state, and when the first power mode setting register 11P is in the active mode, the first slave circuit 11 sets the bias circuit 17 to the on state.

[0050] FIG. 8 is a diagram showing the plurality of individual registers included in the first register 11B, the second sub-register 12B, and the second register 21B (FIG. 3). In FIG. 8, a circle symbol indicates that an individual register is implemented, and a dash symbol indicates that an individual register is not implemented. As shown in FIG. 8, only some of the plurality of individual registers implemented in the second register 21B are implemented in the second sub-register 12B. The same values ​​as the values ​​of the corresponding individual registers in the second register 21B are set in the plurality of individual registers in the second sub-register 12B.

[0051] Next, the meaning of each of the multiple individual registers will be explained. The second register 21B includes a first control register and a second control register for controlling the antenna switch 25A (FIG. 6). The value of the second control register is also used to control the bias circuit 17 (FIG. 6).

[0052] The power mode setting registers of the first register 11B, the second sub-register 12B, and the second register 21B correspond to the first power mode setting register 11P, the second power mode setting sub-register 12P, and the second power mode setting register 21P (FIG. 6), respectively.

[0053] The product ID_1 register and the ID register indicating the manufacturer are registers in which the product ID and manufacturer ID are set, respectively. The unique slave ID register is a register in which the slave ID is set. The product ID_2 register is a register in which the extended product ID is set. The group slave ID register is a register in which the group slave ID is set. The error and reset register contains an error flag and a flag for performing a soft reset. The fuse register is a register for fuse control. The adjustment register is a register for analog adjustment.

[0054] Next, the excellent effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, there is no need to provide a power supply circuit on the second die 20, which can prevent an increase in the circuit size of the second die 20. Furthermore, there is no need to provide a signal line for transmitting information specifying the power mode of the antenna switch 25A from the second die 20 to the first die 10. This can prevent an increase in the size of the circuit module.

[0055] When transmitting a high-frequency signal, the first power mode setting register 11P and the second power mode setting sub-register 12P are both set to the active mode, thereby operating the bias circuit 17 and supplying power to the band selection switch 15A and the antenna switch 25A, as shown in FIG. 7. When receiving a signal, the first power mode setting register 11P is set to the low power mode, and the second power mode setting sub-register 12P is set to the active mode. This allows the antenna switch 25A to be operated, and the signal received by the antenna 36 (FIG. 6) to be transmitted to the receiving circuit (not shown). At this time, the bias circuit (FIG. 6) is in the off state, thereby reducing unnecessary power consumption.

[0056] The second sub-register 12B is provided with individual registers corresponding to some of the multiple individual registers of the second register 21B, and individual registers corresponding to the remaining individual registers are not provided in the second sub-register 12B, which makes it possible to suppress an increase in the circuit size of the second sub-slave circuit 12.

[0057] The above-described embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects resulting from similar configurations of multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0058] Based on the above examples described in this specification, the following invention is disclosed. <1> a power supply circuit formed on the first die; a first functional portion formed on the first die; a first slave circuit formed on the first die, receiving a command specifying a first slave ID, and setting information specifying a power mode of the first functional unit in a first power mode setting register when the received command is a command specifying a power mode of the first functional unit; a second functional portion formed on a second die different from the first die; a second slave circuit formed on the second die, receiving a command specifying a second slave ID, and setting information specifying a power mode of the second functional unit in a second power mode setting register when the received command is a command specifying a power mode of the second functional unit; a second sub-slave circuit formed on the first die, receiving a command specifying the second slave ID, and setting information specifying a power mode of the second functional unit in a second power mode setting sub-register when the received command is a command specifying a power mode of the second functional unit; a first power supply wiring formed on the first die and supplying power from the power supply circuit to the first functional unit; a second power supply wiring that connects the first die and the second die and supplies power from the power supply circuit to the second function unit; a power supply control circuit that operates the power supply circuit when at least one of the first power mode setting register and the second power mode setting sub-register is set to the active mode; and A circuit module comprising:

[0059] <2> the first functional unit includes a band selection switch that selects one filter from a plurality of filters and connects the selected filter to a transmission circuit; The second functional unit includes an antenna switch that selects one of the plurality of filters and connects the selected filter to an antenna. <1> The circuit module according to claim 1.

[0060] <3> further comprising a serial bus connected to the first slave circuit, the second slave circuit, and the second sub-slave circuit; A command is input to the first slave circuit, the second slave circuit, and the second sub-slave circuit through the serial bus. <1> or <2> The circuit module according to claim 1.

[0061] <4> the second slave circuit has a function of detecting a command reception error, and when the second slave circuit detects a reception error, does not execute a process of setting a value of the second power mode setting register according to the command for which the reception error was detected; The second sub-slave circuit has a function of detecting a command reception error, and when a reception error is detected, does not execute a process of setting a value of the second power mode setting sub-register according to the command in which the reception error is detected. <1> ~ <3> 10. The circuit module according to claim 9, wherein:

[0062] <5> the second slave circuit includes a plurality of individual registers in addition to the second power mode setting register; The second sub-slave circuit is provided with individual registers in which the same values ​​as those of the individual registers of the second slave circuit are set, corresponding to some of the individual registers of the second slave circuit, and individual registers corresponding to the remaining individual registers of the second slave circuit are not provided in the second sub-slave circuit. <1> ~ <4> 10. A circuit module according to claim 9, wherein: [Explanation of symbols]

[0063] 10 First Die 11 First slave circuit 11A 1st serial interface section 11B First register 11P First power mode setting register 12 Second sub-slave circuit 12A Second sub-serial interface section 12A1 Data receiver 12A2 Error detection unit 12A3 Slave ID update unit 12A4 ID initial value storage section 12A5 Slave ID storage section 12A6 ID comparison section 12A7 Register write control section 12A8 Register address holder 12A9 Write data storage unit 12B Second subregister 12P Second power mode setting sub-register 13 Power supply control circuit 14 Power circuit 15 First Functional Section 15A band select switch 16 Main power circuit 17 Bias circuit 18 1st power supply wiring 19 Power wiring 20 Second Die 21 Second slave circuit 21A Second serial interface section 21A1 Data receiving unit 21A2 Error detection unit 21A3 Slave ID update unit 21A4 ID initial value storage section 21A5 Slave ID storage unit 21A6 ID comparison section 21A7 Register write control unit 21A8 Register address holder 21A9 Write data storage unit 21B Second register 21P Second power mode setting register 25 Second Functional Section 25A Antenna Switch 28 2nd power supply wiring 30 Transmitting circuit 35 filters 36 Antenna 40 Serial Bus 41 Clock Line 50 module board 51 Antenna terminal

Claims

1. a power supply circuit formed on the first die; a first functional portion formed on the first die; a first slave circuit formed on the first die, receiving a command specifying a first slave ID, and setting information specifying a power mode of the first functional unit in a first power mode setting register when the received command is a command specifying a power mode of the first functional unit; a second functional unit formed on a second die different from the first die; a second slave circuit formed on the second die, receiving a command specifying a second slave ID, and setting information specifying a power mode of the second functional unit in a second power mode setting register when the received command is a command specifying a power mode of the second functional unit; a second sub-slave circuit formed on the first die, receiving a command specifying the second slave ID, and setting information specifying a power mode of the second functional unit in a second power mode setting sub-register when the received command is a command specifying a power mode of the second functional unit; a first power supply wiring formed on the first die and supplying power from the power supply circuit to the first functional unit; a second power supply wiring that connects the first die and the second die and supplies power from the power supply circuit to the second function unit; power modes of the first functional unit and the second functional unit include an active mode and a low power mode, and a power supply control circuit that operates the power supply circuit when at least one of the first power mode setting register and the second power mode setting sub-register is set to the active mode; A circuit module comprising:

2. the first functional unit includes a band selection switch that selects one filter from a plurality of filters and connects the selected filter to a transmission circuit; The circuit module according to claim 1 , wherein the second functional unit includes an antenna switch that selects one of the plurality of filters and connects the selected filter to an antenna.

3. a serial bus connected to the first slave circuit, the second slave circuit, and the second sub-slave circuit; 3. The circuit module according to claim 1, wherein commands are input to the first slave circuit, the second slave circuit, and the second sub-slave circuit through the serial bus.

4. the second slave circuit has a function of detecting a command reception error, and when the second slave circuit detects a reception error, does not execute a process of setting a value of the second power mode setting register according to the command for which the reception error was detected; The circuit module described in claim 1 or 2, wherein the second sub-slave circuit has a function of detecting a command reception error, and when a reception error is detected, does not execute the setting process of the value of the second power mode setting sub-register corresponding to the command in which the reception error was detected.

5. the second slave circuit includes a plurality of individual registers in addition to the second power mode setting register; 3. The circuit module according to claim 1, wherein the second sub-slave circuit is provided with individual registers corresponding to some of the plurality of individual registers of the second slave circuit, and in which the same values ​​as those of the individual registers of the second slave circuit are set, and the second sub-slave circuit is not provided with individual registers corresponding to the remaining individual registers of the second slave circuit.

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