Method of operating information processing apparatus

Abstract

To apply a computer system with a small circuit area and reduced power consumption.SOLUTION: In an information processor 50 including a controller 1197 and a NAND type storage part 1196 of a three dimensional structure, the NAND type storage part of the three dimensional structure has a first string ST1 and a second string ST2 of different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. The controller receives first data and a signal including an instruction to write the first data, writes the first data to the first memory cell, reads the first data from the first memory cell, and writes the first data to the second memory cell. Thus, the computer node can be configured without a main memory such as a DRAM.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a computer system and an operating method of an information processing device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an object, a method of operation, or a method of manufacturing. is a process, machine, manufacture, or composition of matter. Therefore, one embodiment of the present invention disclosed in this specification more specifically relates to The technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, and imaging devices. Devices, storage devices, signal processing devices, sensors, processors, electronic devices, information processing devices, systems , their operation methods, their manufacturing methods, or their inspection methods, can be done. [Background technology]

[0003] The reduction of power consumption in information processing devices is becoming increasingly important. ), reducing the power consumption of memory devices and other devices is a major issue in circuit design. The power consumption can be roughly divided into two parts: the power consumption when the device is in operation (dynamic power) and the power consumption when the device is not in operation (static power). The power consumption (static power) when in standby mode is twofold. Increasing the power consumption increases the dynamic power. Most of the static power is consumed by the transistors. This is the power consumed by the leakage current of the capacitor. Leakage current, gate tunnel leakage current, gate induced drain leakage (GIDL) Gate-induced drain leakage current, junction These leakage currents increase with the miniaturization of transistors. Therefore, the increase in power consumption is a major obstacle to improving the performance and integration of ICs.

[0004] Consumption of semiconductor devices such as integrated circuits and memory devices, or information processing devices including such semiconductor devices To reduce power consumption, the device is operated using power gating, clock gating, etc. Power gating is a method of stopping unnecessary circuits. This has the effect of eliminating standby power. To do this, it is necessary to back up the contents of registers, caches, etc. to non-volatile memory. It will be necessary to

[0005] The channel forming region is made of an oxide semiconductor (or simply A transistor including an oxide semiconductor (hereinafter referred to as an "oxide semiconductor transistor") These transistors are sometimes called "OS transistors." A memory circuit has been proposed that can retain data even in a power-off state by using a memory cell. For example, Non-Patent Document 1 discloses an OS- SRAM (Static Random Access Memory) is disclosed. 1. Microprocessors equipped with OS-SRAM can withstand short losses without affecting normal operation. It is disclosed that power gating at break-even time (BET) is possible. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] T. Ishizu et al., Int. Memory Workshop, 2014, pp.106-103. [Non-patent document 2] S. Bartling et al., ISSCC Dig.Tech.Papers, pp.432-434, 2013. [Non-patent document 3] N. Sakimura et al., ISSCC Dig.Tech.Papers, pp.184-185, 2014. [Non-patent document 4] VK.Singhal et al., ISSCC Dig.Tech.Papers, pp.148-149, 2015. Summary of the Invention [Problem to be solved by the invention]

[0007] As an example, a NAND type storage device having a storage unit and a cache memory: In a NAND type memory device, the speed of inputting data for writing (per unit time) The amount of information input per second is slower than the speed at which data is written to the memory. Using the cache memory included in the storage device, write data input to the storage device is By temporarily storing the data, the speed at which data is written to the storage device can be reduced. In addition, data can be written to the storage unit. The read speed is the speed at which data is read from the storage device (the amount of information output per unit time). Therefore, the cache memory included in the storage device is used to By temporarily storing data read from the device, Data can be read from the storage unit without reducing the read speed.

[0008] As an example, the cache memory may rearrange the data stored in the storage unit, It has the function to temporarily store data when backing up data that is not related to erasure. .

[0009] The cache memory may be, for example, a DRAM (Dynamic Random Access Memory). ss Memory) is applied. Therefore, the cache memory and NAND type Since each memory device is created using a different process, they are created as separate chips. For this reason, a bus line is provided between the cache memory and the NAND type storage device. This may increase the circuit area of ​​the memory device. In this case, the power consumption of the signals flowing through the bus wiring may increase.

[0010] An object of one aspect of the present invention is to provide a computer system with a reduced circuit area. Another aspect of the present invention is to provide a computer system with low power consumption. This is one of the challenges.

[0011] Another object of one aspect of the present invention is to provide a novel computer system. Another object of one embodiment of the present invention is to provide a novel method for operating an information processing device. Let's say.

[0012] Note that the problems to be solved by one embodiment of the present invention are not limited to the problems listed above. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by solving the problem in the specification. It can be derived from the descriptions in the documents or drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all the problems. [Means for solving the problem]

[0013] (1) One aspect of the present invention is a computer system having a processor and a memory. The processor has a memory unit, and the memory unit is a transistor having a metal oxide in a channel forming region. The processor and the memory are located so as to overlap each other.

[0014] (2) Alternatively, in the above (1), a D A configuration in which RAM is not connected is also possible.

[0015] (3) Alternatively, one aspect of the present invention is a computer having a computer node including a processor. The processor includes a memory unit, and the memory unit includes a first transistor and a second transistor. The first transistor and the second transistor are connected to each other. , each of which has a metal oxide in a channel forming region. is electrically connected to the gate of the second transistor, and the gate of the second transistor is connected to a capacitance The first terminal of the power supply is electrically connected to the power supply.

[0016] (4) Alternatively, in the configuration (3), the processor has an SRAM. , and may not have a flip-flop.

[0017] (5) Alternatively, one aspect of the present invention is a computer system having computer nodes, The computer node has a processor and a three-dimensional NAND type storage device. In addition, the three-dimensional structure of NAND type memory devices is characterized by the fact that metal oxide is included in the channel formation region. Furthermore, the computer node may have a configuration without DRAM. It may also be possible to use the following.

[0018] (6) Another embodiment of the present invention is a memory device including a processor, a memory device, and a plurality of wirings. The device has a plurality of strings, and one of the plurality of strings is connected to one of the plurality of wires. A method for operating an information processing device electrically connected to an arithmetic processing device, comprising: The first data inputted by the method is converted into a plurality of second data, and the plurality of second data is converted into a plurality of distribution data. Distributed to each line, multiple secondary data can be simultaneously supplied to multiple strings according to the trigger signal This is an operation method of an information processing device.

[0019] (7) Alternatively, in one aspect of the present invention, in the configuration (6), the string is made up of a plurality of memory cells. The memory cell may include an oxide semiconductor.

[0020] (8) Alternatively, in one aspect of the present invention, in the configuration (6) or (7), the storage device is It may also be an ND type storage device.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are all semiconductors. It is also applicable to storage devices, display devices, light-emitting devices, lighting devices, electronic devices, information The processing device or the like may itself be a semiconductor device or may include a semiconductor device.

[0022] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0023] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0024] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0025] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are directly connected (i.e., there is no other This includes cases where the device is connected without any element or other circuit in between.

[0026] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0028] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" can be used as a circuit element, wiring, etc. " refers to wiring with resistance, transistors with current flowing between the source and drain, and diodes. Therefore, the term "resistive element" is used to refer to "resistor," "Load" or "area with a resistance value" and conversely, "resistance" or The terms "load" and "area having a resistive value" can be replaced with terms such as "resistive element." The resistance value is preferably, for example, 1 mΩ or more and 10 Ω or less, and more preferably The resistance can be set to 5 mΩ or more and 5 Ω or less, and more preferably 10 mΩ or more and 1 Ω or less. , for example, 1 Ω or more, 1×10 9 It may be set to Ω or less.

[0029] In this specification, the term "capacitance element" refers to a capacitance element having a capacitance value higher than 0 F. a circuit element having a capacitance value, a wiring area having a capacitance value, a parasitic capacitance, a gate of a transistor Therefore, in this specification, a "capacitive element" refers to a pair of Not only circuit elements including electrodes and dielectrics included between the electrodes, but also wiring and wiring The parasitic capacitance that appears between the gate and the source or drain of the transistor. Also, the term "capacitance element," "parasitic capacitance," and "gate capacitance" are included. Terms such as "amount" can be replaced with terms such as "capacity" and vice versa. The term "capacitance element," "parasitic capacitance," "gate capacitance," etc. In addition, the term "pair of electrodes" in "capacitance" can be used to refer to "pair of conductors" or "pair of The capacitance value can be expressed as: For example, the capacitance can be set to 0.05 fF or more and 10 pF or less. It may be set to 10 μF or more.

[0030] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are interchangeable. In addition, in this specification and the like, the connection relationship of the transistors will be described. In this case, "one of the source and the drain" (or the first electrode, or the first terminal), "the source or the drain" The term "second electrode" or "second terminal" is used. Depending on the structure, in addition to the three terminals mentioned above, a back gate may also be present. In this case, in this specification, either the gate or the back gate of the transistor is referred to as the first gate. The other of the gate or back gate of the transistor is called the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" are interchangeable. In addition, transistors with three or more gates can be In this specification, the gates are referred to as the first gate, the second gate, the third gate, and the like. It is sometimes called a "to".

[0031] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0032] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the earth potential (ground potential), then "voltage" can be rephrased as "potential." Round potential does not necessarily mean 0V. Also, potential is relative. By changing the reference potential, the potential applied to the wiring, the potential applied to the circuit, etc. The potential, the potential output from the circuit, etc. also changes.

[0033] In addition, in this specification, the terms "high level potential" and "low level potential" are used to refer to For example, if two wires are both at a high level potential, When it says "acts as a wire supplying the The high level potentials do not have to be equal to each other. If both are described as "functioning as wiring that supplies low-level potential," The low level potentials provided by the respective switches may not be equal to each other.

[0034] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged body" The statement "electrical conduction is occurring in the opposite direction" means "electrical conduction is occurring in the negatively charged body." Therefore, in this specification and the like, unless otherwise specified, the term "current" is used. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire is the direction in which positively charged carriers move, and positive current In other words, the direction in which negatively charged carriers move is opposite to the direction of the current. Therefore, in this specification, the positive and negative currents ( If there is no mention of the direction of the current, the description will be "current flows from element A to element B." This can be rephrased as "current flows from element B to element A", etc. A statement such as "current is input to element A" should be rephrased as "current is output from element A" It is possible to obtain this.

[0035] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0036] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0037] The terms "above" and "below" mean that the positional relationship of the components is directly above or directly below, and For example, the expression "electrode B on insulating layer A" does not necessarily mean that the electrodes are in contact with each other. In this case, electrode B does not need to be formed directly on insulating layer A. This does not exclude the inclusion of other components between the two.

[0038] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0039] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, terms such as "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where multiple "electrodes" and "wiring" are formed as a single unit. For example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. The same applies. Furthermore, the term "terminal" can refer to a plurality of "electrodes," "wiring," "terminals," etc. This includes cases where they are formed as one unit. For example, "electrode" can be used in place of "wiring" or can be a part of a "terminal", and for example, a "terminal" can be a "wiring" or an "electrode". In addition, terms such as "electrode," "wiring," and "terminal" may be used in some cases. This may be replaced with terms such as "area."

[0040] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In addition, the opposite is also true, and terms such as "signal line" can be used to refer to "power line". In some cases, it may be possible to change the term to "potential" or "voltage" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0041] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This leads to, for example, an increase in defect level density in semiconductors and a decrease in carrier mobility. When the semiconductor is an oxide semiconductor, the crystallinity may be reduced. Impurities that change the properties of semiconductors include, for example, Group 1 elements, Group 2 elements, and Group 13 elements. Group elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen Specifically, if the semiconductor is silicon, there are impurities that change the properties of the semiconductor. As the pure substance, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements (however, (oxygen and hydrogen not included)

[0042] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0043] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0045] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0046] According to one aspect of the present invention, there is provided a computer system with a reduced circuit area. Alternatively, one aspect of the present invention provides a computer system with low power consumption. It is possible.

[0047] Alternatively, one aspect of the present invention can provide a novel computer system. Another object of one embodiment of the present invention is to provide a method for operating a novel information processing device. It shall be one of the following.

[0048] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing device. [Figure 2] FIG. 2 is a flowchart showing an example of a method for operating the information processing device. [Figure 3] 3A to 3C are schematic diagrams showing an example of an operation method of the information processing device. [Figure 4] 4A to 4C are circuit diagrams showing configuration examples of a storage unit included in an information processing device. [Figure 5] 5A to 5C are circuit diagrams showing configuration examples of a storage unit included in an information processing device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a storage unit included in the information processing device. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of a storage unit included in the information processing device. [Figure 8] 8A and 8B are timing charts showing an example of an operation method of a storage unit included in an information processing device. [Figure 9] FIG. 9 is a circuit diagram showing an example of the configuration of a storage unit included in the information processing device. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a storage unit included in the information processing device. [Figure 11] FIG. 11 is a schematic cross-sectional view illustrating an example of the configuration of an information processing device. [Figure 12] FIG. 12 is a schematic cross-sectional view illustrating a configuration example of a transistor. [Figure 13] FIG. 13 is a schematic cross-sectional view illustrating an example of the configuration of an information processing device. [Figure 14] FIG. 14A is a perspective view illustrating an example of the configuration of a computer, and FIG. 14B is a perspective view illustrating a monolithic IC. [Figure 15] FIG. 15 is a schematic diagram showing an example of the configuration of a monolithic IC. [Figure 16] 16A and 16B are diagrams illustrating the memory hierarchy of a computer, a monolithic IC, respectively. [Figure 17] 17A and 17B are block diagrams illustrating the configuration of an information processing device and its operation method. [Figure 18] FIG. 18A is a diagram illustrating the classification of IGZO crystal structures, FIG. 18B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 18C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 19] FIG. 19A is a perspective view showing an example of a semiconductor wafer, FIG. 19B is a perspective view showing an example of a chip, and FIGS. 19C and 19D are perspective views showing an example of an electronic component. [Figure 20]20A to 20J are perspective views or schematic diagrams illustrating an example of a product. [Figure 21] 21A to 21C are perspective views illustrating an example of a computer. [Figure 22] FIG. 22 is a diagram illustrating an example of a computer. [Figure 23] FIG. 23 is a diagram illustrating an example of a computer system. [Figure 24] 24A and 24B are diagrams illustrating an example of a computer system. [Figure 25] 25A to 25D are circuit diagrams showing an example of a memory cell, and FIG. 25E is a block diagram showing an example of a memory cell array and peripheral circuits. [Figure 26] FIG. 26 is a diagram illustrating an example of a computer system. DETAILED DESCRIPTION OF THE INVENTION

[0050] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), For example, metal oxides are used in the active layer of a transistor. In this case, the metal oxide is sometimes called an oxide semiconductor. a channel forming region of a transistor having at least one of a switching function and a switching function; can be composed of a metal oxide, the metal oxide is called a metal oxide semiconductor (metal oxide semiconductor). It can be called a silicon oxide semiconductor.

[0051] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0052] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0053] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0054] The contents described in the embodiments refer to the following in each embodiment (or example): The content described using various figures or the text in the specification be.

[0055] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0056] The embodiments described in this specification will be described with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0057] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0058] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0059] (Embodiment 1) In this embodiment, a data processing device according to one embodiment of the present invention having a function as a storage device will be described. We will explain about this.

[0060] <Configuration example> FIG. 1 is a block diagram showing an example of the configuration of an information processing device. A storage unit 1196, a controller 1197, a bus interface 1198, It has.

[0061] For example, the information processing device 50 receives a signal including command information from the outside. The memory unit 1196 has a function of writing data to the memory unit 1196 in response to the command. The storage unit 1196 has, for example, a memory cell, and the data is stored in the memory cell. The memory unit 1196 also stores a register for selecting the memory cell. It may have a transistor or the like.

[0062] Specifically, for example, the signal ISG including the command information input to the information processing device 50 is The data is input to the controller 1197 via a data interface 1198.

[0063] The controller 1197 has a function of decoding the signal ISG, for example. The controller 1197 performs various controls based on the commands contained in the decoded signals. Specifically, the controller 1197 has the function of Generates a re-cell address and reads data from the memory unit 1196 according to the state of the information processing device. When writing to the storage unit 1196, The data is input to the information processing device via the bus interface 1198. The data DT can be the data DT of the bus interface 1198. The data is transmitted to the controller 1197 via the

[0064] For this purpose, the controller 1197 includes, for example, a circuit for decoding the signal ISG, A circuit for generating addresses of memory cells included in the storage unit 1196, and the storage unit 1196 outputs a signal to switch the on and off states of the transistors included in The circuit may include:

[0065] The controller 1197 also has a function of generating a signal that controls the timing of the operation. For example, the controller 1197 may generate an internal clock based on the reference clock signal. An internal clock generating unit is provided to generate a signal, and the internal clock signal is supplied to the various circuits. It may also be configured as follows.

[0066] The controller 1197 also stores the string memory cells contained in the storage unit 1196. The controller 1197 may have a function to perform error checks on the message. For example, the controller 1197 can write data to the storage unit 1196. Before this is done, an error check is performed on the memory cells of the string included in the storage unit 1196. If a defective cell is found in the string to be written, The controller 1197 then redirects the data write destination from the defective cell to another cell, The controller 1197 can write data to the storage unit 119. 6, an error check is performed at regular intervals on the memory cells of the string. Therefore, when a defective cell is found in a string, the function of correcting the data may be provided.

[0067] In addition, the information processing device 50 may, for example, receive a signal including command information from the outside. The memory unit 1196 has a function of reading data from the memory unit 1196 in response to the command. The information processing device 50 also uses the controller 1197 to transmit the read data as a signal O As an SG, it has a function of outputting to the outside of the information processing device 50.

[0068] In the data processing device of one embodiment of the present invention, the storage unit 1196 may be, for example, a NAND In particular, a NAND type memory circuit can be used. As an example, a three-dimensional NAND-type memory circuit using OS transistors will be applied. It is preferable that the memory cell be a NAND type memory cell using an OS transistor. The strings are stacked layer by layer in a horizontal configuration, and the OS transistors are The NAND strings used are arranged vertically, and the strings are aligned by etching or the like. In this specification, a NAN using an OS transistor is The vertical structure of the D-type strings is called 3D OS NAND (registered trademark) type memory circuit. 3D OS NAND type memory circuits are capable of storing a large number of memory cells simultaneously. Therefore, the packaging density can be increased with fewer manufacturing steps. This reduces the cost per bit and enables memory circuits with high packaging density to be realized at low cost. For this reason, the storage unit 1196 has a plurality of NAND type strings. , the storage unit 1196 shows an example having strings ST1 to ST3. In addition, in the storage unit 1196 of FIG. 1, strings other than strings ST1 to ST3 are The details of the ping are omitted.

[0069] As an example, the string ST1 includes memory cells L[1] to L[n] (where n is 1). ) and string ST2 has memory cells M[1] to M[2]. string ST3 has memory cells N[1] to N[n]; In FIG. 1, in the string ST1, the memory cell L[1] and the memory cell L[ 2] and memory cell L[n] are selectively illustrated. In this example, memory cells M[1], M[2], and M[n] are selected. In the string ST3, the memory cell N[1] and the memory cell N[2] and memory cell N[n] are selectively illustrated.

[0070] In the string ST1, the memory cells L[1] to L[n] are arranged as follows: The string S is electrically connected in series between the line SL1 and the wiring BL1. At T2, the memory cells M[1] to M[n] are connected to the wirings SL2 and BL2. In the string ST3, the memory cells N[1] to N[2] are electrically connected in series between the The memory cell N[n] is electrically connected in series between the wiring SL3 and the wiring BL3. There are.

[0071] The wirings SL1 to SL3 correspond to the strings ST1 to ST3, respectively. The wirings BL1 to BL3 function as wirings that apply a predetermined potential. Each of them stores data in the memory cells included in the strings ST1 to ST3. It functions as wiring for writing data and / or wiring for reading data from memory cells. It works.

[0072] In addition, for strings not shown, strings ST1 to ST The connection configuration is the same as 3.

[0073] <Example of operation> Here, in the information processing device 50 of FIG. 1, An example of an operation method in which some memory cells are treated as cache memory will be described below.

[0074] FIG. 2 is a flowchart showing an example of a method of operation of the information processing device 50 of FIG. The operation method includes steps STP1 to STP8. The data movement in string ST1 and string ST2 is shown in Figure 3A. As shown in Figure 3C.

[0075] As an example of this operation method, memory cells L[1] to L[2] of string ST1 Assuming that data is stored in each memory cell L[n], ] data is rewritten. It is assumed that no data is stored in the storage ST3.

[0076] When the information processing device 50 of FIG. 1 starts operation, step STP1 is first performed. can be.

[0077] Step STP1 is to write data to the memory cell L[6], for example, Specifically, for example, the step of FIG. The information processing device 50 receives the rewrite data DT and a signal including an instruction to rewrite the data. The controller 1197 receives the signal ISG and writes it to the memory unit 1196. The data DT to be written is transmitted and stored in memory cell N[1].

[0078] After step STP1 is completed, step STP2 is performed. In the string ST1, the memory cells L[1] to L[2] other than the memory cell to be rewritten are The step of reading out the data stored in each of the memory cells L[n]. For example, the data stored in each of memory cells L[1] to L[5] is Assume that data is to be read (see Figure 3A).

[0079] Step STP3 is a step of reading the data from the memory cells L[1] to L[2] in step STP2. The data of each of the memory cells L[5] is transferred to the memory cells M[1] to M[5] of the string ST2. The step S1000 includes a step of sequentially writing data to the memory cell M[5] (see FIG. 3A). By the operations from TP2 to STP3, the memory cell L[1 ] to memory cell L[5] of string ST2. ] to memory cell M[5].

[0080] In the flowchart of FIG. 2, step STP3 is performed after step STP2. However, the method of operating the information processing device according to one embodiment of the present invention is not limited to this. For example, in step STP2, memory cells L[1] to L[2] of string ST1 are The data stored in each memory cell L[5] is read out sequentially. The data is written sequentially to memory cells M[1] to M[5] of string ST2. In other words, step STP2 and step STP3 may be regarded as the same step. You can stop it.

[0081] After step STP3 is completed, step STP4 is performed. Data stored in memory cells L[1] to L[5] of string ST1 The method further comprises the step of erasing the

[0082] When the memory unit 1196 is a NAND type memory circuit, the data erasure operation is performed on a string-by-string basis. Since the data is stored in the memory cells L[1] to L[5] of the string ST1, When trying to erase the data stored in memory cells L[1] to L[n], Since all data is erased, in steps STP2 and STP3 , memory cells L[1] to L[5] as well as memory cells L[7] to L[8] The data of the reseller L[n] must also be written to string ST2.

[0083] For this reason, the storage unit 1196 is configured as shown in FIGS. 4A to 4C, 6, and 7, which will be described later. It is preferable that the memory circuit is an OS NAND type memory circuit having a circuit configuration as described above. In some cases, the circuit configuration of the memory unit 1196 may be a transistor including silicon in the channel forming region. As a structure having a Si transistor (hereinafter referred to as a Si transistor), any of the structures shown in FIGS. 5A to 5C is used. As will be described in detail later, by using the storage device , erase data from memory cell L[1] of string ST1 to any memory cell. Therefore, in this operation example, in order to rewrite the data in the memory cell L[6], Only the data in the memory cells L[1] to L[6] of the string ST1 is erased. (See Figure 3B.)

[0084] Step STP5 reads the rewrite data from memory cell N[1] of string ST3. The method includes the step of reading the DT.

[0085] Step STP6 is a write operation for the memory cell N[1] read in step STP5. writing replacement data DT to memory cell L[6] of string ST1; (See Figure 3B).

[0086] Step STP7 is to check the memory cells M[1] to M[5] of the string ST2. The data is read from each of the steps. This corresponds to the data written in step STP3 (see FIG. 3C).

[0087] Step STP8 is a step of reading the data from the memory cells M[1] to M[2] in step STP5. The data of each of the memory cells M[5] is transferred to the memory cells L[1] to L[5] of the string ST1. The step S1000 includes a step of sequentially writing data to the memory cell L[5] (see FIG. 3C). By the operations from TP7 to STP8, the memory cell M[1 ] to memory cell M[5] of string ST2. ] to memory cell L[5].

[0088] In the flowchart of FIG. 2, step STP8 is performed after step STP7. However, the method of operating the information processing device according to one embodiment of the present invention is not limited to this. For example, in step STP7, the memory cells M[1] to M[2] of the string ST2 are The data stored in each memory cell M[5] is read out sequentially. The data is written sequentially to the memory cells L[1] to L[5] of the string ST1. In other words, step STP7 and step STP8 may be the same step. You can stop it.

[0089] As described above in steps STP1 to STP8, the string in the storage unit 1196 When writing data to a pointer, or when rewriting data stored in a string, In this case, memory cells of another string of the storage unit 1196 can be treated as cache memory. can be done.

[0090] In the information processing device 50 shown in FIG. 1, the substrate on which the circuit is formed is For example, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). The substrate may be, for example, an SOI substrate, a glass substrate, a quartz substrate, or a plastic substrate. Plate, sapphire glass substrate, metal substrate, stainless steel substrate, stainless steel Substrate with foil, tungsten substrate, substrate with tungsten foil, flexible substrate These include plates, laminated films, paper containing fibrous materials, and substrate films. Examples of the substrate include barium borosilicate glass, aluminoborosilicate glass, or silicon dioxide. Examples of flexible substrates, laminated films, and base films include glass. Examples of such materials include polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), polyethersulfone (PES), polytetrafluoroethylene There are plastics such as fluoroethylene (PTFE). acrylic and other synthetic resins. Polyvinyl fluoride, or polyvinyl chloride. Amide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, paper, etc. In particular, transistors are manufactured using semiconductor substrates, single crystal substrates, SOI substrates, etc. This results in less variation in characteristics, size, or shape, a high current capacity, and It is possible to manufacture transistors with small noise. By configuring the circuit as described above, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit.

[0091] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After completing a part or all of the information processing device, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be mounted on a substrate with poor heat resistance, a flexible substrate, or the like. The above-mentioned peeling layer may be formed by, for example, a tungsten film and a silicon oxide film. The laminated structure of inorganic films, or the structure in which an organic resin film such as polyimide is formed on a substrate, etc. You can be there.

[0092] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0093] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This reduces the cost by reducing the number of components, or reduces the number of connections to circuit components. This can improve reliability.

[0094] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function can be formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a given function can be Another part of the circuitry required to realize a specific function is formed on the single crystal substrate. It can be formed on a substrate (or SOI substrate) and realizes a predetermined function. The single crystal substrate (also called an IC chip) on which another part of the circuitry required for (Chip On Glass) connects to the glass substrate and Alternatively, the IC chip can be mounted on a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology) or a printed circuit board. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components, thereby reducing costs, and This reduces the number of circuits, which improves reliability. Also, circuits with high drive frequencies often consume a lot of power. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0095] Note that one embodiment of the present invention is not limited to the configuration of the information processing device 50 shown in FIG. In one aspect, the configuration of the information processing device 50 shown in FIG. 1 may be changed depending on the situation. For example, the string configuration of the storage unit 1196 included in the information processing device 50 shown in FIG. 1 is as follows: The string configuration may be changed to that described in the second embodiment.

[0096] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0097] (Embodiment 2) In this embodiment, a storage unit (NAND type) that can be applied to the storage unit 1196 of the first embodiment is A configuration example of the memory circuit will be described.

[0098] <Configuration example of memory unit (memory circuit)> An example of the storage unit will be described with reference to FIG. 4A. In FIG. 4A, n (n is 1 or more) 4A shows a circuit diagram of a memory cell having a number of bits (number of bits is an integer). That is, the circuit shown in FIG. Memory cells MC[1] to MC[n] and a memory cell for controlling them The wiring WWL[1] to wiring WWL[n], the wiring RWL[1] to wiring RWL[n], The line WBL functions as a write word line, and the line RBL functions as a write word line. The line RWL functions as a read word line, and the line WBL functions as a write bit line. The wiring RBL functions as a read bit line.

[0099] Each memory cell MC includes a transistor WTr, which is an OS transistor, and a transistor The transistor RTr shown in FIG. A transistor having a back gate. When a potential is applied to the back gate, The threshold voltage of the transistor RTr can be varied. The wirings BGL are the transistors of the memory cells MC[1] to MC[n]. The back gate of the transistor RTr is electrically connected to the back gate of the semiconductor device shown in FIG. The wiring BGL is connected to the transistors of the memory cells MC[1] to MC[n]. The back gates of the RTr are not electrically connected to each other, but are connected to the back gates of the RTr. Each port is electrically connected to the other port independently, and a different potential is applied to each port. This may also be configured as follows.

[0100] Since the transistor WTr is an OS transistor, the channel shape of the transistor WTr is The composite region can be, for example, a metal oxide as described in the sixth embodiment. element M (element M may be, for example, aluminum, gallium, yttrium, copper, , vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium Aluminum, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten In the case of a metal oxide containing one or more elements selected from the group consisting of zinc, The metal oxide functions as a wide-gap semiconductor, so the metal oxide is channeled. The transistor included in the hole formation region has a characteristic of having a very low off-state current.

[0101] The transistor WTr may be replaced with a transistor other than an OS transistor depending on the situation. For example, the transistor WTr may be a Si transistor.

[0102] Also, the transistor RTr may be a transistor other than an OS transistor depending on the situation. For example, the transistor RTr may be a Si transistor. Since the field-effect mobility of the Si transistor is large, the drain current of the Si transistor is increased. Therefore, by applying Si transistors to the memory section, It can speed up the action.

[0103] The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. It functions as a readout transistor. It switches the transistor WTr between on and off. The potential of one electrode of the capacitor CS is determined by the potential applied to the wiring WWL. The other electrode of the capacitor CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitor CS can be called a memory node. The memory node of each memory cell MC is the It is electrically connected to the first terminal.

[0104] The second terminal of the transistor WTr is connected to the transistor WT of the adjacent memory cell MC. Similarly, the first terminal of the transistor RTr is electrically connected in series with the first terminal of the transistor RTr. The transistor RTr is electrically connected in series with the second terminal of the transistor RTr of the adjacent memory cell. The second terminal of the transistor WTr in the memory cell MC[n] is connected to the wiring The second terminal of the transistor RTr in the memory cell MC[n] is electrically connected to the WBL. In this embodiment, the memory cell MC The connection point between the second terminal of the transistor RTr in [n] and the wiring RBL is called a node N1. The first terminal of the transistor RTr in the memory cell MC[1] is referred to as a node N2. In order to control the conduction state between the node N1 and the wiring RBL, the memory cell M A selection transistor may be connected in series with the transistor RTr of C[n]. In order to control the conduction state between the node N2 and the wiring connected to the node N2, A selection transistor may be connected in series with the transistor RTr of the rechargeable battery MC[1]. .

[0105] Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. The semiconductor device shown in FIG. 4A can be appropriately modified to have a circuit configuration. As shown in FIG. 4B, one embodiment of the present invention is a semiconductor device in which a back gate is also provided in the transistor WTr. The semiconductor device shown in FIG. 4B may be the same as the semiconductor device shown in FIG. In addition to the configuration of the semiconductor device, the transistors of the memory cells MC[1] to MC[n] A back gate is provided in the resistor WTr, and each of the back gates is connected to the wiring BGL and In addition, for example, one embodiment of the present invention has a configuration in which the , a semiconductor device in which a back gate is not provided in the transistor RTr and the transistor WTr, You may do so.

[0106] Alternatively, one embodiment of the present invention may be modified as shown in FIG. 5A by adding a transistor A semiconductor device in which WTr is an OS transistor and transistor RTr is a Si transistor Alternatively, as shown in FIG. 5B, in the configuration of FIG. 4A, the transistor WT A semiconductor device in which r is a Si transistor and transistor RTr is an OS transistor. Alternatively, as shown in FIG. 5C, in the configuration of FIG. 4A, the transistor WTr may be As a semiconductor device using a Si transistor as the transistor RTr, In this way, one embodiment of the present invention is to provide a semiconductor device that can be used for various purposes or applications. The transistor applied to the transistor WTr is an OS transistor or a Si transistor. Similarly, it is sufficient to select a transistor suitable for the transistor WTr included in the semiconductor device. The transistor to be used may be an OS transistor or a Si transistor.

[0107] By the way, if the storage capacity of the semiconductor device shown in FIGS. 4A to 4C and 5A to 5C is further increased, 4A to 4C, 5A to 5C, etc., can be used as a matrix. For example, the semiconductor devices shown in FIG. When they are arranged in this order, the circuit configuration becomes that shown in FIG.

[0108] The semiconductor device shown in FIG. 6 is arranged in m rows (m is 1 or more), with the semiconductor device shown in FIG. 4B being one row. The wiring RWL and the wiring WWL are arranged in the memory cells of the same row. In other words, the semiconductor shown in Figure 6 is electrically connected to the The device is a matrix-shaped semiconductor device with n rows and m columns, and memory cells MC[1,1] to MC[1,2] Therefore, the semiconductor device shown in FIG. ] to wiring RWL[n], wiring WWL[1] to wiring WWL[n], and wiring RBL[1 ] to wiring RBL[m], wiring WBL[1] to wiring WBL[m], and wiring BGL[1 ] to wiring BGL[m]. Rule MC[j,i] (j is an integer between 1 and n, and i is an integer between 1 and m). One electrode of the capacitor CS is electrically connected to the wiring RWL[j], and the memory cell MC[j , i] has a gate electrically connected to the wiring WWL[j]. The wiring WBL[i] is electrically connected to the second terminal of the transistor WTr of the memory cell MC[n,i]. The wiring RBL[i] is connected to the transistor RTr of the memory cell MC[n,i]. It is electrically connected to the second terminal.

[0109] 6 shows memory cells MC[1,1], MC[1,i], and M C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC [j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[ n,m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1] , Wiring WWL[j], Wiring WWL[n], Wiring RBL[1], Wiring RBL[i], Wiring R BL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1] ], wiring BGL[i], wiring BGL[m], capacitance CS, transistor WTr, transistor Only the node RTr, node N1, and node N2 are shown, and other wiring, elements, symbols, and and symbols are omitted.

[0110] In this specification, as an example, an electrical connection is established between the node N1 and the node N2 in the i-th column. The memory cells MC[1,i] to MC[n,i] connected to the i-th column are As an example, the jth row wiring RWL[j] and the jth row wiring W Memory cells MC[j,1] to MC[j] electrically connected to WL[j] , m] may be called the j-th page. For example, the page with n rows and m columns shown in Figure 6 The memory cells MC[1,1] to MC[n,m] arranged in a trix shape are grouped together. Sometimes referred to as a block.

[0111] Furthermore, the semiconductor device shown in FIG. 4C is arranged in m columns (m is an integer of 1 or more). The semiconductor device shown in FIG. 7 has all the memory cells MC Each transistor has a structure in which a back gate is not provided, and Therefore, the semiconductor device shown in FIG. 7 does not have the wiring BGL. For the arrangement, please refer to the description of the semiconductor device shown in FIG.

[0112] <<Example of operation method>> Next, an example of an operation method of the semiconductor device shown in FIGS. 4A to 4C and 5A to 5C will be described. The low level potential and high level potential used in the following description are specific potentials. This does not mean the potential, and the actual potential may be different depending on the wiring. For example, , the low level potential and the high level potential applied to the wiring WWL are respectively applied to the wiring RWL. The potential may be different from the low-level potential and high-level potential to be applied.

[0113] In this example of the operation method, the wiring BGL shown in FIGS. 4A and 4B is connected to a transistor. A voltage within the range in which the RTr and WTr transistors operate normally is applied in advance. Therefore, the operations of the semiconductor devices shown in FIGS. 4A to 4C are mutually exclusive. can be thought of in the same way.

[0114] FIG. 8A is a timing chart showing an example of an operation for writing data to a semiconductor device; FIG. 8B is a timing chart showing an example of an operation for reading data from a semiconductor device. The timing charts of FIGS. 8A and 8B are for the wiring WWL[1], the wiring WWL[2], [2], Wiring WWL[n], Wiring RWL[1], Wiring RWL[2], Wiring RWL[n], The potentials of the nodes N1 and N2 change. The data supplied to the wiring WBL is shown.

[0115] FIG. 8A shows data D[1] to data D[n] stored in memory cells MC[1] to MC[n]. This shows an example of writing to memory cell MC[n]. n] can be binary, multi-valued, analog, etc. For example, 4-bit, 8-bit, 16-bit, 32-bit, 64-bit, 128-bit , 256 bits, etc. Then, the data D[1] to data D[n] are , is supplied from the wiring WBL. That is, in the semiconductor device shown in FIGS. In the circuit configuration, data is written from memory cell MC[1] to memory cell MC[n For example, if you want to write at high speed, you can use binary data, If high-speed writing is not required, multi-level data may be used for writing.

[0116] For example, after writing data to memory cell MC[2], When you try to write data to memory cell MC[2], the data written to memory cell MC[3] is first written to memory cell MC[4]. If the data is not read and stored elsewhere, the data held in memory cell MC[2] will The data is lost when data is written to the memory cell MC[1].

[0117] In the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, the memory cell MC[i] (herein In this case, i is an integer between 2 and n. When writing data to memory cell MC[1], In order to prevent the data stored in the memory cell MC[i-1] from being rewritten, the wiring W A low-level potential is supplied to the wirings WL[1] to WWL[i-1], and the memory cell MC[1] Each transistor WTr included in the memory cell MC[i-1] is turned off. As a result, the data stored in the memory cells MC[1] to MC[i-1] are Each data can be protected.

[0118] When writing data to the memory cell MC[i], the data is supplied from the wiring WBL. Therefore, a high-level potential is supplied to the wirings WWL[i] to WWL[n] to The transistors WTr of the memory cells MC[i] to MC[n] are sufficiently This causes the data to be stored in the memory node of the memory cell MC[i]. It is possible.

[0119] When writing data to the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, the wiring R Since BL can be controlled independently of other wiring, it is not necessary to set it to a specific potential. That is, the potential of the node N1 can be set to a low level potential. In addition, the potential of the node N2 can also be set to a low level potential.

[0120] Based on the above, an example of operation shown in the timing chart of FIG. 8A will be described. At time T10, the wiring WWL[1] to wiring WWL[n], the wiring RWL[1] to wiring RWL[n], The potentials of RWL[n], the wiring WBL, the node N1, and the node N2 are low. It is an electric potential.

[0121] At time T11, a high-level potential is applied to the wirings WWL[1] to WWL[n]. As a result, during the period from time T11 to time T12, the memory cell MC Each of the transistors WTr of the memory cells MC[1] to MC[n] is in a sufficient ON state. Then, data D[1] is supplied to the wiring WBL. The transistors WTr of the memory cells MC[n] to MC[n] are fully turned on. Therefore, the data D[1] reaches the memory node of the memory cell MC[1]. It is written as follows.

[0122] At time T12, application of a low-level potential to the wire WWL[1] is started, and the wire WWL A high-level potential continues to be applied to the wirings WWL[2] to WWL[n]. Between time T12 and time T13, the transistor of the memory cell MC[1] The transistor WTr is turned off, and the The respective transistors WTr are fully turned on. The data D[2] is supplied to the memory cells MC[2] to MC[n]. Since each transistor WTr is fully on, data D[2] is The data reaches the memory node of memory cell MC[2] and is written. Since the transistor WTr of [1] is in the off state, the data is stored in the memory cell MC[1]. The data D[1] stored in the EEPROM is written by the write operation from time T12 to time T13. and will not be lost.

[0123] Between time T13 and time T14, the memory between time T11 and time T12 The write operation of data D[1] to cell MC[1] and the write operation from time T12 to time T13 Similarly to the write operation of data D[2] to memory cell MC[2] between Data D[3] to D[n-1] are sequentially stored in the memory cells MC[3] to MC[n-1]. Specifically, the data D[n-1] is written to the memory cell where the data has already been written. memory cells MC[1] to MC[j-1] (where j is an integer between 3 and n-1). The transistor WTr in the memory cell 100 is turned off, and the memory cell 100 is turned off. The transistors WTr of the cells MC[j] to MC[n] are fully turned on. The data D[j] is supplied from the wiring WBL to the memory node of the memory cell MC[j]. Then, writing of data D[j] to memory cell MC[j] is completed. In this case, the transistor WTr included in the memory cell MC[j] is turned off, and the wiring W Data D[j+1] is supplied from BL and written to the memory node of memory cell MC[j+1]. In particular, when j is n-1, the write operation is performed as follows: This refers to the operation from time T14 to time T15.

[0124] At time T14, a low-level potential is applied to the wiring WWL[1] to the wiring WWL[n-1]. A high level potential is applied to the wiring WWL[n]. Between time T14 and time T15, memory cells MC[1] to M The transistor WTr of the memory cell MC[n-1] is turned off, and the memory cell MC[n] is enabled. The transistor WTr is fully turned on. The transistor WTr of the memory cell MC[n] is in a fully on state. Therefore, the data D[n] reaches the memory node of the memory cell MC[n]. Also, the transactions of the memory cells MC[1] to MC[n-1] are written. Since the transistor WTr is in the off state, the memory cells MC[1] to MC[ At this time, the data D[1] to data D[n-1] stored in each of the No data is lost due to the write operation between time T14 and time T15.

[0125] By the above-mentioned operation, in any one of the semiconductor devices shown in FIGS. 4A to 4C, Data can be written to the memory cells MC of the semiconductor device.

[0126] FIG. 8B shows data D[1] to data D[n] stored in memory cells MC[1] to MC[n]. An example of a timing chart for reading from memory cell MC[n] is shown. In order to maintain the data stored in each memory cell MC, the transistor WTr Therefore, the memory cells MC[1] to MC[ During the operation of reading data from the wiring WWL[1] to the wiring WWL[n], The potential is a low level.

[0127] In the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, the data of a specific memory cell MC When reading data, the transistor RTr of another memory cell MC is turned on sufficiently. Then, the transistor RTr of the specific memory cell MC is operated in the saturation region. That is, the source-drain of the transistor RTr of the specific memory cell MC is The current flowing between the source and drain is determined by the source-drain voltage and the voltage held in the specific memory cell MC. The decision is based on the data available.

[0128] For example, the data stored in the memory cell MC[k] (where k is an integer between 1 and n) In this case, the data stored in the memory cell MC[k] is read out. The transistors RTr of the memory cells MC[1] to MC[n] are sufficiently In order to achieve a sufficient on-state, the wiring RWL[1] to the wiring RWL[k] are n] is supplied with a high level potential.

[0129] On the other hand, the transistor RTr of the memory cell MC[k] is In order to turn on the memory cell MC[k] in response to the It is necessary to set the potential to the same as the wiring RWL[k] when writing. The potential of the wiring RWL[k] during the write and read operations is considered as a low-level potential. can.

[0130] For example, a potential of +3V is applied to the node N1 and a potential of 0V is applied to the node N2. The potential of the node N2 is measured after floating. When the potentials of the wirings RWL[1] to RWL[n] are set to a high level, The transistors of the memory cells MC[1] to MC[n] except for the memory cell MC[k] are On the other hand, the transistor RTr of the memory cell MC[k] The voltage between the first and second terminals of the RTr is the voltage of the gate of the transistor RTr. The potential of the node N2 is determined by the potential of the memory node N1 of the memory cell MC[k]. It depends on the data held in the card.

[0131] In this way, the data stored in the memory cell MC[k] can be read. do.

[0132] Based on the above, an example of operation shown in the timing chart of FIG. 8B will be described. At time T20, the wiring WWL[1] to wiring WWL[n], the wiring RWL[1] to wiring RWL[n], The potentials of RWL[n], the wiring WBL, the node N1, and the node N2 are low. In particular, node N2 is in a floating state. The memory nodes of the memory cells MC[1] to MC[n] are respectively connected to the data D[ It is assumed that data D[1] to D[n] are held.

[0133] Between time T21 and time T22, a low-level potential is applied to the wiring RWL[1]. is started, and the application of a high-level potential to the wirings RWL[2] to RWL[n] is started. As a result, between time T21 and time T22, memory cells MC[2] to Each transistor RTr in the memory cell MC[n] is fully turned on. The transistor RTr of the memory cell MC[1] is The node is turned on according to the data D[1] held in the node. Place V R As a result, the potential of node N1 becomes V R The potential of the node N2 is The potential V of node N1 R and the data stored in the memory node of memory cell MC[1]. Here, the potential of node N2 is determined by V D[1] Then, the node N2 Potential V D[1] By measuring The stored data D[1] can be read out.

[0134] Between time T22 and time T23, the wirings RWL[1] to RWL[n] A low level potential is applied to the node N1. After that, the node N2 is in a floating state. Between the potentials of the wirings RWL[1] to RWL[n] and the node N2, The situation is the same as that between time T20 and time T21. Next, the potential V R Alternatively, a low level potential may be supplied. After time T21, the wiring RBL is at a potential V R will continue to be supplied.

[0135] Between time T23 and time T24, a low-level potential is applied to the wiring RWL[2]. A high-level potential is applied to the wiring RWL[1], the wiring RWL[3], and the wiring RWL[n]. As a result, during the period from time T23 to time T24, the memory cell M C[1], and the transistors of the memory cells MC[3] to MC[n]. The transistor RTr of the memory cell MC[2] is fully turned on. r is an offset corresponding to the data D[2] stored in the memory node of the memory cell MC[2]. In addition, the wiring RBL is in a potential V R continues to be supplied. The potential of node N2 is V R and stored in the memory node of memory cell MC[2]. Here, the potential of node N2 is determined by V D[2] Let's say. Then, the potential V of the node N2 D[2] By measuring The data D[2] stored in the memory node can be read.

[0136] Between time T24 and time T25, the memory between time T20 and time T22 Read operation of data D[1] from cell MC[1] and from time T22 to time T24 The read operation of data D[2] from memory cell MC[2] during The data D[ Specifically, data D[n-1] to D[n-3] are read from memory cell MC[j] (here, In this case, j is an integer between 3 and n-1. When reading data D[j] from After the potential of N2 is set to a low level potential and the node N2 is set to a floating state, A high-level potential is supplied to the wirings RWL[1] to RWL[n] except for the line RWL[j]. The memory cells MC[1] to MC[n], excluding the memory cell MC[j], are available. The transistor RTr corresponding to the memory cell MC[j] is fully turned on, and the transistor RTr of the memory cell MC[j] is turned on. Next, the potential of the node N1 is set to V R to By doing so, the potential of the node N2 becomes a potential according to the data D[j], and this potential is measured. By doing so, the data D[j] can be read. After the readout of the stored data D[j] is completed, the array is read out in preparation for the next readout operation. The application of a low-level potential to the lines RWL[1] to RWL[n] is started, and the potential of the node N2 is The node N1 is set to a low level potential, and then the node N2 is set to a floating state. When it is -1, this preparation refers to the operation between time T25 and time T26.

[0137] Between time T25 and time T26, the wiring RWL[1] to the wiring RWL[n] A low level potential is applied to the node N1. After the potential of the node N2 becomes a low level potential, the node N2 becomes a floating state. That is, between time T25 and time T26, the wiring RWL[1] to the wiring RW The potentials of the node N2 and L[n] are the same as those between time T20 and time T21. The wiring RBL continues to be connected to the potential V R or low level In this operation example, at time T21, a potential V R Application of After time T22, the potential V R is continuously applied. do.

[0138] At time T26, a low-level potential is applied to the wiring RWL[n], and the wiring RWL[1] A high-level potential is supplied to the wiring RWL[n-1]. From time T27 to time T28, the memory cells MC[1] to MC[n-1] The transistors RTr are fully turned on. The transistor RTr of [n] is held at the memory node of the memory cell MC[n]. The line RBL is turned on in accordance with the data D[n]. R continues to be supplied As a result, the potential of the node N2 is equal to the potential V of the node N1. R and memory cell MC In this case, the voltage of node N2 is determined by the data stored in the memory node [n]. V D[n] Then, the potential V of the node N2 D[n] By measuring The data D[n] stored in the memory node of the memory cell MC[n] can be read. Cut.

[0139] By the above operation, each memory cell MC of the semiconductor device shown in FIGS. 4A to 4C You can read data from

[0140] Note that the operation of the information processing device of one embodiment of the present invention is not limited to the above-described operation example. The operation of the information processing device according to one embodiment of the present invention may be performed by appropriately performing the above-described operation examples depending on the situation. For example, in the read operation described above, the node N1 is supplied with a potential V R supply By this, the data held in the memory node of the MC of the desired memory cell is transmitted from the node N2. The resulting potential V D Read out.

[0141] Next, when the NAND type memory circuit shown in FIG. 6 or FIG. 7 is applied to the memory unit 1196 in FIG. In order to do this, an example of a method of treating it as a cache memory will be described.

[0142] FIG. 9 shows blocks BLK_1 to BLK_k (k is an integer equal to or greater than 1). 1 is a configuration example of a storage unit having the following blocks: For example, the memory cell MC[1,1] in a matrix of n rows and m columns shown in FIG. 6 or FIG. 9. The blocks BLK_1 to BLK_m shown in FIG. In the block BLK_k, only the memory cells MC of interest in a certain column are shown. Therefore, in FIG. 9, the addresses of the rows of the matrix-shaped memory cells MC included in the block BLK are The address of the block is written as “[ ]” and the address of the block BLK is written as “_ ”. The column addresses for the codes are omitted. Also, the memory unit shown in FIG. 6 is configured as the memory unit shown in FIG. When applying this, the back gates of each transistor shown in Fig. 9 are omitted. do.

[0143] The memory unit shown in FIG. 9 differs from the memory unit shown in FIG. 6 or FIG. 7 in that the transistor BTr _1 to transistor BTr_k, and transistors STr_1 to STr_ k and is configured.

[0144] Specifically, in the storage unit of FIG. 9, the wiring RBL_1 is the first The first terminal of the transistor STr_1 is electrically connected to the first terminal of the transistor STr_2. The second terminal of the transistor STr_1 is connected to the wiring WBL_1 and the first terminal of the switch SW_1. , and the wiring RBL_h (h is an integer between 1 and k) is The first terminal of the transistor BTr_h and the first terminal of the transistor STr_h are electrically connected to each other. The second terminal of the transistor STr_h is connected to the wiring WBL_h. The wiring RBL_k is electrically connected to the first terminal of the transistor SW_h. a first terminal of the transistor BTr_k and a first terminal of the transistor STr_k; The second terminal of the transistor STr_k is connected to the wiring WBL_k and the switch S and the first terminal of W_k.

[0145] The second terminals of the switches SW_1 to SW_k are electrically connected to the line LN1. Also, the third terminals of the switches SW_1 to SW_k are connected to is electrically connected to the wiring LN2.

[0146] Each of the switches SW_1 to SW_k has a first terminal and a second terminal or a third terminal. In other words, the switches SW_1 to SW_2 have the function of establishing a conductive state between the switches SW_1 to SW_2 and either of the switches SW_3 to SW_4. Each of the switches SW_k is connected to each of the blocks BLK_1 to BLK_k. It is possible to select whether the line LN1 or the line LN2 is to be brought into a conductive state.

[0147] The wiring LN1 is, for example, a wiring for each of the blocks BLK_1 to BLK_k. It functions as a wiring that transmits write data to the memory cells of the ring. , the wiring LN2 is, for example, a wiring for each of the blocks BLK_1 to BLK_k. It functions as a wiring for transmitting data read from the memory cells of the ring. The data processing device according to the embodiment is not limited to this configuration. Instead of two lines, they may be combined into one line (in this case, the switches SW_1 to SW_ k may not be provided), or may be three or more (in this case, the switches SW_1 to SW_k (Each switch SW_k can be replaced with a selector circuit according to the number of wires.) .

[0148] Each of the transistors BTr_1 to BTr_k is connected to the wiring RBL_1 through The transistor functions as a transistor for adjusting the potential of each node N1 of the wiring RBL_k. Therefore, the first transistors BTr_1 to BTr_k A predetermined potential is input to the two terminals and the gate. , memory cell MC[1]_h of block BLK_h (h is an integer between 1 and k) When the potential is read from any one of the memory cells MC[n]_h to MC[n]_h, the transistor B Tr[i] changes the potential of the node N1 of the wiring RBL_h to a potential for writing. Therefore, the transistors BTr_1 to BTr_k have the sensor function. It may be replaced with an amplifier circuit such as a boost amplifier.

[0149] Each of the transistors STr_1 to STr_k is a switching element. Therefore, the transistors STr_1 to STr_k function as The gates of the transistors STr_1 to STr_k are connected to the respective on-states of the transistors STr_1 to STr_k. It is electrically connected to the wiring that sends the signal to switch it to the on or off state. There are.

[0150] Next, when a part of the storage unit in FIG. 9 functions as a cache memory, the operation of the storage unit will be described. The operation method will be described below. The operation method will be described with reference to the storage unit shown in FIG. It will be used.

[0151] The storage unit in FIG. 10 is a simplified representation of the storage unit in FIG. 9. Specifically, The storage unit has a configuration in which m is set to 3 and k is set to 3 in the storage unit of FIG.

[0152] The storage unit in FIG. 10 has blocks BLK_1 to BLK_3, and the block BL Each of blocks K_1 to BLK_3 has one or more strings. The block BLK_1 is made up of memory cells MC[1]_1 to MC[2]_3 as a string. The block BLK_2 has a memory cell MC[3]_1 as one string. The block BLK_3 has one memory cell MC[1]_2 to one memory cell MC[3]_2. The string includes memory cells MC[1]_3 to MC[3]_3.

[0153] The memory cells MC[1]_2 to MC[2]_3 included in the string of the block BLK_2 are It is assumed that data is held in each memory node of cell MC[3]_2. Specifically, for example, each of the memory cells MC[1]_2 to MC[3]_2 The potentials held in these memory nodes are V[1]_2, V[2]_2, and V[3]_2. It is assumed that

[0154] Also, memory cells MC[1]_1 to MC[1]_2 included in the string of block BLK_1 Memory cell MC[3]_1, a memory cell included in a string of block BLK_3 Data is stored in each memory node of memory cells MC[1]_3 to MC[3]_3. It is assumed that the information is not held.

[0155] Here, V[1]_2 stored in the memory node of memory cell MC[1]_2 is written. Consider the case where you replace

[0156] When the potential of the memory node of the memory cell MC[1]_2 is rewritten, the wiring WBL_2 Therefore, the transistors of the memory cell MC[2]_2 and the memory cell MC[3]_2 To send rewrite data to memory cell MC[1]_2 via WTr, The memory nodes of the memory cell MC[2]_2 and the memory cell MC[3]_2 are It is necessary to temporarily save the held V[2]_2 and V[3]_2.

[0157] First, the potential V REW For example, the block BLK_1 The data is written to the memory node of the memory cell MC[3]_1 included in the string. puts the first and second terminals of the switch SW_1 into a conductive state, and connects the wire WWL[3]_ A high-level potential is input to 1 to turn on the transistor WTr of the memory cell MC[3]_1. and connect the wire LN1 to V REW At this time, the wiring WWL of block BLK_2 is [3]_2 and block BLK_3 wiring WWL[3]_3 are input with a low level potential. , the transistors of the memory cell MC[3]_2, and the memory cell MC[3]_3 With WTr in the off state, wire WBL_1 to block BLK_2 and block BLK_ V to each memory cell MC of 3 REW You need to prevent writing to In each of the switches SW_2 and SW_3, a conduction current is introduced between the first and third terminals. In other words, the first terminal and the second terminal are brought into a non-conductive state.

[0158] At this time, the memory cell MC[3]_1 can be regarded as a cache memory. Cut.

[0159] Next, the data stored in the memory node of the memory cell MC[3]_2 in the block BLK_2 is In this operation example, the memory cell MC[3]_2 is temporarily saved. V[3]_2 of the memory node is set to memory cell MC[2]_3 of block BLK_3. Specifically, the status of switches SW_2 and SW_3 will be saved in the The first terminal and the second terminal of each are brought into a conductive state, and the wiring RWL[1]_2 and the wiring RW L[2]_2, a high level potential is input to the memory cell MC[1]_2 and the memory cell M C[2]_2, each transistor RTr is fully turned on. The potentials of the memory nodes of the memory cells MC[1]_2 and MC[2]_2 are increased. Also, a high-level potential is input to the gate of the transistor STr_2 to turn on the transistor STr_2 is turned on. Also, a low level potential is applied to the gate of transistor STr_3. Input to turn off transistor STr_3 and connect wire WWL[2 ]_3 and the wiring WWL[3]_3, a high level potential is input to the memory cell MC[2]_ The transistors WTr of memory cell MC[3]_3 and memory cell MC[3]_3 are turned on.

[0160] Here, V is applied to node N2 of block BLK_2. R Block B The potential of the node N1 of the block BLK_2 is set to the potential of the memory cell MC[3]_2 of the block BLK_2. The potential can be set according to V[3]_2 held in the transistor. The potential of the node N1 can be changed to V[3]_2 by the transistor BTr_2.

[0161] At this time, the node N1 of the block BLK_2 and the memory cell N2 of the block BLK_3 are Since the memory node of block MC[2]_3 is in a conductive state, The potential of the memory node of the memory cell MC[2]_3 becomes V[3]_2. A low-level potential is input to WL[2]_3, and the transistor W By turning off Tr, V[3 ]_2 potential can be maintained.

[0162] Next, the data stored in the memory node of the memory cell MC[2]_2 in the block BLK_2 is In this operation example, the memory cell MC[2]_2 is temporarily saved. V[2]_2 of the memory node is set to memory cell MC[3]_3 of block BLK_3. Specifically, the status of switches SW_2 and SW_3 will be saved in the The first terminal and the second terminal of each are brought into a conductive state, and the wiring RWL[1]_2 and the wiring RW L[3]_2, a high level potential is input to the memory cell MC[1]_2 and the memory cell M The memory cell C[3]_2 is configured so that each transistor RTr of the memory cell C[3]_2 is fully turned on. The potentials of the memory nodes of the memory cells MC[1]_2 and MC[3]_2 are increased. Also, a high-level potential is input to the gate of the transistor STr_2 to turn on the transistor STr_2 is turned on. Also, a low level potential is applied to the gate of transistor STr_3. Input to turn off transistor STr_3 and connect wire WWL[3 ]_3, a high-level potential is input to each transistor of memory cell MC[3]_3. Turn on the WTr.

[0163] Here, V is applied to node N2 of block BLK_2. R Block B The potential of the node N1 of the block BLK_2 is set to the potential of the memory cell MC[2]_2 of the block BLK_2. The potential can be set to correspond to V[2]_2 held in the transistor. The potential of the node N1 can be changed to V[2]_2 by the transistor BTr_2.

[0164] At this time, the node N1 of the block BLK_2 and the memory cell N2 of the block BLK_3 are Since the memory node of block MC[3]_3 is in a conductive state, The potential of the memory node of the memory cell MC[3]_3 becomes V[2]_2. A low-level potential is input to WL[3]_3, and the transistor W By turning off Tr, V[2 ]_2 potential can be maintained.

[0165] Next, memory cells MC[1]_2 to MC[3]_2 of block BLK_2 The data stored in each memory node is erased.

[0166] Specifically, first, the first terminal and the second terminal of the switch SW_2 are brought into a conductive state, A low-level potential is applied to the gates of the transistors STr_1 to STr_3. is input, and each of the transistors STr_1 to STr_3 is turned off. In addition, the wiring WWL[3]_1 of the block BLK_1 and the wiring WWL[3]_2 of the block BLK_3 are A low-level potential is input to the wiring WWL[3]_3, and the memory cell MC [3]_1, and the transistors of the memory cell MC[3]_3 of the block BLK_3. Switch SW_1 and switch SW_3 are turned off. Conduction state between the first terminal and the third terminal, that is, non-conduction state between the first terminal and the second terminal It can also be set to

[0167] Then, the wiring WWL[1]_2 to the wiring WWL[3]_2 of the block BLK_2 are A high-level potential is input to each of the memory cells MC[1]_2 to MC[2]_3 of the block BLK_2. The transistors WTr of the memory cell MC[3]_2 are turned on. , the wiring LN1 to the memory cells MC[1]_2 to MC[3]_2, respectively. A potential for data initialization (e.g., low level potential, ground potential, etc.) is applied to the memory node. By doing so, each of the memory cells MC[1]_2 to MC[3]_2 The potential held in the memory node of the block BL is rewritten to the potential for initialization. A low-level potential is input to each of the wirings WWL[1]_2 to WWL[3]_2 of K_2. Thus, memory cells MC[1]_2 to MC[3]_2 of block BLK_2 By turning off the transistors WTr of the block BLK_2, The data in each of the memory cells MC[1]_2 to MC[3]_2 has been completely erased. At the timing of writing data, which will be described below, the memory cell MC[1] By turning on the transistors WTr of the memory cells MC[3]_2 to MC[4]_2, the data Since the data is rewritten, the erase operation described above does not need to be performed.

[0168] Next, the data stored in the memory node of the memory cell MC[3]_1 in the block BLK_1 is RuV REW is written to memory cell MC[2]_2 of block BLK_2. The first terminal and the second terminal of each of the switches SW_1 and SW_2 are electrically connected. A high-level potential is input to the wiring RWL[1]_1 and the wiring RWL[2]_1. The transistors R of the memory cell MC[1]_1 and the memory cell MC[2]_1 Tr is in a sufficient ON state, the memory cell MC[1]_1 and the memory cell MC[ 2]_1. A high-level potential is input to the gate to turn on the transistor STr_1. A low level potential is input to the gate of the transistor STr_2 to turn it off. In this state, high-level wiring WWL[1]_3 to wiring WWL[3]_3 of block BLK_2 are A potential is input to each of the memory cells MC[1]_3 to MC[3]_3. The transistor WTr is turned on.

[0169] At this time, a low-level potential is input to the wiring WWL[3]_3 of the block BLK_3. The transistor WTr of the rechargeable cell MC[3]_3 is turned off, and the transistor STr_3 A low-level potential is input to the gate to turn off transistor STr_3, and block B V from LK_1 to memory cell MC[3]_3 of block BLK_3 REW Write Or, the first and third terminals of the switch SW_3 must be in a conductive state. In this way, the first terminal and the second terminal may be brought into a non-conductive state.

[0170] Here, V is applied to node N2 of block BLK_1. R Block B The potential of the node N1 of the block BLK_1 is set to the potential of the memory cell MC[3]_1 of the block BLK_1. V held in the linode REW The potential of the transistor B can be set to a value according to the Tr_2 sets the potential of node N1 to V REW can be varied to

[0171] At this time, the node N1 of the block BLK_1 and the memory cell N2 of the block BLK_2 are Since the memory node of block MC[1]_2 is in a conductive state, The potential of the memory node of memory cell MC[1]_2 is V REW Then, the wiring WWL A low-level potential is input to [1]_2, and the transistor WTr of the memory cell MC[1]_2 By turning off the REW of The potential can be maintained.

[0172] Next, the data stored in the memory node of the memory cell MC[3]_3 in the block BLK_3 is V[2]_2 is written back to memory cell MC[2]_2 of block BLK_2. In this case, a voltage is applied between the first terminal and the second terminal of each of the switches SW_2 and SW_3. Put it in a conductive state and input a high-level potential to the wiring RWL[1]_3 and wiring RWL[2]_3. Then, the transistors of the memory cell MC[1]_3 and the memory cell MC[2]_3 The memory cell MC[1]_3 and the memory cell The potential of each memory node of the transistor STr A high level potential is input to the gate of transistor STr_3 to turn it on. , a low level potential is input to the gate of the transistor STr_2, and the transistor STr_2 is turned on. Turn it off, and wire WWL[2]_2 and wire WWL[3]_2 of block BLK_2 A high level potential is input to the memory cells MC[2]_2 and MC[3]_2. Each of the transistors WTr is turned on.

[0173] At this time, a low-level voltage is input to the wiring WWL[3]_1 of the block BLK_1, and the memory The transistor WTr of the rechargeable cell MC[3]_1 is turned off, and the transistor STr_1 A low-level potential is input to the gate to turn off the transistor STr_1, and block B Write V[2]_2 from LK_3 to memory cell MC[3]_1 of block BLK_1 Or, the first and third terminals of the switch SW_1 are in a conductive state. In other words, the first terminal and the second terminal may be brought into a non-conductive state.

[0174] Here, V is applied to node N2 of block BLK_3. R Block B The potential of the node N1 of the block BLK_3 is set to the potential of the memory cell MC[3]_3 of the block BLK_3. The potential can be set to correspond to V[2]_2 held in the transistor. The potential of the node N1 can be changed to V[2]_2 by the transistor BTr_3.

[0175] At this time, the node N1 of the block BLK_3 and the memory cell N2 of the block BLK_2 are Since the memory node of block MC[2]_2 is in a conductive state, The potential of the memory node of the memory cell MC[2]_2 becomes V[2]_2. A low-level potential is input to WL[2]_2, and the transistor W By turning off Tr, V[ 2]_2 potential write-back is completed.

[0176] Next, the data stored in the memory node of the memory cell MC[2]_3 in the block BLK_3 is V[3]_2 is written back to memory cell MC[3]_2 of block BLK_2. In this case, a voltage is applied between the first terminal and the second terminal of each of the switches SW_2 and SW_3. Put it in a conductive state and input a high-level potential to the wiring RWL[1]_3 and wiring RWL[3]_3. Then, the transistors of the memory cell MC[1]_3 and the memory cell MC[3]_3 are The memory cell MC[1]_3 and the memory cell The potential of each memory node of the transistor STr A high level potential is input to the gate of transistor STr_3 to turn it on. , a low level potential is input to the gate of the transistor STr_2, and the transistor STr_2 is turned on. In the OFF state, a high-level voltage is input to the wire WWL[3]_2 of the block BLK_2. Each transistor WTr of the memory cell MC[3]_2 is turned on.

[0177] At this time, a low-level voltage is input to the wiring WWL[3]_1 of the block BLK_1, and the memory The transistor WTr of the rechargeable cell MC[3]_1 is turned off, and the transistor STr_1 A low-level potential is input to the gate to turn off the transistor STr_1, and block B Write V[3]_2 from LK_3 to memory cell MC[3]_1 of block BLK_1 Or, the first and third terminals of the switch SW_1 are in a conductive state. In other words, the first terminal and the second terminal may be brought into a non-conductive state.

[0178] Here, V is applied to node N2 of block BLK_3. R Block B The potential of the node N1 of the block BLK_3 is set to the potential of the memory cell MC[2]_3 of the block BLK_3. The potential can be set according to V[3]_2 held in the transistor. The potential of the node N1 can be changed to V[3]_2 by the transistor BTr_3.

[0179] At this time, the node N1 of the block BLK_3 and the memory cell N2 of the block BLK_2 are Since the memory node of block MC[3]_2 is in a conductive state, The potential of the memory node of the memory cell MC[3]_2 becomes V[3]_2. A low level potential is input to WL[3]_2, and the transistor W By turning off Tr, V[ 3]_2 potential write-back is completed.

[0180] By performing the above-described operation, the storage unit shown in FIG. 9 or FIG. 10 stores the data in the storage unit. When writing data to the memory unit, or when rewriting data stored in the memory unit, A part of the storage unit can be used as a cache memory.

[0181] By the way, software errors caused by the environment of information processing equipment (temperature, humidity, etc.) and natural radiation 9 or 10. Transistor WTr, transistor RTr, transistor BTr, transistor At least one transistor characteristic of the STr is degraded (for example, the transistor in the off state In this case, the data processing device shown in FIG. The controller 1197 of the 50 controls the execution of an error to a string (memory cell) included in the storage unit. By having the function of performing a byte check, the string in the memory section shown in FIG. 9 or FIG. 10 can be The controller 1197 can perform an error check on the When an error is found in a checked memory cell, the stream containing that memory cell is The function may be to stop accessing one string and access another string.

[0182] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0183] (Embodiment 3) In this embodiment, the configuration example of the information processing device described in the first embodiment and the information processing An example of the structure of a transistor applicable to the device will be described.

[0184] <Configuration example 1 of information processing device> The information processing device shown in Fig. 11 includes a storage unit 100 and a control unit 200. 12 is a cross-sectional view of the transistor 300 in the channel length direction. FIG. 2 is a cross-sectional view in the channel width direction.

[0185] In FIG. 11, the control unit 200 corresponds to a circuit including the controller 1197 in FIG. In this case, the storage unit 100 corresponds to the storage unit 1196 in FIG.

[0186] First, the transistor 300 included in the control unit 200 and the transistors formed around it This section explains the insulators, conductors, etc. that are used.

[0187] The transistor 300 is, for example, provided on a substrate 311, and includes a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, The transistor has a low resistance region 314a and a low resistance region 314b. 300 can be applied to, for example, a transistor included in the controller 1197. This can be done.

[0188] The substrate 311 is a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). It is preferable that

[0189] As shown in FIG. 12, the transistor 300 has an upper surface of a semiconductor region 313 and a channel width The side surface of the transistor is covered with a conductor 316 via an insulator 315. By making the transistor 300 a fin type, the effective channel width is increased, The on-state characteristics of the transistor 300 can be improved. Since the temperature can be increased, the off-state characteristics of the transistor 300 can be improved.

[0190] The transistor 300 may be either a p-channel type or an n-channel type. .

[0191] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Nitride), GaAlAs (Gallium Aluminum Arsenide), GaN (Gallium Nitride), etc. The effective mass can be increased by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, a structure using silicon with controlled conductivity may be used. This allows the transistor 300 to be a HEMT (High Electron Mobilit y Transistor).

[0192] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0193] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0194] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0195] The transistor 300 shown in FIGS. 11 and 12 is an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the circuit configuration, driving method, etc. The control unit 200 of the processing device may be a unipolar circuit including only OS transistors.

[0196] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0197] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0198] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0199] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0200] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A memory unit 100 including a transistor 700, a plurality of transistors 800, and a transistor 900 is It is preferable to use a film having a barrier property that prevents the diffusion of impurities such as the above.

[0201] An example of a film that has barrier properties against hydrogen is silicon nitride formed by CVD. Here, a transistor 700, a plurality of transistors 800, and a transistor When transistor 900 is an OS transistor, transistor 700, multiple transistors Hydrogen diffuses into the semiconductor element including the oxide semiconductor of the transistor 800 and the transistor 900. Therefore, the characteristics of the semiconductor element may be deteriorated. 00, a plurality of transistors 800, a transistor 900, and a transistor 300 It is preferable to use a film that suppresses hydrogen diffusion between the electrodes. Specifically, the film is one that releases a small amount of hydrogen.

[0202] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0203] It is preferable that the insulator 326 has a lower relative dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the body 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. can be reduced.

[0204] In addition, the insulators 320, 322, 324, and 326 may include, for example, The conductors 328 and 330 are embedded in the insulating film 324. The conductor 330 functions as a plug or wiring. In the case of a conductor having a function, multiple structures may be collectively assigned the same symbol. In this specification, the wiring and the plug connected to the wiring may be an integrated unit. That is, when a part of the conductor functions as a wiring, and when a part of the conductor functions as a plug, There are cases like this.

[0205] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring board from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0206] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0207] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. A transistor 300, a transistor 700, a plurality of transistors 800, and a transistor The memory section 100 including the transistor 900 can be separated by a barrier layer. Diffusion of hydrogen from 00 to the memory section 100 can be suppressed.

[0208] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0209] An insulator having a barrier property against hydrogen is used on the insulator 354 and the conductor 356. For example, in FIG. 11, an insulating layer is formed on the insulator 354 and the conductor 356. An opening is provided in the insulator 360 to allow electrical connection to the conductor 356. In this case, the conductor may be formed so as to be electrically connected to the plug. The conductors 328 and 330 also function as wirings. In particular, the conductor has a barrier property against hydrogen. It is preferable that the conductive material includes a conductor having the formula:

[0210] In addition, the insulator 360 is made of an insulator having a barrier property against hydrogen, and the conductor By using a conductor having a barrier property against hydrogen, the transistor 300 and A transistor 700, a plurality of transistors 800, and a transistor 900, which will be described later; Therefore, the transistor 300 can be separated from the transistor 301 by the barrier layer. Diffusion of hydrogen into transistor 700, multiple transistors 800, and transistor 900 It can be suppressed.

[0211] Next, the transistor 700 and the plurality of transistors 800 included in the memory unit 100 Regarding the transistor 900 and the insulators, conductors, etc. formed around it, explain.

[0212] FIG. 11 shows an example in which the memory unit 100 has a NAND type memory circuit with a three-dimensional structure. The storage unit 100 of the information processing device shown in FIG. 11 is a NAND type storage circuit with a three-dimensional structure. The components include a transistor 700, a plurality of transistors 800, and a transistor 9. 00. The transistors 700 and 900 have the same This corresponds to a transistor for selecting a plurality of transistors 800 located in the same opening. The transistor 800 corresponds to a cell transistor that stores data. In the above, a transistor 700, a plurality of transistors 800, and a transistor The transistor 900 is sometimes called a string.

[0213] The storage unit 100 shown in FIG. 11 is provided on the control unit 200. Above the control unit 200, the insulators 111 to 117, the insulator 121, the insulator The conductor 122, the insulator 131, the insulator 132, the insulator 133, the conductors 151 to 156 , semiconductors 141 to 143.

[0214] The insulator 111 is provided above the control unit 200. The insulator 360 located in the upper portion is preferably formed by a film forming method that provides good flatness. In addition, it is preferable that the insulator 360 has been subjected to a CMP process.

[0215] The insulator 111 is made of a material containing, for example, silicon oxide or silicon oxynitride. In addition, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum can be used. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium, tantalum, etc. The insulating material may be used in a single layer or a multilayer.

[0216] The conductor 151 is provided by being laminated on the insulator 111. For example, the conductor 151 is Thus, it functions as a wiring that applies a predetermined potential to all strings in the storage unit 100.

[0217] The conductor 151 may be, for example, aluminum, chromium, copper, silver, gold, platinum, or tantalum. , nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, Select from calcium, magnesium, zirconium, beryllium, indium, ruthenium, etc. Materials containing one or more of the above metal elements can be used. Highly conductive semiconductors, such as polycrystalline silicon, and nickel silicide Silicides such as those contained in the metal oxides described in the sixth embodiment may also be used. Conductive materials containing metal elements and oxygen may also be used. Metals such as titanium and tantalum may also be used. Conductive materials containing elements such as titanium nitride and tantalum nitride may also be used. Alternatively, a conductive material containing nitrogen may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium zinc Indium tin oxide or silicon-added indium tin oxide may also be used. Indium gallium zinc oxide containing silicon may also be used. This may enable the capture of hydrogen or water that may be mixed in from surrounding insulators.

[0218] There is no particular limitation on the method for forming the conductor 151. For example, sputtering, CVD (thermal CVD method, MOCVD method, PECVD method, etc.), MBE (Molecular Be am Epitaxy) method, ALD (Atomic Layer Deposition) ) method, PLD (Pulsed Laser Deposition) method, etc. It is possible.

[0219] The insulators 112 to 117 are made of, for example, a material similar to that of the insulator 111. The insulators 112 to 117 can be made of, for example, a material with a low dielectric constant. It is preferable to use a material with a low dielectric constant for the insulators 112 to 117. By using the conductors 152 to 156 and the insulators 112 to 117, Therefore, the drive speed of the memory unit 100 can be improved. It can be raised.

[0220] There is no particular limitation on the method for forming the insulators 112 to 117. For example, sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD The film can be formed by the PLD method or the like.

[0221] The conductor 152 is electrically connected to the gate of the transistor 900. The conductors 153 to 155 function as wirings between a plurality of transistors. It functions as the gate of 800 and the wiring electrically connected to the gate. The conductor 156 is electrically connected to the gate of the transistor 700 and It functions as a wiring.

[0222] The conductors 152 to 156 are made of, for example, a material similar to that of the conductor 151. In addition, the conductors 152 to 156 can be formed by the same method as that for forming the conductors 151 A similar method can be used.

[0223] In addition, openings are formed in the insulators 112 to 117 and the conductors 152 to 156. The opening is provided with an insulator 121, an insulator 122, an insulator 131 to an insulator 132, and an insulator 133. The body 133, semiconductors 141 to 143 are provided.

[0224] The semiconductor 141 is provided so as to contact part of the side surface and the bottom surface of the opening. Specifically, the semiconductor 141 is provided on a part of the conductor 151 and is also provided on the insulating layer on the side of the opening. It is provided so as to cover a part of the edge body 112 .

[0225] The semiconductor 141 is preferably silicon with impurities diffused therein. As the impurity, an n-type impurity (donor) can be used. For example, phosphorus, arsenic, etc. can be used. As the p-type impurity, for example, boron, aluminum, As for silicon, for example, single crystal silicon can be used. Silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc. may be used. In addition to silicon, the semiconductor 141 can be a metal with a high carrier concentration. Oxides may be applicable. Semiconductors such as Ge, ZnSe, CdS, GaAs In some cases, compound semiconductors such as InP, GaN, and SiGe can be applied.

[0226] The materials used for the semiconductors 142 and 143 described later are the same as those used for the semiconductor 141. The carrier concentration of the semiconductor 142 is preferably the same as that of the semiconductor 141 and the semiconductor 143. It may be preferable to have a lower

[0227] For example, when silicon in which p-type impurities are diffused is used as the semiconductor 141, After the semiconductor 141 is formed on the conductor 151, boron, aluminum, and the like are added to the semiconductor 141. It is preferable to add p-type impurities such as silicon or gallium to the semiconductor 141. A p-type region is formed. Also, for example, when using silicon in which n-type impurities are diffused, After forming the semiconductor 141 on the conductor 151, the semiconductor 141 is doped with phosphorus, arsenic, or the like. It is preferable to add n-type impurities. This forms an n-type region in the semiconductor 141. will be done.

[0228] In addition, when a metal oxide is used as the semiconductor 141, for example, the semiconductor 141 is After forming the semiconductor 141 on the conductor 151, it is preferable to add a metal element or the like to the semiconductor 141. This makes it possible to increase the carrier concentration in the semiconductor 141. When the metal oxide described in the sixth embodiment is used as the semiconductor 141, the semiconductor 141 is the n-type region (n + In addition, a metal element or the like is added to the semiconductor 141. Instead of adding oxygen, water, hydrogen, etc. are added and then heat treatment is performed to create oxygen vacancies in the semiconductor 141. In the region of the semiconductor 141 where oxygen vacancies occur, an n-type region is formed. As a result, the carrier concentration of the semiconductor 141 increases.

[0229] The insulator 121 is provided so as to contact a part of the bottom surface of the opening. The insulator 121 is formed so as to cover a part of the semiconductor 141 and the conductor 152 on the side of the opening. It is provided.

[0230] The insulator 121 functions as a gate insulating film of the transistor 900.

[0231] The insulator 121 may be made of, for example, silicon oxide or silicon oxynitride. In particular, when a metal oxide is used as the semiconductor 142 described later, the insulator 121 can be It is preferable that the material is one that releases oxygen when heated. By providing the body 142 in contact with the metal oxide, Oxygen vacancies can be reduced, and the reliability of the transistor 900 can be improved.

[0232] The method for forming the insulator 121 is not particularly limited. 152 and the side surface of the opening provided in the insulator 113, so that a highly coating-like growth can be achieved. A method for forming a film with high film-forming properties is required. For example, the ALD method is one example. do.

[0233] The insulator 131 is provided so as to contact a part of the side surface of the opening. The insulator 131 is provided to cover the conductors 153 to 155 on the side surfaces of the opening. Therefore, the insulator 131 is also insulated from the insulators 114 and 115 on the side of the opening. It is designed to cover.

[0234] The insulator 132 is provided so as to be in contact with the insulator 131. The insulator 133 is , and are provided so as to be in contact with the insulator 132. That is, the insulators 131 to 133 are stacked in order from the side surface of the opening toward the center.

[0235] The insulator 131 functions as a gate insulating film of the transistor 800. The insulator 32 functions as a charge storage layer of the transistor 800. It functions as a tunnel insulating film for the transistor 800 .

[0236] The insulator 131 may be made of, for example, silicon oxide or silicon oxynitride. The insulator 131 may be, for example, aluminum oxide, hafnium oxide, Alternatively, an oxide containing aluminum and hafnium can be used. The insulator 131 may be a laminate of these. By making the thickness of the insulator 133 thicker than that of the semiconductor 142, the insulator 133 can be easily transferred from the semiconductor 142 to be described later. , the insulator 132 can be used to transfer charges.

[0237] The insulator 132 may be made of, for example, silicon nitride or silicon nitride oxide. However, the materials that can be used for the insulator 132 are not limited to these.

[0238] The insulator 133 may be made of, for example, silicon oxide or silicon oxynitride. The insulator 133 is preferably made of, for example, aluminum oxide, hafnium oxide, Alternatively, an oxide containing aluminum and hafnium may be used. 33 may be an insulator made by laminating these.

[0239] The insulator 122 is provided so as to contact a part of the side surface of the opening. , and is provided to cover the conductor 156 on the side of the opening.

[0240] The insulator 122 functions as a gate insulating film for the transistor 700 .

[0241] The insulator 122 may be made of the same material as the insulator 121. The insulator 122 can be formed by the same method as that for the insulator 121 .

[0242] The semiconductor 142 is formed in the opening by the insulators 121, 133, and It is provided so as to contact the side surface of the insulator 122 .

[0243] The semiconductor 142 includes transistors 700, 800, and 900. The channel forming region, the transistor 700, the transistor 800, and the transistor 900 It functions as wiring for electrical connection in series.

[0244] For example, silicon is preferably used as the semiconductor 142. Examples of suitable silicon include monocrystalline silicon, hydrogenated amorphous silicon, microcrystalline silicon, and The semiconductor 142 may be made of a material other than silicon. In some cases, metal oxides can be used. Semiconductors such as Ge, ZnSe, and CdS Compound semiconductors such as GaAs, InP, GaN, and SiGe may be applicable.

[0245] The semiconductor 143 is formed by stacking the semiconductor 141, the semiconductor 142, the insulator 121, and the insulator 122 in the opening. 22, after the insulators 131, 132, and 133 are formed, the opening is filled Specifically, the semiconductor 143 is disposed on the insulator 122 and the semiconductor 14 2 and is provided so as to be in contact with the side surface of the insulator 117.

[0246] The semiconductor 143 is preferably made of the same material as the semiconductor 141. Therefore, it is preferable that the polarities of the semiconductor 141 and the semiconductor 143 are the same.

[0247] A wiring layer may be provided on the insulator 117 and the semiconductor 143. For example, in FIG. As a wiring layer, an insulator 382 and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulator 382 and the insulator 384. 6 functions as a plug or wiring. The conductor 330 can be formed using the same material.

[0248] Note that the data processing device of one embodiment of the present invention includes the NAN included in the storage unit 100 illustrated in FIG. The present invention is not limited to the configuration of a D-type memory circuit. The D-type memory circuit may have a different configuration from the NAND-type memory circuit shown in FIG.

[0249] <Configuration example 2 of information processing device> FIG. 13 shows an example of the configuration of an information processing device different from that shown in FIG. 11. The information processing device has a configuration in which the configuration of the storage unit 100 of the information processing device in FIG. 11 is modified. Specifically, the storage unit 100 of the information processing device in FIG. 13 is the same as the storage unit in FIG. 4A described in the second embodiment. The memory section is configured as follows.

[0250] In the storage unit 100 of the information processing device shown in FIG. 13, as an example, a three-dimensional structure NAN The memory cell MC[1] included in the D-type memory circuit is composed of a transistor RTr and a transistor The transistor WTr and the capacitor CS are included.

[0251] 11, the storage unit 100 shown in FIG. 13 is configured to store the data stored in the storage unit 100 on the control unit 200. The storage unit 100 is provided above the control unit 200 and is surrounded by an insulator 211. to insulator 215, insulators 240 to 243, conductor 221, conductor 222, conductor The semiconductor device includes a body 250 to a conductor 253, a semiconductor 231, and a semiconductor 232.

[0252] The insulator 240 is provided above the control unit 200. The insulator 360 located in the upper portion is preferably formed by a film forming method that provides good flatness. In addition, it is preferable that the insulator 360 has been subjected to a CMP process.

[0253] For example, the material applicable to the insulator 111 can be used as the insulator 240. .

[0254] The insulator 241 is provided by being laminated on the insulator 240 .

[0255] The insulator 241 may be made of a material that can be used for the insulator 111, similar to the insulator 240. Fees can be used.

[0256] The insulator 240 has a conductor 250 embedded therein, and the insulator 241 has a conductor 250 embedded therein. The conductor 250 and the conductor 251 are used as plugs or wiring. 11, and also functions as a plug or wiring shown in FIG. In some cases, the same symbol may be used to denote multiple structures of a conductor. In the above, the wiring and the plug connected to the wiring may be integrated. In some cases, a part of the conductor functions as a wiring, and in other cases, a part of the conductor functions as a plug. .

[0257] The conductor 250 and the conductor 251 are, for example, the conductor 328 and the conductor 330. Materials applicable to the above can be used.

[0258] The insulator 211 is provided on the insulator 241. The conductor 221 is provided on the insulator 241. 11. Insulator 212 is provided on conductor 221. In addition, the conductor 222 is provided on the insulator 212. 221, the insulator 212, and the conductor 222 are stacked in this order (these are called a stack). 13. The storage unit 100 of the information processing device in FIG. 13 stores the data contained in one string. The number of stacked bodies is equal to the number of memory cells MC.

[0259] In addition, in the manufacturing process of the information processing device shown in FIG. 2. An opening is formed in the conductor 222 by forming a resist mask and etching. At this time, the conductor 221 is selectively removed, and the insulator 211 and the conductor 222 are removed. 21, the recess is formed by the insulator 212. In this case, the conductor 221 is The etching rate of the insulator 211, the insulator 212, and the conductor 222 is higher than that of the insulator 211, the insulator 212, and the conductor 222. It is preferable to use a material that can

[0260] The resist mask can be formed by, for example, lithography, printing, or inkjet printing. When the resist mask is formed by an ink-jet method, Since no mask is used, the manufacturing cost can be reduced. Either dry etching or wet etching may be used, or both may be used.

[0261] As will be described later in detail, the opening formed by the etching process is filled with an insulator 2. 13, semiconductor 231, insulator 214, insulator 215, semiconductor 232, insulator 216, conductive The body 223 is formed in turn.

[0262] The insulators 211 and 212 are, for example, made of a material that prevents diffusion of hydrogen, impurities, etc. It is preferable to use a film having such a barrier property. For example, the same material as that of the insulator 111 can be used for the insulator 2 .

[0263] For the conductors 221 and 222, for example, materials applicable to the conductor 151 are used. In particular, the conductors 221 and 222 are preferably made of impurities such as water or hydrogen. It is preferable to use a conductive material that has the function of suppressing the permeation of pure substances.

[0264] The side of the opening formed by the etching process is covered with an insulator 213, a semiconductor 231 is formed in order. In addition, an insulator 214 is formed so as to fill the recess of the opening. will be done.

[0265] As a method for forming the insulator 214, for example, first, a layer of the insulator 214 is formed to such an extent that the recess of the opening is filled. forming an insulator 214 on the side surface of the opening, and then leaving the insulator 214 in the recess; A portion of the insulator 214 is removed by etching so that the semiconductor 231 is exposed. Just do that.

[0266] The insulator 213 may be made of, for example, silicon oxide or silicon oxynitride. The insulator 213 may be, for example, aluminum oxide, hafnium oxide, or Alternatively, oxides containing aluminum and hafnium can be used. The edge 213 may be an insulator made by laminating these.

[0267] As the semiconductor 231, it is preferable to use the metal oxide described in the sixth embodiment. In the present embodiment, it is assumed hereinafter that a metal oxide is used as the semiconductor 231. As the metal oxide, it is preferable to use the CAAC-OS described later. For example, the semiconductor 2 When polycrystalline silicon is used for 31, grain bows that may be formed in the polycrystalline silicon The electron trap density increases due to the dummy layer, which may cause large variations in transistor characteristics. On the other hand, in CAAC-OS, no clear grain boundaries are observed, so it is difficult to Variations in characteristics can be suppressed.

[0268] Before forming the insulator 214, the formed semiconductor 231 is exposed to an oxygen atmosphere. By performing the heat treatment in the atmosphere, oxygen can be supplied to the metal oxide of the semiconductor 231 . After that, after forming the insulator 214, a supply process of impurities and the like is performed on the metal oxide of the semiconductor 231. By performing this treatment, the resistance of the region exposed to the opening of the semiconductor 231 can be reduced. That is, the region of the semiconductor 231 in contact with the insulator 214 becomes a high resistance region, and the insulator 214 of the semiconductor 231 The region not in contact with the insulator 214 becomes a low resistance region.

[0269] In addition, as a supply process of impurities to the metal oxide of the semiconductor 231, for example, an opening After filling the recess with the insulator 214, a conductor is formed on the side of the opening, and the conductor When the conductive film comes into contact with the metal oxide of the semiconductor 231, The metal elements contained in the conductive film diffuse into the semiconductor 231, and the constituent elements of the semiconductor 231 When the metal compound is formed, the semiconductor 231 may have a low resistance. Anti-regions are formed.

[0270] The insulator 214 is formed by: It is preferable that the component does not form a compound with the component contained in the semiconductor 231. Specifically, For example, the insulator 214 may be made of silicon oxide.

[0271] Then, on the surface where the semiconductor 231 and the insulator 214 are formed, the insulator 215, the semiconductor 232, and the insulator 215 are formed. The edge 216 and the conductor 223 are formed in this order. The openings in the body shall be filled.

[0272] The insulators 215 and 216 may be made of a material that can be used for the insulator 213, for example. It is preferable to use

[0273] The semiconductor 232 may be, for example, a metal as described in the sixth embodiment, similar to the semiconductor 231. It is preferable to use an oxide.

[0274] For the conductor 223, it is preferable to use a material that can be applied to the conductor 151, for example. In particular, the conductor 223 has a function of suppressing the permeation of impurities such as water or hydrogen. It is preferable to use a conductive material that can

[0275] An insulator 242 and an insulator 243 are provided in this order on the top of the formed string. There are.

[0276] The insulators 242 and 243 may be made of a material that can be applied to the insulator 111, for example. It can be used.

[0277] The insulator 242 has a conductor 252 embedded therein, and the insulator 243 has a conductor 252 embedded therein. The conductor 252 and the conductor 253 are used as plugs or wiring. It has a function.

[0278] The conductor 252 and the conductor 253 are, for example, the conductor 328 and the conductor 330. Materials applicable to the above can be used.

[0279] By carrying out the above-described steps, an information processing device having the storage unit 100 shown in FIG. 4A is manufactured. It is possible.

[0280] Specifically, the wiring WBL, the wiring RBL, and the wiring BGL in the storage unit of FIG. 4A are correspond to the semiconductor 231, the semiconductor 232, and the conductor 223 in FIG. 13. The wiring WWL and wiring RWL in the memory unit correspond to the conductors 221 and 222, respectively. do.

[0281] Therefore, the conductor 222 is used as one electrode, and the region of the insulator 213 that is in contact with the conductor 222 is is the dielectric, and the region of the semiconductor 231 that overlaps with the conductor 222 is the other electrode. The region of the semiconductor 231 that overlaps with the conductor 222 is used as a gate, and the conductive The region of the insulator 215 overlapping with the conductor 222 is used as a gate insulating film, and the region of the semiconductor 215 overlapping with the conductor 222 is used as a gate insulating film. The region of the conductor 232 is a channel formation region, and the region of the insulator 216 that overlaps with the conductor 222 is a is used as a gate insulating film, and the region of the conductor 223 overlapping with the conductor 222 is used as a back gate. The conductor 221 is used as a gate, and the conductor 221 and The overlapping insulator 213 is used as a gate insulating film, and the region of the semiconductor 231 overlapping with the conductor 221 The transistor WTr is formed with the region as a channel formation region.

[0282] It should be noted that the insulators, conductors, semiconductors, etc. disclosed in this specification and the like may be deposited by PVD (Physical Vapor Deposition). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, The PVD method can be, for example, , sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed Laser Deposition) In addition, the CVD method is a plasma Examples of the thermal CVD method include MOCV. D(Metal Organic Chemical Vapor Depositio n) method and ALD (Atomic Layer Deposition) method. do.

[0283] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0284] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0285] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first An inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, Alternatively, instead of introducing an inert gas, the first source gas may be discharged by vacuum evacuation. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first thin film. The first thin layer is formed, and then reacts with the second source gas introduced later, and the second thin layer is formed on the first thin layer. The order of gas introduction is controlled until the desired thickness is reached. By repeating the above steps several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas introduction sequence is repeated. This is possible and is suitable for fabricating miniaturized FETs.

[0286] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. When forming a-Zn-O film, trimethylindium (In(CH3)3), trimethylindium (Tm(CH3)3) Using methylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) Furthermore, the present invention is not limited to these combinations, and trimethylgallium may be replaced with triethylgallium. Zinc (Ga(C2H5)3) can also be used, and diethylzinc ( Zn(C2H5)2) can also be used.

[0287] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and a liquid containing hafnium precursor compounds (hafnium alkoxide, tetrakis(dimethyl Hafnium amides such as (TDMAH, Hf[N(CH3)2]4) Two types of gases are used: vaporized ozone (O3) as a raw material gas and ozone (O3) as an oxidant. Other materials include tetrakis(ethylmethylamido)hafnium.

[0288] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (trimethylaluminum (TMA), Al(C) Two types of gases are used: vaporized H3)3) and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanediol), Onato), etc.

[0289] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are removed. The adsorbate is reacted with the adsorbate.

[0290] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. SiH4 gas may be used instead of gas.

[0291] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O are formed using It is also possible to use the HClO3 gas. Although H2O gas may be used, it is preferable to use O3 gas that does not contain H. Instead of (CH3)3 gas, In(C2H5)3 gas may be used. 3) Ga(C2H5)3 gas may be used instead of Zn(CH3)2 Gas may also be used.

[0292] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0293] (Fourth embodiment) In this embodiment, an application example of a data processing device according to one embodiment of the present invention will be described.

[0294] Generally, a computer consists of a processor, main memory, and Each component has, for example, a bus wiring. Therefore, the longer the bus wiring, the larger the parasitic resistance becomes. The power consumption required to transmit the signal is also higher.

[0295] Specifically, the computer has a configuration as shown in FIG. The computer has a motherboard BD, and on the motherboard BD, a processing unit (PC) is processor, CPU, etc.) 10, main memory (DRAM (Dynamic Random Access Memory) Access Memory)30, storage (three-dimensional structure NAND type memory) Storage device, 3D OS NAND type storage device, etc.) 40, interface 60, etc. are set up. In addition, in FIG. 14A, there is an SRAM (Static Random Access Memory) that also functions as a main memory. The IC Random Access Memory (RAM) 20 is also shown in the diagram, but It is not necessarily required to provide it on the BD.

[0296] 14A shows a configuration in which the arithmetic processing device 10 has a register 11.

[0297] In FIG. 14A, the processor 10 includes an SRAM 20, a main memory 30, and a storage device. The main memory is electrically connected to the storage 40 and the interface 60. The memory 30 is electrically connected to the SRAM 20 and the storage 40 .

[0298] The components of the computer shown in FIG. 14A are electrically connected by a bus line BSH. This means that the more components in a computer or the more motherboards are used, the The larger the bus, the longer the bus wiring BSH is required to transmit the signal. The power will be higher.

[0299] By the way, the computer of FIG. 14A has each component of the computer on one chip. and combine them into a monolithic IC (Integrated Circuit). In this case, the information processing device 50 shown in FIG. 1 and the like described in the above embodiment may be used as a memory. It can be applied as an in-memory 30 and a storage 40. In this way, FIG. The computer is shown in FIG. 14B as a monolithic IC.

[0300] The monolithic IC of FIG. 14B has a circuit layer LGC on a semiconductor substrate having Si. In addition, a memory layer STR is provided on the circuit layer LGC, and a circuit layer OSC is provided on the memory layer STR. It has.

[0301] The circuit layer LGC is, for example, a Si transistor formed on a semiconductor substrate SBT having Si. As a part of the plurality of circuits, for example, The information processing device 10, the SRAM 20, etc. When the processing device is applied as the main memory 30 and the storage 40, one of the plurality of circuits The unit may be a controller 1197 included in the information processing device 50. .

[0302] In particular, the SRAM 20 uses, for example, Si transistors to The driving frequency of M can be increased.

[0303] The memory layer STR is a memory unit having a Si transistor and / or an OS transistor. The memory layer STR is, for example, a three-dimensional NAND type memory circuit, Therefore, the memory layer STR can be a memory circuit of the OS NAND type. 14A and the like. do.

[0304] By using a 3D OS NAND type memory circuit, the monolithic memory shown in FIG. This can reduce the power consumption of the IC.

[0305] The circuit layer OSC has, for example, a plurality of circuits including OS transistors. As a part of the circuit, for example, the arithmetic processing unit 10, the SRAM 20, etc. included in the circuit layer LGC The circuit may be different from the circuit shown.

[0306] In the monolithic IC of Figure 14B, the bus wiring BSH for routing on the motherboard is Since no wiring is provided, the wiring that electrically connects the components is short. Therefore, the power consumption required for transmitting signals can be reduced.

[0307] The monolithic IC of FIG. 14B also includes an information processing device 50. The information processing device 50 has the functions of the storage 40 and the main memory 30 in FIG. 14A. Therefore, the monolithic IC of FIG. 14B has the main memory 30 as a memory layer S It can be the storage unit 1196 of the TR.

[0308] The bus wiring BSH is not provided, and the memory unit 1196 is used as a substitute for the main memory 30. Because of this, the monolithic IC of FIG. 14B is smaller in circuit area than the computer of FIG. 14A. The product can be reduced.

[0309] A specific schematic diagram of the monolithic IC of FIG. 14B is shown in FIG. 15. The IC 1500 has a 3D OS NAND type memory device as described in the previous embodiment. do.

[0310] The monolithic IC 1500 of FIG. 15 includes a circuit layer LGC, a memory layer STR, and a circuit layer O. The monolithic IC 1500 shown in FIG. The T is omitted.

[0311] The memory layer STR has a plurality of strings STG. corresponds to strings ST1 to ST3 in the first embodiment.

[0312] The conductor ME1 included in the memory layer STR is connected to the circuit layer LGC and the circuit layer OSC. , and functions as wiring that electrically connects them.

[0313] The conductor ME2 included in the memory layer STR is connected to the circuit layer OSC and a plurality of conductors M It functions as a wiring that electrically connects E3.

[0314] The conductor ME3 included in the memory layer STR is included in the plurality of strings STG. The gate of the cell transistor and the wiring electrically connected to the gate are That is, the conductor ME3 functions similarly to the conductor 15 in FIG. 2, conductor 153, conductor 154, conductor 155, conductor 156, conductor 222 in FIG. 1 (e.g., wiring RWL[1], etc.), conductor 221 (e.g., wiring WWL[1], etc.) etc.

[0315] Next, an example of the memory hierarchy of the computer of FIG. 14A and the monolithic IC of FIG. 14B is shown. These are shown in Figures 16A and 16B, respectively.

[0316] Generally, in the memory hierarchy, the higher the storage device is located, the faster the operating speed is required. The larger the storage device, the larger the storage capacity and recording density required. Then, from the top layer, there are registers included in the CPU (arithmetic processing unit 10) and SRAM. the DRAM included in the main memory 30, and the three-dimensional memory included in the storage 40. 1 shows a NAND type memory circuit having a structure.

[0317] The registers and SRAM included in the arithmetic processing device 10 are used for temporarily storing the results of calculations. Therefore, the access frequency from the arithmetic processing unit 10 is high. In addition, registers are used to store setting information for the arithmetic processing unit. It also has the function of

[0318] The DRAM included in the main memory 30 is, for example, a memory read from the storage 40. DRAM has the function of storing programs, data, etc. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0319] The storage 40 stores data that needs to be stored for a long period of time and various programs used by the processing unit. Therefore, the storage 40 has a function to store a larger memory capacity than the operating speed. The storage device used in the storage 40 has a recording density of: Approximately 0.6 to 6.0 Gbit / mm 2 Therefore, the storage 40 is , three-dimensional structure NAND type memory circuit (3D OS NAND), hard disk drive Hard disk drives (HDDs) are used.

[0320] Incidentally, in the monolithic IC of FIG. 14B, as described above, the information processing device 50 of FIG. 14B. The memory hierarchy of the Norlissic IC is shown in Figure 16B.

[0321] That is, in the monolithic IC of FIG. 14B, the memory unit 10 of the information processing device 50 of FIG. The memory cells included in the 0 are not only the cache memory of the storage unit 100 but also the This can be treated as the main memory 30 in the computer. In the monolithic IC, there is no need to provide a main memory 30 such as a DRAM. , the circuit area of ​​the monolithic IC of FIG. 14B can be reduced, and the size of the monolithic IC can be reduced. The power consumption required to operate the main memory 30 can be reduced.

[0322] The configuration of the monolithic IC shown in FIG. 14B is an example and is not limited to one embodiment of the present invention. The monolithic IC shown in FIG. 14B may be reconfigured depending on the situation. For example, in the monolithic IC of FIG. 14B, for example, the SRAM can operate at 1 GHz or more. If high-speed memory is required, SRAM may be integrated into the processor. .

[0323] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0324] (Embodiment 5) In this embodiment, an example of a method for writing data to a NAND type storage device such as that described in this specification will be described. and explain.

[0325] FIG. 17A shows a processor (such as a processor or CPU) 70 and a storage device (with a three-dimensional structure) NAND type storage device, 3D OS NAND type storage device) 80 and electrical connection Specifically, the arithmetic processing unit 70 is connected to the storage device 8 via a plurality of wirings 90. Electrically connected to 0.

[0326] The arithmetic processing unit 70 is connected to the storage device 80 via a plurality of wirings 90. It has the function of transmitting data to be written to the memory cells that are being distributed. The line 90 functions as a write bit line, which corresponds to the wiring WBL in the above-described embodiment. For example, if the memory device 80 is a NAND structure memory device and stores multiple strings, If so, each of the plurality of wires 90 is electrically connected to a plurality of strings. There are.

[0327] By the way, in order to increase the speed of writing data to the memory cells included in the storage device 80, To achieve this, a material with a low resistance value is used for forming the wiring 90, the length of the wiring 90 is shortened, etc. Examples include:

[0328] Also, means for increasing the speed at which data is written to memory cells included in the storage device 80 In other words, the number of wires 90 (the number of wires 90 electrically connected) can be increased. By increasing the number of strings of storage devices 80 connected to the This allows for an increase in the number of data stored in memory cells.

[0329] Next, a method for transmitting write data will be described with reference to FIG. 17B.

[0330] The arithmetic processing unit 70, for example, includes latch circuits LT1[1] to LT1[z ] (z is an integer of 2 or more), and latch circuit LT2[1] to latch circuit LT2[z ] and wirings 90[1] to 90[z]. As a NAND type memory device, strings STG[1] to STG[z ].

[0331] In the arithmetic processing device 70, the latch circuits LT1[1] to LT1[z] are A shift register is configured. Therefore, the latch circuit LT1[1] to the latch circuit LT Each clock input terminal of 1[z] is electrically connected to a wiring CLK that transmits a clock signal. The shift register is connected to the input terminal of the latch circuit LT1[1]. The write data DA is input as a clock signal from the line CLK. Depending on the number of voltages, the signals are sent to the latch circuits LT1[2] to LT1[z] in sequence. It is possible.

[0332] Also, the output terminal of the latch circuit LT1[v] (where v is an integer between 1 and z) The input terminal of the latch circuit LT2[v] is electrically connected to the input terminal of the latch circuit LT2[v]. The data DA output from the circuit LT1[v] is input to the latch circuit LT2[v]. The latch circuit LT2[v] is electrically connected to the string STG[v] via the wiring 90[v]. electrically connected.

[0333] The clock input terminals of the latch circuits LT2[1] to LT2[z] are The wiring ENL is electrically connected to the arithmetic processing unit 70. The wiring functions as a wiring for transmitting a trigger signal for transmitting data DA to the device 80.

[0334] By serial transmission, data DA is input to the latch circuit LT1[1], and the latch Data DA is input sequentially to latch circuit LT1[1]. Data DA is input sequentially to the latch circuits LT1[1] to LT1[z], and the latch circuits LT Data DA[1] to data DA[z] are stored in latch circuits LT1[1] to LT1[z], respectively. ] is assumed to be stored.

[0335] At this time, the output terminals of the latch circuits LT1[1] to LT1[z] Data DA[1] to data DA[z] are output from to data DA[z] are latched by latch circuits LT2[1] to LT2[z], respectively. ] will be entered.

[0336] In this way, the data DA input by serial transmission is The data DA[z] is distributed to the latch circuits LT1[1] to LT1[z]. In other words, the data DA input by serial transmission can be DA[1] to DA[z] are distributed to wiring 90[1] to wiring 90[z]. This can be done.

[0337] Then, the latch circuits LT2[1] to LT2[z] are connected to the wiring ENL. When a trigger signal is applied to each clock signal input terminal, the latch circuit Data DA[1] to data DA[2] are output from latch circuits LT2[1] to LT2[z], respectively. DA[z] is transmitted to the storage device 80 in parallel via wiring 90[1] to wiring 90[z]. The inputs can be strings STG[1] through STG[z].

[0338] By applying the above-mentioned configuration and driving method, the serially transmitted data is stored in the storage device 80. The data to be written is sent in parallel to the strings STG[1] to STG[2] of the storage device 80. The data can be sent to the STG[z].

[0339] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0340] (Embodiment 6) In this embodiment, the semiconductor device can be used for the OS transistor described in the above embodiment. The metal oxide (hereinafter also referred to as an oxide semiconductor) will be described.

[0341] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that the material contains yttrium, tin, etc. Also, boron, silicon, titanium, etc. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Selected from among odymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. One or more of these may be included.

[0342] <Classification of crystal structures> First, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. 18A. FIG. 18A shows an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides.

[0343] As shown in FIG. 18A, oxide semiconductors are broadly divided into "amorphous" and "non-amorphous" oxide semiconductors. ) and "Crystalline" and "Crystal" Also, among "Amorphous" there are those that are completely amorphous. Also, "Crystalline" contains CAAC (ca xis-aligned crystalline), nc(nanocrystall ine), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal al). The classification of "Crystalline" includes single crystal , poly crystal, and completely amorphous are excluded. Also, "Crystal" includes single crystal and poly Contains crystals.

[0344] The structures within the bold frame in Figure 18A are "Amorphous" and "Cr It is an intermediate state between "crystal" and "new crystal" In other words, the structure is in the It is completely different from the unstable "Amorphous" and "Crystal" This can be rephrased as a different structure.

[0345] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). The crystallinity can be evaluated using the crystallinity spectrum. The GIXD (Grazing-Incidence) of CAAC-IGZO films The XRD spectrum obtained by the GIXD measurement is shown in Figure 18B. This is also called the membrane method or the Seemann-Bohlin method. The XRD spectrum obtained by the measurement is simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 18B is 500 nm.

[0346] As shown in Figure 18B, the XRD spectrum of the CAAC-IGZO film shows clear crystalline Specifically, in the XRD spectrum of the CAAC-IGZO film, A peak indicating the c-axis orientation is detected near 2θ=31°. The peak intensity at 2θ=31° is detected at the angle It is asymmetrical about the axis.

[0347] The crystal structure of the film or substrate was also analyzed by nanobeam electron diffraction (NBED). Diffraction patterns (ultra-small) observed by electron diffraction It can be evaluated by the electron diffraction pattern. The folding pattern is shown in Figure 18C. Figure 18C shows the NB method in which the electron beam is incident parallel to the substrate. The diffraction pattern observed by ED is shown in Figure 18C. The composition of the film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0348] As shown in Figure 18C, the diffraction pattern of the CAAC-IGZO film shows multiple patterns indicating c-axis orientation. Several spots are observed.

[0349] <<Oxide semiconductor structure>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in FIG. 18A. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, the above-mentioned CAAC-OS Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-crystalline oxide semiconductors, and nc-OS. Amorphous-like oxide semiconductor (a-like OS) semiconductor), amorphous oxide semiconductor, etc.

[0350] Here, for details on the above-mentioned CAAC-OS, nc-OS, and a-like OS, , and provide an explanation.

[0351] [CAAC-OS] The CAAC-OS has multiple crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. , in the normal direction to the surface on which the CAAC-OS film is formed, or in the normal direction to the surface of the CAAC-OS film. The crystalline region is a region in which the atomic arrangement has periodicity. When viewed as a crystal arrangement, the crystalline region is also a region with a uniform lattice arrangement. The OS has a region where multiple crystalline regions are connected in the ab-plane direction, and this region has strain. The distortion may occur in a region where multiple crystal regions are connected. The area where the orientation of the lattice arrangement changes between a region with one lattice arrangement and a region with a different lattice arrangement. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that has not been

[0352] Each of the plurality of crystalline regions is made up of one or more minute crystals (maximum diameter 10 When a crystalline region is made up of a single microcrystal (crystals less than 1 nm in size), The maximum diameter of the crystalline region is less than 10 nm. When such crystal regions are formed, the size of the crystal regions may be on the order of several tens of nanometers.

[0353] In-M-Zn oxide (where element M is aluminum, gallium, yttrium, copper, , vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium Aluminum, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten In the case of (one or more selected from the group consisting of magnesium, etc.), CAAC-OS is A layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing elements M, zinc (Zn), and The layered crystal structure (layered structure) is composed of a layer containing oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M can be substituted for each other. Therefore, the (M, Zn) layer may contain indium. The In layer may contain Zn. For example, it is observed as a lattice image in a high-resolution TEM image.

[0354] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ phase In the out-of-plane XRD measurement using a can, two peaks indicating the c-axis orientation were observed. The peak indicating the c-axis orientation is detected at or near θ=31°. ) may vary depending on the type and composition of the metal elements that make up the CAAC-OS.

[0355] For example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) Note that one spot and another spot are the incident electron beams that have passed through the sample. The spot (also called the direct spot) is the center of symmetry, and the points are observed at positions that are point-symmetric. can be.

[0356] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is a hexagonal lattice. However, the unit cell is not necessarily a regular hexagon, and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. -In OS, clear grain boundaries were confirmed even near the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is close-packed in the ab-plane direction. The bond distance between atoms changes when metal atoms are substituted. This is thought to be because distortion can be tolerated.

[0357] The crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries act as recombination centers, trapping carriers and forming transistors. It is highly likely that this will cause a decrease in on-state current and a decrease in field effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystalline structure suitable for the semiconductor layer of a transistor. It is one of the crystalline oxides containing Zn to form CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are made of In oxide. This is preferable because it can suppress the generation of grain boundaries more effectively than oxides.

[0358] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, the CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. In addition, the crystallinity of an oxide semiconductor is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. CAAC-OS can withstand the high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for an OS transistor, the manufacturing process can be automated. This allows for greater flexibility.

[0359] [nc-OS] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). In other words, nc-OS has a periodic atomic arrangement in the region of 3 nm or less. It has small crystals. The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. Since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, depending on the analytical method, nc-OS may be considered as a-like In some cases, it may be difficult to distinguish between an OS and an amorphous oxide semiconductor. On the other hand, when structural analysis is performed using an XRD device, out-of- In the plane XRD measurement, no peaks indicating crystallinity were detected. In contrast, electron beams with a probe diameter larger than that of nanocrystals (e.g., 50 nm or larger) are used. When performing selected area electron diffraction (also called selected area electron diffraction), a diffraction pattern like a halo pattern appears. On the other hand, for the nc-OS film, the size of the nanocrystals is close to or smaller than that of the nanocrystals. Electron beam diffraction (nano-beam diffraction) using an electron beam with a small probe diameter (for example, 1 nm to 30 nm) When electron beam diffraction is performed, a ring-shaped area is detected around the direct spot. In some cases, an electron diffraction pattern is obtained in which multiple spots are observed within a single electron beam.

[0360] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has pores or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0361] <<Oxide semiconductor structure>> Next, the details of the above-mentioned CAC-OS will be explained. Regarding the formation of

[0362] [CAC-OS] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are 0.5 nm to 10 nm in size. Preferably, the material is unevenly distributed in a size of 1 nm to 3 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in a metal oxide. The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A mixed state of particles with sizes of less than 1 m or close to that size is called a mosaic or patch state. .

[0363] Furthermore, CAC-OS is a material that is separated into a first region and a second region. The first regions are in a shape similar to a cloud, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud shape). ) In other words, the CAC-OS is a mixture of the first area and the second area. It is a composite metal oxide having a structure in which

[0364] Here, the I ratio of the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of n, Ga, and Zn are defined as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has [In] higher than the [In] in the second region. In this region, [Ga] is larger than [Ga] in the first region. In addition, the second region has a larger [Ga] than the [Ga] in the first region and a smaller [I [n] is smaller than [In] in the first region.

[0365] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region containing gallium oxide, gallium zinc oxide, etc. In other words, the first region is called a region in which In is the main component. The second region can be rephrased as a region containing Ga as the main component. It is possible.

[0366] Note that there are cases where a clear boundary between the first region and the second region cannot be observed. .

[0367] For example, in the case of CAC-OS in In-Ga-Zn oxide, energy dispersive X-ray diffraction (EDX) Optical method (EDX:Energy Dispersive X-ray spectrosc) The EDX mapping obtained using the opy revealed a region containing In as the main component (the first region). The structure has a structure in which a first region (a first region) and a region (a second region) mainly composed of Ga are unevenly distributed and mixed. It can be confirmed that

[0368] When CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are The insulating properties due to the region act complementary to each other to provide a switching function (On In other words, the CAC-OS and has a conductive function in a part of the material and an insulating function in a part of the material, and By separating the conductive function from the insulating function, Therefore, by using CAC-OS in transistors, This allows for a high on-state current (I on ), high field-effect mobility (μ), and good switching This allows for realizing a switching operation.

[0369] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductors in Two or more of AC-OS, nc-OS, and CAAC-OS may be included.

[0370] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0371] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0372] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. , the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 c m -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm - 3 In order to reduce the carrier concentration of the oxide semiconductor film, The impurity concentration in the semiconductor film may be reduced to reduce the defect state density. A low impurity concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. The oxide semiconductor having a low carrier concentration is preferably a high-purity intrinsic or substantially high-purity intrinsic oxide. These are sometimes called nitride semiconductors.

[0373] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0374] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. This may be the case.

[0375] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, it is effective to reduce It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0376] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0377] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, Defect levels are formed in the oxide semiconductor. The concentration of silicon, carbon, etc. near the interface with the oxide semiconductor (secondary ions) Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by 18 atoms / cm 3 Below, preferably 2 x10 17 atoms / cm 3 The following applies.

[0378] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may be included. Transistors using oxide semiconductors, which are widely used in semiconductors, tend to be normally on. Therefore, the concentration of alkali metals or alkaline earth metals in oxide semiconductors obtained by SIMS Degrees, 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0379] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor becomes a semiconductor. The transistors used for the oxide semiconductors tend to be normally on. Therefore, if nitrogen is contained, trap levels may be formed. Therefore, the electrical properties of the oxide semiconductor obtained by SIMS may become unstable. The nitrogen concentration in 19 atoms / cm 3 Less than 5 x 10 18 ato ms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following are more preferred: Kuha 5 x 10 17 atoms / cm 3 Do the following:

[0380] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Make it less than.

[0381] By using an oxide semiconductor with sufficiently reduced impurities in a channel formation region of a transistor, This makes it possible to impart stable electrical properties.

[0382] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0383] (Embodiment 7) In this embodiment mode, a semiconductor wafer on which the information processing device or the like shown in the above embodiment mode is formed is used. and an example of an electronic component incorporating the information processing device will be described.

[0384] <Semiconductor wafer> First, an example of a semiconductor wafer on which an information processing device or the like is formed will be described with reference to FIG. 19A. do.

[0385] The semiconductor wafer 4800 shown in FIG. 19A includes a wafer 4801 and a The wafer 4801 has a plurality of circuit portions 4802. The area without the circuit portion 4802 is a spacing 4803, which is an area for dicing. .

[0386] The semiconductor wafer 4800 has a plurality of circuits formed on the surface of the wafer 4801 by a previous process. The wafer 4801 can be fabricated by forming a portion 4802. The surface opposite to the surface on which the plurality of circuit portions 4802 are formed is ground to thin the wafer 4801. This process reduces warpage of the wafer 4801 and allows for miniaturization of the components. It is possible.

[0387] The next step is the dicing process. Scribe line SCL1 and scribe line SCL2 (dicing line or cutting line) The spacing 4803 is the same as the dicing process. To facilitate this process, multiple scribe lines SCL1 are arranged in parallel, and multiple The scribe line SCL2 is set parallel to the scribe line SCL1. It is preferable that the live line SCL2 is arranged vertically.

[0388] By performing a dicing process, a chip 4800a as shown in FIG. 19B is obtained. The chip 4800a can be cut from the wafer 4800. The chip 4800a is made of a wafer 4801a and The circuit portion 4802 and the spacing 4803a are included. It is preferable that a is as small as possible. In this case, the distance between adjacent circuit portions 4802 is The width of the spacing 4803 is the width of the cutting allowance of the scribe line SCL1 or the width of the scribe line SCL2. It is sufficient if the length is approximately the same as the cutting allowance of the brine SCL2.

[0389] The shape of the element substrate according to one embodiment of the present invention is the same as that of the semiconductor wafer 4800 shown in FIG. 19A. For example, the semiconductor wafer may be rectangular. The shape can be appropriately changed depending on the manufacturing process of the element and the device for manufacturing the element. Cut.

[0390] <Electronic components> FIG. 19C shows electronic component 4700 and a substrate on which electronic component 4700 is mounted (mounting substrate 47 19C shows a perspective view of the electronic component 4700. The electronic component 4700 shown in FIG. 19C is a chip in a mold 4711. The chip 4800a shown in FIG. 19C includes a circuit section 480 2 indicates a stacked structure. The information processing device described above can be applied. The electronic component 4700 is mounted on the outside of the mold 4711. The land 4712 is electrically connected to an electrode pad 4713. The head 4713 is electrically connected to the chip 4800a by a wire 4714. The sub-component 4700 is mounted on, for example, a printed circuit board 4702. The components are assembled together and electrically connected to the printed circuit board 4702. The substrate 4704 is completed.

[0391] 19D shows a perspective view of the electronic component 4730. The electronic component 4730 is a SiP (System in Package) em in Package) or MCM (Multi Chip Module) This is an example. The electronic component 4730 is mounted on a package substrate 4732 (printed circuit board). An interposer 4731 is provided, and a semiconductor device 4735 is provided on the interposer 4731. A plurality of semiconductor devices 4710 are provided.

[0392] The electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 includes: For example, the semiconductor device described in the above embodiment, the high-bandwidth memory (HBM), The semiconductor device 4735 can be a It is possible to use integrated circuits (semiconductor devices) such as CPUs, GPUs, FPGAs, and memory devices. Cut.

[0393] The package substrate 4732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 4731 is a silicon interposer. , a resin interposer, etc. can be used.

[0394] The interposer 4731 has multiple wirings and can support multiple integrated circuits with different terminal pitches. The wiring has a function of electrically connecting. The wiring is provided in a single layer or in multiple layers. The interposer 4731 is a package that holds the integrated circuit mounted on the interposer 4731. It has a function of electrically connecting to an electrode provided on the substrate 4732. An interposer is sometimes called a "rewiring board" or "intermediate board." The laser 4731 is provided with a through electrode, and the through electrode is used to connect the integrated circuit to the package substrate 47 32 may be electrically connected. In addition, in the silicon interposer, Therefore, TSV (Through Silicon Via) can also be used.

[0395] It is preferable to use a silicon interposer as the interposer 4731. Since the interposer does not require active elements, it can be manufactured at a lower cost than integrated circuits. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring, which is difficult to do with resin interposers.

[0396] In HBM, many wires must be connected to achieve a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is recommended to use a silicon interposer for implementing HBM. It is preferable that:

[0397] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to differences in the expansion coefficient between the posers. The surface of the silicon interposer is highly flat, so the integrated circuit mounted on the silicon interposer and the silicon Connection failures between interposers are unlikely to occur. In particular, it is possible to mount multiple integrated circuits on an interposer. In a 2.5D package (2.5-dimensional mounting) where devices are arranged side by side, the silicon interposer It is preferable to use the

[0398] A heat sink (heat dissipation plate) may be provided on top of the electronic component 4730. When providing a circuit board, it is preferable to align the height of the integrated circuit provided on the interposer 4731. For example, the electronic component 4730 shown in this embodiment is a semiconductor device 4710. It is preferable to align the height of the body devices 4735.

[0399] In order to mount the electronic component 4730 on another substrate, electrodes 4 are attached to the bottom of the package substrate 4732. 19D shows an example in which the electrode 4733 is formed by a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 4732, A (Ball Grid Array) mounting can be realized. Also, the electrode 4733 can be made conductive. The bottom of the package substrate 4732 may be provided with conductive pins in a matrix. By providing this, PGA (Pin Grid Array) mounting can be achieved.

[0400] The electronic component 4730 is not limited to BGA and PGA, but can be mounted on other boards using various mounting methods. For example, SPGA (Staggered Pin Grid A) rray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) ), or QFN (Quad Flat Non-leaded package), etc. The following implementation method can be used.

[0401] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0402] (Embodiment 8) In this embodiment, an example of an electronic device including the information processing device described in the above embodiment will be described. 20A to 20J show an electronic component having the information processing device. 4700 is included in each electronic device.

[0403] [mobile phone] The information terminal 5500 shown in FIG. 20A is a mobile phone (smartphone) which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511. As a power interface, a touch panel is provided on the display unit 5511, and buttons are attached to the housing. It is equipped in the 5510.

[0404] The information terminal 5500 is configured to use the information processing device described in the above embodiment. Temporary files generated when running applications (for example, when using a web browser) It is possible to keep the cache of

[0405] [Wearable devices] FIG. 20B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, and an operation key. 5904, band 5905, etc.

[0406] The wearable terminal is the same as the information terminal 5500 described above. By applying an information processing device, temporary files generated when an application is executed can be It is possible to hold the rule.

[0407] [Information terminal] Also, FIG. 20C shows a desktop information terminal 5300. The portable information terminal 5300 comprises a main body 5301 of the information terminal, a display 5302, and a keyboard. It has a code 5303.

[0408] The desktop information terminal 5300, like the information terminal 5500 described above, By applying the information processing device described in the embodiment, Temporary files can be stored.

[0409] In the above description, a smartphone and a desktop information terminal are used as information processing devices. As an example, as shown in FIG. 20A and FIG. 20C, a smartphone and a desk Information terminals other than top-down information terminals can be applied. Examples of information terminals other than top-level information terminals include PDAs (Personal Digital Assistants). IT Assistant), notebook information terminals, and workstations. can be.

[0410] [electric appliances] FIG. 20D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, and a freezer door 5803. etc.

[0411] By applying the information processing device described in the above embodiment to the electric refrigerator-freezer 5800, So, for example, we are using the electric refrigerator / freezer 5800 in IoT (Internet of Things) By using IoT, it can be used as an electric refrigerator / freezer5 800 is the information on the food stored in the electric refrigerator-freezer 5800, including the expiration date of the food. The information can be sent and received via the Internet to the information terminals mentioned above. In addition, when transmitting the information, the electric refrigerator-freezer 5800 stores the information in a temporary file. The file can be stored in the information processing device.

[0412] In this example, an electric refrigerator-freezer was described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water dispenser, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0413] [Game consoles] FIG. 20E also shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0414] Furthermore, FIG. 20F illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game console 7500 has a main body 7520 and a controller 7522. The main body 7520 can be connected to a controller 7522 by wireless or wired means. Although not shown in FIG. 20F, the controller 7522 can also be used to display the game screen. A display unit that displays the image, a touch panel that serves as an input interface other than buttons, and a stick The controller 7 can be equipped with a knob, a rotary knob, a sliding knob, etc. 522 is not limited to the shape shown in FIG. 20F, and may be changed to any shape depending on the genre of the game. The shape of 7522 may be changed in various ways. For example, FPS (First Person Shooting) In shooting games such as "Shooter," the trigger is a button and a gun is used. For example, in music games, controllers of various shapes can be used. Controllers shaped like musical instruments can be used. The robot does not use a controller, but instead is equipped with a camera, depth sensor, microphone, etc. In addition, it can be operated by the game player's gestures and / or voice. good.

[0415] In addition, the images of the above-mentioned game machines can be displayed on television sets, personal computer displays, etc. Display devices such as sprays, gaming displays, and head-mounted displays , can be output.

[0416] By applying the information processing device described in the above embodiment to the portable game machine 5200, This makes it possible to realize a portable game machine 5200 with low power consumption. This reduces heat generated by the circuit, preventing damage to the circuit itself, peripheral circuits, and And the impact on the module can be reduced.

[0417] Furthermore, the information processing device described in the above embodiment may be applied to the portable game machine 5200. This allows the game to store temporary files and other data necessary for calculations that occur while the game is running. This can be done.

[0418] In Figures 20E and 20F, a portable game machine is illustrated as an example of a game machine. The information processing device of one embodiment of the present invention is not limited to this. For example, home game consoles, entertainment facilities (game centers, amusement parks, etc.) arcade game machines installed in sports facilities, and batting practice pitches installed in sports facilities. Ball machines, etc.

[0419] [Moving object] The information processing device described in the above embodiment is a vehicle that is a moving object, and a driver's seat of the vehicle. It can be applied to the surrounding area.

[0420] FIG. 20G illustrates an automobile 5700 as an example of a moving object.

[0421] Around the driver's seat of the 5700 car are a speedometer, tachometer, mileage, and fuel It provides various information by displaying the meter, gear status, air conditioning settings, etc. The display panel is also equipped with a display device that shows this information around the driver's seat. may be provided.

[0422] In particular, the display device receives images from an imaging device (not shown) installed in the automobile 5700. By projecting images, it compensates for visibility obstructed by pillars and blind spots around the driver's seat. This can improve safety.

[0423] The information processing device described in the above embodiment can temporarily store information. For example, the computer may be used as an automatic driving system for an automobile 5700, Used to store necessary temporary information in systems that provide road guidance, risk prediction, etc. The display device can display temporary information such as road guidance and hazard prediction. In addition, the video of the driving recorder installed in the automobile 5700 may be recorded. It may be configured to hold the above.

[0424] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, Other examples include drones, airplanes, and rockets.

[0425] [camera] The information processing device described in the above embodiment can be applied to a camera.

[0426] FIG. 20H shows a digital camera 6240, which is an example of an imaging device. The barrel camera 6240 includes a housing 6241, a display unit 6242, an operation button 6243, a shutter The digital camera 6240 has a detachable lens 62 46 is attached. In this example, the digital camera 6240 is attached to the lens 6246. The lens 6246 and the housing 6241 can be removed and replaced. The digital camera 6240 may be integrated with the body 6241. A configuration may be adopted in which a camera, a viewfinder, etc. can be separately attached.

[0427] By applying the information processing device described in the above embodiment to the digital camera 6240, This makes it possible to realize a low-power digital camera 6240. This reduces heat generated by the circuit, preventing damage to the circuit itself and surrounding circuits caused by heat. This reduces the impact on the circuit and modules.

[0428] [Video camera] The information processing device described in the above embodiment can be applied to a video camera.

[0429] FIG. 20I shows a video camera 6300, which is an example of an imaging device. The camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, and operation keys 6304. 304, a lens 6305, a connection part 6306, etc. 6305 is provided in a first housing 6301, and a display unit 6303 is provided in a second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection part 6306. The angle between the first housing 6301 and the second housing 6302 is determined by the connection part 6306. The image on the display unit 6303 can be displayed on the first housing at the connection unit 6306. It may be configured to switch according to the angle between 6301 and the second housing 6302.

[0430] When recording video taken with the 6300 video camera, the encoding is performed according to the data recording format. By using the above-mentioned information processing device, 300 can store temporary files generated during encoding.

[0431] [ICD] The information processing device described in the above embodiment is applied to an implantable cardioverter defibrillator (ICD). It is possible.

[0432] 20J is a cross-sectional view showing an example of an ICD. The ICD main body 5400 includes a battery. 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, , a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0433] The ICD body 5400 is surgically placed in the body, and two wires are inserted into the subclavian vein. 5405 and the superior vena cava 5406, one wire tip is inserted into the right ventricle, and the other wire The tip of the catheter should be placed in the right atrium.

[0434] The ICD main body 5400 has a function as a pacemaker and detects when the heart rate falls outside the specified range. If the device comes off, the heart is paced. Pacing also improves the heart rate. If not present (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment is with electric shock.

[0435] The ICD main unit 5400 constantly monitors the heart rate to perform appropriate pacing and electrical shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 also stores the heart rate data acquired by the sensor. The electronic component 4700 can store the data, the number of times pacing therapy was performed, and the time. can.

[0436] In addition, the antenna 5404 can receive power, and the power is charged in the battery 5401. In addition, the ICD main body 5400 has multiple batteries, which increases safety. Specifically, some of the batteries in the ICD unit 5400 have become unusable. The remaining battery can still function as an auxiliary power source.

[0437] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals is also provided. For example, physiological signals such as pulse, respiratory rate, heart rate, and temperature may be monitored externally. A system may be configured to monitor cardiac activity as seen by the device.

[0438] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0439] (Embodiment 9) In this embodiment, a computer having the information processing device described in the above embodiment will be described. Reveal.

[0440] The computer 9600 shown in FIG. 21A is an example of a large-scale computer. A rack 9610 houses a plurality of rack-mounted computers 9620 .

[0441] The computer 9620 can have the configuration shown in the perspective view of FIG. 21B, for example. In B, the computer 9620 has a motherboard 9630, which is The slot 9631 has a plurality of slots 9631 and a plurality of connection terminals. In addition, the PC card 9621 has a connection terminal 9623, a connection terminal 9624 and a connection terminal 9625, which are connected to a motherboard 9630. do.

[0442] The PC card 9621 shown in FIG. 21C is a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 9621 has a board 9622. 22 is a connection terminal 9623, a connection terminal 9624, a connection terminal 9625, and a semiconductor device 9 626, a semiconductor device 9627, a semiconductor device 9628, and a connection terminal 9629. In addition, in FIG. 21C, a semiconductor device 9626, a semiconductor device 9627, and a semiconductor device Although semiconductor devices other than 9628 are shown, those semiconductor devices are described below. Please refer to the description of the semiconductor device 9626, the semiconductor device 9627, and the semiconductor device 9628. Just pour some drinks.

[0443] The connector 9629 can be inserted into the slot 9631 on the motherboard 9630. The connection terminal 9629 connects the PC card 9621 and the motherboard 9630. It functions as an interface for connecting. The standard for the connection terminal 9629 is, for example, For example, PCIe is one example.

[0444] The connection terminals 9623, 9624, and 9625 are, for example, the PC card 96 21 can be used as an interface for supplying power, inputting signals, etc. In addition, for example, the interface for outputting signals calculated by the PC card 9621 is The connection terminal 9623, the connection terminal 9624, the connection terminal 9 625, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Comput er System Interface). Also, connection terminal 9623 When outputting video signals from the connection terminals 9624 and 9625, An example is HDMI (registered trademark).

[0445] The semiconductor device 9626 has a terminal (not shown) for inputting and outputting signals. By inserting the terminal into a socket (not shown) provided on the board 9622, The body device 9626 and the board 9622 can be electrically connected.

[0446] The semiconductor device 9627 has a plurality of terminals, and the terminals are provided on the board 9622. For example, by performing reflow soldering on the wiring, the semiconductor device 9627 and The board 9622 can be electrically connected. , FPGA (Field Programmable Gate Array), GPU The semiconductor device 9627 may include, for example, an electronic component 4730. You can be there.

[0447] The semiconductor device 9628 has a plurality of terminals, and the terminals are provided on the board 9622. For example, by performing reflow soldering on the wiring, the semiconductor device 9628 and The board 9622 can be electrically connected. Examples of the semiconductor device 9628 include an electronic Part 4700 can be used.

[0448] The computer 9600 can also function as a parallel computer. By using it, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence. can.

[0449] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, The device can be made smaller, faster, or consumes less power. The semiconductor device has low power consumption, so heat generation from the circuit can be reduced. This reduces the adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using a semiconductor device according to one embodiment of the present invention, stable operation can be achieved even in a high-temperature environment. Therefore, the reliability of the electronic device can be improved.

[0450] Next, an example of the configuration of a computer system applicable to the computer 9600 will be described. FIG. 22 is a diagram illustrating an example of the configuration of a computer system 1000. The system 1000 is comprised of software and hardware. e) and the hardware included in the computer system are referred to as information processing equipment. This is sometimes called ``oki''.

[0451] The software that constitutes the computer system 1000 includes device drivers. Including operating systems, middleware, various development environments, and AI-related applications AI Application, an application unrelated to AI There are also other programs available.

[0452] Device drivers include external devices such as auxiliary storage devices, display devices, and printers. This includes application programs for controlling the

[0453] The hardware constituting the computer system 1000 includes a first processor, a second processor, The second processing unit includes a first storage device. It has a location.

[0454] The first processing unit is, for example, a central processing unit such as a Noff OS CPU. It is recommended to use the Noff OS CPU. For example, a non-volatile memory is provided, and when no operation is required, the necessary information is stored in the storage means. The first processor has a function to stop the power supply to the central processing unit. By using an off-OS CPU, the power consumption of the computer system 1000 is reduced. can.

[0455] The second processing unit may be, for example, a GPU or an FPGA. It is preferable to use an AI OS Accelerator as the second processing unit. The AI ​​OS Accelerator is constructed using OS transistors and is a multiply-accumulate It has calculation means such as calculation circuits. AI OS Accelerator is a general GPU It consumes less power than the AI ​​OS Accelerator as a second processing unit. By using "or", the power consumption of the computer system 1000 can be reduced.

[0456] The first memory device and the second memory device preferably include the semiconductor device according to one embodiment of the present invention. The semiconductor device of one embodiment of the present invention is preferably a 3D OS NAND memory device, for example. In this case, the 3D OS NAND storage device may have a cache, main It can function as memory and storage. It also supports 3D OS NAND By using this storage device, it becomes easier to realize a non-von Neumann type computer system.

[0457] 3D OS NAND type memory devices are 3D NAND type memory devices that use Si transistors. It consumes less power than a storage device. 3D OS NAND type storage device is used as a storage device. By using this, the power consumption of the computer system 1000 can be reduced. OS NAND type storage devices function as universal memory, allowing computers to The number of parts required to configure the data system 1000 can be reduced.

[0458] The semiconductor device that constitutes the hardware is configured with a semiconductor device including an OS transistor. This allows for a monolithic hardware system that includes a central processing unit, processing units, and storage devices. Monolithic hardware makes it easier to make the device smaller, lighter, and thinner. This not only simplifies the design but also makes it easier to further reduce power consumption.

[0459] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0460] (Embodiment 10) In this embodiment, a computer system different from that described in the ninth embodiment is used. This section describes the computer system.

[0461] First, a conventional computer system will be described with reference to FIG. 23. The right side shows an example of the configuration of a computer system 2000, and the left side shows the computer nodes 2 shows an example of a storage hierarchy of storage nodes 2100 and 2200.

[0462] The computer system 2000 includes a plurality of computer nodes 2100 and a storage Node 2200.

[0463] The computer system 2000 includes, as an example, a plurality of computer nodes 2100. The storage node 2200 and the network 2900 communicate with each other. The devices are configured to be able to communicate electrically with each other.

[0464] The computer node 2100 may include, for example, a processor (e.g., a CPU, a GPU, a NPU, a Off OS CPU etc. 2110, main memory 2120, storage memory 2 130. The storage node 2200 also includes, for example, a processor 22 10, a main memory 2220, and a storage memory 2230.

[0465] In addition, the processor 2110 included in the computer node 2100 is, for example, , a core 2111, a register 2112, and a cache memory 2113. The processor 2210 included in the storage node 2200 may be, for example, a core 2211, a register 2212, and a cache memory 2213.

[0466] The register 2112 and / or the register 2212 may be, for example, a flip-flop. Also, the cache memory 2113 and / or the cache memory As the memory 2213, for example, an SRAM can be applied.

[0467] The main memory 2120 included in the computer node 2100 may be, for example, For example, DRAM or the like can be applied. The storage memory 2130 may be, for example, a NAND type storage device, a hard disk drive, or the like. Hard disk drives (HDDs) and the like can be applied.

[0468] In the memory hierarchy shown in FIG. 23, the memory area included in the core 2111 is at the top level. Next, from the top, there are flip-flops, SRAM, gap area, DRAM, S CM (storage class memory) (gap area), NAND type storage device (hard disk The drive is located in order.

[0469] As described in the fourth embodiment, in the memory hierarchy, the higher the storage device is located, the faster the operating speed. The lower the layer of storage, the greater the storage capacity and recording density required. In particular, the storage devices at the lowest level are required to retain data for a long period of time. .

[0470] Next, a computer system according to one embodiment of the present invention will be described with reference to FIG. 24A. 24A shows an example of the configuration of a computer system 2000A on the right side, similar to FIG. On the left side, the computer node 2500A (computer node 2500B) is displayed. 1 shows an example of a memory hierarchy.

[0471] The computer system 2000A of FIG. 24A is, by way of example, a computer system including multiple computer nodes. 2500A and an overall management host 2400.

[0472] The computer system 2000A includes, as an example, a plurality of computer nodes 2500 A can electrically communicate with each other among the nodes via the overall management host 2400. Therefore, the overall management host 2400 is configured to be able to manage multiple computers. The function of sending and receiving signals including data and commands to and from the computer node 2500A. The computer system 2000A includes an overall management host 2400 and a plurality of computers. The network may be referred to as a network having computer nodes 2500A and 2500B.

[0473] The computer node 2500A is, for example, the monolithic computer shown in FIG. 15 described in the fourth embodiment. The computer node 2500A can be a block IC. By applying monolithic ICs, the components contained in the monolithic IC can be The wiring that electrically connects the devices is shorter, which reduces the power consumption required to transmit signals. can.

[0474] As an example, computer node 2500A may be configured to The computer node 2500B can be configured as a block diagram. 2600 and a storage device 2700.

[0475] The processor 2600 may be, for example, a computer node 2100 shown in FIG. Any applicable processor can be used as the included processor 2110.

[0476] The storage device 2700 is the main memory included in the computer node 2100 of FIG. 2120 and storage memory 2130. Specifically, the storage device 2700 may be, for example, the information processing device described in the first embodiment. It can be set to 50.

[0477] As explained in the first embodiment, the information processing device 50 stores a plurality of NAND strings. The information processing device 50 has a memory circuit including In other words, the information processing device 50 can be treated as a storage device 2. 700, the main memory 2 in the computer node 2100 in FIG. The functions of 120 can be operated by the storage device 2700. The computer node 2500B differs from the computer node 2100 of FIG. The main memory 2120 corresponding to the above may not be provided.

[0478] The storage device 2700 may be, for example, a 3D OS NAND type storage device. In addition, the 3D OS NAND type storage device can, for example, include a cache unit 271 The cache unit 2711 includes, for example, a memory unit 2712. These correspond to the strings ST2 and ST3 described in the example of the operation method of the first mode. The memory unit 2712 corresponds to, for example, the string ST1 described in the example of the operation method of the first embodiment. do.

[0479] The storage device 2700 is, for example, a 3D OS NAND type storage device. In this case, the memory hierarchy in computer node 2500B is as shown on the left side of FIG. 24A. The storage hierarchy in the computer node 2500B is the same as that of the computer node in FIG. In the memory hierarchy of the 2100, the hierarchy from NAND type storage / HDD to DRAM The layer is replaced with a 3D OS NAND type memory device. For convenience, the memory tiers are referred to as the cache unit 2711 and the memory unit 2712. Although the diagram shows "3D OS NAND memory," these memory hierarchies are in a single hierarchy. It may also be a summary.

[0480] Also, the computer node 2500A (computer node 2500B) includes The circuits, such as processors and memory devices, preferably have OS transistors. The OS transistor has a higher conductivity than a transistor having silicon in the channel formation region. Therefore, the transistor characteristics and field effect mobility are less likely to change with temperature changes. The circuit included in computer node 2500A (computer node 2500B) By using OS transistors, the computer node 2500A (computer The node 2500B can be made into a device that is resistant to heat generated by driving.

[0481] Furthermore, the computer system according to one embodiment of the present invention is not limited to the configuration shown in FIG. 24A. A computer system according to an embodiment of the present invention may be configured as shown in FIG. The composition may be changed.

[0482] For example, computer node 2500A (computer node 2500B) in FIG. 24A In this case, the flip-flops in the processor 2600 (CPU) are M(Nonvolatile Oxide Semiconductor Random It may be replaced with IEEE 802.11a (registered trademark) or IEEE 802.11b (registered trademark). In the computer system 2000B, flip-flops were replaced with NOSRAM. However, the SRAM may be replaced with NOSRAM, or the SRAM The flip-flops may be replaced with NOSRAM.

[0483] NOSRAM is a memory device having memory cells, for example, as shown in FIGS. 25A to 25D. The memory cell is a gain cell type memory cell with two transistors and one capacitor. It is a memory element that can retain data for a long period of time.

[0484] The memory cell 1440 shown in FIG. 25A includes a transistor M2, a transistor M3, and a capacitor. The transistor M2 has a front gate (sometimes simply called the gate). ) and a back gate.

[0485] Furthermore, each of the transistors M2 and M3 is an OS transistor. It is preferable that the metal oxide contained in the channel formation region of the OS transistor is This is explained in the sixth embodiment.

[0486] The first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C2. A second terminal of the transistor M2 is electrically connected to the wiring WBLL, and a gate of the transistor M2 is The back gate of the transistor M2 is electrically connected to the wiring WL. The second terminal of the capacitor C2 is electrically connected to the wiring CL. The first terminal of the transistor M3 is electrically connected to the wiring RBLL, and the second terminal of the transistor M3 is electrically connected to the wiring RBLL. The terminal is electrically connected to the line SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor C2. is electrically connected to the

[0487] The wiring WBLL functions as a write bit line, and the wiring RBLL functions as a read bit line. The wiring WL functions as a word line. The wiring CL functions as a second terminal of the capacitor C2. For example, during data retention, It is preferable that a low level potential (sometimes called a reference potential) is applied to the wiring CL. Preferably, when writing data and when reading data, the wiring CL is Preferably, a voltage potential is applied to the electrode.

[0488] The wiring BGLL is used as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGLL, the threshold voltage of the transistor M2 is The voltage can be increased or decreased by a small amount.

[0489] As a method for writing data, first, a high-level potential is applied to the wiring SL. A high-level potential is applied to the wiring WL, the transistor M2 is turned on, and the wiring WBLL and the capacitor This is done by bringing the first terminal of the transistor C1 into a conductive state. When the sensor M2 is in the ON state, a potential corresponding to the information to be recorded is applied to the wiring WBLL. As a result, the potential is written to the first terminal of the capacitor C2 and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WL to turn off the transistor M2. This maintains the potential of the first terminal of the capacitor C2 and the potential of the gate of the transistor M3. do.

[0490] As a method for reading data, first, a high level potential is applied to the line SL. The current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 is determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential of the wiring RBLL connected to the first terminal of the transistor M3 is read out. By doing so, the voltage held at the first terminal of the capacitor C2 (or the gate of the transistor M3) That is, the potential at the first terminal of the capacitor C2 (or the potential at the first terminal of the transistor M3) can be read out. The information written in this memory cell is read from the potential held at the gate. It is possible.

[0491] Also, the memory cells applicable to the NOSRAM of FIG. 24B are limited to memory cells 1440. Depending on the situation, the circuit configuration can be changed.

[0492] For example, the memory cell included in the semiconductor device described in the previous embodiment may be configured as shown in FIG. The memory cell 1450 may have such a configuration. The gate is electrically connected to the wiring WL, not the wiring BGLL. By using this configuration, the back gate of the transistor M2 is connected to the gate of the transistor M2. Therefore, when the transistor M2 is in the ON state, This allows the current flowing through transistor M2 to increase.

[0493] Furthermore, for example, the memory cells included in the semiconductor device described in the above embodiment may be formed by back gate The memory cell may be configured with a transistor M2 that does not have a gate. An example of the circuit configuration is shown in FIG. 25C. The memory cell 1460 is a transistor of the memory cell 1440. The semiconductor device has a configuration in which a back gate is not provided from the memory cell M2. By applying resistor 1460, transistor M2 does not have a back gate. Therefore, the manufacturing process of the semiconductor device is shorter than that of the memory cell 1440 and the memory cell 1450. It is possible.

[0494] Also, for example, the wiring WBLL and the wiring RBLL are combined into one wiring BL. An example of the circuit configuration of the memory cell is shown in FIG. 25D. The wiring WBLL and wiring RBLL of the memory cell 1440 are connected to one wiring BL. The second terminal of the transistor M2 and the first terminal of the transistor M3 are electrically connected to the wiring BL. That is, the memory cell 1470 has a write bit line and a read bit line. The BL line and the BL line are configured to operate as a single wiring BL.

[0495] The memory cells shown in FIGS. 25A to 25D are arranged in a matrix. For example, memory cell 144 in FIG. 25A can function as a memory device. When 0s are arranged in a matrix, the memory device shown in FIG. 25E can be configured.

[0496] The memory device shown in FIG. 25E includes a cell array CA, a circuit WBD, a circuit CD, and a circuit WD. and a circuit RBD.

[0497] The cell array CA is, for example, as described above, a plurality of memory cells arranged in a matrix. It has 1440.

[0498] The circuit WBD is electrically connected to the wiring WBLL. As a write circuit for writing data to memory cells included in the array CA It works.

[0499] The circuit WD is electrically connected to the wiring WL. The circuit WD is, for example, a circuit for writing data. It functions as a selection circuit for selecting a memory cell to be inserted.

[0500] The circuit RBD is electrically connected to the wiring RBLL and the wiring SL. For example, the read / write circuit 100 may be used to read data from memory cells included in the cell array CA. It functions as a readout circuit.

[0501] The circuit CD is electrically connected to the wiring CL. For example, the circuit CD reads data. It functions as a selection circuit for selecting the memory cell to be output.

[0502] The circuit configuration of the storage device shown in FIG. 25E is an example, and the circuit configuration may be changed as appropriate. It is possible.

[0503] Furthermore, as a computer system according to one aspect of the present invention, the computer shown in FIG. The configuration of the data system 2000 may be modified.

[0504] For example, the computer system 2000C shown in FIG. 26 is the same as the computer system 2000C shown in FIG. In the system 2000, the processor 2110 (processor 2210) and the storage memory 2130 (storage memory 2230) is connected to the main memory 21 20 (main memory 2220).

[0505] In particular, the storage memory 2130 (storage memory 2230) is The storage device 2700 described in the computer system 2000A, that is, the storage device 2700 in the first embodiment The information processing device 50 described above is preferable.

[0506] The computer node 2100 (storage node 2200) is configured as shown in FIG. By this, the main memory 2120 (main memory 2220) equivalent to DRAM is Without this, the processor 2110 (processor 2210) and the storage device 2700 (storage device The memory 2130 or the storage memory 2230 can be electrically connected to the main The computer system 2000C is configured without the main memory 2120 (main memory 2220). It can be made to work.

[0507] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do. [Explanation of symbols]

[0508] ST1, ST2, ST3: strings, L[1], L[2], L[n]: memory cells, M [1], M[2], M[n]: memory cells, N[1], N[2], N[n]: memory cells ,SL1: wiring,SL2: wiring,SL3: wiring,BL1: wiring,BL2: wiring,BL3: Wiring, ISG: signal, OSG: signal, DT: data, STP1: step, STP2: step STP1:Step, STP2:Step, STP3:Step, STP4:Step, STP5:Step, STP6:Step STP, STP7: Step, STP8: Step, MC[1]: Memory cell, MC[2 ]: memory cell, MC[n]: memory cell, MC[1,1]: memory cell, MC[j,1 ]: memory cell, MC[n,1]: memory cell, MC[1,i]: memory cell, MC[j ,i]: memory cell, MC[n,i]: memory cell, MC[1,m]: memory cell, MC [j,m]: memory cell, MC[n,m]: memory cell, N1: node, N2: node, RWL[1]: Wiring, RWL[2]: Wiring, RWL[j]: Wiring, RWL[n]: Wiring, WWL[1]: Wiring, WWL[2]: Wiring, WWL[j]: Wiring, WWL[n]: Wiring, WBL: Wiring, WBL[1]: Wiring, WBL[i]: Wiring, WBL[m]: Wiring, RBL :Wiring, RBL[1]:Wiring, RBL[i]:Wiring, RBL[m]:Wiring, BGL:Wiring ,BGL[1]: Wiring, BGL[i]: Wiring, BGL[m]: Wiring, WTr: Transistor RTr: transistor, CS: capacitor, BLK_1: block, BLK_h: block ,BLK_k: Block, BLK_2: Block, BLK_3: Block, MC[1]_ 1: memory cell, MC[j]_1: memory cell, MC[n]_1: memory cell, MC[1 ]_h: memory cell, MC[j]_h: memory cell, MC[n]_h: memory cell, MC [1]_k: memory cell, MC[j]_k: memory cell, MC[n]_k: memory cell, MC[2]_1: memory cell, MC[3]_1: memory cell, MC[1]_2: memory cell MC[2]_2: memory cell, MC[3]_2: memory cell, MC[1]_3: memory Resell, MC[2]_3: Memory cell, MC[3]_3: Memory cell, RWL[1]_1 :Wiring, RWL[j]_1:Wiring, RWL[n]_1:Wiring, RWL[1]_h:Wiring, RWL[j]_h: wiring, RWL[n]_h: wiring, RWL[1]_k: wiring, RWL[ j]_k: wiring, RWL[n]_k: wiring, RWL[2]_1: wiring, RWL[3]_1 : Wiring, RWL[1]_2: Wiring, RWL[2]_2: Wiring, RWL[3]_2: Wiring, RWL[1]_3: Wiring, RWL[2]_3: Wiring, RWL[3]_3: Wiring, WWL[ 1]_1: Wiring, WWL[j]_1: Wiring, WWL[n]_1: Wiring, WWL[1]_h :Wiring, WWL[j]_h:Wiring, WWL[n]_h:Wiring, WWL[1]_k:Wiring, WWL[j]_k: Wiring, WWL[n]_k: Wiring, WWL[2]_1: Wiring, WWL[ 3]_1: Wiring, WWL[1]_2: Wiring, WWL[2]_2: Wiring, WWL[3]_2 : wiring, WWL[1]_3: wiring, WWL[2]_3: wiring, WWL[3]_3: wiring, RBL_1: Wiring, RBL_h: Wiring, RBL_k: Wiring, RBL_2: Wiring, RBL_ 3: Wiring, WBL_1: Wiring, WBL_h: Wiring, WBL_k: Wiring, WBL_2: Wiring ,WBL_3: Wiring, LN1: Wiring, LN2: Wiring, BTr_1: Transistor, BTr _h: transistor, BTr_k: transistor, BTr_2: transistor, BTr_ 3: Transistor, STr_1: Transistor, STr_h: Transistor, STr_k :Transistor, STr_2:Transistor, STr_3:Transistor, BD:Mother Board, BSH: Bus wiring, SBT: Semiconductor substrate, LGC: Circuit layer, STR: Memory layer, O SC: Circuit layer, ME1: Conductor, ME2: Conductor, ME3: Conductor, LT1[1]: Wrap Latch circuit, LT1[2]: Latch circuit, LT1[3]: Latch circuit, LT1[z]: Latch circuit, LT2[1]: latch circuit, LT2[2]: latch circuit, LT2[3]: latch circuit Path, LT2[z]: Latch circuit, DA: Data, CLK: Wiring, ENL: Wiring, STG[ 1]: string, STG[2]: string, STG[3]: string, STG[z ]: String, STG: String, M2: Transistor, M3: Transistor, C2 :Capacitance, WBLL:Wiring, RBLL:Wiring, SL:Wiring, BL:Wiring, WL:Wiring, CL : wiring, BGLL: wiring, CA: cell array, WBD: circuit, WD: circuit, CD: circuit, RBD: circuit, 10: arithmetic processing unit, 11: register, 20: SRAM, 30: main memory memory, 40: storage, 50: information processing device, 60: interface, 70: calculation processing processing device, 80: storage device, 90: wiring, 100: storage unit, 111: insulator, 112: insulation body, 113: insulator, 114: insulator, 115: insulator, 116: insulator, 117: insulator body, 121: insulator, 122: insulator, 131: insulator, 132: insulator, 133: insulator body, 141: semiconductor, 142: semiconductor, 143: semiconductor, 151: conductor, 152: conductor body, 153: conductor, 154: conductor, 155: conductor, 156: conductor, 200: control Part, 211: insulator, 212: insulator, 213: insulator, 214: insulator, 215: insulator 216: insulator, 221: conductor, 222: conductor, 223: conductor, 231: semiconductor body, 232: semiconductor, 240: insulator, 241: insulator, 242: insulator, 243: insulation 250: conductor, 251: conductor, 252: conductor, 253: conductor, 300: transistor transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region Resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 700: Transistor, 800: Transistor, 900: Tra Transistor, 1000: Computer system, 1196: Memory unit, 1197: Controller 1198: bus interface, 1440: memory cell, 1450: memory cell, 1460: Memory cell, 1470: Memory cell, 2000: Computer system, 20 00A: Computer System, 2000B: Computer System, 2000C: Computer computer system, 2100: computer node, 2110: processor, 2111: Core, 2112: Register, 2113: Cache memory, 2120: Main memory, 2 130: Storage memory, 2200: Storage node, 2210: Processor, 22 11: Core, 2212: Register, 2213: Cache memory, 2220: Main memory 2230: Storage memory, 2400: Central management host, 2500A: Computer 2500B: computer node, 2600: processor, 2700: memory 2711: cache unit, 2712: storage unit, 2900: network, 4700: Electronic components, 4702: Printed circuit boards, 4704: Mounting boards, 4710: Semiconductor devices, 47 14: Wire, 4730: Electronic components, 4731: Interposer, 4732: Package Substrate, 4733: electrode, 4735: semiconductor device, 4800: semiconductor wafer, 4800a: Chip, 4801: wafer, 4801a: wafer, 4802: circuit part, 4803: space Sing, 4803a: Spacing, 5200: Portable game console, 5201: Cabinet, 520 2: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display, 5303: Keyboard, 5400: ICD body, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Clavicle Inferior vena cava, 5406: superior vena cava, 5500: information terminal, 5510: housing, 5511: display unit , 5700: Automobiles, 5800: Electric refrigerator-freezers, 5801: Housings, 5802: For refrigerator compartments Door, 5803: Freezer door, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation button, 5904: Control, 5905: Band, 6240: Digital camera 6241: Housing, 6242: Display, 6243: Operation buttons, 6244: Shutter Button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: display, 6304: operation keys, 6305: lens, 6306: connection Unit, 7520: Main unit, 7522: Controller, 9600: Computer, 9610: Rack, 9620: Calculator, 9621: PC card, 9622: Board, 9623: Connection terminal, 9 624: Connection terminal, 9625: Connection terminal, 9626: Semiconductor device, 9627: Semiconductor device 9628: semiconductor device, 9629: connection terminal, 9630: motherboard, 9631: Lot

Claims

[Claim 1] a processor, a memory device, and a plurality of interconnects; the storage device has a plurality of strings; A method for driving an information processing device, wherein one of the plurality of strings is electrically connected to the arithmetic processing device via one of the plurality of wirings, The first data input by serial transmission is Converting the data into a plurality of second data; Distributing the plurality of second data for each of the plurality of wirings; simultaneously supplying the plurality of second data to the plurality of strings in response to a trigger signal; The string includes a plurality of memory cells; the memory cell includes an oxide semiconductor; The method for operating an information processing device, wherein the storage device is a NAND type storage device.

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