Method for manufacturing printed wiring board, printed wiring board, method for manufacturing seed layer, seed layer, and semiconductor package

Abstract

To provide a method of manufacturing a printed wiring board which is excellent in formation accuracy even with a small L / S, can form a circuit pattern having high adhesion, and is excellent in working environment.SOLUTION: A method for producing a printed wiring board, comprising the following steps 1 to 7 in this order: Step 1: A step of attaching a first catalyst to a surface of an insulating material. Step 2: a step of adhering a second catalyst containing at least nickel to the surface of the insulating material by bringing the insulating material into contact with an electroless nickel plating solution containing hypophosphite as a reducing agent. Step 3: a step of forming a seed layer by contact with an electroless copper plating solution containing hypophosphite as a reducing agent. Step 4: a step of forming a resist pattern on the surface of the seed layer. Step 5: a step of forming a copper layer by electrolytic copper plating in a region exposed from the resist pattern. Step 6: Step of removing the resist pattern. Step 7: a step of removing the exposed seed layer and the first catalyst and the second catalyst between the seed layer and the insulating material to obtain a circuit pattern.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a method for manufacturing a printed wiring board, a printed wiring board, a method for manufacturing a seed layer, a seed layer, and a semiconductor package. [Background technology]

[0002] The information society has seen remarkable development in recent years, with consumer devices such as personal computers and mobile phones becoming smaller, lighter, and more powerful and functional. Meanwhile, industrial devices, including network-related equipment such as wireless base stations, optical communication devices, servers, and routers, are demanding improved functionality regardless of their size. Furthermore, as the volume of information transmitted increases, the signals they handle tend to become higher in frequency, spurring the development of high-speed processing and transmission technologies. For example, along with the increasing speed and functionality of large-scale integration (LSI) devices such as central processing units (CPUs), digital signal processing (DSPs), and various types of memory, new high-density packaging technologies such as system-on-chip (SoC) and system-in-package (SiP) are being actively developed. Therefore, to accommodate higher frequencies, higher-density wiring, and higher functionality, build-up multilayer wiring boards with fine wiring widths and spaces (L / S) have begun to be used for semiconductor chip mounting substrates and motherboards. Around 2012, there was a demand for fine wiring with L / S of approximately 15 μm / 15 μm, but in recent years there has been a demand for fine wiring with L / S of approximately 8 μm / 8 μm, and it is thought that in the near future there will be a demand for fine wiring with L / S of 5 μm / 5 μm.

[0003] The semi-additive process (SAP, hereinafter also referred to as the "SAP process") is generally considered to be useful for forming fine wiring. In the semi-additive process, first, an electroless copper plating layer called a seed layer is provided on an insulating resin, and then a dry film resist layer is provided on the copper plating layer. A resist pattern is then formed by exposure through a photomask (photolithography) or by direct drawing and exposure with laser light. Next, after performing plasma treatment as needed, a circuit pattern is formed by electrolytic copper plating in areas where there is no resist pattern, the resist pattern is removed, and finally, the seed layer in unnecessary areas is etched and removed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-208471 Summary of the Invention [Problem to be solved by the invention]

[0005] When forming fine wiring with an L / S ratio of less than 10 μm / 10 μm, the resist pattern tends to peel off from the seed layer. Therefore, it is necessary to increase the surface roughness of the insulating resin to a certain extent to impart roughness to the seed layer, thereby increasing the adhesion between the seed layer and the resist pattern through the anchor effect.

[0006] In conventional SAP processes, a seed layer with a certain thickness, for example, 0.5 μm or more, must be formed to fully function as a seed layer. However, a thick seed layer increases the amount of etching required to remove unnecessary seed layer, resulting in a problem of increased circuit pattern miniaturization. Another possible method is to reverse-calculate the circuit pattern miniaturization and design the circuit pattern width before etching to be thicker. However, this requires reducing the resist pattern width, which can lead to problems such as poor resist pattern adhesion. This problem becomes more pronounced as the L / S becomes smaller. Furthermore, as the L / S becomes smaller, it becomes more difficult to completely remove the seed layer, resulting in problems such as a loss of insulation reliability due to seed layer residue. On the other hand, simply reducing the thickness of the seed layer makes it difficult to form a uniform seed layer, as pinholes, voids, etc. may occur in the seed layer. Furthermore, the increase in etching amount when thickening the seed layer and the occurrence of pinholes when thinning the seed layer can cause undercutting, peeling, etc. of the circuit pattern, leading to a decrease in the adhesion of the circuit pattern. In particular, the seed layer formed by electroless copper plating using conventional methods is subject to accelerated oxidation by palladium, which is an electroless copper plating catalyst present in the vicinity, making the problems of undercutting and peeling of the circuit pattern even more pronounced. Furthermore, after etching the seed layer to form a circuit pattern, CZ treatment is generally performed as a pretreatment for forming an insulating resin such as a solder resist or build-up material on the circuit pattern. CZ treatment is a roughening treatment performed by etching, for example, to a depth of about 1.0 to 1.5 μm. This treatment further promotes undercutting and peeling of the circuit pattern. Furthermore, in the conventional SAP method, the electroless copper plating solution used to form the seed layer contains highly toxic compounds such as formalin and cyanide compounds. From the viewpoint of improving the working environment and safety, a method that does not use these compounds is desired.

[0007] Therefore, an object of this embodiment is to provide a method for manufacturing a printed wiring board that can form a circuit pattern with excellent formation accuracy and high adhesion even with small L / S and that is excellent in the working environment, a printed wiring board obtained by this manufacturing method, and a semiconductor package having a semiconductor element mounted on the printed wiring board.Another object of this embodiment is to provide a method for manufacturing a thinned seed layer that can form a circuit pattern with excellent formation accuracy and high adhesion even with small L / S, and a seed layer obtained by this manufacturing method. [Means for solving the problem]

[0008] As a result of extensive research into solving the above problems, the present inventors have found that the above problems can be solved by the present embodiment described below. That is, this embodiment relates to the following [1] to

[14] . [1] A method for producing a printed wiring board, comprising the following steps 1 to 7 in this order: Step 1: Applying a first catalyst to the surface of an insulating material Step 2: A step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached. Step 3: A step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached. Step 4: forming a resist pattern on the surface of the seed layer to form a circuit pattern. Step 5: forming a copper layer by electrolytic copper plating on the surface of the seed layer in the area exposed by the resist pattern. Step 6: Removing the resist pattern Step 7: A step of removing the seed layer exposed by removing the resist pattern, as well as the first catalyst and the second catalyst between the seed layer and the insulating material, to obtain a circuit pattern. [2] The method for producing a printed wiring board according to [1] above, wherein the resist pattern in step 4 is formed by a method including the following steps 4-1 and 4-2 in this order: Step 4-1: Step of laminating a photosensitive resin film of a supported photosensitive resin film on the seed layer to form a resist layer Step 4-2: a step of exposing at least a part of the resist layer through the support of the supported photosensitive resin film by a direct writing exposure method, and then developing the exposed resist layer. [3] The method for producing a printed wiring board according to the above [1] or [2], wherein the pH of the electroless nickel plating solution is 7 to 10. [4] The method for producing a printed wiring board according to any one of the above [1] to [3], wherein the phosphorus content in the second catalyst is 6 mass % or less. [5] The method for producing a printed wiring board according to any one of the above [1] to [4], wherein the seed layer has a thickness of 0.4 μm or less. [6] The method for producing a printed wiring board according to any one of the above [1] to [5], wherein the insulating material is an insulating material layer formed on a support substrate. [7] A printed wiring board manufactured by the method for manufacturing a printed wiring board according to any one of [1] to [6] above. [8] A semiconductor package comprising the printed wiring board according to [7] above and a semiconductor element mounted thereon. [9] A method for producing a seed layer, comprising the following steps 1 to 3 in this order: Step 1: Applying a first catalyst to the surface of an insulating material Step 2: A step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached. Step 3: A step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached.

[10] The method for producing a seed layer according to [9] above, wherein the pH of the electroless nickel plating solution is 7 to 10.

[11] The method for producing a seed layer according to the above [9] or

[10] , wherein the phosphorus content in the second catalyst is 6 mass % or less.

[12] The method for producing a seed layer according to any one of the above [9] to

[11] , wherein the seed layer has a thickness of 0.4 μm or less.

[13] The method for producing a seed layer according to any one of the above [9] to

[12] , wherein the insulating material is an insulating material layer formed on a support substrate.

[14] A seed layer manufactured by the method for manufacturing a seed layer according to any one of [9] to

[13] above. [Effects of the Invention]

[0009] According to this embodiment, it is possible to provide a method for manufacturing a printed wiring board that is excellent in forming accuracy and can form a circuit pattern with high adhesion even with small L / S, and that is excellent in working environment, a printed wiring board obtained by this manufacturing method, and a semiconductor package having a semiconductor element mounted on the printed wiring board. Furthermore, according to this embodiment, it is possible to provide a method for manufacturing a thinned seed layer that is excellent in forming accuracy and can form a circuit pattern with high adhesion even with small L / S, and a seed layer obtained by this manufacturing method. [Brief explanation of the drawings]

[0010] [Figure 1] 2A to 2C are cross-sectional views illustrating steps of a manufacturing method according to the present embodiment. [Figure 2] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 3] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 4] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 5] 1 is a scanning ion microscope (SIM) photograph of a cross section of the seed layer formed in the example and comparative example, which was processed with a focused ion beam (FIB) and photographed at an angle of 45 degrees. [Figure 6] FIG. 1 is a schematic diagram for explaining a method for evaluating throwing power. [Figure 7] 1 is a scanning ion microscope (SIM) photograph of a cross section of the seed layer formed in the example and comparative example, which was processed with a focused ion beam (FIB) and photographed at an angle of 45 degrees. [Figure 8] 1 is a scanning ion microscope (SIM) photograph of a cross section of the circuit patterns formed in the examples and comparative examples, which were processed with a focused ion beam (FIB) and photographed at an angle of 45 degrees. [Figure 9] 1 is a scanning ion microscope (SIM) photograph of a cross section of a circuit pattern formed in an example and a comparative example after a HAST test, which was processed with a focused ion beam (FIB) and photographed at an angle of 45 degrees. DETAILED DESCRIPTION OF THE INVENTION

[0011] In this specification, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In the numerical ranges described herein, the upper or lower limit of the numerical range may be replaced with the values ​​shown in the examples. In addition, the lower and upper limit of a numerical range may be arbitrarily combined with the lower and upper limit of another numerical range. Furthermore, unless otherwise specified, each of the components and materials exemplified in this specification may be used alone or in combination of two or more. The mechanism of action described in this specification is speculation and does not limit the mechanism by which the resin composition according to this embodiment exhibits its effects. Any combination of the features described in this specification is also included in this embodiment.

[0012] In this specification, the term "layer" includes layers that are partially missing and layers in which vias or patterns are formed.

[0013] [Printed wiring board manufacturing method and printed wiring board] The method for producing a printed wiring board of this embodiment is a method for producing a printed wiring board that includes the following steps 1 to 7 in this order. Step 1: Applying a first catalyst to the surface of an insulating material Step 2: A step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached. Step 3: A step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached. Step 4: forming a resist pattern on the surface of the seed layer to form a circuit pattern. Step 5: forming a copper layer by electrolytic copper plating on the surface of the seed layer in the area exposed by the resist pattern. Step 6: Removing the resist pattern Step 7: A step of removing the seed layer exposed by removing the resist pattern, as well as the first catalyst and the second catalyst between the seed layer and the insulating material, to obtain a circuit pattern. The printed wiring board of this embodiment is a printed wiring board manufactured by the method for manufacturing a printed wiring board of this embodiment. In this specification, the term "printed wiring board" is a concept that also includes "multilayer printed wiring boards."

[0014] Each step of this embodiment will be described in detail below with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicated explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios in the drawings are not limited to those shown in the drawings.

[0015] <Step 1: Attachment of the first catalyst> Step 1 is a step of attaching a first catalyst to the surface of an insulating material. The insulating material used in step 1 is not particularly limited, and any known insulating material used in printed wiring boards can be used. The insulating material is preferably a resin or a composition containing at least a resin, and is preferably a cured product of a curable resin composition. When the insulating material is a curable material, the first catalyst is preferably adhered to the insulating material in a cured state. Examples of the resin include a thermosetting resin, a thermoplastic resin, or a material containing a mixture of these resins. Examples of thermosetting resins include epoxy resins, phenolic resins, urea resins, melamine resins, alkyd resins, cyanate compounds, bismaleimide compounds, reaction products of bismaleimide compounds with at least one selected from the group consisting of monoamine compounds and diamine compounds, acrylic resins, unsaturated polyester resins, diallyl phthalate resins, polybenzimidazole resins, polyamide resins, polyamideimide resins, silicone resins, resins synthesized from cyclopentadiene, resins containing tris(2-hydroxyethyl)isocyanurate, resins synthesized from aromatic nitriles, trimerized aromatic dicyanamide resins, furan resins, ketone resins, xylene resins, thermosetting resins containing condensed polycyclic aromatic compounds, benzocyclobutene resins, bisallylnadiimide resins, and benzoxazine compounds. Examples of thermoplastic resins include polyimide resins, polyphenylene oxide resins, polyphenylene sulfide resins, aramid resins, and liquid crystal polymers. In addition to the resin, the insulating material may contain at least one selected from the group consisting of a curing agent, a curing accelerator, an inorganic filler, an organic filler, a flame retardant, a thickener, an ultraviolet absorber, an adhesion promoter, a colorant, etc. Furthermore, the insulating material may contain components other than those described above. The insulating material may be a prepreg made by impregnating glass cloth with the above-mentioned resin or a composition containing at least the resin. The insulating material may be a combination of two or more of the above-mentioned materials.

[0016] The insulating material used in step 1 is preferably an insulating material layer formed on a supporting substrate. FIG. 1(a) shows an insulating material layer 2 formed on a supporting substrate 1 having a copper layer 1a. The insulating material layer 2 is formed by forming a layer of the above insulating material. The thickness of the insulating material layer 2 may be, for example, 1 to 100 μm or 1 to 40 μm, and is preferably 2 to 20 μm from the viewpoint of thinning.

[0017] The surface roughness (Ra) of the insulating material layer 2 is preferably 0.05 μm or more, more preferably 0.10 μm or more, and even more preferably 0.15 μm or more, from the viewpoint of obtaining sufficient adhesion between the seed layer and the resist pattern. If the surface roughness (Ra) of the insulating material layer 2 is small, the surface roughness (Ra) of the seed layer also becomes small, and the proportion of specularly reflected light from the seed layer increases when the resist layer (described later) is exposed to light. This specularly reflected light is reflected by a support on the resist layer, such as a polyethylene terephthalate film, and re-enters the resist layer and seed layer, causing a decrease in the resolution of the resist pattern. Therefore, it is preferable that the specularly reflected light is also small. From this viewpoint, the surface roughness (Ra) of the insulating material layer 2 is preferably within the above range. On the other hand, the surface roughness (Ra) of the insulating material layer 2 is preferably 0.35 μm or less, more preferably 0.3 μm or less, and even more preferably 0.25 μm or less, from the viewpoint of facilitating etching and removal of unnecessary portions of the seed layer. In this embodiment, the surface roughness refers to the arithmetic mean roughness Ra, which is calculated by extracting a reference length (L) from a roughness curve in the direction of the mean line, plotting the X axis in the direction of the mean line of the extracted portion and the Y axis in the direction of the longitudinal magnification, and expressing the roughness curve as y = f(x). In this embodiment, Ra is calculated using a reference length (L) of 0.8 mm. Specifically, Ra can be measured in accordance with JIS B0601 (1994) using the method described in the examples.

[0018]

number

[0019] The insulating material layer 2 can be formed, for example, by a method of laminating an insulating material onto the support substrate 1 or the copper layer 1a on the support substrate 1 by laminating, pressing, or the like. In the following description, the support substrate 1 on which the insulating material is laminated can be read as the copper layer 1a on the support substrate 1 when it has a copper layer 1a. Specifically, for example, first, a prepreg made by impregnating glass cloth with a resin or a resin composition is pressed against the support substrate 1, and then a resin-coated copper foil, which has a resin composition layer formed on one side of copper foil, is placed with the resin composition layer facing the prepreg, and then pressed. The copper foil is then removed by etching, thereby forming the insulating material layer 2 on the support substrate 1. According to this method, the insulating material layer 2 is composed of the prepreg and the resin composition layer. Alternatively, a resin-coated copper foil having a resin composition layer formed on one side of the copper foil can be placed on a support substrate 1 with the resin composition layer facing the support substrate 1, pressed, and then the copper foil removed by etching, thereby forming the insulating material layer 2 on the support substrate 1. According to this method, the insulating material layer 2 is made of a resin composition layer. The insulating material layer 2 formed by the above method has a surface onto which the irregularities of the copper foil removed by etching are transferred. The resin-coated copper foil is preferably a primer-coated copper foil, and in this case, the insulating material layer 2 has a primer on its surface onto which the irregularities of the copper foil are transferred. Note that etching of the copper foil derived from the resin-coated copper foil is preferably carried out after forming the opening 2a from above the copper foil using a direct laser or the like in the step of forming the opening described later in Fig. 1(b), and then desmearing the bottom surface (surface of the copper layer 1a) and side surface (insulating material layer 2) of the opening 2a to remove smears from the bottom surface. According to this method, the surface of the insulating material layer 2 is covered with copper foil when the opening 2a is desmeared, so that the surface irregularities of the insulating material layer 2 to which the irregularities of the copper foil have been transferred can be maintained. In this specification, a support substrate having an insulating material layer on its surface may be referred to as an "insulating resin substrate."

[0020] Examples of the support substrate 1 include a silicon plate, a glass plate, a SUS plate, a wiring board including glass cloth, and a sealing resin containing a semiconductor element. The thickness of the support substrate 1 is not particularly limited, but is, for example, 0.2 to 2.0 mm.

[0021] In FIG. 1(a), the support substrate 1 has a copper layer 1a on its surface, but it may have wiring and / or pads instead of the copper layer 1a, or may not have these.

[0022] The manufacturing method of this embodiment may include a step of forming an opening in the insulating material. FIG. 1( b ) shows a step of forming an opening 2 a in the insulating material layer 2 . The opening 2a is formed so as to penetrate the insulating material layer 2 in the thickness direction thereof, and is composed of a bottom surface (the surface of the copper layer 1a) and a side surface (the insulating material layer 2). The openings 2a can be formed by applying an opening method such as laser ablation, sandblasting, water blasting, etc. Among these, laser ablation is preferred because it can form fine openings 2a. Examples of lasers used for laser ablation include CO2 lasers, UV-YAG lasers, and excimer lasers, and CO2 lasers are preferred from the viewpoint of cost. After the opening 2a is formed in the insulating material layer 2, it is preferable to perform a desmear treatment on the bottom surface (surface of the copper layer 1a) and side surface (insulating material layer 2) of the opening 2a.

[0023] FIG. 2( a ) shows a step of depositing a first catalyst 3 on the surface of an insulating material layer 2 . The first catalyst 3 is a catalyst for accelerating the electroless nickel plating in step 2, which will be described later. In FIG. 2(a), for convenience, the first catalyst 3 is shown as a layer, but the first catalyst 3 may be present in any form as long as it can promote adhesion of the second catalyst described below.

[0024] A palladium catalyst is preferably used as the first catalyst 3, but is not particularly limited as long as it is a catalyst that promotes the electroless nickel plating in step 2 described below. In the following explanation, an embodiment in which a palladium catalyst is used as the first catalyst 3 will be mainly described. The first catalyst 3 can be attached to the insulating material layer 2, for example, by a step of treating the insulating material layer 2 with an electroless plating catalyst (first catalyst). Specifically, the first catalyst 3 is preferably attached to the insulating material layer 2 by subjecting the insulating material layer 2 to a cleaning treatment step, a soft etching treatment step, a neutralization treatment step, a treatment step with an electroless plating catalyst (first catalyst), a reduction treatment step, and the like, in this order. The cleaner treatment step can be carried out, for example, using an alkaline cleaner treatment liquid, preferably at 40 to 70° C. for 1 to 10 minutes, followed by rinsing with hot water and water. The soft etching step is preferably carried out from the viewpoint of maintaining good interlayer connection between the inner layer copper and the electroless copper plating when the surface of the insulating material containing the via holes and through holes to be electrolessly copper plated contains an inner layer copper. The soft etching step can be carried out, for example, using a treatment solution containing a sulfuric acid-hydrogen peroxide mixed solution and a sodium persulfate solution, preferably at 15 to 30°C, for preferably 0.5 to 2 minutes, followed by rinsing with water. The neutralization step can be carried out by treating the surface with, for example, an aqueous sulfuric acid solution at preferably 20 to 30° C. for preferably 0.5 to 1 minute, followed by washing with water. In the treatment step with the electroless plating catalyst (first catalyst), for example, a plating catalyst solution containing a palladium salt can be used. Note that as a pretreatment for applying the electroless plating catalyst, a pre-dip treatment solution may be used, preferably at 20 to 40°C for preferably 0.5 to 2 minutes, followed by treatment with an alkaline palladium application solution, preferably at 30 to 50°C for preferably 3 to 7 minutes, followed by rinsing with water. The reduction treatment step can be carried out, for example, by treating the product with a palladium reduction treatment solution, preferably at 20 to 35° C. for preferably 3 to 7 minutes, followed by washing with water.

[0025] The amount of the first catalyst deposited in step 1 is preferably 0.5 to 50 mg / m from the viewpoint of allowing the deposition of the second catalyst in step 2 to proceed appropriately. 2 , more preferably 1 to 30 mg / m 2 , and more preferably 5 to 20 mg / m 2 is.

[0026] <Step 2: Attachment of the second catalyst> Step 2 is a step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached.

[0027] FIG. 2(b) shows the step of depositing a second catalyst 4 onto the insulating material layer 2 to which the first catalyst 3 has been deposited. In FIG. 2(b), the second catalyst 4 is shown as a layer for convenience, but the second catalyst 4 may be present in any form as long as it can promote the formation of a seed layer, which will be described later.

[0028] The second catalyst 4 mainly contains nickel, but may also contain phosphorus derived from the reducing agent. In this case, this step can be said to be electroless nickel-phosphorus plating. However, in this specification, the step of applying the second catalyst may be referred to as "electroless nickel plating" for convenience.

[0029] The lower the phosphorus content of the second catalyst 4, the easier it is to etch, and the less the second catalyst 4 remains when the seed layer is removed. Therefore, the lower the phosphorus content in the second catalyst 4, the better, and it is preferably 6% by mass or less, more preferably 4% by mass or less, and even more preferably 3% by mass or less. On the other hand, from the viewpoint of ease of production, the phosphorus content in the second catalyst 4 may be 1% by mass or more.

[0030] The electroless nickel plating solution may contain, in addition to a nickel source such as nickel sulfate and a hypophosphite as a reducing agent, a pH adjuster such as sodium hydroxide; a complexing agent such as an organic acid salt; a pH buffer such as an organic acid or an inorganic acid; an accelerator such as a sulfide; a stabilizer; a surfactant; etc. The nickel concentration in the electroless nickel plating solution is, for example, 0.01 to 1.0 g / L. The hypophosphite serving as the reducing agent is preferably sodium hypophosphite. The concentration of the hypophosphite in the electroless nickel plating solution is, for example, 0.1 to 0.5 mol / L. The organic acid salt serving as the complexing agent is preferably a citrate. The concentration of the complexing agent in the electroless nickel plating solution is, for example, 0.01 to 0.1 mol / L. The organic acid that is the pH buffer is preferably boric acid. The concentration of the pH buffer in the electroless nickel plating solution is, for example, 0.1 to 1.0 mol / L. As the electroless nickel plating solution using hypophosphite as a reducing agent, a commercially available plating solution can also be used.

[0031] The temperature at which the insulating material layer 2 is brought into contact with the electroless nickel plating solution is preferably 20 to 50° C., more preferably 25 to 45° C., and even more preferably 30 to 40° C. When the contact temperature is within the above range, the second catalyst 4 adhered to the insulating material layer 2 has a low phosphorus content and is easily removed by etching. The time for which the insulating material layer 2 is brought into contact with the electroless nickel plating solution may be, for example, 5 to 20 minutes, or 10 to 15 minutes.

[0032] The pH of the electroless nickel plating solution is preferably 7 to 10, more preferably 7.5 to 9.5, and even more preferably 8 to 9. When the pH of the electroless nickel plating solution is within the above range, the second catalyst 4 adhered to the insulating material layer 2 has a low phosphorus content and is easily removed by etching.

[0033] The amount of the second catalyst 4 deposited in step 2 is preferably 10 to 300 mg / m from the viewpoint of appropriately adjusting the thickness of the seed layer in step 3. 2 , more preferably 20 to 200 mg / m 2 , and more preferably 50 to 150 mg / m 2 is.

[0034] <Step 3: Formation of seed layer> Step 3 is a step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached.

[0035] FIG. 2(c) shows the step of forming a seed layer 5 on the insulating material layer 2 to which the second catalyst 4 has been attached.

[0036] The electroless copper plating solution may contain, in addition to a copper source such as copper sulfate and a hypophosphite as a reducing agent, a pH adjuster such as sodium hydroxide; a complexing agent such as an organic acid salt; a pH buffer such as an organic acid or an inorganic acid; an accelerator such as a metal salt or a sulfide; a stabilizer; a surfactant; etc. The copper concentration in the electroless copper plating solution is, for example, 0.5 to 0.7 g / L. The hypophosphite that serves as the reducing agent is preferably sodium hypophosphite. The concentration of hypophosphite in the electroless copper plating solution is, for example, 0.1 to 0.5 mol / L. The organic acid salt serving as the complexing agent is preferably a citrate. The concentration of the complexing agent in the electroless copper plating solution is, for example, 0.01 to 0.1 mol / L. The organic acid that is the pH buffer is preferably boric acid. The concentration of the pH buffer in the electroless copper plating solution is, for example, 0.1 to 1.0 mol / L. An example of the metal salt that serves as the accelerator is nickel sulfate. As the electroless copper plating solution using hypophosphite as a reducing agent, a commercially available plating solution can also be used.

[0037] The temperature at which the insulating material layer 2 is brought into contact with the electroless copper plating solution may be, for example, 30 to 80°C, or 60 to 70°C. The time for which the insulating material layer 2 is brought into contact with the electroless copper plating solution may be, for example, 5 to 20 minutes, or 10 to 15 minutes. The pH of the electroless copper plating solution is preferably 7 to 10, more preferably 7.5 to 9.5, and even more preferably 8 to 9.

[0038] From the viewpoint of forming a circuit pattern having excellent fine wiring properties and insulating reliability, the thickness of the seed layer 5 formed in this step is preferably 0.4 μm or less, more preferably 0.35 μm or less, even more preferably 0.3 μm or less, even more preferably 0.25 μm or less, particularly preferably 0.2 μm or less, and most preferably 0.15 μm or less. Furthermore, from the viewpoint of fully exhibiting the function as a seed layer, the thickness of the seed layer 5 may be 0.1 μm or more, or may be 0.12 μm or more. In this specification, the thickness of the seed layer refers to the average thickness (n=10) of the seed layer measured by forming a cross section of the seed layer using a focused ion beam (FIB) and observing the cross section with a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees.

[0039] After the seed layer 5 is formed, in order to remove excess plating solution, washing with water or an organic solvent, heating and drying, etc. may be carried out as necessary.

[0040] <Step 4: Formation of Resist Pattern> Step 4 is a step of forming a resist pattern for forming a circuit pattern on the surface of the seed layer. The resist pattern in step 4 is preferably formed by a method including the following steps 4-1 and 4-2 in this order. Step 4-1: A step of laminating a photosensitive resin film of a supported photosensitive resin film on the seed layer to form a resist layer Step 4-2: a step of exposing at least a part of the resist layer through the support of the supported photosensitive resin film by a direct writing exposure method, and then developing the exposed resist layer.

[0041] (Step 4-1) Step 4-1 is a step of laminating the photosensitive resin film of the supported photosensitive resin film on the seed layer to form a resist layer. FIG. 3(a) shows a step of laminating the photosensitive resin film of the supported photosensitive resin film 6 on the seed layer 5 to form a resist layer 7. The supported photosensitive resin film 6 is a film formed from a photosensitive resin composition on the surface of a support 6a, and a commercially available product used as a dry film resist for the SAP method can be used. Examples of the support 6a of the supported photosensitive resin film 6 include various plastic films such as polyolefin films such as polyethylene, polypropylene, and polyvinyl chloride; polyester films such as polyethylene terephthalate (hereinafter also referred to as "PET") and polyethylene naphthalate; polycarbonate films; and polyimide films. Among these, PET is preferred.

[0042] The thickness of the resist layer 7 formed by the supported photosensitive resin film 6 may be determined appropriately depending on the thickness and shape of the circuit pattern to be formed, but is preferably 5 to 100 μm, more preferably 7 to 50 μm, and even more preferably 10 to 30 μm.

[0043] The supported photosensitive resin film 6 can be laminated onto the seed layer 5, for example, by placing the photosensitive resin film on the seed layer 5 side and then thermally laminating it using a laminator such as a roll laminator.

[0044] (Step 4-2) Step 4-2 is a step of exposing at least a part of the resist layer through the support of the supported photosensitive resin film by a direct writing exposure method, and then developing the exposed resist layer to form a resist pattern. FIG. 3(b) shows a resist pattern 8 formed by exposing and developing the resist layer 7.

[0045] The resist layer 7 is preferably exposed by a direct writing exposure method, preferably at 5 to 2,000 mJ / cm 2 through the support 6a of the supported photosensitive resin film 6. 2 , more preferably 10 to 500 mJ / cm 2 , and more preferably 20 to 100 mJ / cm 2 The film is irradiated with light at an exposure amount of . The wavelength of light used for exposure may be a semiconductor laser, metal halide, mercury lamp, excimer laser, extreme ultraviolet (EUV), electron beam, etc., and is preferably the emission spectrum of mercury (G-line: wavelength 436 nm, H-line: wavelength 405 nm, I-line: wavelength 365 nm), with H-line (wavelength 405 nm) being more preferred. Furthermore, the light source may be a low-pressure mercury lamp, a high-pressure mercury lamp, an ultra-high-pressure mercury lamp, a halogen lamp, an LED lamp, etc.

[0046] Thereafter, the unexposed areas are dissolved and removed with a dilute alkaline aqueous solution for development, and further, if necessary, residues are removed by oxygen plasma ashing to form a resist pattern 8.

[0047] <Step 5: Formation of copper layer> Step 5 is a step of forming a copper layer by electrolytic copper plating on the surface of the seed layer in the area exposed from the resist pattern. FIG. 3(c) shows a step of forming a copper layer 9 on the surface of the seed layer 5 in the area exposed from the resist pattern 8 by electrolytic copper plating. As the electrolytic copper plating solution used in the electrolytic copper plating treatment, a commercially available electrolytic copper plating solution such as an electrolytic copper plating solution containing copper sulfate can be used.

[0048] <Step 6: Removal of resist pattern> Step 6 is a step of removing the resist pattern. FIG. 4(a) shows the substrate after the resist pattern 8 has been removed. The resist pattern 8 can be removed using a resist remover. The resist stripping liquid may be a chemical solution such as an inorganic alkali, an organic alkali, or an organic solvent, or may be a commercially available resist stripping liquid. Furthermore, if there is a stripping liquid specifically designed for the photosensitive resin composition used to form the resist pattern, that may also be used. Examples of methods for removing the resist pattern include a method in which the resist is immersed in a chemical solution to swell, destroy, or dissolve the resist, and then the resist is removed. In order to sufficiently impregnate the resist with the chemical solution, techniques such as ultrasonic waves, heating, and stirring may be used in combination. In addition, in order to promote peeling of the resist pattern, the chemical solution may be applied by shower, spray, jet, or the like. In addition, if the insulating material has sufficiently high heat resistance, the resist may be removed by carbonizing it by baking at a high temperature, or by burning it off by irradiating it with a laser.

[0049] <Step 7: Removal of seed layer and catalyst> Step 7 is a step of removing the seed layer exposed by removing the resist pattern, as well as the first catalyst and the second catalyst between the seed layer and the insulating material, to obtain a circuit pattern. Figure 4(b) shows a step of removing the seed layer 5 exposed by removing the resist pattern 8, as well as the first catalyst 3 and second catalyst 4 between the seed layer 5 and the insulating material layer 2, to obtain a circuit pattern 10. As a removal liquid for removing the seed layer 5, for example, an acidic etching liquid such as a sulfuric acid-hydrogen peroxide solution etching liquid, a nitric acid-hydrogen peroxide solution etching liquid, or a ferric chloride-hydrochloric acid etching liquid can be used. As a remover for removing the first catalyst 3 and the second catalyst 4, for example, an acidic etching solution such as a nitric acid-hydrogen peroxide solution or a ferric chloride-hydrochloric acid etching solution can be used. Alternatively, any commercially available etching solution can be used as long as it can remove the first catalyst 3 and the second catalyst 4. The seed layer 5, the first catalyst 3 and the second catalyst 4 can also be removed simultaneously using an acidic etching solution such as a nitric acid-hydrogen peroxide solution or a ferric chloride-hydrochloric acid etching solution.

[0050] In the manufacturing method of this embodiment, the insulating material layer described in step 1 may be formed on the circuit pattern 10 produced by the above method, and the above steps may be repeated to form a multilayer structure. In this way, a multilayer printed wiring board can be manufactured.

[0051] The printed wiring board of this embodiment manufactured by the above method has a circuit pattern that is excellent in formation precision and has high adhesiveness even if the L / S is small. Furthermore, the printed wiring board of this embodiment manufactured by the above method has better insulation reliability in a High Accelerated Stress Test (HAST) test (hereinafter also referred to as "HAST resistance") than conventional printed wiring boards. The reason for this is not clear, but is thought to be as follows. In a circuit pattern formed by a conventional method, the seed layer is formed from a palladium catalyst and copper, so the copper forming the wiring is electrochemically more base than the seed layer and is easily corroded. In contrast, the circuit pattern of the printed wiring board of this embodiment contains nickel, which is electrochemically more base than copper, in the seed layer, so the potential difference between the seed layer and the copper forming the wiring is smaller, making the copper forming the wiring less susceptible to corrosion, and it is thought that this results in high HAST resistance.

[0052] [Seed layer manufacturing method and seed layer] The method for producing a seed layer according to this embodiment includes the following steps 1 to 3 in this order. Step 1: Applying a first catalyst to the surface of an insulating material Step 2: A step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached. Step 3: A step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached. Steps 1 to 3 are as described above in the method for manufacturing a printed wiring board of this embodiment.

[0053] [Semiconductor Package] This embodiment also provides a semiconductor package having a semiconductor element mounted on the printed wiring board of this embodiment. The semiconductor package of this embodiment can be manufactured by mounting a semiconductor element such as a semiconductor chip or memory at a predetermined position on the printed wiring board of this embodiment and sealing the semiconductor element with a sealing resin or the like. [Example]

[0054] Next, the present embodiment will be described in more detail with reference to the following examples, but these examples do not limit the present embodiment.

[0055] Examples A1 to A2, B1 to B6, C1 to C2, D1 to D2 (Preparing an insulating resin substrate) A support substrate was prepared by etching away the copper foil of a multilayer copper-clad laminate "MCL-E-700G" (manufactured by Hitachi Chemical Co., Ltd., thickness 0.4 mm). A prepreg (manufactured by Hitachi Chemical Co., Ltd., product name "GEA-700G") was pressed onto one side of the support substrate, and then the primer side of a copper foil with a primer (insulating material) was attached to the prepreg using a laminating press, after which the copper foil was etched away to produce an insulating resin substrate having an insulating material layer on the surface of the support substrate. The primer-coated copper foil used was from the "PF-EL" series manufactured by Hitachi Chemical Co., Ltd., and the primer (insulating material) had the specified surface roughness Ra (μm) shown in each table.

[0056] (Step 1: Attachment of the first catalyst) The insulating resin substrate obtained above was subjected to the following treatment. As a cleaning treatment step, the plate was immersed in "Cleaner Securigant 902" (trade name, manufactured by Atotech Japan Co., Ltd.) for 5 minutes at 60°C, followed by rinsing with hot water for 1 minute and then rinsing with water for 3 minutes. Next, as a neutralization treatment step, the plate was immersed in a 5% sulfuric acid solution at 30°C for 0.5 minutes and then rinsing with water for 1 minute. Subsequently, as a treatment step using an electroless plating catalyst, the plate was immersed in a mixed solution of 20 ml / L of "Pre-Dip Neogant B" (trade name, manufactured by Atotech Japan Co., Ltd.) and 1 ml / L of 98% sulfuric acid at 30°C for 1 minute. Further, the plate was immersed in a mixed solution of 40 ml / L of "Activator Neogant 834" (trade name, manufactured by Atotech Japan Co., Ltd.), 5 g / L of boric acid aqueous solution, and 4 g / L of sodium hydroxide aqueous solution at 40°C for 5 minutes and then rinsing with water for 1 minute. Thereafter, in the reduction treatment step, the substrate was immersed in a mixture of 5 ml / L of "Reducer Neogant WA" (trade name, manufactured by Atotech Japan Co., Ltd.) and 5 g / L of boric acid at 30°C for 5 minutes, and then washed with water for 0.5 minutes. The amount of the first catalyst attached in step 1 was 10 mg / m 2 It was.

[0057] (Step 2: Attachment of the second catalyst) An electroless nickel plating solution using sodium hypophosphite as the reducing agent was prepared using an aqueous solution of 0.2 g / L nickel sulfate hexahydrate, 30.0 g / L sodium hypophosphite monohydrate, 25 g / L trisodium citrate, and 30 g / L boric acid. The pH of the electroless nickel plating solution was adjusted to 9 with sodium hydroxide. The insulating resin substrate to which the first catalyst had been attached in step 1 was immersed in the electroless nickel plating solution at 35°C for 10 minutes to attach the second catalyst to the insulating resin substrate to which the first catalyst had been attached. The amount of the second catalyst attached in step 2 was 100 mg / m 2 It was.

[0058] (Step 3: Formation of seed layer) An electroless copper plating solution using sodium hypophosphite as the reducing agent was prepared using an aqueous solution of 2.4 g / L copper sulfate pentahydrate, 30.0 g / L sodium hypophosphite monohydrate, 25 g / L trisodium citrate, and 30 g / L boric acid. The pH of the electroless copper plating solution was adjusted to 9 with sodium hydroxide. The insulating resin substrate to which the second catalyst had been attached in step 2 was immersed in the electroless copper plating solution prepared above at 65° C., and electroless copper plating was carried out until a seed layer of a predetermined thickness was obtained. Thereafter, washing with water and drying were carried out to obtain an insulating resin substrate on which a seed layer was formed.

[0059] Next, a circuit pattern was formed on the insulating resin substrate on which the seed layer had been formed by the method described below.

[0060] (Step 4: Formation of resist pattern) The insulating resin substrate on which the seed layer was formed in step 3 was immersed in a 5% aqueous sulfuric acid solution for 0.5 minutes, washed with water for 1 minute, and then dried at 80°C for 20 minutes. Immediately after drying, a dry film resist "RD-1619" (Hitachi Chemical Co., Ltd., product number), which is a photosensitive resin film with a support, was laminated by atmospheric pressure lamination under the conditions of a roll pressure of 0.4 MPa, a processing temperature of 120°C, and a conveying speed of 1.0 m / s to form a dry film resist layer. Next, the dry film resist layer was applied at 55 mJ / cm using a direct imaging exposure machine "DE-1UH" (Via Mechanics Co., Ltd., product number). 2One minute later, a PEB (Post Exposure Bake) process was performed at 70°C for one minute, followed by processing using a 1% sodium carbonate developer at a spray pressure of 0.17 MPa and 30°C for 70 seconds, and then oxygen plasma ashing was performed to remove the residue and form a resist pattern.

[0061] (Step 5: Formation of copper layer) The insulating resin substrate on which the resist pattern was formed in step 4 was immersed in a 5% sulfuric acid solution at 30° C. for 10 seconds. Next, an electrolytic copper plating solution (200 g / L of copper sulfate pentahydrate, 50 g / L of 98% sulfuric acid, 40 mg / L of chloride ions, 20 ml / L of "Cu-Brite VF-IIA" (trade name, manufactured by JCU Corporation), and 1 ml / L of "Cu-Brite VF-IIB" (trade name, manufactured by JCU Corporation) was used at 23° C. and 1.0 A / dm 2 Then, electrolytic copper plating was carried out to form a copper layer of a predetermined height.

[0062] (Step 6: Removal of resist pattern) Next, the insulating resin substrate on which the copper layer was formed in step 5 was treated with a mixed solution of 100 ml / L of "R-100S" (trade name, manufactured by Hishiko Chemical Co., Ltd.) and 100 ml / L of "R-101" (trade name, manufactured by Hishiko Chemical Co., Ltd.) at a spray pressure of 0.15 MPa at 45°C for 4 minutes to remove the resist pattern. After that, the substrate was washed with water for 3 minutes and then dried at 180°C for 30 minutes.

[0063] (Step 7: Removal of seed layer (Cu) and catalyst) Next, the insulating resin substrate from which the resist pattern was removed in step 6 was etched using a sulfuric acid-hydrogen peroxide solution (100 ml / L of 98% sulfuric acid, 100 g / L of DL-malic acid, 10 ml / L of hydrogen peroxide, and 1 g / L of 1,2,3-benzotriazole) at 30°C and a spray pressure of 0.14 MPa until the etching thickness reached a predetermined value, thereby removing the seed layer (Cu). Note that the "etching thickness" here is a value that can be determined from the amount of thickness reduction of the circuit pattern. Therefore, the etching thickness is usually set to a value greater than the thickness of the seed layer. Next, the first catalyst and the second catalyst were removed using a nitric acid-hydrogen peroxide etching solution (nitric acid 100 ml / L, DL-malic acid 100 g / L, hydrogen peroxide 10 ml / L, 1,2,3-benzotriazole 1 g / L) at 30°C and a spray pressure of 0.14 MPa, thereby forming a predetermined circuit pattern.

[0064] Depending on the evaluation items described later, the "CZ treatment" or "formation of via holes" described below was carried out.

[0065] (CZ processing) The CZ treatment was carried out by treating the insulating resin substrate on which the circuit pattern obtained above was formed using the etching agent "CZ-8101" (manufactured by MEC Co., Ltd.) under conditions of 30°C, 40 seconds, and a spray pressure of 0.15 MPa.

[0066] (Formation of via holes) To form the via holes, after preparing the insulating resin substrate, and before step 1, a carbon dioxide laser processing machine "LC-2K212 / 2C" (manufactured by Via Mechanics Co., Ltd.) was used as the laser processing machine to form the via holes under the conditions of a mask diameter of 3 mm, a frequency of 2 kHz, a pulse width of 4 μs, and two shots.

[0067] The circuit patterns formed in each example were of the following three types. <Types of circuit patterns> Pattern A: Circuit pattern with L / S=5 / 5 (height 12 μm) Pattern B: A single circuit after etching the seed layer and before CZ processing, with L (width) = 13 μm (height 18 μm). Pattern C: A single circuit after etching the seed layer and then CZ processing, with L (width) = 10 μm (height 16 to 17.5 μm).

[0068] Example A3 A circuit pattern was formed in the same manner as in Example A1, except that the electroless copper plating solution used in step 3 in Example A1 was changed to an aqueous solution containing 2.4 g / L of copper sulfate pentahydrate, 30.0 g / L of sodium hypophosphite monohydrate, 25 g / L of trisodium citrate, 30 g / L of boric acid, and 0.05 g / L of nickel sulfate hexahydrate, and the circuit pattern formation conditions were changed as shown in Table 1.

[0069] Comparative examples A1~A2, B1~B6, C1~C2, D1~D2 A circuit pattern was formed in the same manner as in Example A1, except that step 2 in Example A1 was not performed and the conditions for forming the circuit pattern were changed as shown in each table.

[0070] Comparative example A3 An insulating resin substrate prepared in the same manner as in Example A2 was subjected to 10 nm sputtering using an intervac high-rate sputtering device "SIH-350-T08-0" (manufactured by ULVAC, Inc.) with nickel as the target, followed by sputtering with copper as the target until a seed layer of a predetermined thickness was formed. Thereafter, a circuit pattern was formed in the same manner as in Example A2.

[0071] [Evaluation method and results] 1. Evaluation of throwing power of electroless copper plating (Pinholes in the seed layer) A substrate with a circuit pattern prepared under the conditions shown in Table 1 was used as a measurement sample. A cross section of the seed layer was formed using a focused ion beam (FIB). The cross section was then observed with a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees to check for the presence or absence of pinholes (voids) in the seed layer. The fewer pinholes there were, the better the deposition performance of electroless copper plating on insulating materials. The results are shown in Table 1 and Figure 5.

[0072] (Throwing power around the beer hall) A substrate with a circuit pattern fabricated under the conditions shown in Table 1 was used as a measurement sample. A cross section of a via hole was formed using a focused ion beam (FIB), and the cross section was observed using a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees. The ratio of the seed layer thickness B μm in the trench portion of the via hole to the seed layer thickness A μm on the top surface of the insulating material around the via hole was calculated as the throwing power (%) (see Figure 6 for the positions of A and B). The thickness of each portion was the average of 10 arbitrarily selected locations. The closer the throwing power is to 100%, the more uniform the seed layer thickness. The results are shown in Table 1.

[0073] [Table 1]

[0074] From Table 1 and FIG. 5, it can be seen that the seed layers obtained in Examples A1 to A3, which are the manufacturing method of this embodiment, did not contain pinholes and exhibited high throwing power values. On the other hand, pinholes were observed in the seed layers obtained in Comparative Examples A1 and A2, which did not undergo the second catalyst deposition step, and exhibited low throwing power values. Furthermore, pinholes were observed in the seed layer formed by vapor deposition in Comparative Example A3. From the above, it can be seen that the circuit pattern obtained by the manufacturing method of this embodiment has excellent electroless copper plating throwing power.

[0075] 2. Evaluation of circuit pattern peel strength Next, the circuit pattern substrates prepared under the conditions shown in Table 2 were used as measurement samples, and the peel strength (perpendicular peel strength) of the circuit patterns was measured at a peel speed of 50 mm / min using an Autograph AC-100C (Shimadzu Corporation, product number). The results are shown in Table 2.

[0076] [Table 2]

[0077] From Table 2, it can be seen that the circuit patterns formed by Examples B1 to B6, which are the manufacturing method of this embodiment, have stronger peel strength and better adhesion than the circuit patterns formed by Comparative Examples B1 to B6, which did not undergo the second catalyst adhesion process.

[0078] 3. Evaluate the presence or absence of undercut or peeling and the shear strength of the circuit pattern (Presence or absence of undercut or peeling) Next, a substrate having a circuit pattern prepared under the conditions shown in Table 3 was used as a measurement sample, and a cross section of the circuit pattern was formed using a focused ion beam (FIB). The cross section was observed with a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees to check for the presence or absence of undercuts and peeling of the circuit pattern. The results are shown in Table 3. A cross section of the seed layer of the measurement sample of Example C1 is shown in FIG. 7(a), a cross section of the seed layer of the measurement sample of Comparative Example C1 is shown in FIG. 7(b), and cross sections of the circuit patterns (wiring) of the measurement samples of each example are shown in FIGS. 8(a) to 8(d).

[0079] (Circuit pattern shear strength) For Example C2 and Comparative Example C2, the shear strength was measured using a Bond tester 4000 Plus (manufactured by Nordson DAGE) under the conditions of a shear speed of 200 μm / sec and a shear position at a circuit pattern height of 3 μm. The results are shown in Table 3.

[0080] [Table 3]

[0081] From Table 3 and FIG. 8, it can be seen that the circuit patterns formed by Examples C1 and C2, which are the manufacturing method of this embodiment, have less undercut and peeling and higher shear strength than the circuit patterns formed by Comparative Examples C1 and C2, which do not undergo the second catalyst adhesion step.

[0082] 4. Evaluation of short circuit occurrence rate between wiring and HAST resistance Next, a substrate having a circuit pattern (comb-shaped pattern) prepared under the conditions shown in Table 4 was used as a measurement sample, and the incidence of short circuits and HAST resistance were measured by the following methods. (Short circuit occurrence rate) The number of measurement samples was N=48, and the spaces between the wiring of each measurement sample were observed at 500x magnification using a metallurgical microscope. Those in which copper residue was found between the wiring were judged to be NG. Next, for measurement samples in which copper residue was not found between the wiring, a resistance meter was used to measure the resistance between the wiring, and if the resistance value was 1 x 10 10 Those that were less than Ω were considered NG. The number of NGs for N=48 (number of NGs × 100 / 48) was calculated as the short circuit occurrence rate (%). (HAST resistance) The substrates having the circuit patterns (comb-shaped patterns) produced in Example D2 and Comparative Example D2 shown in Table 4 were subjected to reflow treatment three times at 260°C and used as measurement samples for the HAST test. The HAST test measured the insulation resistance between wiring under conditions of a constant temperature and humidity of 130°C and 85% RH with an applied voltage of 5.5 V. When the insulation resistance value was 1.0 × 10 6 The time it took for the resistance to drop below Ω was measured for up to 200 hours.

[0083] [Table 4]

[0084] From Table 4, it can be seen that the circuit patterns formed by Examples D1 and D2, which are the manufacturing method of this embodiment, have a lower short-circuit occurrence rate and superior wiring formability than the circuit patterns formed by Comparative Examples D1 and D2, which do not undergo the second catalyst adhesion step. Furthermore, the circuit pattern formed in Example D2 maintained a high insulation resistance value even 200 hours after the start of the HAST test, whereas the circuit pattern formed in Comparative Example D2 shorted out 182 hours after the start of the HAST test, and the insulation resistance value fell below the threshold value. Next, for the substrate of Example D2 after 200 hours of HAST testing and the substrate of Comparative Example D2 after 182 hours of HAST testing, cross sections of the wiring that would become the positive electrode were formed using a focused ion beam (FIB), and the cross sections were observed with a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees. As a result, no corrosion was observed on the wiring surface of Example D2 (FIG. 9(a)), but corrosion (13 in FIG. 9(b)) was observed on the wiring surface of Comparative Example D2 (FIG. 9(b)). This shows that the wiring formed by the manufacturing method of this embodiment is less likely to corrode on its surface than wiring formed by conventional methods, and therefore has superior insulation reliability. [Explanation of symbols]

[0085] 1 Support substrate 1a copper layer 2. Insulating resin layer 2a opening 3. The First Catalyst 4. The Second Catalyst 5 Seed layer 6. Photosensitive resin film with support 6a Support 7 Resist layer 8 Resist pattern 9 copper layers 10 Circuit Pattern 11 Primer layer 12 Prepreg 13 Corrosion area

Claims

1. A method for manufacturing a printed wiring board, comprising the following steps 1 to 7 in this order: Step 1: Adhering a first catalyst to the surface of an insulating material Step 2: A step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached. Step 3: A step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached. Step 4: forming a resist pattern for forming a circuit pattern on the surface of the seed layer Step 5: forming a copper layer by electrolytic copper plating on the surface of the seed layer in the area exposed from the resist pattern. Step 6: Removing the resist pattern Step 7: A step of removing the seed layer exposed by removing the resist pattern, as well as the first catalyst and the second catalyst between the seed layer and the insulating material, to obtain a circuit pattern.

2. The method for producing a printed wiring board according to claim 1, wherein the resist pattern in step 4 is formed by a method including the following steps 4-1 and 4-2 in this order: Step 4-1: A step of laminating a photosensitive resin film of a supported photosensitive resin film on the seed layer to form a resist layer Step 4-2: A step of exposing at least a part of the resist layer through the support of the supported photosensitive resin film by a direct writing exposure method, and then developing the exposed resist layer.

3. 3. The method for producing a printed wiring board according to claim 1, wherein the electroless nickel plating solution has a pH of 7 to 10.

4. 4. The method for producing a printed wiring board according to claim 1, wherein the second catalyst has a phosphorus content of 6 mass % or less.

5. The method for producing a printed wiring board according to any one of claims 1 to 4, wherein the seed layer has a thickness of 0.4 µm or less.

6. The method for producing a printed wiring board according to any one of claims 1 to 5, wherein the insulating material is an insulating material layer formed on a support substrate.

7. A printed wiring board manufactured by the method for manufacturing a printed wiring board according to any one of claims 1 to 6.

8. A semiconductor package comprising a semiconductor element mounted on the printed wiring board according to claim 7.

9. A method for producing a seed layer, comprising the following steps 1 to 3 in this order: Step 1: Adhering a first catalyst to the surface of an insulating material Step 2: A step of contacting the insulating material to which the first catalyst has been attached with an electroless nickel plating solution containing hypophosphite as a reducing agent, thereby attaching a second catalyst containing at least nickel to the surface of the insulating material to which the first catalyst has been attached. Step 3: A step of contacting the insulating material to which the second catalyst has been attached with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the surface of the insulating material to which the second catalyst has been attached.

10. The method for producing a seed layer according to claim 9, wherein the electroless nickel plating solution has a pH of 7 to 10.

11. The method for producing a seed layer according to claim 9 or 10, wherein the phosphorus content in the second catalyst is 6 mass % or less.

12. The method for producing a seed layer according to any one of claims 9 to 11, wherein the seed layer has a thickness of 0.4 µm or less.

13. The method for producing a seed layer according to any one of claims 9 to 12, wherein the insulating material is an insulating material layer formed on a support substrate.

14. A seed layer manufactured by the method for manufacturing a seed layer according to any one of claims 9 to 13.

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