Device module, network device, and vehicle

Abstract

To provide a device module, a network device, and a vehicle that suppress an increase in the time required for setting a semiconductor device.SOLUTION: In the network device 100, the device module 2a includes a communication path 6, a semiconductor element 5, an interface 7, and a second controller 4. The semiconductor device is connected to the communication path and operates based on the input setting information. The interface is connected to the communication path and establishes communication between the first controller 1 and a plurality of targets connected to the communication path. The second control unit is connected to the communication path, operates in a first state in which the second control unit serves as a controller and communicates with the semiconductor device serving as a target or a second state in which the second control unit serves as a target and communicates with the first control unit serving as a controller via the interface, and generates a setting signal including setting information and inputs the setting signal to the semiconductor device in the first state.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The invention disclosed herein relates to a device module, a network appliance, and a vehicle. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there are network devices such as in-vehicle devices that include a plurality of device modules.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-211864

[0005] [overview] The device module disclosed in Patent Document 1 leaves room for further consideration regarding the time required for various settings to be made via a network device.

[0006] The device module disclosed in this specification includes a communication path, a semiconductor device, an interface, and a second control unit. The semiconductor device is connected to the communication path and configured to operate based on input setting information. The interface is connected to the communication path and configured to establish communication between the first control unit and multiple targets connected to the communication path. The second control unit is connected to the communication path and configured to operate in a first state in which it serves as a controller and communicates with the semiconductor device, with the semiconductor device being the target, or in a second state in which it serves as a target and communicates with the first control unit via the interface, with the first control unit being the controller. In the first state, the second control unit generates a setting signal including the setting information and inputs it to the semiconductor device.

[0007] The network device disclosed in this specification includes the device module having the above-described configuration, a first control unit, and a communication bus. The communication bus electrically connects the device module and the first control unit so as to establish communication between the device module and the first control unit via an interface.

[0008] The vehicle disclosed in this specification is equipped with the network device having the above configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of a network device 100 according to the present disclosure. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of the device module 2a. [Figure 3] FIG. 3 is a diagram showing in more detail the internal configuration of the device module 2a according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing in more detail the internal configuration of the device module 2a according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram showing the configuration of a device module 2a according to the second embodiment. [Figure 6] FIG. 6 is a block diagram showing the configuration of a vehicle 200 equipped with the network device 100. As shown in FIG.

[0010] [Detailed explanation] <Basic configuration> First, the basic configuration of the network device 100 of the present disclosure will be described.

[0011] 1 is a block diagram showing the configuration of a network device 100 according to the present disclosure. The network device 100 includes a processor 1, a plurality of device modules (device modules 2a, 2b, 2c, and 2d in this figure), and a communication bus 3.

[0012] The processor 1 is an arithmetic circuit (for example, an MPU (Micro Processing Unit), an ECU (Electronic Control Unit), etc.) that comprehensively controls the network device 100. The processor 1 includes an oscillator OSC1. The oscillator OSC1 generates a clock signal for communication between the processor 1 and the device modules 2a to 2d.

[0013] Here, the device modules 2a to 2d will be described as having a common configuration, and therefore only the device module 2a will be described, and some of the descriptions of the device modules 2b to 2d will be omitted.

[0014] The device module 2a is an on-board device mounted on a vehicle. Here, as an example, the device module 2a is described as an on-board camera module including an image sensor (an imager 5, which will be described later). The device module 2a generates an electrical signal based on the brightness of an image formed through a lens. The detailed configuration of the device module 2a will be described later.

[0015] The communication bus 3 is a communication path that electrically connects the processor 1 and each of the device modules 2a to 2d so that they can communicate with each other. The communication bus 3 can be compliant with serial communication standards (e.g., I2C [Inter-Integrated Circuit]). In this case, the communication bus 3 is a two-wire system that includes an SDL line that transmits clock signals and an SDA line that transmits data signals (not shown). Note that the signals described below are basically described as indicating data signals, but they may also be interpreted to include clock signals.

[0016] In the normal state (=second state), the processor 1 acts as a controller, and each of the device modules 2a to 2d acts as a target, establishing communication via the communication bus 3. That is, in the normal state, a predetermined signal is input from the processor 1 to each of the device modules 2a to 2d, and in response to this signal, each of the device modules 2a to 2d inputs a predetermined signal to the processor 1. Specifically, this is as follows.

[0017] The processor 1 inputs a communication signal S1 to the device module 2a. The device module 2a then generates a communication signal S2 in response to the communication signal S1 and inputs the communication signal S2 to the processor 1. At this time, the processor 1 acts as the controller and the device module 2a acts as the target. The communication signal S2 includes information corresponding to the communication signal S1 (for example, information regarding the brightness of an image formed through a lens).

[0018] 2 is a block diagram showing the internal configuration of the device module 2a. The device module 2a includes a PMIC (Power Management IC) 4, an imager 5, a communication path 6, and an interface 7.

[0019] The PMIC 4 is a power supply control integrated circuit (IC) that controls the power supply of the device module 2 a. Specifically, the PMIC 4 controls the drive power of the imager 5 and the interface 7.

[0020] The PMIC 4 includes an internal memory 14. The internal memory 14 is a temporary storage area such as a register. The PMIC 4 can generate a signal that includes information stored in the internal memory 14. When communicating with the imager 5 and the interface 7, the PMIC 4 temporarily stores information in the internal memory 14 as necessary.

[0021] The imager 5 is a semiconductor device (not shown) such as an image sensor including a CMOS sensor, a lens, etc. The imager 5 is configured to acquire image information (= information regarding brightness and darkness formed through the lens).

[0022] The imager 5 includes an internal memory 15. The internal memory 15 is configured to be able to store predetermined information (for example, setting information If1, information on various states within the imager 5, environmental information, etc.). The setting information If1 is information for determining the operation of the imager 5 and includes control values. The imager 5 operates based on the setting information If1 stored in the internal memory 15. Specific examples of the setting information If1 include exposure time, gain, resolution (pixel addition, number of thinning-out operations), frame rate, ROI [Region of Interest], various counter values, and other operating modes.

[0023] The communication path 6 is a communication path provided inside the device module 2a. The communication path 6 electrically connects the PMIC 4, the imager 5, and the interface 7 to one another. The communication path 6 complies with serial communication standards (e.g., I2C).

[0024] The interface 7 is electrically connected to the communication path 6 inside the device module 2a. The interface 7 is electrically connected to the processor 1 via the communication bus 3 outside the device module 2a.

[0025] The interface 7 includes a Ser / Des (SERializer / DESerializer) circuit 8. The Ser / Des circuit 8 is capable of serial communication between the PMIC and the imager 5. The Ser / Des circuit 8 is capable of parallel communication between the processor 1 and the device modules 2b to 2c.

[0026] The Ser / Des circuit 8 converts parallel signals input from the communication bus 3 into serial signals and inputs them to the PMIC 4 or the imager 5. The Ser / Des circuit 8 also converts serial signals input from the PMIC 4 or the imager 5 into parallel signals and inputs them to the processor 1 or the device modules 2b to 2c via the communication bus 3.

[0027] <Basic Communication of the Network Device 100> As described above, the processor 1 can communicate with the device modules 2a to 2d via the communication bus 3. The internal configuration of the device module 2a can communicate with the processor 1 via the interface 7. More details are as follows.

[0028] The PMIC 4 and imager 5 can each communicate with the processor 1 via a communication path 6 and an interface 7. When the PMIC 4 and processor 1 communicate, the interface 7 acts as the controller and the PMIC 4 acts as the target, establishing communication. That is, the PMIC 4 communicates with the processor 1 based on the clock signal generated by the oscillator OSC1. Specifically, this is as follows.

[0029] First, the processor 1 inputs a communication signal S1 to the interface 7 via the communication bus 3. The interface 7 then converts the input communication signal S1 into a communication signal S1a using the Ser / Des circuit 8. The interface 7 then inputs the communication signal S1a to the PMIC 4 via the communication path 6. The communication signal S1 is a parallel signal, and the communication signal S1a is a serial signal.

[0030] In response to the communication signal S1a, the PMIC 4 then inputs a communication signal S2a to the interface 7 via the communication path 6. The interface 7 generates a communication signal S2 suitable for the communication bus 3 based on the communication signal S2a, and inputs the communication signal S2 to the processor 1 via the communication bus 3. Note that when the imager 5 communicates with the processor 1, the communication mode between the PMIC 4 and the processor 1 is similar to that described above.

[0031] <Imager Settings Considerations> Next, the setting of an imager will be described, which corresponds to the above-described configuration of the network device 100 and employs a conventional general configuration. In the device employing such a general configuration, a setting signal for setting the imager (corresponding to imager 5) is output from a central processing circuit (corresponding to processor 1). This setting signal is then input to each device module (corresponding to device modules 2a to 2d described above). This setting signal is input to the imager via an interface (corresponding to interface 7). Various settings are made to the imager based on this setting signal.

[0032] However, in a system employing such a configuration, the timing of communication between each of the device modules and the central processing circuit is separate. Specifically, each device module is individually assigned a timing for communication with the central processing circuit so that the timing does not overlap with that of other device modules. Therefore, upon startup, each device module enters a standby state until its assigned timing arrives. Therefore, when simultaneously setting up the imagers of each device module (for example, when initializing the imagers), it may take a relatively long time to complete all the settings.

[0033] To address this problem, the device modules 2a to 2d of the present disclosure are capable of suppressing the length of time required to set up the imager 5. The device module 2a according to each embodiment of the network device 100 will be described in more detail below.

[0034] <Detailed configuration of the device module according to the first embodiment of the present disclosure> 3 is a diagram showing in more detail the internal configuration of the device module 2a according to the first embodiment of the present disclosure. Fig. 3 illustrates a case in which communication is established within the device module 2a, with the PMIC 4 acting as the controller. As shown in Fig. 3, the device module 2a according to the first embodiment of the present disclosure includes a non-volatile memory 10 in addition to the above-described configuration.

[0035] The nonvolatile memory 10 is a memory that can store various types of information in a nonvolatile manner. The nonvolatile memory 10 stores setting information If1.

[0036] The nonvolatile memory 10 is capable of communicating with each of the PMIC 4 and the interface 7 via the communication path 6. The nonvolatile memory 10 is configured to output information stored therein (for example, setting information If1) in response to instructions from each of the PMIC 4 and the interface 7.

[0037] At a predetermined timing (for example, when configuring the imager 5 as described below), the PMIC 4 can communicate with itself as the controller and with the nonvolatile memory 10, the imager 5, and the interface 7 as targets. At another timing (for example, in the normal state described above), the PMIC 4 can communicate with itself as the target and with the interface 7 as the controller. This is explained in detail below.

[0038] In addition to the above-mentioned configuration, the PMIC 4 includes an oscillator OSC2. The oscillator OSC2 generates a clock signal for communication with the non-volatile memory 10, the imager 5, or the interface 7 as a target, with the PMIC 4 acting as a controller.

[0039] When the PMIC 4 is in a state (=first state) where it is configuring the imager 5, it acts as a controller and establishes communication with both the nonvolatile memory 10 and the imager 5. At this time, the PMIC 4 communicates with both the nonvolatile memory 10 and the imager 5 via the communication path 6 based on a clock signal generated by the oscillator OSC2.

[0040] At this time, the PMIC 4 first reads the setting information If1 from the nonvolatile memory 10. Specifically, the PMIC 4 inputs a communication signal S7 to the nonvolatile memory 10 via the communication path 6. In response to the communication signal S6, the nonvolatile memory 10 inputs a communication signal S8 to the PMIC 4 via the communication path 6. The communication signal S8 includes the setting information If1.

[0041] When the PMIC 4 receives the communication signal S8, it writes the setting information If1 included in the communication signal S8 to the internal memory 15 of the imager 5. More specifically, the PMIC 4 receives the communication signal S8 and temporarily stores the setting information If1 included in the communication signal S8 in the internal memory 14. The PMIC 4 then generates a setting signal S9 that includes the setting information If1 stored in the internal memory 14. The PMIC 4 then inputs the setting signal S9 to the imager 5 via the communication path 6. Note that the communication signals S7, S8, and the setting signal S9 are serial signals.

[0042] When the setting signal S9 is input, the imager 5 stores the setting information If1 included in the setting signal S9 in the internal memory 15. This completes the setting of the imager 5. From this point on, the imager 5 operates based on the setting information If1 stored in the internal memory 15. The setting of the imager 5 is performed, for example, when the network device 100 is started up.

[0043] When writing the setting information If1 to the internal memory 15, the PMIC 4 may read all of the bits that make up the setting information If1 and store them in the internal memory 14, and then input a setting signal S9 that includes all of the bits that make up the setting information If1 to the imager 5. In this case, the imager 5 stores the setting information If1 included in the setting signal S9 in the internal memory 15. This completes the setting of the imager 5 in one go.

[0044] Alternatively, the following method may be employed. For example, the PMIC 4 first stores a predetermined number of bits of all bits constituting the setting information If1 in the internal memory 14. The PMIC 4 then temporarily terminates communication with the nonvolatile memory 10. The PMIC 4 then inputs a setting signal S9, including the bits of the setting information If1 stored in the internal memory 14, to the imager 5. The imager 5 then stores the bits of the setting information If1 included in the setting signal S9 in the internal memory 15. Thereafter, the PMIC 4 reads the remaining bits of the setting information If1 from the nonvolatile memory 10 at a predetermined timing and stores them in the internal memory 14. The PMIC 4 then inputs the setting signal S9, including the remaining bits stored in the internal memory 14, to the imager 5. The imager 5 then stores the bits of the setting information If1 included in the setting signal S9 in the internal memory 15. Note that the predetermined number of bits is determined in units of bytes. The number of bytes may be arbitrary.

[0045] As described above, when the PMIC 4 is in the normal state (=second state), it becomes the target and establishes communication with the interface 7. At this time, the PMIC 4 communicates with the processor 1 via the communication bus 3 based on the clock signal generated by the oscillator OSC1 as described above. For example, in this normal state, the processor 1 can read information stored in the nonvolatile memory 10.

[0046] 4 is a diagram showing in more detail the internal configuration of the device module 2a according to the first embodiment of the present disclosure. In this case (= the above-described normal state (second state)), as shown in FIG. 4, the processor 1 (more specifically, the interface 7) acts as the controller, and communication is established with the nonvolatile memory 10 as the target.

[0047] First, the processor 1 inputs a communication signal S10 to the interface 7 via the communication bus 3. The interface 7 then generates a communication signal S10a suitable for the nonvolatile memory 10 based on the communication signal S10. The interface 7 then inputs the communication signal S10a to the nonvolatile memory 10 via the communication path 6.

[0048] In response to the communication signal S10a, the nonvolatile memory 10 inputs a communication signal S11a to the interface 7 via the communication path 6. The interface 7 generates a communication signal S11 suitable for the communication bus 3 based on the communication signal S11a. The interface 7 then inputs the communication signal S11 to the processor 1 via the communication bus 3. At this time, the communication signals S10a and S11a are serial signals, and the communication signals S10 and S11 are parallel signals.

[0049] In this case, the PMIC 4 may read information from the nonvolatile memory 10 and input a signal containing this information to the processor 1 via the communication path 6, the interface 7, and the communication bus 3.

[0050] In this way, the PMIC 4 of the present disclosure is configured to act as the controller when in a state where the imager 5 is being configured (=first state), and to act as the target when in a normal state (=second state), and to be able to communicate with each of the non-volatile memory 10, the imager 5, and the interface 7 (more specifically, the processor 1).

[0051] Similarly, when the interface 7 is in a state where the imager 5 is being configured, the interface 7 itself becomes the target or does not communicate with the PMIC 4. In addition, in the normal state, the interface 7 itself becomes the controller and is configured to be able to communicate with both the non-volatile memory 10 and the imager 5.

[0052] As described above, the imager 5 is configured based on the configuration signal S7 output from the PMIC 4 (see FIG. 3). That is, when configuring the imager 5, communication between the device module 2a and the processor 1 is not required. This allows the configuration of the imager 5 to be completed within the device module 2a. Therefore, even when the imagers 5 of the device modules 2a to 2d are configured simultaneously, each of the device modules 2a to 2d can configure its own imager 5 without waiting for the timing of communication with the processor 1. In this way, the device modules 2a to 2d of the present disclosure can prevent the time required for configuring the imager 5 from becoming too long.

[0053] As described above, the communication path 6 is an existing communication path that electrically connects the PMIC 4, nonvolatile memory 10, imager 5, and interface 7 so that they can communicate with each other under normal conditions. Therefore, there is no need to provide a new communication path between the PMIC 4 and imager 5 for configuring the imager 5. Therefore, the device modules 2a to 2d of the present disclosure can suppress increases in circuit area and manufacturing costs.

[0054] <Detailed configuration of the device module according to the second embodiment of the present disclosure> Next, a device module 2a according to a second embodiment of the present disclosure will be described in detail. The device module 2a according to this embodiment has a configuration common to the device module 2a according to the first embodiment described above. Therefore, the common configuration will be denoted by the same reference numerals as those in the first embodiment, and a description thereof will be omitted. The same applies to the device modules 2b to 2d.

[0055] 5 is a diagram showing in more detail the configuration of the device module 2a according to the second embodiment. As shown in FIG. 5, the PMIC 4 according to this embodiment further includes an internal memory 16 in addition to the internal memory 14. The internal memory 16 is a non-volatile memory (e.g., OTP [One Time Programmable], MTP [Multiple Time Programmable], etc.). The internal memory 16 stores setting information If1.

[0056] 5, when the imager 5 is being configured, the PMIC 4 acts as the controller and the imager 5 acts as the target to establish communication. In this state, the interface 7 can also act as the target as necessary.

[0057] When configuring the imager 5, the PMIC 4 according to this embodiment reads the configuration information If1 from the internal memory 16 and writes it to the internal memory 15 of the imager 5. More specifically, the PMIC 4 first reads the configuration information If1 from the internal memory 16 and generates a configuration signal S9. The PMIC 4 then inputs the configuration signal S9 to the imager 5 via the communication path 6. While reading the configuration information If1 from the internal memory 16, the PMIC 4 also generates a configuration signal S9 that includes the sequentially read configuration information If1 and inputs the signal to the imager 5.

[0058] When the setting signal S9 is input, the imager 5 stores the setting information If1 included in the setting signal S9 in the internal memory 15. This completes the setting of the imager 5. From this point on, the imager 5 will operate based on the setting information If1 stored in the internal memory 15.

[0059] As described above, the PMIC 4 of this embodiment includes the internal memory 16. The PMIC 4 reads the setting information If1 from the internal memory 16 and writes it to the imager 5. This eliminates the need to provide an external nonvolatile memory for storing the setting information If1 to the PMIC 4. This allows the circuit area of ​​the device module 2a to be reduced.

[0060] As described above, the PMIC 4 of this embodiment inputs the setting signal S9 to the imager 5 simultaneously with reading the setting information If1. This allows the amount of setting information If1 temporarily stored in the internal memory 14 to be relatively small. This allows the capacity of the internal memory 14 to be relatively small, thereby reducing the circuit area of ​​the PMIC 4.

[0061] <Regarding the vehicle 200 equipped with the network device 100> Next, a vehicle 200 equipped with the above-described network device 100 will be described. FIG. 6 is a block diagram showing the configuration of the vehicle 200 equipped with the network device 100. As shown in FIG. 6, the network device 100 can be mounted on the vehicle 200. The network device 100 includes an ECU 20, device modules 2a to 2d, and a communication bus 3. The ECU 20 corresponds to the above-described processor 1. The ECU 20 is electrically connected to the device modules 2a to 2d via the communication bus 3.

[0062] Device module 2a is disposed at the front (forward) of vehicle 200. Device module 2a captures images of the front side. Device module 2b is disposed at the right side of vehicle 200. Device module 2b captures images of the right side. Device module 2c is disposed at the left side of vehicle 200. Device module 2c captures images of the left side. Device module 2d is disposed at the rear (rear) of vehicle 200. Device module 2d captures images of the rear side.

[0063] Each of the device modules 2a to 2d converts the captured image into an imaging signal and outputs it to the ECU 20. This allows the ECU 20 to capture 360-degree (omnidirectional) images of the front, left, right, and rear of the vehicle 200.

[0064] <Modification> Additionally, the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure. For example, in the above-described embodiments, the device modules 2b to 2d are the same as the device module 2a, but this is not limited to this. For example, each of the device modules 2b to 2d may be an in-vehicle camera module equivalent to the device module 2a, or may be a device module with other functions. In this case, the device modules 2b to 2d are capable of communicating with the processor 1 in a manner in which they themselves are targets and the processor 1 is a controller, similar to the above-described device module 2a.

[0065] The setting of the imager 5 by the setting signal S9 as described above can also be applied to other settings besides the initial setting. For example, when changing the settings of the imager 5 at a predetermined timing after starting up the network device 100, the setting signal S9 may be input from the PMIC 4 to the imager 5 as described above to change the settings of the imager 5.

[0066] <Additional Notes> The device modules (2a to 2d) disclosed in the specification include a communication path (6), a semiconductor device (5) connected to the communication path (6) and configured to operate based on setting information (If1), an interface (7) connected to the communication path (6) and configured to establish communication between a first control unit (1) and multiple targets connected to the communication path (6), and a second control unit (4) connected to the communication path (6) and configured to operate in a first state in which the second control unit (4) serves as a controller and communicates with the semiconductor device (5) as a target, or in a second state in which the second control unit (4) serves as a target and communicates with the first control unit (1) via the interface (7), with the interface (7) serving as a controller, and the second control unit (4) configured to generate a setting signal (S9) including the setting information (If1) in the first state and input it to the semiconductor device (5) (first configuration).

[0067] The device modules (2a to 2d) according to the first configuration may include a non-volatile memory (10) storing setting information (If1), and the second control unit (4) may be configured to read the setting information (If1) stored in the non-volatile memory (10) via the communication path (6) in the first state and generate a setting signal (S9) (second configuration).

[0068] In the device modules (2a to 2d) according to the second configuration, the second control unit (4) may be configured to simultaneously read out the setting information (If1) from the nonvolatile memory (10) and input the setting signal (S9) to the semiconductor device (5) at least temporarily in the first state (third configuration).

[0069] In the device module (2a to 2d) according to any one of the first to third configurations, the second control unit (4) may be configured to have an internal memory in which setting information (If1) is stored, and to read the setting information (If1) from the internal memory in the first state to generate a setting signal (S9) (fourth configuration).

[0070] In the device module (2a to 2d) according to any one of the first to fourth configurations, the setting information (If1) includes a plurality of bits, and the second control unit (4) is configured to generate a setting signal (S9) including a portion of all the bits in the first state and input it to the semiconductor device (5) (fifth configuration).

[0071] The device modules (2a to 2d) according to the fifth configuration may be configured such that some of them are a plurality of bits organized in byte units (sixth configuration).

[0072] In the device module (2a to 2d) according to the fifth configuration, the semiconductor device (5) is an image sensor configured to capture an image based on setting information, and functions as a camera module (sixth configuration).

[0073] The network device (100) disclosed in the specification is configured to include device modules (2a to 2d) according to any one of the first to seventh configurations, a first control unit (1), and a communication bus (3) that electrically connects the device modules (2a to 2d) and the first control unit (1) so as to establish communication between the device modules (2a to 2d) and the first control unit (1) via an interface (7) (eighth configuration).

[0074] The network device (100) according to the eighth configuration may be configured to include a plurality of device modules (2a to 2d) (ninth configuration).

[0075] The vehicle (200) is configured to include the network device (100) according to the eighth or ninth configuration (tenth configuration). [Explanation of symbols]

[0076] 1 processor (first control unit) 2a~2d Device modules 3 Communication Bus 4 PMIC4 (second control unit) 5 Imager (semiconductor device) 6. Communication Path 7 Interface 8 Ser / Des circuits 10 Non-volatile memory 14 Internal Memory 15 Imager 15 Internal Memory 16 internal memory 20 ECU 100 Network Devices 200 vehicles IC power control If1 setting information OSC1 oscillator OSC2 oscillator S1, S7, S8, S10, S11, S1a, S2a, S10a, S11a communication signal S9 Setting signal

Claims

1. A communication path; a semiconductor device connected to the communication path and configured to operate based on input setting information; an interface connected to the communication path and configured to establish communication between a first controller and a plurality of targets connected to the communication path; a second control unit connected to the communication path and configured to operate in a first state in which the second control unit acts as a controller and communicates with the semiconductor device, with the semiconductor device as a target, or in a second state in which the second control unit acts as a target and communicates with the first control unit via the interface, with the interface as a controller; Equipped with The second control unit is a device module that generates a setting signal including the setting information in the first state and inputs the setting signal to the semiconductor device.

2. a nonvolatile memory that stores the setting information; The device module according to claim 1 , wherein in the first state, the second control unit reads out the setting information stored in the nonvolatile memory via the communication path and generates the setting signal.

3. The device module according to claim 2 , wherein the second control unit simultaneously reads the setting information from the nonvolatile memory and inputs the setting signal to the semiconductor device at least temporarily in the first state.

4. The device module according to claim 1 , wherein the second control unit has an internal memory in which the setting information is stored, and in the first state, reads the setting information from the internal memory to generate the setting signal.

5. the configuration information includes a plurality of bits, The device module according to claim 1 , wherein in the first state, the second control unit generates the setting signal including a part of all the bits and inputs the setting signal to the semiconductor device.

6. The device module according to claim 5 , wherein the part is a plurality of the bits organized in byte units.

7. the semiconductor device is an image sensor configured to capture an image based on the setting information, The device module according to claim 1 , which functions as a camera module.

8. A device module according to any one of claims 1 to 7; the first control unit; a communication bus electrically connecting the device module and the first controller so as to establish communication between the device module and the first controller via the interface; A network device comprising:

9. The network device according to claim 8 , comprising a plurality of the device modules.

10. A vehicle comprising the network device according to claim 8.

Images