Nitride semiconductor device

Abstract

To provide a nitride semiconductor device having improved short-circuit resistance.SOLUTION: A nitride-semiconductor device 100 includes first and second transistors 10T1 and 10T2 composed of nitride semiconductors. The first gate electrodes 10T1 of the first transistors 24G1 and the second drain electrodes 10T2 of the second transistors 30D2 are connected to gate terminals Tg. The first drain electrodes 10T1 of the first transistors 30D1 are connected to drain terminals Td. The first source electrodes 10T1 of the first transistors 28S1 are connected to the source terminals Ts via resistive elements R1. A second source electrode 10T2 of the second transistor 28S2 is connected to the source connection Ts, and a second gate electrode 10T2 of the second transistor 24G2 is connected to a node 28S1 between the first source electrode R1 and the resistive component N1.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel) (see, for example, Patent Document 1). Power devices using HEMTs are recognized as devices that have lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-116995

[0004] [overview] HEMTs are transistors with a horizontal structure in which current flows horizontally through a 2DEG generated near the surface of the electron transport layer. For this reason, HEMTs have a lower short-circuit resistance than vertical transistors, such as those using Si or silicon carbide (SiC), in which current flows vertically through the entire silicon.

[0005] A nitride semiconductor device according to one embodiment of the present disclosure includes a first transistor and a second transistor. The first transistor is made of a nitride semiconductor and includes a first gate electrode, a first source electrode, and a first drain electrode. The second transistor is made of a nitride semiconductor and includes a second gate electrode, a second source electrode, and a second drain electrode. The nitride semiconductor device further includes a gate terminal connected to the first gate electrode and the second drain electrode, a drain terminal connected to the first drain electrode, and a source terminal connected to the first source electrode via a resistive element. The second source electrode is connected to the source terminal, and the second gate electrode is connected to a node between the first source electrode and the resistive element. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view of the transistor chip shown in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of a first transistor and a second transistor as an exemplary HEMT structure formed on the transistor chip of FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a portion of the first transistor shown on the left side of FIG. [Figure 5] FIG. 5 is an enlarged cross-sectional view of a portion of the second transistor shown on the right side of FIG. [Figure 6] FIG. 6 is a schematic plan view showing an exemplary planar layout of the first transistor and the second transistor. [Figure 7] FIG. 7 is a partial enlarged plan view of the first transistor shown in FIG. [Figure 8] FIG. 8 is a partial enlarged plan view of the second transistor shown in FIG. [Figure 9] FIG. 9 is a schematic circuit diagram of the nitride semiconductor device according to the first embodiment including the first transistor and the second transistor. [Figure 10] FIG. 10 is a schematic circuit diagram of a nitride semiconductor device according to the second embodiment including a first transistor, a second transistor, and a third transistor. [Figure 11] FIG. 11 is a schematic plan view showing an exemplary planar layout of the first transistor, the second transistor, and the third transistor.

[0007] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] As used in this disclosure, terms such as "first," "second," and "third" are used merely to distinguish between objects and not to rank them. For example, in a structure including a first element and a second element, a claim may refer to the second element without referring to the first element. Also, in a structure in which a first element includes a first sub-element and a second element includes a second sub-element, a claim may refer to the second sub-element of the second element without referring to the first sub-element of the first element.

[0009] Additionally, the phrase "at least one" used in this disclosure means one or more of a desired plurality of options. As an example, if the number of options is two, the phrase "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the phrase "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [First embodiment] A nitride semiconductor device 100 according to a first embodiment will be described with reference to FIGS. 1 to 9. In the present disclosure, components will be described based on mutually orthogonal X, Y, and Z axes shown in the drawings. The term "plan view" used in the present disclosure refers to viewing the nitride semiconductor device 100 in the Z-axis direction, unless explicitly stated otherwise. In the following description, for convenience, the +Z direction may be referred to as up, the -Z direction as down, the +X direction as right, and the -X direction as left in the nitride semiconductor device 100 shown in FIG. 1. However, the up, down, left, and right directions of the nitride semiconductor device 100 are not limited to these orientations.

[0012] [1-1. Package Structure of Nitride Semiconductor Device] FIG. 1 is a schematic plan view of a nitride semiconductor device 100 having a surface-mount package structure as an example. FIG. 1 also shows the internal structure of the package of the nitride semiconductor device 100. The nitride semiconductor device 100 includes a transistor chip 101. FIG. 2 is a plan view of the transistor chip 101 shown in FIG. 1.

[0013] 1, a nitride semiconductor device 100 includes a plurality of electrode pads arranged on a transistor chip 101. The plurality of electrode pads include one or a plurality (one in the example of FIG. 1) of gate pads 102, a plurality (two in the example of FIG. 1) of source pads 103, and a plurality (two in the example of FIG. 1) of drain pads 104. Note that the number and arrangement of the gate pads 102, source pads 103, and drain pads 104 are not limited to those illustrated in FIG. 1.

[0014] The nitride semiconductor device 100 includes a plurality of connection members. The plurality of connection members include a plurality (two in the example of FIG. 1 ) of first source connection members 121, a plurality (two in the example of FIG. 1 ) of drain connection members 122, and one or more (one in the example of FIG. 1 ) of gate connection members 123. The plurality of connection members may further include one or more (one in the example of FIG. 1 ) second source connection members 124. Each of the plurality of first source connection members 121 is electrically connected to one of the plurality of source pads 103, and each of the plurality of drain connection members 122 is electrically connected to one of the plurality of drain pads 104. The gate connection member 123 is electrically connected to the gate pad 102. The second source connection member 124 is electrically connected to one of the plurality of source pads 103. In the example of FIG. 1 , the second source connection member 124 is connected to the source pad 103 closest to the gate pad 102 (located at the right end in FIG. 1 ). The number and arrangement of the first source connecting members 121, the drain connecting members 122, the gate connecting members 123, and the second source connecting members 124 are not limited to those illustrated in FIG.

[0015] The nitride semiconductor device 100 includes a plurality of lead frames, which include a source lead frame 131, a drain lead frame 132, a gate lead frame 133, and a die pad .

[0016] The source lead frame 131 is electrically connected to the first source connection member 121 and the second source connection member 124. In the example of FIG. 1, the source lead frame 131 includes a first source lead frame 131A and a second source lead frame 131B that are separated from each other. The first source lead frame 131A is connected to the first source connection member 121, and the second source lead frame 131B is connected to the second source connection member 124. However, the first source lead frame 131A and the second source lead frame 131B do not necessarily need to be separated from each other and may be integrally formed and connected to each other. The drain lead frame 132 is electrically connected to the drain connection member 122, and the gate lead frame 133 is electrically connected to the gate connection member 123. The gate lead frame 133 is disposed adjacent to, for example, closely adjacent to, the second source lead frame 131B.

[0017] The die pad 134 is disposed between the source lead frame 131 and the drain lead frame 132. The source lead frame 131 and the gate lead frame 133 are located adjacent to one side of the die pad 134, and the drain lead frame 132 is located adjacent to the other side (opposite side) of the die pad 134. The transistor chip 101 is mounted on the die pad 134.

[0018] The nitride semiconductor device 100 further includes a sealing resin 105 that seals the transistor chip 101. For ease of understanding, only the outline of the sealing resin 105 is shown in FIG.

[0019] [1-2. Electrode pads] The electrode pads provided as the gate pad 102, the source pad 103, and the drain pad 104 are formed of at least one conductive material selected from the group consisting of titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), an AlCu alloy, nickel (Ni), and gold (Au). For example, the electrode pads may have a laminated structure including a metal layer and a plating layer covering the metal layer. In this case, the metal layer may have a four-layer structure including, from the top, a Ti layer, a TiN layer, an AlCu layer, and a TiN layer. The plating layer may have a structure in which a Cu layer, a Ni layer, and an Au layer are laminated in this order on the metal layer.

[0020] As shown in FIG. 2, the gate pad 102 may have a rectangular shape (e.g., a square shape) in a plan view. The gate pad 102 is located, for example, near one corner of a transistor chip 101 that has a rectangular shape in a plan view. The multiple source pads 103 and the multiple drain pads 104 are spaced apart from each other and arranged alternately one by one in one direction (the X-axis direction in FIG. 2). For ease of explanation, hereinafter, the direction in which the source pads 103 and the drain pads 104 are arranged alternately in a plan view (the X-axis direction) will be referred to as a first direction X, and the direction perpendicular to the first direction X in a plan view (the Y-axis direction) will be referred to as a second direction Y.

[0021] The multiple source pads 103 may have the same or different shapes and sizes in a plan view. In the example of Fig. 1, the multiple source pads 103 include a first source pad 103A located close to the gate pad 102 and one or more (one in the example of Fig. 2) second source pads 103B located farther from the gate pad 102 than the first source pad 103A. The first source pad 103A may have a different shape from the second source pad 103B.

[0022] For example, the first source pad 103A includes a main region 103A1 and an extension region 103A2 extending from the main region 103A1 toward the gate pad 102. In the first source pad 103A, the main region 103A1 has a rectangular shape elongated in the second direction Y. The extension region 103A2 extends in the first direction X from one end of the main region 103A1 in its longitudinal direction (second direction Y). The first source pad 103A has, for example, an L-shape as a whole. The extension region 103A2 is adjacent to but spaced apart from the gate pad 102 in the first direction X. The second source pad 103B has, for example, a rectangular shape elongated in the second direction Y, i.e., a shape similar to the main region 103A1 of the first source pad 103A.

[0023] The multiple drain pads 104 may have the same or different shapes and sizes in a plan view. In the example of Fig. 1, the multiple drain pads 104 include a first drain pad 104A located close to the gate pad 102 and one or more (one in the example of Fig. 2) second drain pads 104B located farther from the gate pad 102 than the first drain pad 104A. For example, the first drain pad 104A has the same shape as the second drain pad 104B but is smaller in size than the second drain pad 104B.

[0024] For example, the first drain pad 104A has a rectangular shape that is elongated in the second direction Y. Similarly, the second drain pad 104B has a rectangular shape that is elongated in the second direction Y. The first drain pad 104A has a dimension that is shorter in the second direction Y than the second drain pad 104B. Furthermore, the first drain pad 104A has a dimension that is shorter in the second direction Y than the source pad 103 (first and second source pads 103A, 103B). One end of the first drain pad 104A in the longitudinal direction (second direction Y) is adjacent to but spaced apart from the extension region 103A2 of the gate pad 102 and the first source pad 103A in the second direction Y.

[0025] [1-3. Lead frame] The source lead frame 131, the drain lead frame 132, the gate lead frame 133, and the die pad 134 are formed of, for example, Cu or an alloy containing Cu. These lead frames will be described in detail below with reference to FIG.

[0026] As described above, the source lead frame 131 includes the first source lead frame 131A and the second source lead frame 131B. The same potential is applied to the first and second source lead frames 131A and 131B. For example, a ground voltage is applied to the first and second source lead frames 131A and 131B. The first source lead frame 131A includes multiple (two in the example of FIG. 1) lead ends 131E1 and 131E2 that are extended outside the package (on the outer surface of the nitride semiconductor device 100) as a source terminal Ts (see FIG. 9). The second source lead frame 131B includes a lead end 131E3 that is extended outside the package as a Kelvin source terminal Tks (see FIG. 9). In one example, the back surfaces of the lead ends 131E1 and 131E2 (the back side of the paper in FIG. 1) are exposed from the sealing resin 105 as the source terminal Ts. Similarly, the back surface of the lead end 131E3 is exposed from the sealing resin 105 as a Kelvin source terminal Tks.

[0027] The first source lead frame 131A and the second source lead frame 131B are adjacent to each other in the first direction X in which the first source pad 103A and the second source pad 103B are aligned. The first source lead frame 131A is disposed in a position facing all the source pads 103 (i.e., the first and second source pads 103A and 103B) in the second direction Y. Note that the first source lead frame 131A faces the main region 103A1 (see FIG. 2) of the first source pad 103A in the second direction Y, but does not face the extension region 103A2 (see FIG. 2) of the first source pad 103A in the second direction Y.

[0028] The first source lead frame 131A is electrically connected to the source pad 103 by a first source connection member 121. In the example of Fig. 1, the first and second source pads 103A, 103B are each electrically connected to the first source lead frame 131A by one of the multiple first source connection members 121. Therefore, a ground voltage is applied to the first and second source pads 103A, 103B via the first source lead frame 131A and each of the first source connection members 121.

[0029] The second source lead frame 131B faces the extension region 103A2 (see FIG. 2) of the first source pad 103A in the second direction Y. The second source lead frame 131B may face a part of the main region 103A1 (see FIG. 2) of the first source pad 103A in the second direction Y. The second source lead frame 131B is electrically connected to the extension region 103A2 of the first source pad 103A by the second source connecting member 124. Therefore, a ground voltage is applied to the first source pad 103A via the second source lead frame 131B and the second source connecting member 124.

[0030] A given power supply voltage is applied to the drain lead frame 132. The drain lead frame 132 includes a plurality of lead ends 132E1, 132E2, 132E3, and 132E4 (four in the example of FIG. 1) that are drawn out of the package as drain terminals Td (see FIG. 9). In one example, the back surfaces of the lead ends 132E1 to 132E4 are exposed from the sealing resin 105 as the drain terminals Td. The drain lead frame 132 is electrically connected to the drain pad 104 by drain connection members 122. In the example of FIG. 1, the first and second drain pads 104A and 104B are each electrically connected to the drain lead frame 132 by one of the plurality of drain connection members 122. Therefore, a power supply voltage is applied to the first and second drain pads 104A and 104B via the drain lead frame 132 and each of the drain connection members 122.

[0031] A given gate control voltage is applied to the gate lead frame 133. The gate lead frame 133 includes a lead end 133E that is drawn out of the package as a gate terminal Tg (see FIG. 9). In one example, the back surface of the lead end 133E is exposed from the sealing resin 105 as the gate terminal Tg. The gate lead frame 133 is electrically connected to the gate pad 102 by a gate connection member 123. Therefore, a gate control voltage is applied to the gate pad 102 via the gate lead frame 133 and the gate connection member 123. The gate lead frame 133 is provided adjacent to but spaced apart from the second source lead frame 131B in the first direction X.

[0032] As described above, the die pad 134 is provided as a mounting portion for the transistor chip 101. The die pad 134 also functions as a heat dissipation member for dissipating heat generated in the transistor chip 101 to the outside. The die pad 134 has a rectangular shape in a plan view, and has, for example, a size equal to or larger than that of the transistor chip 101. The transistor chip 101 is mounted on the die pad 134 with a conductive bonding material (not shown) such as solder or a conductive paste (for example, silver (Ag) paste).

[0033] [1-4. Connecting parts] The first source connection member 121, the drain connection member 122, the gate connection member 123, and the second source connection member 124 are formed of any conductive member (conductive material). In the example of FIG. 1, the first source connection member 121 and the drain connection member 122 are formed of a bridge-shaped conductive member. Such a bridge-shaped conductive member may be called a conductive clip or simply a clip. An example of a clip material is Cu, and a clip made of Cu may be called a Cu clip. On the other hand, the gate connection member 123 and the second source connection member 124 are conductive wires (bonding wires) formed by a wire bonding apparatus and are formed of a conductor such as Au, Al, or Cu.

[0034] Compared to wires, clips have advantages such as large current capacity, low resistance, low inductance, and high heat dissipation. Because the first source connecting member 121 and the drain connecting member 122 are located on the current path between the drain and the source, by using clips for the first source connecting member 121 and the drain connecting member 122, it is possible to take advantage of the above advantages and create a structure suitable for power transistor applications.

[0035] On the other hand, wires have advantages over clips, such as ease of mounting and high design freedom. By using wires for the gate connecting member 123 and the second source connecting member 124, it is possible to easily mount the gate connecting member 123 and the second source connecting member 124 while flexibly responding to changes in the size of the transistor chip 101 and changes in the relative positions among the source pad 103, source lead frame 131, gate pad 102, and gate lead frame 133.

[0036] 1, clips are used for the first source connecting member 121 and the drain connecting member 122, but wires may be used for at least one of the first source connecting member 121 and the drain connecting member 122. In addition, in the example of FIG. 1, wires are used for the gate connecting member 123 and the second source connecting member 124, but clips may be used for at least one of the gate connecting member 123 and the second source connecting member 124.

[0037] [1-5.Transistor Structure] Next, an exemplary transistor structure of the nitride semiconductor device 100 will be described with reference to FIGS. 3 to 5. FIG. 3 is a schematic cross-sectional view of a transistor structure formed in a transistor chip 101 (see FIG. 1). The nitride semiconductor device 100 includes a first transistor 10T1 located in a first transistor region RT1 and a second transistor 10T2 located in a second transistor region RT2. The first transistor 10T1 and the second transistor 10T2 are provided in the same transistor chip 101. The first and second transistors 10T1 and 10T2 are each formed as a HEMT using a nitride semiconductor, and in one example, the first and second transistors 10T1 and 10T2 are each a GaN-HEMT.

[0038] Fig. 4 is a partially enlarged cross-sectional view of the first transistor 10T1 shown on the left side of Fig. 3, and Fig. 5 is a partially enlarged cross-sectional view of the second transistor 10T2 shown on the right side of Fig. 3. For clarity, some of the components shown in Fig. 3 are omitted in Fig. 4 and Fig. 5. Below, the components of each of the first and second transistors 10T1 and 10T2 will be described with reference to Figs. 3 to 5.

[0039] 3, the nitride semiconductor device 100 includes a semiconductor substrate 12 and a buffer layer 14 located on the semiconductor substrate 12. The nitride semiconductor device 100 further includes an electron transit layer 16 and an electron supply layer 18 located on the electron transit layer 16. A back surface electrode 11 bonded to a die pad 134 is provided on the lower surface (back surface) of the semiconductor substrate 12.

[0040] The semiconductor substrate 12 may be formed of Si, SiC, GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 is a conductive Si substrate. The semiconductor substrate 12 may have a thickness of, for example, 100 μm to 1500 μm. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0041] The buffer layer 14 includes one or more nitride semiconductor layers. The electron transport layer 16 is located on the buffer layer 14. The buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transport layer 16.

[0042] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different Al compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0043] The electron transit layer 16 may be, for example, a GaN layer. The electron transit layer 16 may have a thickness of, for example, 0.5 μm or more and 2 μm or less. To suppress leakage current in the electron transit layer 16, impurities may be introduced into a portion of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the impurity concentration in the electron transit layer 16 may be, for example, 4×10 16 cm -3 It can be more than that.

[0044] The electron supply layer 18 has a larger band gap than the electron transit layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. For example, the electron supply layer 18 is an Al GaN layer with an Al composition ratio X. X Ga (1-X)It is composed of N. The Al composition ratio X may be 0.1 < X < 0.4, and preferably may be 0.1 < X < 0.3. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the electron supply layer 18 is 8 nm or more.

[0045] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a lattice-mismatched heterojunction. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo polarization caused by the crystal strain near the heterojunction interface, the energy level of the conduction band of the electron transport layer 16 near the heterojunction interface becomes lower than the Fermi level. As a result, 2DEG20 spreads in the electron transport layer 16 at a position close to the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0046] The nitride semiconductor device 100 further includes a first gate layer 22G1 located on the electron supply layer 18 and a first gate electrode 24G1 located on the first gate layer 22G1. The first gate layer 22G1 is partially provided on the electron supply layer 18. The first gate layer 22G1 is located in the first transistor region RT1.

[0047] The nitride semiconductor device 100 further includes a second gate layer 22G2 located on the electron supply layer 18 and a second gate electrode 24G2 located on the second gate layer 22G2. The second gate layer 22G2 is partially provided on the electron supply layer 18. The second gate layer 22G2 is located in the second transistor region RT2.

[0048] The first and second gate layers 22G1 and 22G2 are made of a nitride semiconductor containing acceptor-type impurities. For example, the first and second gate layers 22G1 and 22G2 may each be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the first and second gate layers 22G1 and 22G2 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 In one example, the first and second gate layers 22G1 and 22G2 are each GaN containing at least one of Mg and Zn as an impurity.

[0049] The first and second gate electrodes 24G1 and 24G2 each include one or more metal layers. In one example, the first and second gate electrodes 24G1 and 24G2 are each TiN layers. In another example, the first and second gate electrodes 24G1 and 24G2 each include a first metal layer made of Ti and a second metal layer formed of TiN and located on the first metal layer. The first gate electrode 24G1 forms a Schottky junction with the first gate layer 22G1. The first gate electrode 24G1 is partially disposed on the first gate layer 22G1. Similarly, the second gate electrode 24G2 forms a Schottky junction with the second gate layer 22G2. The second gate electrode 24G2 is partially disposed on the second gate layer 22G2. The first and second gate electrodes 24G1 and 24G2 may each have a thickness of, for example, 50 nm to 200 nm.

[0050] The nitride semiconductor device 100 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the first and second gate layers 22G1 and 22G2, and the first and second gate electrodes 24G1 and 24G2. The passivation layer 26 is formed of at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON), for example. In one example, the passivation layer 26 is formed of a material containing SiN. The passivation layer 26 may have a thickness of, for example, 80 nm to 150 nm.

[0051] 4, in the first transistor region RT1, the passivation layer 26 includes a first source opening 26S1 and a first drain opening 26D1 that are spaced apart from each other in the first direction X. The first gate layer 22G1 is located between the first source opening 26S1 and the first drain opening 26D1 in the first direction X. The first gate layer 22G1 is located closer to the first source opening 26S1 than the first drain opening 26D1.

[0052] The nitride semiconductor device 100 includes a first source electrode 28S1 in contact with the electron supply layer 18 through the first source opening 26S1 and a first drain electrode 30D1 in contact with the electron supply layer 18 through the first drain opening 26D1. The first source electrode 28S1 and the first drain electrode 30D1 may each include one or more metal layers. For example, the first source electrode 28S1 and the first drain electrode 30D1 may each be formed by combining two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. In one example, the first source electrode 28S1 and the first drain electrode 30D1 each have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including, from the top surface side, a Ti layer, an AlCu layer, a Ti layer, and a TiN layer. The first source electrode 28S1 and the first drain electrode 30D1 are located in the first transistor region RT1.

[0053] The first source electrode 28S1 includes a first source contact portion 28SC1 that fills the first source opening 26S1 and is in contact with the electron supply layer 18, and a first source field plate portion 28SF1 that is formed integrally with the first source contact portion 28SC1 and is located on the passivation layer 26. The first source contact portion 28SC1 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the first source opening 26S1.

[0054] The first source field plate portion 28SF1, for example, entirely covers the first gate electrode 24G1 and the first gate layer 22G1. The first source field plate portion 28SF1 includes a first field plate end portion 28E1 facing the first drain electrode 30D1. The first source field plate portion 28SF1 serves to alleviate electric field concentration near the end portion of the first gate layer 22G1 when a high voltage is applied between the source and drain of the first transistor 10T1 in an off state in which the 2DEG 20 in the region of the electron transit layer 16 directly below the first gate layer 22G1 has disappeared.

[0055] The first drain electrode 30D1 includes a first drain contact portion 30DC1 that fills the first drain opening 26D1 and is in contact with the electron supply layer 18. The first drain contact portion 30DC1 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first drain opening 26D1.

[0056] The first transistor 10T1 is composed of the electron transit layer 16 of the first transistor region RT1, the electron supply layer 18 of the first transistor region RT1, the first gate layer 22G1, the first gate electrode 24G1, the first source electrode 28S1, and the first drain electrode 30D1. In other words, the first transistor region RT1 can be referred to as the region where the components of the first transistor 10T1 are arranged.

[0057] 5, in the second transistor region RT2, the passivation layer 26 includes a second source opening 26S2 and a second drain opening 26D2 that are spaced apart from each other in the first direction X. The second gate layer 22G2 is located between the second source opening 26S2 and the second drain opening 26D2 in the first direction X. The second gate layer 22G2 is located closer to the second source opening 26S2 than the second drain opening 26D2.

[0058] The nitride semiconductor device 100 includes a second source electrode 28S2 in contact with the electron supply layer 18 through the second source opening 26S2, and a second drain electrode 30D2 in contact with the electron supply layer 18 through the second drain opening 26D2. The second source electrode 28S2 and the second drain electrode 30D2 may be formed using a material similar to the material of the first source electrode 28S1 and the first drain electrode 30D1 described above. The second source electrode 28S2 and the second drain electrode 30D2 are located in the second transistor region RT2.

[0059] The second source electrode 28S2 includes a second source contact portion 28SC2 that fills the second source opening 26S2 and is in contact with the electron supply layer 18, and a second source field plate portion 28SF2 that is formed integrally with the second source contact portion 28SC2 and is located on the passivation layer 26. The second source contact portion 28SC2 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the second source opening 26S2.

[0060] The second source field plate portion 28SF2, for example, entirely covers the second gate electrode 24G2 and the second gate layer 22G2. The second source field plate portion 28SF2 includes a second field plate end portion 28E2 facing the second drain electrode 30D2. The second source field plate portion 28SF2 serves to alleviate electric field concentration near the end portion of the second gate layer 22G2 when a high voltage is applied between the source and drain of the second transistor 10T2 in an off state in which the 2DEG 20 in the region of the electron transit layer 16 directly below the second gate layer 22G2 has disappeared.

[0061] The second drain electrode 30D2 includes a second drain contact portion 30DC2 that fills the second drain opening 26D2 and is in contact with the electron supply layer 18. The second drain contact portion 30DC2 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first drain opening 26D1.

[0062] The second transistor 10T2 is composed of the electron transit layer 16 of the second transistor region RT2, the electron supply layer 18 of the second transistor region RT2, the second gate layer 22G2, the second gate electrode 24G2, the second source electrode 28S2, and the second drain electrode 30D2. In other words, the second transistor region RT2 can be referred to as the region where the components of the second transistor 10T2 are arranged.

[0063] In the first transistor 10T1, the first gate layer 22G1 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. Therefore, in the region immediately below the first gate layer 22G1, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. As a result, when a gate control voltage that turns off the first transistor 10T1 is applied to the first gate electrode 24G1 (for example, when the gate-source voltage is 0 V or lower), a 2DEG 20 is not formed in the region of the electron transit layer 16 immediately below the first gate layer 22G1. On the other hand, a 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the first gate layer 22G1.

[0064] In this way, the presence of the first gate layer 22G1 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region of the electron transit layer 16 immediately below the first gate layer 22G1, thereby achieving normally-off operation of the first transistor 10T1. When an appropriate gate control voltage (on voltage) is applied to the first gate electrode 24G1, a channel is formed by the 2DEG 20 in the region of the electron transit layer 16 immediately below the first gate layer 22G1, establishing electrical conduction between the source and drain.

[0065] Similarly, in the second transistor 10T2, the second gate layer 22G2 contains acceptor-type impurities, and therefore, the second transistor 10T2 also achieves normally-off operation based on the same principle as in the first transistor 10T1. The electrical connection structure of the first and second transistors 10T1 and 10T2 will be described later.

[0066] 3, the nitride semiconductor device 100 further includes a first insulating layer 32, a wiring layer 34 located on the first insulating layer 32, a second insulating layer 36 located on the first insulating layer 32 so as to cover the wiring layer 34, and an electrode layer 38 located on the second insulating layer 36. The first insulating layer 32 is located on the passivation layer 26 so as to cover the first and second source electrodes 28S1, 28S2 and the first and second drain electrodes 30D1, 30D2.

[0067] The first and second insulating layers 32, 36 are, for example, SiO layers, but may be formed of other insulating materials. The wiring layer 34 is formed of a conductive material such as Au, Cu, or Al. The electrode layer 38 includes a plurality of electrode pads provided as the gate pad 102, source pad 103, and drain pad 104 described above.

[0068] [1-6. Planar Layout of Nitride Semiconductor Devices] Next, an exemplary planar layout of the nitride semiconductor device 100 will be described with reference to FIGS. 6 to 8. FIG. 6 is a schematic plan view showing the planar layout of the first transistor 10T1 and the second transistor 10T2 formed on the transistor chip 101 (see FIG. 1). FIG. 7 is a partial enlarged plan view of the first transistor 10T1, and is an enlarged view of a region F7 enclosed by a dashed-dotted line frame shown in FIG. 6. FIG. 8 is a partial enlarged plan view of the second transistor 10T2, and is an enlarged view of a region F8 enclosed by a dashed-dotted line frame shown in FIG. 6.

[0069] 6, the wiring layer 34 (see FIG. 3) includes, for example, a first gate wiring 42, a first source wiring 44, a first drain wiring 46, a gate wiring pad 48, and a Kelvin source wiring pad 49, which are used as wiring paths to the first transistor 10T1. The wiring layer 34 also includes a second gate wiring 52, a second source wiring 54, and a second drain wiring 56, which are used as wiring paths to the second transistor 10T2. The gate wiring pad 48 and the Kelvin source wiring pad 49 are also used as wiring paths to the second transistor 10T2.

[0070] The first gate wiring 42 includes, for example, gate wiring portions 42A, 42B, 42C, 42D, and 42E as a plurality of first gate wiring portions. The gate wiring portions 42A, 42B, 42C, and 42D and the gate wiring pad 48 are located on the outer periphery of the wiring layer 34 in a plan view and are connected to each other in a ring shape. The gate wiring portion 42E is located, for example, between the gate wiring portions 42B and 42D and connects the gate wiring portion 42C and the gate wiring pad 48 to each other. Therefore, the gate wiring portions 42A, 42B, 42C, 42D, and 42E and the gate wiring pad 48 are electrically connected to each other.

[0071] The first source wiring 44 includes, for example, source wiring portions 44A, 44B, 44C, and 44D as a plurality of first source wiring portions. The first drain wiring 46 includes, for example, drain wiring portions 46A, 46B, 46C, and 46D as a plurality of first drain wiring portions. The source wiring portions 44A, 44B, 44C, and 44D and the drain wiring portions 46A, 46B, 46C, and 46D are arranged in the first transistor region RT1.

[0072] 6, the source wiring portions 44A, 44B and the drain wiring portions 46A, 46B are alternately arranged one by one in the second direction Y. Similarly, the source wiring portions 44C, 44D and the drain wiring portions 46C, 46D are alternately arranged one by one in the second direction Y. The source wiring portions 44C, 44D are connected to a Kelvin source wiring pad 49 (the left edge of the Kelvin source wiring pad 49 in the example of FIG. 6).

[0073] The second gate wiring 52 includes, for example, gate wiring portions 52A and 52B as a plurality of second gate wiring portions. The gate wiring portions 52A and 52B are connected to the Kelvin source wiring pad 49 (the right edge of the Kelvin source wiring pad 49 in the example of FIG. 6).

[0074] The second source wiring 54 includes, for example, source wiring portions 54A and 54B as a plurality of second source wiring portions. The second drain wiring 56 includes, for example, drain wiring portions 56A and 56B as a plurality of second drain wiring portions. The drain wiring portions 56A and 56B are connected to the gate wiring pad 48 (in the example of FIG. 6, the left edge of the gate wiring pad 48). The gate wiring portions 52A and 52B, the source wiring portions 54A and 54B, and the drain wiring portions 56A and 56B are arranged in the second transistor region RT2.

[0075] As shown in FIG. 6, the second transistor 10T2 (second transistor region RT2) is disposed in a position close to the gate wiring pad 48. In the example of FIG. 6, the second transistor 10T2 is disposed adjacent to the gate wiring pad 48, and the second drain wiring 56 (drain wiring portions 56A and 56B) is directly connected to the gate wiring pad 48. Therefore, no other wiring (e.g., the first gate wiring 42 for the first transistor 10T1, etc.) is interposed between the gate wiring pad 48 and the second drain wiring 56. Therefore, the amount of heat generated in the wiring layer 34 by providing the second transistor 10T2 can be minimized.

[0076] Furthermore, the second gate wiring 52 (gate wiring portions 52A and 52B) of the second transistor 10T2 is connected to a Kelvin source wiring pad 49, which is connected to the first source wiring 44 of the first transistor 10T1 (source wiring portions 44C and 44D in the example of FIG. 6). Therefore, the second gate wiring 52 of the second transistor 10T2 is connected to the first source wiring 44 of the first transistor 10T1 via the Kelvin source wiring pad 49. In this configuration, the gate potential of the second transistor 10T2 can be controlled by the potential generated in the first source wiring 44 of the first transistor 10T1.

[0077] 7, in the first transistor region RT1, the first gate electrode 24G1 is connected to the first gate wiring 42 (gate wiring portions 42B and 42E in the example of FIG. 7) and the gate wiring pad 48 by a gate through conductor 42V that penetrates the first insulating layer 32 (see FIG. 3). The gate wiring pad 48 is connected to the gate pad 102 (see FIG. 1) of the electrode layer 38 by a gate through conductor (not shown) that penetrates the second insulating layer 36 (see FIG. 3). Therefore, the first gate electrode 24G1 is electrically connected to the gate pad 102.

[0078] The first source electrode 28S1 is connected to the first source wiring 44 (source wiring portions 44A and 44B in the example of FIG. 7) by a source penetrating conductor 44V that penetrates the first insulating layer 32 (see FIG. 3). The first source wiring 44 is connected to the source pad 103 (see FIG. 1) of the electrode layer 38 by a source penetrating conductor 62V that penetrates the second insulating layer 36 (see FIG. 3). Therefore, the first source electrode 28S1 is electrically connected to the source pad 103.

[0079] The first drain electrode 30D1 is connected to the first drain wiring 46 (drain wiring portions 46A and 46B in the example of FIG. 7) by a drain through conductor 46V that penetrates the first insulating layer 32 (see FIG. 3). The first drain wiring 46 is connected to the drain pad 104 (see FIG. 1) of the electrode layer 38 by a drain through conductor 64V that penetrates the second insulating layer 36 (see FIG. 3). Therefore, the first drain electrode 30D1 is electrically connected to the drain pad 104.

[0080] As shown in FIG. 8, in the second transistor region RT2, the second gate electrode 24G2 is connected to the second gate wiring 52 (gate wiring portions 52A and 52B) by a gate penetrating conductor 52V that penetrates the first insulating layer 32 (see FIG. 3). The second gate wiring 52 is connected to the first source wiring 44 (source wiring portions 44C and 44D in FIG. 6) via the Kelvin source wiring pad 49 as described above. The first source wiring 44 (source wiring portions 44C and 44D) is connected to the first source pad 103A (see FIG. 1) of the electrode layer 38 by a source penetrating conductor 62V that penetrates the second insulating layer 36 (see FIG. 3). Therefore, the second gate electrode 24G2 is electrically connected to the first source pad 103A.

[0081] The second source electrode 28S2 is connected to the second source wiring 54 (source wiring portions 54A and 54B) by a source penetrating conductor 54V that penetrates the first insulating layer 32 (see FIG. 3). The second source wiring 54 is connected to the first source pad 103A (see FIG. 1) of the electrode layer 38 by a source penetrating conductor 62V that penetrates the second insulating layer 36 (see FIG. 3). Therefore, the second source electrode 28S2 is electrically connected to the first source pad 103A.

[0082] The second drain electrode 30D2 is connected to the second drain wiring 56 (drain wiring portions 56A and 56B) by a drain through conductor 56V that penetrates the first insulating layer 32 (see FIG. 3). The second drain wiring 56 is connected to the gate wiring pad 48 as described above. The gate wiring pad 48 is connected to the gate pad 102 (see FIG. 1) of the electrode layer 38 by a gate through conductor (not shown) that penetrates the second insulating layer 36 (see FIG. 3). Therefore, the second drain electrode 30D2 is electrically connected to the gate pad 102.

[0083] 6, the first transistor 10T1 includes a plurality of first transistor cells 10TC1 arranged along each of the first direction X and the second direction Y. The second transistor 10T2 includes a plurality of second transistor cells 10TC2 arranged along the first direction X. Note that the planar layout of the first and second transistors 10T1 and 10T2 shown in FIG. 6 is merely an example. The number of first transistor cells 10TC1 arranged along the first direction X, the number of first transistor cells 10TC1 arranged along the second direction Y, and the number of second transistor cells 10TC2 arranged along the first direction X can be changed as appropriate depending on transistor design conditions such as the chip size of the nitride semiconductor device 100.

[0084] [1-7. Size of the first and second transistors] Next, the size of first transistor 10T1 and the size of second transistor 10T2 will be described with reference to the above-mentioned FIGS.

[0085] The second transistor 10T2 may have a size smaller than the size of the first transistor 10T1. That is, the ratio of the size of the second transistor 10T2 to the size of the first transistor 10T1 is less than 1.0. For example, as shown in FIGS. 6 to 8, the second transistor region RT2 in which the second transistor 10T2 is arranged may have an area smaller than the first transistor region RT1 in which the first transistor 10T1 is arranged. In other words, the proportion of the chip area of ​​the transistor chip 101 (or the layout area shown in FIG. 6) occupied by the second transistor region RT2 is smaller than the proportion of the chip area occupied by the first transistor region RT1. The areas of the first and second transistor regions RT1 and RT2 may be determined, for example, in consideration of the on-resistances of the first and second transistors 10T1 and 10T2.

[0086] In addition, in the first transistor 10T1 (see Figure 4), the first drain contact portion 30DC1 is spaced a first distance D1 from the first gate electrode 24G1, while in the second transistor 10T2 (see Figure 5), the second drain contact portion 30DC2 is spaced a second distance D2 from the second gate electrode 24G2 that is shorter than the first distance D1.

[0087] For example, the first distance D1 and the second distance D2 are determined taking into consideration the drain-source voltages of the first and second transistors 10T1 and 10T2. For example, the drain-source voltage of the second transistor 10T2, which is connected between the gate and source of the first transistor 10T1, may be sufficient if it is equal to or greater than the gate-source breakdown voltage of the first transistor 10T1. In consideration of this, the second distance D2 is set to a minimum distance shorter than the first distance D1. This further reduces the proportion of the second transistor region RT2 in the chip area of ​​the transistor chip 101, thereby minimizing the reduction in the area of ​​the first transistor region RT1.

[0088] [1-8. Electrical Connection Between the First Transistor and the Second Transistor] Next, with reference to FIG. 9 as well as to FIGS. 6 to 8 described above, the electrical connection between the first transistor 10T1 and the second transistor 10T2 will be described.

[0089] 10, the first gate electrode 24G1 of the first transistor 10T1 and the second drain electrode 30D2 of the second transistor 10T2 are connected to the gate terminal Tg. The first drain electrode 30D1 of the first transistor 10T1 is connected to the drain terminal Td. The first source electrode 28S1 of the first transistor 10T1 is connected to the source terminal Ts via the resistive element R1. The second source electrode 28S2 of the second transistor 10T2 is connected to the source terminal Ts, and the second gate electrode 24G2 of the second transistor 10T2 is connected to a node N1 between the first source electrode 28S1 and the resistive element R1. In the first embodiment, the Kelvin source terminal Tks is connected to the node N1.

[0090] The resistive element R1 includes resistive elements on a current path from the first source electrode 28S1 to the source terminal Ts, through which the drain current of the first transistor 10T1 flows. For example, in the nitride semiconductor device 100 having the above-described package structure (see FIG. 1) and layout structure (see FIG. 6), the resistive element R1 includes resistive elements on a current path from the first source electrode 28S1 to the lead ends 131E1 and 131E2 (the source terminal Ts) via the source through conductor 44V, the first source wiring 44 (source wiring portions 44A, 44B, 44C, and 44D), the source through conductor 62V, the source pad 103 (first and second source pads 103A and 103B), the first source connecting member 121, and the first source lead frame 131A. Note that, although not explicitly shown in the circuit of FIG. 9, resistive elements also exist on other current paths of the first and second transistors 10T1 and 10T2.

[0091] [1-9. Function of nitride semiconductor device] Next, the operation of the nitride semiconductor device 100 will be described with reference to the circuit diagram of FIG. 9, when the gate control voltage applied to the gate terminal Tg reaches the gate threshold of the first transistor 10T1 and the first transistor 10T1 turns on, the drain current of the first transistor 10T1 flows from the first source electrode 28S1 to the source terminal Ts. As a result, the drain current flows through the resistance element R1 on the current path from the first source electrode 28S1 to the source terminal Ts, causing the potential of the node N1 to rise. When this increased potential at the node N1 reaches the gate threshold of the second transistor 10T2, the second transistor 10T2 turns on. As a result, the gate potential of the first transistor 10T1 is pulled down to the potential of the source terminal Ts, turning the first transistor 10T1 off.

[0092] Therefore, the second transistor 10T2 functions as an overcurrent protection transistor that turns off the first transistor 10T1 when the drain current of the first transistor 10T1 becomes an overcurrent, thereby preventing damage to the first transistor 10T1. The overcurrent value detected by the second transistor 10T2 can be controlled, for example, by the gate threshold value of the second transistor 10T2 and the resistance value of the resistive element R1.

[0093] Here, the second gate electrode 24G2 of the second transistor 10T2 is connected to a node N1 between the first source electrode 28S1 of the first transistor 10T1 and the resistive element R1. This increases the responsiveness (turn-on speed) of the second transistor 10T2 when an overcurrent flows through the first transistor 10T1 (when the potential at the node N1 rises sharply), allowing the second transistor 10T2 to instantly turn off the first transistor 10T1 when an overcurrent occurs.

[0094] [1-10. Advantages of nitride semiconductor devices] The nitride semiconductor device 100 of the first embodiment has the following advantages. (1-A) The nitride semiconductor device 100 includes a first transistor 10T1 and a second transistor 10T2. The first gate electrode 24G1 and the second drain electrode 30D2 are connected to a gate terminal Tg. The first drain electrode 30D1 is connected to a drain terminal Td. The first source electrode 28S1 is connected to a source terminal Ts via a resistive element R1. The second source electrode 28S2 is connected to the source terminal Ts. The second gate electrode 24G2 is connected to a node N1 between the first source electrode 28S1 and the resistive element R1. With this configuration, an overcurrent flowing through the first transistor 10T1 can be detected by the second transistor 10T2, and the first transistor 10T1 can be instantly turned off. This prevents breakdown of the first transistor 10T1.

[0095] (1-B) A resistive element on the current path from the first source electrode 28S1, through which the drain current of the first transistor 10T1 flows, to the source terminal Ts is used as the resistive element R1. With this configuration, the second transistor 10T2 detects an overcurrent based on an increase in the potential at the node N1 using the resistive element R1. Therefore, an overcurrent can be detected simply by providing the second transistor 10T2, without providing an external element such as a separate resistive element or fuse element to detect the overcurrent flowing through the first transistor 10T1. As a result, when an overcurrent occurs, the second transistor 10T2 instantly turns off the first transistor 10T1, preventing damage to the first transistor 10T1.

[0096] (1-C) The size of the second transistor 10T2 is smaller than the size of the first transistor 10T1. With this configuration, the second transistor 10T2 can be formed with a relatively small area, and the reduction in the area of ​​the first transistor 10T1 (first transistor region RT1) relative to the chip area of ​​the transistor chip 101 can be minimized. This makes it possible to obtain the function of the second transistor 10T2 as an overcurrent protection transistor while maintaining the high-speed switching characteristics of the first transistor 10T1 in a good condition.

[0097] (1-D) The nitride semiconductor device 100 includes a Kelvin source terminal Tks connected to the node N1. With this configuration, the gate-source voltage of the first transistor 10T1 can be controlled by utilizing the potential of the Kelvin source terminal Tks (i.e., the potential of the node N1) that is free from the influence of electromotive noise due to parasitic inductance components present in the current path (the source through conductors 44V and 62V, the first source wiring 44, the source pad 103, the first source connecting member 121, and the first source lead frame 131A) between the first source electrode 28S1 and the first source terminal Ts. This allows the first transistor 10T1 to maintain its high-speed switching characteristics.

[0098] (1-E) The first transistor 10T1 and the second transistor 10T2 are provided on the same transistor chip 101. This configuration shortens the length of the wiring path between the second gate electrode 24G2 of the second transistor 10T2 and the first source electrode 28S1 of the first transistor 10T1. This improves the responsiveness of the second transistor 10T2 compared to when the second transistor 10T2 is provided as a separate chip.

[0099] (1-F) The nitride semiconductor device 100 is configured as a HEMT using GaN. This allows the nitride semiconductor device 100 having the advantages of (1-A) to (1-E) described above to be used as a power device using a GaN-HEMT.

[0100] [Second embodiment] Next, a nitride semiconductor device 100 according to a second embodiment will be described with reference to Figures 10 and 11. The second embodiment differs from the first embodiment in that the circuit configuration in Figure 9 is changed to the circuit configuration in Figure 10. Below, a description of components similar to those in the first embodiment will be omitted, and components different from those in the first embodiment will be described.

[0101] 10, the nitride semiconductor device 100 according to the second embodiment includes three transistors made of nitride semiconductors: a first transistor 10T11, a second transistor 10T12, and a third transistor 10T13. Each of the first to third transistors 10T11, 10T12, and 10T13 is formed as a HEMT, and in one example, is a GaN-HEMT.

[0102] The first transistor 10T11 includes a first gate electrode 24G11 connected to a gate terminal Tg, a first source electrode 28S11 connected to a source terminal Ts, and a first drain electrode 30D11 connected to a drain terminal Td. In the second embodiment, the first source electrode 28S11 is further connected to a Kelvin source terminal Tks. The first transistor 10T11 may be configured similarly to the first transistor 10T1 described in the first embodiment. For example, the first gate electrode 24G11, the first source electrode 28S11, and the first drain electrode 30D11 are configured similarly to the first gate electrode 24G1, the first source electrode 28S1, and the first drain electrode 30D1 described in the first embodiment.

[0103] The second transistor 10T12 includes a second gate electrode 24G12 connected to the gate terminal Tg, a second source electrode 28S12 connected to the source terminal Ts via a resistive element R2, and a second drain electrode 30D12 connected to the drain terminal Td. The second transistor 10T12 may be configured similarly to the first transistor 10T1 described in the first embodiment. For example, the second gate electrode 24G12, the second source electrode 28S12, and the second drain electrode 30D12 are configured similarly to the first gate electrode 24G11, the first source electrode 28S11, and the first drain electrode 30D11 described in the first embodiment.

[0104] In the second embodiment, the second transistor 10T12 may have a size smaller than the size of the first transistor 10T11. That is, the ratio of the size of the second transistor 10T12 to the size of the first transistor 10T11 is less than 1.0. That is, the second transistor 10T12 is configured similarly to the first transistor 10T11, except for the difference in size.

[0105] The third transistor 10T13 includes a third gate electrode 24G13, a third source electrode 28S13 connected to the source terminal Ts, and a third drain electrode 30D13 connected to the gate terminal Tg. The third gate electrode 24G13 is connected to a node N2 between the second source electrode 28S12 of the second transistor 10T12 and the resistive element R2. The third transistor 10T13 may be configured similarly to the second transistor 10T2 described in the first embodiment. For example, the third gate electrode 24G13, the third source electrode 28S13, and the third drain electrode 30D13 are configured similarly to the second gate electrode 24G2, the second source electrode 28S2, and the second drain electrode 30D2 described in the first embodiment.

[0106] In the second embodiment, the third transistor 10T13 may have a size smaller than the first transistor 10T11 and may have a size smaller than the second transistor 10T12. That is, the ratio of the size of the third transistor 10T13 to the size of the first transistor 10T11 is less than 1.0. That is, the third transistor 10T13 has the same configuration as the first and second transistors 10T11 and 10T12, except for the difference in size.

[0107] Fig. 11 is a schematic plan view showing an exemplary planar layout of the first to third transistors 10T11, 10T12, and 10T13 in the nitride semiconductor device 100 according to the second embodiment. Note that the layout shown in Fig. 11 is merely an example for realizing the circuit of Fig. 10, and other layouts may also be adopted.

[0108] In the example of FIG. 11, the first transistor 10T11 includes a plurality of first transistor cells 10TC11 arranged along each of the first direction X and the second direction Y in the first transistor region RT11. The second transistor 10T12 includes a plurality of second transistor cells 10TC12 arranged along the first direction X in the second transistor region RT12. The third transistor 10T13 includes a plurality of third transistor cells 10TC13 arranged along the first direction X in the third transistor region RT13. Note that the numbers of the first to third transistor cells 10TC11, 10TC12, and 10TC13 shown in FIG. 11 are merely examples. For example, to avoid complexity in the illustration, FIG. 11 shows the same number of second transistor cells 10TC12 and third transistor cells 10TC13, but in reality, the number of second transistor cells 10TC12 may be greater than the number of third transistor cells 10TC13.

[0109] In the first transistor 10T11, the first gate electrode 24G11 is electrically connected to the first gate wiring 42, the first source electrode 28S11 is electrically connected to the first source wiring 44, and the first drain electrode 30D11 is electrically connected to the first drain wiring 46. The connection structure of these elements in the first transistor 10T11 is similar to the connection structure of the first transistor 10T1 described in the first embodiment, and therefore a description thereof will be omitted.

[0110] In the second transistor 10T12, the second gate electrode 24G12 is electrically connected to the second gate wiring (a part of the first gate wiring 42), the second source electrode 28S12 is electrically connected to the second source wirings 441 and 442, and the second drain electrode 30D12 is electrically connected to the second drain wiring 461. Although not shown in detail, the second source wirings 441 and 442 are electrically connected to the source pad 103 (see FIG. 1), and the second drain wiring 461 is electrically connected to the drain pad 104 (see FIG. 1).

[0111] In the third transistor 10T13, the third gate electrode 24G13 is electrically connected to the third gate wirings 481 and 482, the third source electrode 28S13 is electrically connected to the third source wiring 443, and the third drain electrode 30D13 is electrically connected to the third drain wiring 462. Although not shown in detail, the third gate wirings 481 and 482 are electrically connected to each other, and the third source wiring 443 is electrically connected to the source pad 103 (see FIG. 1).

[0112] 11, the third gate wiring 481 of the third transistor 10T13 is connected to the second source wiring 441 of the second transistor 10T12. Therefore, the third gate electrode 24G13 of the third transistor 10T13 is electrically connected to the second source electrode 28S12 of the second transistor 10T12.

[0113] The third source wiring 443 of the third transistor 10T13 is connected to the first source wiring 44 of the first transistor 10T11 via the Kelvin source wiring pad 49. Therefore, the third source electrode 28S13 of the third transistor 10T13 is electrically connected to the source pad 103 (see FIG. 1).

[0114] The third drain wiring 462 of the third transistor 10T13 is connected to the first gate wiring 42. Therefore, the third drain electrode 30D13 of the third transistor 10T13 is electrically connected to the first gate electrode 24G11 of the first transistor 10T11 and the second gate electrode 24G12 of the second transistor 10T12.

[0115] In the second embodiment, the second transistor region RT12 in which the second transistor 10T12 is arranged may have a smaller area than the first transistor region RT11 in which the first transistor 10T11 is arranged. That is, the proportion of the second transistor region RT12 in the chip area of ​​the transistor chip 101 (or the layout area shown in FIG. 11) is smaller than the proportion of the first transistor region RT11 in the chip area. Also, the third transistor region RT13 in which the third transistor 10T13 is arranged may have a smaller area than the second transistor region RT12 in which the second transistor 10T12 is arranged. That is, the proportion of the third transistor region RT13 in the chip area of ​​the transistor chip 101 is smaller than the proportion of the second transistor region RT12 in the chip area.

[0116] In the second embodiment, the resistance element R2 shown in the circuit of FIG. 10 includes a resistance component of the third gate electrode 24G13 of the third transistor 10T13. For example, if the third gate electrode 24G13 is formed of TiN, the resistance element R2 includes a resistance component of TiN. The resistance element R2 also includes a resistance element on a current path from the second source electrode 28S12 to the source terminal Ts, through which the drain current of the second transistor 10T12 flows. For example, in the nitride semiconductor device 100 of the second embodiment having the above-described package structure (see FIG. 1) and layout structure (see FIG. 11), the resistance element R2 includes a resistance element on a current path from the second source electrode 28S12 to the lead ends 131E1 and 131E2 (the source terminal Ts) via the second source wirings 441 and 442, the source pad 103 (first and second source pads 103A and 103B), the first source connecting member 121, and the first source lead frame 131A. Although not shown in the circuit of FIG. 10, resistance elements also exist on other current paths of the first to third transistors 10T11, 10T12, and 10T13.

[0117] In the nitride semiconductor device 100 of the second embodiment configured as described above, when the gate control voltage applied to the gate terminal Tg reaches the gate threshold of the first transistor 10T11 and the first transistor 10T11 is turned on, the drain current of the first transistor 10T11 flows from the first source electrode 28S11 to the source terminal Ts. The gate control voltage also simultaneously turns on the second transistor 10T12, causing the drain current of the second transistor 10T12 to flow from the second source electrode 28S12 to the source terminal Ts. This causes the drain current flowing through the resistive element R2 on the current path from the second source electrode 28S12 to the source terminal Ts to increase the potential of the node N2. When this increased potential at the node N2 reaches the gate threshold of the third transistor 10T13, the third transistor 10T13 is turned on. As a result, the gate potential of the first transistor 10T11 is pulled down to the potential of the source terminal Ts, turning off the first transistor 10T11.

[0118] Therefore, third transistor 10T13 detects the drain current of second transistor 10T12 and thereby detects when the drain current of first transistor 10T11 becomes an overcurrent. Therefore, third transistor 10T13 functions as an overcurrent protection transistor that turns off first transistor 10T11 to prevent breakdown of first transistor 10T11 when the drain current of first transistor 10T11 becomes an overcurrent. The overcurrent value detected by third transistor 10T13 can be controlled, for example, by the gate threshold of third transistor 10T13 and the resistance value of resistive element R2 (i.e., the resistance component of third gate electrode 24G13 and the resistance value of the resistive element on the current path from second source electrode 28S12 to source terminal Ts).

[0119] The nitride semiconductor device 100 of the second embodiment described above has the following advantages. (2-A) Third transistor 10T13 detects the drain current of second transistor 10T12 to detect when the drain current of first transistor 10T11 becomes an overcurrent, thereby preventing breakdown of first transistor 10T11.

[0120] (2-B) The resistance component of third gate electrode 24G13 and the resistance element on the current path from second source electrode 28S12 to source terminal Ts are used as resistance element R2. Therefore, an overcurrent can be detected by providing only second transistor 10T12 and third transistor 10T13, without providing an external element such as a separate resistance element or fuse element to detect an overcurrent flowing through first transistor 10T11.

[0121] (2-C) The size of the second transistor 10T12 is smaller than the size of the first transistor 10T11. The size of the third transistor 10T13 is also smaller than the size of the second transistor 10T12. With this configuration, the second transistor 10T12 and the third transistor 10T13 can be formed in a relatively small area, minimizing the reduction in the area of ​​the first transistor 10T11 (first transistor region RT11) relative to the chip area of ​​the transistor chip 101. This makes it possible to obtain the function of the third transistor 10T13 as an overcurrent protection transistor while maintaining the high-speed switching characteristics of the first transistor 10T11 favorably.

[0122] (2-D) The nitride semiconductor device 100 includes a Kelvin source terminal Tks. This configuration, similar to the first embodiment, makes it possible to control the gate-source voltage of the first transistor 10T11 by eliminating the influence of electromotive noise caused by a parasitic inductance component coupled to the source terminal Ts. This allows the high-speed switching characteristics of the first transistor 10T11 to be maintained.

[0123] (2-E) The first to third transistors 10T11, 10T12, and 10T13 are provided on the same transistor chip 101. This configuration can improve the responsiveness of the third transistor 10T13.

[0124] (2-F) The nitride semiconductor device 100 is configured as a HEMT using GaN. This allows the nitride semiconductor device 100 having the advantages of (2-A) to (2-E) described above to be used as a power device utilizing a GaN-HEMT.

[0125] [Example of change] The above-described embodiments can be modified, for example, as follows: The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above-described embodiments will be assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0126] In each of the above embodiments, the Kelvin source terminal Tks (and the Kelvin source wiring pad 49) is not an essential component and can be omitted. However, by providing the Kelvin source terminal Tks in the nitride semiconductor device 100, the high-speed switching characteristics of the first transistor 10T1 can be effectively utilized.

[0127] In each of the above embodiments, the nitride semiconductor device 100 may include a surge protection diode for protecting the HEMT from unexpected surges caused by static electricity, etc. One example of such a surge protection diode is a TVS (Transient Voltage Suppressor) diode.

[0128] In each of the above embodiments, the nitride semiconductor device 100 is not limited to a GaN-HEMT, and may be provided as a transistor using other nitride semiconductors. The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0129] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X axis direction may be the vertical direction, or the Y axis direction may be the vertical direction.

[0130] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0131] [Appendix 1] a first transistor (10T1) made of a nitride semiconductor and including a first gate electrode (24G1), a first source electrode (28S1), and a first drain electrode (30D1); a second transistor (10T2) made of a nitride semiconductor and including a second gate electrode (24G2), a second source electrode (28S2), and a second drain electrode (30D2); a gate terminal (Tg) connected to the first gate electrode (24G1) and the second drain electrode (30D2); a drain terminal (Td) connected to the first drain electrode (30D1); a source terminal (Ts) connected to the first source electrode (28S1) via a resistive element (R1); The second source electrode (28S2) is connected to the source terminal (Ts), The nitride semiconductor device, wherein the second gate electrode (24G2) is connected to a node (N1) between the first source electrode (28S1) and the resistance element (R1).

[0132] [Appendix 2] 2. The nitride semiconductor device according to claim 1, wherein the second transistor (10T2) is smaller in size than the first transistor (10T1).

[0133] [Appendix 3] 2. The nitride semiconductor device according to claim 1, further comprising a Kelvin source terminal (Tks) connected to the node (N1) between the first source electrode (28S1) and the resistive element (R1).

[0134] [Appendix 4] The nitride semiconductor device according to Appendix 1, wherein the resistive element (R1) is a resistive element on a current path from the first source electrode (28S1) to the source terminal (Ts) through which a drain current of the first transistor (10T1) flows.

[0135] [Appendix 5] The nitride semiconductor device according to claim 1, wherein the first transistor (10T1) and the second transistor (10T2) are provided on the same transistor chip (101).

[0136] [Appendix 6] an electron transit layer (16); an electron supply layer (18) having a band gap larger than that of the electron transit layer (16); a gate layer located on the electron supply layer (18) and containing acceptor-type impurities, a first gate layer (22G1) located in a first transistor region (RT1); the gate layer including a second gate layer (22G2) located in a second transistor region (RT2); Equipped with the first source electrode (28S1) and the first drain electrode (30D1) are located in the first transistor region (RT1) and are in contact with the electron supply layer (18); The first gate electrode (24G1) is located on the first gate layer (22G1), the second source electrode (28S2) and the second drain electrode (30D2) are located in the second transistor region (RT2) and are in contact with the electron supply layer (18); the second gate electrode (24G2) is located on the second gate layer (22G2), the first transistor (10T1) is composed of the electron transit layer (16) in the first transistor region (RT1), the electron supply layer (18) in the first transistor region (RT1), the first gate layer (22G1), the first source electrode (28S1), the first drain electrode (30D1), and the first gate electrode (24G1); The nitride semiconductor device according to any one of Appendices 1 to 5, wherein the second transistor (10T2) is composed of the electron transit layer (16) in the second transistor region (RT2), the electron supply layer (18) in the second transistor region (RT2), the second gate layer (22G2), the second source electrode (28S2), the second drain electrode (30D2), and the second gate electrode (24G2).

[0137] [Appendix 7] the electron transit layer (16) is GaN, 7. The nitride semiconductor device according to claim 6, wherein the electron supply layer (18) is AlGaN.

[0138] [Appendix 8] a first transistor (10T11) made of a nitride semiconductor and including a first gate electrode (24G11), a first source electrode (28S11), and a first drain electrode (30D11); a second transistor (10T12) made of a nitride semiconductor and including a second gate electrode (24G12), a second source electrode (28S12), and a second drain electrode (30D12); a third transistor (10T13) made of a nitride semiconductor and including a third gate electrode (24G13), a third source electrode (28S13), and a third drain electrode (30D13); a gate terminal (Tg) connected to the first gate electrode (24G11), the second gate electrode (24G12), and the third drain electrode (30D13); a drain terminal (Td) connected to the first drain electrode (30D11) and the second drain electrode (30D12); a source terminal (Ts) connected to the first source electrode (28S11); The second source electrode (28S12) is connected to the source terminal (Ts) via a resistive element (R2), the third source electrode (28S13) is connected to the source terminal (Ts); The nitride semiconductor device, wherein the third gate electrode (24G13) is connected to a node (N2) between the second source electrode (28S12) and the resistance element (R2).

[0139] [Appendix 9] 9. The nitride semiconductor device according to claim 8, wherein the second transistor (10T12) is smaller in size than the first transistor (10T11).

[0140] [Appendix 10] 9. The nitride semiconductor device according to claim 8, wherein the size of the third transistor (10T13) is smaller than the size of the first transistor (10T11) and smaller than the size of the second transistor (10T12).

[0141] [Appendix 11] 9. The nitride semiconductor device according to claim 8, further comprising a Kelvin source terminal (Tks) connected to the first source electrode (28S11).

[0142] [Appendix 12] 9. The nitride semiconductor device according to claim 8, wherein the resistance element (R2) includes a resistance component of the third gate electrode (24G13) of the third transistor (10T13).

[0143] [Appendix 13] The nitride semiconductor device according to claim 8, wherein the resistive element (R2) is a resistive element on a current path from the second source electrode (28S12) through which a drain current of the second transistor (10T12) flows to the source terminal (Ts).

[0144] [Appendix 14] 9. The nitride semiconductor device according to claim 8, wherein the first transistor (10T11), the second transistor (10T12), and the third transistor (10T13) are provided on the same transistor chip (101).

[0145] [Appendix 15] an electron transit layer (16); an electron supply layer (18) having a band gap larger than that of the electron transit layer (16); a gate layer located on the electron supply layer (18) and containing acceptor-type impurities, a first gate layer (22G1) located in a first transistor region (RT11); a second gate layer (22G1) located in a second transistor region (RT12); the gate layer including a third gate layer located in a third transistor region (RT13); Equipped with the first source electrode (28S11) and the first drain electrode (30D11) are located in the first transistor region (RT11) and are in contact with the electron supply layer (18); The first gate electrode (24G11) is located on the first gate layer (22G1), the second source electrode (28S12) and the second drain electrode (30D12) are located in the second transistor region (RT12) and are in contact with the electron supply layer (18); the second gate electrode (24G12) is located on the second gate layer (22G2), the third source electrode (28S13) and the third drain electrode (30D13) are located in the third transistor region (RT13) and are in contact with the electron supply layer (18); the third gate electrode (24G13) is located on the third gate layer, the first transistor (10T11) is composed of the electron transit layer (16) in the first transistor region (RT11), the electron supply layer (18) in the first transistor region (RT11), the first gate layer (22G1), the first source electrode (28S11), the first drain electrode (30D11), and the first gate electrode (24G11); the second transistor (10T12) is composed of the electron transit layer (16) in the second transistor region (RT12), the electron supply layer (18) in the second transistor region (RT12), the second gate layer (22G2), the second source electrode (28S12), the second drain electrode (30D12), and the second gate electrode (24G12); The nitride semiconductor device according to any one of Appendices 8 to 14, wherein the third transistor (10T13) is composed of the electron transit layer (16) in the third transistor region (RT13), the electron supply layer (18) in the third transistor region (RT13), the third gate layer (22G3), the third source electrode (28S13), the third drain electrode (30D13), and the third gate electrode (24G13).

[0146] [Appendix 16] the electron transit layer (16) is GaN, 16. The nitride semiconductor device according to claim 15, wherein the electron supply layer (18) is AlGaN. [Explanation of symbols]

[0147] 100...Nitride semiconductor device 101...Transistor chip 102...Gate pad 103...Sauce Pad 103A...First source pad 103A1…Main area 103A2…extension area 103B...Second sauce pad 104...Drain pad 104A...First drain pad 104B...Second drain pad 105...Sealing resin 121...first source connection member 122...Drain connection member 123...Gate connecting member 124...Second source connection member 131...Source lead frame 131A...First source lead frame 131B...Second source lead frame 131E1, 131E2...Lead end (source terminal Ts) 131E3...Lead end (Kelvin source terminal Tks) 132...Drain lead frame 132E1, 132E2, 132E32, 132E4...Lead end (drain terminal Td) 133...Gate lead frame 133E...Lead end (gate terminal Tg) 134...Die pad 10T1, 10T11...first transistor 10TC1, 10TC11...first transistor cell 10T2, 10T12...Second transistor 10TC2, 10TC12...Second transistor cell 10T13...Third transistor 10TC13...Third transistor cell 11...Back electrode 12...Semiconductor substrate 14...Buffer layer 16...Electron transit layer 18...electron supply layer 20...2DEG 22G1...first gate layer 22G2: Second gate layer 24G1, 24G11...First gate electrode 24G2, 24G12...Second gate electrodes 24G13...Third gate electrode 26...passivation layer 26S1...First source opening 26D1...First drain opening 26S2...Second source opening 26D2...Second drain opening 28S1, 28S11...First source electrode 28SC1...First source contact 28SF1: First source field plate 28E1...First field plate edge 28S2, 28S12...Second source electrode 28SC2...Second source contact part 28SF2: Second source field plate 28E2...Second field plate edge 28S13...Third source electrode 30D1, 30D11...first drain electrodes 30DC1...First drain contact part 30D2, 30D12...Second drain electrode 30DC2...Second drain contact part 30D13...Third drain electrode 32...First insulating layer 34...Wiring layer 36...Second insulating layer 38...electrode layer 42...First gate wiring 42A, 42B, 42C, 42D, 42E...Gate wiring section 42V...Gate through conductor 44...First source wiring 44A, 44B, 44C, 44D...Source wiring section 44V...Source through conductor 46...First drain wiring 46A, 46B, 46C, 46D...Drain wiring section 46V...Drain through conductor 48...Gate wiring pad 49...Kelvin source wiring pad 52...Second gate wiring 52A, 52B...Gate wiring section 52V...Gate through conductor 54,441,442...Second source wiring 54A, 54B...Source wiring section 54V...Source through conductor 56,461,461...Second drain wiring 56A, 56B...Drain wiring section 443...Third source wiring 462...Third drain wiring 481, 482...Third gate wiring 56V...Drain through conductor 62V...Source through conductor 64V...Drain through conductor RT1, RT11...first transistor region RT2, RT12...Second transistor region RT13: Third transistor region D1: First distance D2…Second distance X…first direction Y...Second direction

Claims

1. a first transistor made of a nitride semiconductor and including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor made of a nitride semiconductor and including a second gate electrode, a second source electrode, and a second drain electrode; a gate terminal connected to the first gate electrode and the second drain electrode; a drain terminal connected to the first drain electrode; a source terminal connected to the first source electrode via a resistive element; the second source electrode is connected to the source terminal; The second gate electrode is connected to a node between the first source electrode and the resistance element.

2. The nitride semiconductor device according to claim 1 , wherein a size of said second transistor is smaller than a size of said first transistor.

3. The nitride semiconductor device according to claim 1 , further comprising a Kelvin source terminal connected to the node between the first source electrode and the resistive element.

4. The nitride semiconductor device according to claim 1 , wherein said resistance element is a resistance element on a current path through which a drain current of said first transistor flows from said first source electrode to said source terminal.

5. The nitride semiconductor device according to claim 1 , wherein said first transistor and said second transistor are provided on the same transistor chip.

6. an electron transit layer; an electron supply layer having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing acceptor-type impurities, a first gate layer located in the first transistor region; a second gate layer located in a second transistor region; Equipped with the first source electrode and the first drain electrode are located in the first transistor region and are in contact with the electron supply layer; the first gate electrode is located on the first gate layer; the second source electrode and the second drain electrode are located in the second transistor region and are in contact with the electron supply layer; the second gate electrode is located on the second gate layer; the first transistor is configured by the electron transit layer in the first transistor region, the electron supply layer in the first transistor region, the first gate layer, the first source electrode, the first drain electrode, and the first gate electrode; 6. The nitride semiconductor device according to claim 1, wherein the second transistor is configured by the electron transit layer in the second transistor region, the electron supply layer in the second transistor region, the second gate layer, the second source electrode, the second drain electrode, and the second gate electrode.

7. the electron transit layer is made of GaN; The nitride semiconductor device according to claim 6 , wherein said electron supply layer is made of AlGaN.

8. a first transistor made of a nitride semiconductor and including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor made of a nitride semiconductor and including a second gate electrode, a second source electrode, and a second drain electrode; a third transistor made of a nitride semiconductor and including a third gate electrode, a third source electrode, and a third drain electrode; a gate terminal connected to the first gate electrode, the second gate electrode, and the third drain electrode; a drain terminal connected to the first drain electrode and the second drain electrode; a source terminal connected to the first source electrode; the second source electrode is connected to the source terminal via a resistive element; the third source electrode is connected to the source terminal; The third gate electrode is connected to a node between the second source electrode and the resistance element.

9. The nitride semiconductor device according to claim 8 , wherein a size of said second transistor is smaller than a size of said first transistor.

10. The nitride semiconductor device according to claim 8 , wherein a size of said third transistor is smaller than a size of said first transistor and is smaller than a size of said second transistor.

11. The nitride semiconductor device according to claim 8 , further comprising a Kelvin source terminal connected to the first source electrode.

12. The nitride semiconductor device according to claim 8 , wherein said resistance element includes a resistance component of said third gate electrode of said third transistor.

13. The nitride semiconductor device according to claim 8 , wherein said resistance element is a resistance element on a current path through which a drain current of said second transistor flows from said second source electrode to said source terminal.

14. The nitride semiconductor device according to claim 8 , wherein said first transistor, said second transistor, and said third transistor are provided on the same transistor chip.

15. an electron transit layer; an electron supply layer having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing acceptor-type impurities, a first gate layer located in the first transistor region; a second gate layer located in the second transistor region; a third gate layer located in a third transistor region; Equipped with the first source electrode and the first drain electrode are located in the first transistor region and are in contact with the electron supply layer; the first gate electrode is located on the first gate layer; the second source electrode and the second drain electrode are located in the second transistor region and are in contact with the electron supply layer; the second gate electrode is located on the second gate layer; the third source electrode and the third drain electrode are located in the third transistor region and are in contact with the electron supply layer; the third gate electrode is located on the third gate layer; the first transistor is configured by the electron transit layer in the first transistor region, the electron supply layer in the first transistor region, the first gate layer, the first source electrode, the first drain electrode, and the first gate electrode; the second transistor is configured by the electron transit layer in the second transistor region, the electron supply layer in the second transistor region, the second gate layer, the second source electrode, the second drain electrode, and the second gate electrode; 15. The nitride semiconductor device according to claim 8, wherein the third transistor is configured by the electron transit layer in the third transistor region, the electron supply layer in the third transistor region, the third gate layer, the third source electrode, the third drain electrode, and the third gate electrode.

16. the electron transit layer is made of GaN; The nitride semiconductor device according to claim 15, wherein said electron supply layer is made of AlGaN.

Images