Power supply control device, switching power supply, and electronic

Abstract

To quickly return from a light load mode while suppressing overshoot of an output voltage.SOLUTION: The power supply control device 200, which mainly controls the switching power supply 100, includes an error amplifier 142, a ramp signal generation circuit 143, a comparison signal generation circuit 145, a logic circuit 146, a switch drive circuit 147, a backflow detection circuit 148, and a ramp signal holding circuit 149. The logic circuit 146 adjusts the input offset OFS of the comparison signal generation circuit 145, the difference signal ERR, or the ramp signal RAMP in a direction in which the difference between the difference signal ERR and the ramp signal RAMP decreases according to a predetermined trigger signal I2C.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device, a switching power supply, and an electronic device. [Background technology]

[0002] Some switching power supplies are equipped with an operation mode that reduces switching losses by thinning out switching pulses under light load conditions, a so-called light load mode.

[0003] Incidentally, examples of prior art related to the above include Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-90271 [Patent Document 2] Japanese Patent Application Publication No. 2017-11931

[0005] [overview] In conventional switching power supplies, particularly in the power supply control device that is the main controller thereof, there is room for further study on recovery control from the light load mode.

[0006] For example, a power supply control device according to the present disclosure is a power supply control device configured to act as a main controller of a switching power supply that generates an output voltage from an input voltage by turning on / off an output transistor and a synchronous rectification transistor to drive an inductor current, and includes an error amplifier configured to generate an error signal corresponding to the output voltage or a difference between a feedback voltage corresponding to the output voltage and a reference voltage, a ramp signal generation circuit configured to generate a ramp signal that rises from a first signal value during an on-period of the output transistor, a comparison signal generation circuit configured to generate a comparison signal according to the error signal and the ramp signal, and a logic circuit configured to generate a pulse width modulation signal according to the comparison signal. a switch drive circuit configured to drive each of the output transistor and the synchronous rectifier transistor in response to the pulse width modulation signal; a backflow detection circuit configured to detect a backflow of the inductor current and forcibly turn off the synchronous rectifier transistor; and a ramp signal holding circuit configured to hold the ramp signal at a second signal value higher than the first signal value during at least a part of a forced-off period of the synchronous rectifier transistor, wherein the logic circuit adjusts the input offset of the comparison signal generation circuit, the error signal, or the ramp signal in a direction that reduces the difference between the error signal and the ramp signal in response to a predetermined trigger signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a switching power supply. [Figure 2] FIG. 2 is a diagram showing a first embodiment of a control circuit. [Figure 3] FIG. 3 is a diagram illustrating an example of a switching operation in the first embodiment. [Figure 4] FIG. 4 is a diagram showing a second embodiment of the control circuit. [Figure 5] FIG. 5 is a diagram illustrating an example of a switching operation in the second embodiment. [Figure 6] FIG. 6 is a diagram showing a third embodiment of the control circuit. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of the comparison signal generating circuit. [Figure 8] FIG. 8 is a diagram showing a first example of a switching operation in the third embodiment. [Figure 9] FIG. 9 is a diagram showing a second example of the switching operation in the third embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of input offset adjustment.

[0008] [Detailed explanation] <Switching power supply> 1 is a diagram showing the overall configuration of a switching power supply. A switching power supply 100 of this configuration example is mounted in electronic device A together with load Z. Load Z may be a microcomputer equipped with a power saving priority mode and a performance priority mode. Switching power supply 100 is a DC (direct current) / DC converter that generates a desired output voltage OUT from an input voltage IN and supplies it to load Z, and includes a switch output stage 110, a feedback voltage generation circuit 120, and a control circuit 140.

[0009] The above components, except for some components included in the switch output stage 110 (inductor 113 and capacitors 114 and 115 in this figure), may be integrated into a semiconductor device 200 (a so-called power supply control IC, equivalent to a power supply control device) that serves as the main controller of the switching power supply 100. Note that the semiconductor device 200 can also incorporate any other components (such as various protection circuits) as appropriate.

[0010] The semiconductor device 200 also includes a plurality of external terminals T1 to T3 as means for establishing electrical connections with the outside of the device.

[0011] The switch output stage 110 is a step-down switch output stage that generates a desired output voltage OUT from an input voltage IN by driving an inductor current IL by turning on / off an upper switch and a lower switch connected to form a half bridge, and includes an output transistor 111, a synchronous rectifier transistor 112, an inductor 113, and capacitors 114 and 115.

[0012] The output transistor 111 is an N-channel metal oxide semiconductor field effect transistor (NMOSFET) that functions as an upper switch of the switch output stage 110. Inside the semiconductor device 200, the drain of the output transistor 111 is connected to an external terminal T1 (= an application terminal of an input voltage IN). The source of the output transistor 111 is connected to an application terminal of an external terminal T2 (= an application terminal of a switch voltage SW). The gate of the output transistor 111 is connected to an application terminal of an upper gate signal G1. The output transistor 111 is turned on when the upper gate signal G1 is at a high level and turned off when the upper gate signal G1 is at a low level. When an NMOSFET is used as the output transistor 111, a bootstrap circuit or a charge pump circuit (not shown in this figure) is required to raise the high level of the upper gate signal G1 to a voltage value higher than the input voltage IN.

[0013] The synchronous rectifier transistor 112 is an NMOSFET that functions as a lower switch of the switch output stage 110. Inside the semiconductor device 200, the drain of the synchronous rectifier transistor 112 is connected to an external terminal T2 (= an application terminal of a switch voltage SW). The source of the synchronous rectifier transistor 112 is connected to a ground terminal (= an application terminal of a ground voltage GND). The gate of the synchronous rectifier transistor 112 is connected to an application terminal of a lower gate signal G2. The synchronous rectifier transistor 112 is turned on when the lower gate signal G2 is at a high level, and is turned off when the lower gate signal G2 is at a low level.

[0014] The inductor 113 and the capacitors 114 and 115 are discrete components externally attached to the semiconductor device 200. A first terminal of the capacitor 114 is connected to the external terminal T1 of the semiconductor device 200. A second terminal of the capacitor 114 is connected to the ground terminal. A first terminal of the inductor 113 is connected to the external terminal T2 of the semiconductor device 200. A second terminal of the inductor 113 and a first terminal of the capacitor 115 are connected to the application terminal of the output voltage OUT and the external terminal T3 of the semiconductor device 200. A second terminal of the capacitor 115 is connected to the ground terminal. The capacitor 114 functions as an input capacitor for smoothing the input voltage IN. Furthermore, the inductor 113 and the capacitor 115 function as an LC filter that rectifies and smoothes the switch voltage SW to generate the output voltage OUT.

[0015] The output transistor 111 and the synchronous rectifier transistor 112 are basically turned on / off in a complementary manner in response to the upper gate signal G1 and the lower gate signal G2. This on / off operation generates a square-wave switch voltage SW at the first end of the inductor 113, pulse-driven between the input voltage IN and the ground voltage GND. The term "complementary" should be understood to include not only the case where the on / off states of the output transistor 111 and the synchronous rectifier transistor 112 are completely reversed, but also the case where a period (dead time) during which both transistors are simultaneously off is provided. Furthermore, upon detection of a zero-crossing of the inductor current IL (detection of reverse flow), both the output transistor 111 and the synchronous rectifier transistor 112 may be turned off, temporarily halting the operation of the switch output stage 110 (details will be described later).

[0016] The output format of the switch output stage 110 is not limited to the step-down type described above, but may be any of step-up type, step-up / step-down type, and inverting type.

[0017] The output transistor 111 can also be replaced with a PMOSFET, in which case the above-mentioned bootstrap circuit or charge pump circuit becomes unnecessary.

[0018] It is also possible to attach the output transistor 111 and the synchronous rectifier transistor 112 externally to the semiconductor device 200. In that case, instead of the external terminal T2, external terminals for outputting the upper gate signal G1 and the lower gate signal G2 to the outside of the device, and an external terminal for receiving the input of the switch voltage SW, are required.

[0019] Furthermore, when a high voltage is applied to the switch output stage 110, it is preferable to use high-voltage elements such as a power MOSFET, an IGBT (insulated gate bipolar transistor), and a SiC transistor as the output transistor 111 and the synchronous rectifier transistor 112.

[0020] The feedback voltage generating circuit 120 includes resistors 121 and 122 connected in series between an external terminal T3 (= the application terminal of the output voltage OUT) and a ground terminal, and outputs a feedback voltage FB (= the divided voltage of the output voltage OUT) corresponding to the output voltage OUT from the connection node between the two resistors.

[0021] If the output voltage OUT is within the input dynamic range of the control circuit 140, the feedback voltage generating circuit 120 may be omitted, and the output voltage OUT itself may be directly input to the control circuit 140 as the feedback voltage FB. A speed-up capacitor may be connected in parallel to the resistor 121. The feedback voltage generating circuit 120 may be external to the semiconductor device 200.

[0022] As a basic output feedback control, the control circuit 140 performs pulse width modulation (PWM) control of the upper gate signal G1 and the lower gate signal G2 so that the feedback voltage FB matches a predetermined target value (a reference voltage REF described later).

[0023] In addition, the control circuit 140 also has a light load mode (PFM [pulse frequency modulation] mode) that, under light load conditions, thins out switching pulses and reduces switching losses by repeatedly stopping the drive of the switch output stage 110 (= output high impedance state) and restoring the drive (= resuming complementary switching operation) within a range in which the output voltage OUT does not fall below a target value.

[0024] <Control Circuit (First Embodiment)> 2 is a diagram showing a first embodiment of the control circuit 140. The control circuit 140 of this embodiment includes a reference voltage generation circuit 141, an error amplifier 142, a ramp signal generation circuit 143, an oscillator 144, a comparison signal generation circuit 145, a logic circuit 146, a drive circuit 147, and a zero-cross detection unit 148.

[0025] The reference voltage generation circuit 141 generates a reference voltage REF for setting a target value for the output voltage OUT. The reference voltage generation circuit 141 may be a digital-to-analog converter (DAC) that converts a digital reference voltage setting signal into an analog reference voltage REF. With this configuration, the reference voltage setting signal can be used to implement a soft start operation during startup and to adjust the output voltage OUT.

[0026] The error amplifier 142 generates an error signal ERR corresponding to the difference between a feedback voltage FB applied to its inverting input terminal (-) and a reference voltage REF applied to its non-inverting input terminal (+). The error signal ERR increases when the feedback voltage FB is lower than the reference voltage REF, and decreases when the feedback voltage FB is higher than the reference voltage REF. A phase compensation circuit (phase compensation resistor and phase compensation resistor) may be connected between the output terminal of the error amplifier 142 and the inverting input terminal (-) or the ground terminal.

[0027] The ramp signal generating circuit 143 generates a ramp signal RAMP having a triangular waveform, a sawtooth waveform, or an n-th order slope waveform (for example, n=2) that rises during the on-period Ton of the output transistor 111. Note that the ramp signal RAMP starts to rise from a minimum signal value RAMP1 (for example, zero value) when the output transistor 111 is turned on, and is reset to the minimum signal value RAMP1 when the output transistor 111 is turned off. In addition, by adding a current sense signal corresponding to the inductor current IL to the ramp signal RAMP, output feedback control of a current mode control method can also be performed.

[0028] The oscillator 144 generates an ON signal ON (=clock signal) that is pulse-driven at a predetermined frequency.

[0029] The comparison signal generating circuit 145 may be a comparator that compares the error signal ERR applied to the non-inverting input terminal (+) with the ramp signal RAMP applied to the inverting input terminal (-) to generate the off signal OFF. The off signal OFF corresponds to the comparison signal. The off signal OFF is at a high level when the ramp signal RAMP is lower than the error signal ERR, and is at a low level when the ramp signal RAMP is higher than the error signal ERR. In other words, the pulse generation timing of the off signal OFF is delayed as the error signal ERR is higher, and is accelerated as the error signal ERR is lower.

[0030] The logic circuit 146 basically generates the upper control signal S1 and the lower control signal S2 in response to the on signal ON and the off signal OFF. More specifically, when a pulse is generated in the on signal ON, the logic circuit 146 raises the upper control signal S1 to a high level and lowers the lower control signal S2 to a low level. As a result, the output transistor 111 turns on and the synchronous rectifier transistor 112 turns off, causing the switch voltage SW to rise to a high level (≒VIN). On the other hand, when a pulse is generated in the off signal OFF, the logic circuit 146 lowers the upper control signal S1 to a low level and raises the lower control signal S2 to a high level. As a result, the output transistor 111 turns off and the synchronous rectifier transistor 112 turns on, causing the switch voltage SW to fall to a low level (≒GND).

[0031] Therefore, the on-period Ton (=high-level period of the switch voltage SW) of the output transistor 111 is PWM controlled so that it becomes longer the later the pulse generation timing of the off signal OFF, and becomes shorter the earlier the pulse generation timing of the off signal OFF. In other words, the on-duty D (=proportion of the on-period Ton in one cycle) of the output transistor 111 becomes larger the higher the error signal ERR, and becomes smaller the lower the error signal ERR.

[0032] In addition, the logic circuit 146 has a function (so-called backflow prevention function) of turning off the synchronous rectifier transistor 112 when the output transistor 111 is turned off and the synchronous rectifier transistor 112 is turned on, at the timing when the zero-cross detection signal ZC input from the zero-cross detection unit 148 rises from low level to high level (=the zero-cross detection timing of the inductor current IL).

[0033] The drive circuit 147 includes an upper driver 147a that receives an input of an upper control signal S1 and generates an upper gate signal G1, and a lower driver 147b that receives an input of a lower control signal S2 and generates a lower gate signal G2. Note that the upper driver 147a and the lower driver 147b may each be a buffer or an inverter.

[0034] When the output transistor 111 is turned off and the synchronous rectifier transistor 112 is turned on, the zero-crossing detection unit 148 detects the zero-crossing of the inductor current IL by comparing the voltage across the synchronous rectifier transistor 112 (=switch voltage SW) with a predetermined offset voltage Vofs.

[0035] For example, as shown in this figure, the zero-cross detector 148 may be a comparator that compares the switch voltage SW input to the non-inverting input terminal (+) with the ground voltage GND input to the inverting input terminal (+) to generate the zero-cross detection signal ZC. The zero-cross detection signal ZC goes high when SW>GND, and <GNDであるときにローレベルとなる。

[0036] FIG. 3 is a diagram showing an example of a switching operation in the first embodiment, depicting, from the top, the behavior of the output voltage OUT, the switch voltage SW, and the inductor current IL.

[0037] Regarding the inductor current IL, the direction from the external terminal T2 (= the application terminal of the switch voltage SW) toward the inductor 113 is defined as the positive direction (+), and the direction from the inductor 113 toward the external terminal T2 is defined as the negative direction (-).

[0038] Before time t11, both the output transistor 111 and the synchronous rectification transistor 112 are turned off.

[0039] At time t11, when the output voltage OUT drops to a predetermined lower limit OUTL (≧target value), the output transistor 111 is turned on. Therefore, a forward inductor current IL starts to flow through a path from the application terminal of the input voltage IN via the output transistor 111 to the inductor 113, and the output voltage OUT starts to rise.

[0040] At this time, the switch voltage SW becomes a positive voltage (=IN-VdsH) lower than the input voltage IN by the drain-source voltage VdsH of the output transistor 111 (=RonH×IL, where RonH is the on-resistance value of the output transistor 111).

[0041] The drain-source voltage VdsH increases as the inductor current IL increases, and decreases as the inductor current IL decreases. Therefore, during the period Ta (=times t11 to t12), the switch voltage SW decreases as the inductor current IL increases.

[0042] At time t12, the output transistor 111 is turned off and the synchronous rectifier transistor 112 is turned on. At this time, a back electromotive force is generated in the inductor 113 due to the electrical energy stored during the period Ta. Therefore, the forward inductor current IL continues to flow through the current path from the application terminal of the ground voltage GND via the synchronous rectifier transistor 112 to the inductor 113, and the output voltage OUT continues to rise.

[0043] At this time, the switch voltage SW becomes a negative voltage (=GND-VdsL) lower than the ground voltage GND by the drain-source voltage VdsL of the synchronous rectifier transistor 112 (=RonL×IL, where RonL is the on-resistance value of the synchronous rectifier transistor 112).

[0044] The drain-source voltage VdsL increases as the inductor current IL increases, and decreases as the inductor current IL decreases. Therefore, during the period Tb (=times t12 to t13), the switch voltage SW increases as the inductor current IL decreases.

[0045] At time t13, when the switch voltage SW rises to the ground voltage GND, the synchronous rectifier transistor 112 is turned off. In this way, the synchronous rectifier transistor 112 is forcibly turned off at the timing (ZC=H) when the zero crossing of the inductor current IL is detected. Therefore, the reverse flow of the inductor current IL is blocked, and the discharge of the output voltage OUT via the synchronous rectifier transistor 112 can be suppressed. As a result, the efficiency of the switching power supply 100 can be improved.

[0046] When both the output transistor 111 and the synchronous rectifier transistor 112 are turned off, the external terminal T2 is brought into a high impedance state. Therefore, during the period Tc (=time t13 to t14), the output voltage OUT gradually decreases at a slope corresponding to the load current flowing through the load Z. Furthermore, the switch voltage SW generates ringing immediately after the synchronous rectifier transistor 112 is turned off, but eventually becomes approximately equal to the output voltage OUT.

[0047] After that, at time t14, when the output voltage OUT drops again to the predetermined lower limit OUTL, the output transistor 111 is turned on, and the output voltage OUT starts to rise. After this, by performing the same switching operation as above, the driving of the switch output stage 110 is stopped and resumed repeatedly within a range in which the output voltage OUT does not fall below the target value.

[0048] <Control Circuit (Second Embodiment)> 4 is a diagram showing a second embodiment of the control circuit 140. The control circuit 140 of this embodiment is based on the first embodiment (FIG. 2) and further includes a ramp signal holding circuit 149.

[0049] The ramp signal holding circuit 149 holds the ramp signal RAMP at a signal value RAMP2 that is higher than the minimum signal value RAMP1 (for example, a zero value) during at least a part of the forced-off period (corresponding to the period Tc in FIG. 3) of the synchronous rectifier transistor 112. Referring to this figure, the ramp signal holding circuit 149 includes a signal value setting circuit 149a and a switch 149b.

[0050] The signal value setting circuit 149a sets the signal value RAMP2. The signal value RAMP2 may be a variable value depending on the output voltage OUT. For example, the signal value RAMP2 may be a divided voltage of the output voltage OUT (=OUT×A).

[0051] The switch 149b switches whether to hold the ramp signal RAMP at the signal value RAMP2 by connecting or disconnecting the output terminal of the ramp signal generating circuit 143 and the output terminal of the signal value setting circuit 149a. The switch 149b may be controlled by, for example, the logic circuit 146.

[0052] The logic circuit 146 receives a communication signal I2C from outside the semiconductor device 200 and controls the reference voltage generating circuit 141. The communication signal I2C may include, for example, a command VID (voltage identification digital) that arbitrarily specifies the voltage value of the reference voltage REF. The communication protocol of the communication signal I2C is, for example, 2 It may also be a C [inter-integrated circuit] communication protocol.

[0053] 5 is a diagram showing an example of a switching operation in the second embodiment. In this diagram, from top to bottom, the driving state (STATUS) of the switch output stage 110, the output voltage OUT, the switch voltage SW, the inductor current IL, the feedback voltage FB and the reference voltage REF, the ramp signal RAMP and the error signal ERR, and the communication signal I2C are depicted.

[0054] The switch output stage 110 can take any one of an output high-level state H, an output low-level state L, and an output high-impedance state HiZ as its driving state (STATUS). The output high-level state H corresponds to a state in which the output transistor 111 is turned on and the synchronous rectifier transistor 112 is turned off, thereby outputting a high-level (≈IN) switch voltage SW from the external terminal T2. The output low-level state L corresponds to a state in which the output transistor 111 is turned off and the synchronous rectifier transistor 112 is turned on, thereby outputting a low-level (≈GND) switch voltage SW from the external terminal T2. The output high-impedance state HiZ corresponds to a state in which both the output transistor 111 and the synchronous rectifier transistor 112 are turned off, thereby setting the external terminal T2 to high impedance.

[0055] This figure illustrates switching operation in a state where the current consumption of the load Z is small, i.e., in a light load state. In the light load state, as shown at time t23, for example, when the switch output stage 110 is in the low output level state L, the inductor current IL falls below zero. Therefore, the synchronous rectifier transistor 112 is forcibly turned off, blocking the reverse flow of the inductor current IL. In this way, times t21 to t24 in this figure can be understood to correspond to times t11 to t14 in FIG. 3.

[0056] Here, during the forced-off period of the synchronous rectifier transistor 112 from time t23 to t24, i.e., the period during which the switch output stage 110 is in the output high impedance state HiZ, the ramp signal RAMP is held at a signal value RAMP2 (=OUT×A) corresponding to the output voltage OUT by the operation of the ramp signal holding circuit 149. That is, during the forced-off period of the synchronous rectifier transistor 112, the error signal ERR does not decrease to near the minimum signal value RAMP1 of the ramp signal RAMP even in a light load state.

[0057] Furthermore, the slope of the ramp signal RAMP when it rises may be a variable value according to the input voltage IN. With such a setting, the voltage value at which the ramp signal RAMP intersects with the error signal ERR can be made to match the signal value RAMP2 of the ramp signal RAMP that is held during the forced-off period of the synchronous rectifier transistor 112.

[0058] For example, as shown at time t24, when the feedback voltage FB falls below the reference voltage REF as the output voltage OUT drops, the output transistor 111 is turned on, and the output voltage OUT begins to rise. At this time, as described above, the error signal ERR is maintained near a signal value RAMP2 (=OUT×A) that is higher than the minimum signal value RAMP1 of the ramp signal RAMP, specifically, a voltage value corresponding to the difference between the feedback voltage FB and the reference voltage REF. Therefore, even if a sudden load fluctuation occurs, fluctuations in the output voltage OUT are suppressed. In other words, the introduction of the ramp signal hold circuit 149 can improve the load response characteristics in light load mode.

[0059] In the voltage change sequence using the command VID described above, it is necessary to return from light load mode to continuous current mode (CCM [continuous current mode]) when changing the output voltage OUT. In other words, the command VID may be understood as a command FCCM [Forcible CCM] that forcibly instructs a return from light load mode to continuous current mode.

[0060] When the above command VID (or command FCCM) is accepted, the timing of returning from the light load mode to the continuous mode generally coincides with the timing of the intersection of the ramp signal RAMP and the error signal ERR.

[0061] However, if the reference voltage REF is reduced by a command VID received in the light-load mode, a delay may occur in the timing of returning from the light-load mode to the continuous mode. For example, as shown in this figure, a case is assumed in which, after the synchronous rectifier transistor 112 is forcibly turned off at time t25, a command VID is received at time t26 to reduce the voltage value of the reference voltage REF, and therefore the lower limit value OUTL of the output voltage OUT.

[0062] In this case, the output voltage OUT gradually decreases at a slope corresponding to the load current flowing through the load Z after time t25. The error signal ERR finally begins to increase when the feedback voltage FB decreases to near the reference voltage REF that has been lowered in response to the command VID. The switch output stage 110 does not resume switching operation until the error signal ERR exceeds the ramp signal RAMP (=OUT×A) at time t27.

[0063] Therefore, the time Tx required from receipt of the command VID to returning to the continuous mode is load-dependent and cannot be controlled by the control circuit 140. Therefore, it may be difficult to complete the return to the continuous mode within the specified time Ty required for the electronic device A. For example, if the load Z is a microcomputer, the transition from the power-saving priority mode to the performance priority mode may be delayed.

[0064] In view of the above considerations, a novel embodiment is proposed below that can achieve a quick return to continuous mode.

[0065] <Control Circuit (Third Embodiment)> 6 is a diagram showing a third embodiment of the control circuit 140. The control circuit 140 of this embodiment is based on the second embodiment (FIG. 4) described above, and a new function is added to the logic circuit 146.

[0066] Referring to this figure, the logic circuit 146 generates an offset adjustment signal SD to adjust the input offset OFS of the comparison signal generation circuit 145 and outputs the signal to the comparison signal generation circuit 145. The offset adjustment signal SD may be a digital signal.

[0067] For example, the logic circuit 146 may adjust the input offset OFS of the comparison signal generation circuit 145 in a direction that reduces the difference between the error signal ERR and the ramp signal RAMP in response to a predetermined trigger signal. The trigger signal may be, for example, a command VID (or a command FCCM) input as a communication signal I2C.

[0068] 7 is a diagram showing an example of the configuration of the comparison signal generation circuit 145. The comparison signal generation circuit 145 of this example configuration includes a digital / analog conversion circuit 145a and a comparator 145b.

[0069] The digital-to-analog conversion circuit 145a converts the digital offset adjustment signal SD into an analog positive offset adjustment signal OFSP and a negative offset adjustment signal OFSN, which correspond to a first analog signal and a second analog signal, respectively.

[0070] The comparator 145b is a four-input type having two non-inverting input terminals (+) and two inverting input terminals (-). The first non-inverting input terminal (+) receives the error signal ERR. The first inverting input terminal (-) receives the ramp signal RAMP. The second non-inverting input terminal (+) receives the positive offset adjustment signal OFSP. The second inverting input terminal (-) receives the negative offset adjustment signal OFSN.

[0071] The comparator 145b compares an addition signal ADD1 (=ERR+OFSP) obtained by adding together the error signal ERR and the positive offset adjustment signal OFSP with an addition signal ADD2 (=RAMP+OFSN) obtained by adding together the ramp signal RAMP and the negative offset adjustment signal OFSN to generate an off signal OFF. Therefore, the off signal OFF goes high when the addition signal ADD1 is higher than the addition signal ADD2. On the other hand, the off signal OFF goes low when the addition signal ADD1 is lower than the addition signal ADD2.

[0072] From another perspective, the comparator 145b compares the offset error signal (ERR+OFS) with the ramp signal RAMP to generate the off signal OFF. That is, the input offset OFS of the comparison signal generation circuit 145 can be understood as a difference signal (OFSP-OFSN) between the positive offset adjustment signal OFSP and the negative offset adjustment signal OFSN.

[0073] 8 is a diagram showing a first example of a switching operation in the third embodiment. In this diagram, from top to bottom, the driving state (STATUS) of the switch output stage 110, the output voltage OUT, the switch voltage SW, the inductor current IL, the feedback voltage FB and the reference voltage REF, the ramp signal RAMP and the error signal ERR, the input offset OFS of the comparison signal generation circuit 145, and the communication signal I2C are depicted.

[0074] The behavior from time t21 to time t26 is the same as that shown in Fig. 5. Therefore, in the following, redundant explanations will be omitted, and the explanation will focus on the behavior from time t26 onwards.

[0075] As shown in the figure, when a command VID to lower the reference voltage REF is received at time t26, the input offset OFS of the comparison signal generation circuit 145 is raised. This is equivalent to the error signal ERR being artificially raised in the direction that reduces the difference between the error signal ERR and the ramp signal RAMP, as indicated by the small dashed line. In other words, the timing at which the offset error signal (ERR+OFS) intersects with the ramp signal RAMP becomes earlier (time t27 → time t27').

[0076] As a result, the time Tx required from receiving the command VID to returning to the continuous mode is shortened compared to the case of Fig. 5. Therefore, it becomes possible to complete the return to the continuous mode within the specified time Ty required for the electronic device A.

[0077] Furthermore, it is desirable to have a sequence in which the reference voltage REF is lowered after the return to the continuous mode is completed, rather than at the timing of receiving the command VID. In this figure, the lowering of the reference voltage REF is put on hold until the switching operation of the switch output stage 110 is resumed at time t27'.

[0078] Incidentally, as shown in the balloon box in the figure, the ideal behavior of returning from light load mode to continuous mode is for the inductor current IL to switch from positive to negative at the first instant after switching operation resumes at time t27'.

[0079] However, in actual recovery behavior, as with normal light load recovery, the inductor current IL may become a pulse that is only in the positive direction. In this case, if switching operation continues with the same on-duty D as immediately after light load recovery, the output voltage OUT may rise, i.e., overshoot may occur.

[0080] 9 is a diagram showing a second example of the switching operation in the third embodiment. In this diagram, as in the above-mentioned Fig. 8, from top to bottom, the drive state (STATUS) of the switch output stage 110, the output voltage OUT, the switch voltage SW, the inductor current IL, the feedback voltage FB and the reference voltage REF, the ramp signal RAMP and the error signal ERR, the input offset OFS of the comparison signal generation circuit 145, and the communication signal I2C are depicted.

[0081] The switching operation in this figure is basically the same as that in the first example (FIG. 8) described above. However, after the switching operation resumes at time t27', the input offset OFS of the comparison signal generation circuit 145 is reduced. For example, the logic circuit 146 may rapidly reduce the input offset OFS without delay in response to the turn-on of the output transistor 111, i.e., the transition of the switch voltage SW to high level.

[0082] This offset control narrows the pulse width (high-level period) of the switch voltage SW immediately after returning from the light load mode to the continuous mode, thereby making it possible to complete the return to the continuous mode within the specified time Ty from the receipt of the command VID while suppressing overshoot of the output voltage OUT.

[0083] 10 is a diagram showing an example of adjustment of the input offset OFS. Note that times t26 and t27' in this figure correspond to times t26 and t27' in FIGS. 8 and 9, respectively.

[0084] As shown by the solid line a, the logic circuit 146 may gradually increase the input offset OFS at a predetermined slope in response to a command VID (or a command FCCM) received as the communication signal I2C. This slope can adjust the amount of overshoot in the output voltage OUT and the time Tx required to return to the continuous mode.

[0085] Furthermore, as indicated by the dashed line b, the logic circuit 146 may rapidly reduce the input offset OFS without delay in response to the turn-on of the output transistor 111. This control is as exemplified in the switching operation of the second example (FIG. 9). This control is suitable, for example, when it is desired to quickly reduce the output voltage OUT.

[0086] On the other hand, as indicated by the dashed line c, the logic circuit 146 may gradually reduce the input offset OFS at a predetermined slope in response to the turn-on of the output transistor 111. This control is suitable, for example, when it is desired to suppress changes in the output voltage OUT.

[0087] <Modification> In the above series of explanations, a configuration is exemplified in which, prior to returning from the light load mode to the continuous mode, the input offset OFS of the comparison signal generation circuit 145 is increased in a direction that reduces the difference between the error signal ERR and the ramp signal RAMP. However, the method of advancing the timing at which the error signal ERR and the ramp signal RAMP intersect is not limited to the above. For example, the error signal ERR may be increased relative to the ramp signal RAMP, or the ramp signal RAMP may be decreased relative to the error signal ERR.

[0088] <Additional Notes> The power supply control device according to the present disclosure makes it possible to quickly return from the light load mode while suppressing the overshoot of the output voltage.

[0089] [Appendix 1] A power supply control device (200) configured to be a main controller of a switching power supply (100) that generates an output voltage (OUT) from an input voltage (IN) by turning on / off an output transistor (111) and a synchronous rectification transistor (112) to drive an inductor current (IL), an error amplifier (142) configured to generate an error signal (ERR) corresponding to the difference between the output voltage (OUT) or a feedback voltage (FB) corresponding thereto and a reference voltage (REF); a ramp signal generating circuit (143) configured to generate a ramp signal (RAMP) rising from a first signal value (RAMP1) during an on-period (Ta) of the output transistor (111); a comparison signal generating circuit (145) configured to generate a comparison signal (OFF) in response to the error signal (ERR) and the ramp signal (RAMP); a logic circuit (146) configured to generate pulse width modulation signals (S1, S2) in response to the comparison signal (OFF); a switch driver circuit (147) configured to drive the output transistor (111) and the synchronous rectifier transistor (112), respectively, in response to the pulse width modulation signals (S1, S2); a reverse current detection circuit (148) configured to detect a reverse current of the inductor current (IL) and forcibly turn off the synchronous rectification transistor (112); a ramp signal holding circuit (149) configured to hold the ramp signal (RAMP) at a second signal value (RAMP2) higher than the first signal value (RAMP1) during at least a part of a forced-off period (Tc) of the synchronous rectification transistor (112); Equipped with The logic circuit (146) adjusts the input offset (OFS) of the comparison signal generation circuit (145), the error signal (ERR), or the ramp signal (RAMP) in a direction that reduces the difference between the error signal (ERR) and the ramp signal (RAMP) in response to a predetermined trigger signal (I2C).

[0090] [Appendix 2] 2. The power supply control device (200) according to claim 1, wherein the ramp signal (RAMP) has a rising gradient that is a variable value according to the input voltage (IN).

[0091] [Appendix 3] 3. The power supply control device according to claim 1, wherein the second signal value (RAMP2) is a variable value that varies depending on the output voltage (OUT).

[0092] [Appendix 4] The power supply control device (200) according to any one of appendices 1 to 3, wherein the trigger signal (I2C) is a command (VID) instructing a voltage value of the reference voltage (REF) or a command (FCCM) instructing a return from a light load mode to a continuous mode.

[0093] [Appendix 5] 5. The power supply control device (200) according to any one of appendices 1 to 4, wherein the logic circuit (146) gradually increases the input offset (OFS) at a predetermined gradient in response to the trigger signal (I2C).

[0094] [Appendix 6] 6. The power supply control device (200) according to claim 5, wherein the logic circuit (146) rapidly reduces the input offset (OFS) without delay in response to the output transistor (111) being turned on.

[0095] [Appendix 7] 6. The power supply control device (200) according to claim 5, wherein the logic circuit (146) gradually reduces the input offset (OFS) at a predetermined gradient in response to the output transistor (111) being turned on.

[0096] [Appendix 8] The comparison signal generating circuit (145) a digital-to-analog conversion circuit (145a) configured to convert the digital signal (SD) into a first analog signal (OFSP) and a second analog signal (OFSN); a comparator (145b) configured to compare a first sum signal (ERR+OFSP) obtained by adding the error signal (ERR) and the first analog signal (OFSP) with a second sum signal (RAMP+OFSN) obtained by adding the ramp signal (RAMP) and the second analog signal (OFSN) to generate the comparison signal (OFF); 8. A power supply control device (200) according to any one of appendices 1 to 7, comprising:

[0097] [Appendix 9] A power supply control device (200) according to any one of Supplementary Notes 1 to 8; a switch output stage (110) configured to be controlled by the power supply control device (200); A switching power supply (100).

[0098] [Appendix 10] A switching power supply (100) according to Supplementary Note 9; a load (Z) configured to operate by receiving power supply from the switching power supply (100); An electronic device (A) comprising:

[0099] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0100] 100 Switching Power Supply 110 Switch output stage 111 Output transistor 112 Synchronous rectification transistor 113 Inductor 114, 115 Capacitors 120 Feedback voltage generation circuit 121, 122 Resistor 140 Control circuit 141 Reference voltage generation circuit 142 Error amplifier 143 Ramp signal generation circuit 144 oscillators 145 Comparison signal generation circuit 145a Digital / analog conversion circuit 145b Comparator 146 Logic Circuits 147 Drive Circuit 147a Upper driver 147b Lower driver 148 Zero-cross detector 149 Lamp signal holding circuit 149a Signal value setting circuit 149b Switch 200 Semiconductor device (power supply control device) A Electronic equipment T1, T2, T3 external terminals Z load

Claims

1. A power supply control device configured to act as a main controller of a switching power supply that generates an output voltage from an input voltage by turning on / off an output transistor and a synchronous rectification transistor to drive an inductor current, an error amplifier configured to generate an error signal corresponding to a difference between the output voltage or a feedback voltage corresponding to the output voltage and a reference voltage; a ramp signal generating circuit configured to generate a ramp signal that rises from a first signal value during an on-period of the output transistor; a comparison signal generating circuit configured to generate a comparison signal in response to the error signal and the ramp signal; a logic circuit configured to generate a pulse width modulated signal in response to the comparison signal; a switch driver circuit configured to drive each of the output transistor and the synchronous rectifier transistor in response to the pulse width modulated signal; a reverse current detection circuit configured to detect a reverse current of the inductor current and forcibly turn off the synchronous rectification transistor; a ramp signal holding circuit configured to hold the ramp signal at a second signal value higher than the first signal value during at least a portion of a forced-off period of the synchronous rectification transistor; Equipped with The logic circuit adjusts the input offset of the comparison signal generation circuit, the error signal, or the ramp signal in a direction that reduces the difference between the error signal and the ramp signal in response to a predetermined trigger signal.

2. 2. The power supply control device according to claim 1, wherein a gradient of the ramp signal when rising is a variable value that varies depending on the input voltage.

3. 2. The power supply control device according to claim 1, wherein the second signal value is a variable value that varies depending on the output voltage.

4. 2. The power supply control device according to claim 1, wherein the trigger signal is a command instructing a voltage value of the reference voltage or a command instructing a return from a light load mode to a continuous mode.

5. 2. The power supply control device according to claim 1, wherein the logic circuit gradually increases the input offset at a predetermined gradient in response to the trigger signal.

6. 6. The power supply control device according to claim 5, wherein the logic circuit rapidly reduces the input offset without delay in response to the output transistor being turned on.

7. 6. The power supply control device according to claim 5, wherein the logic circuit gradually reduces the input offset at a predetermined gradient in response to the output transistor being turned on.

8. The comparison signal generation circuit a digital-to-analog conversion circuit configured to convert the digital signal into a first analog signal and a second analog signal; a comparator configured to compare a first sum signal obtained by adding the error signal and the first analog signal with a second sum signal obtained by adding the ramp signal and the second analog signal to generate the comparison signal; The power control device of claim 1 , comprising:

9. A power supply control device according to any one of claims 1 to 8, a switch output stage configured to be controlled by the power supply controller; A switching power supply comprising:

10. A switching power supply according to claim 9; a load configured to operate by receiving power from the switching power supply; An electronic device comprising:

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