Semiconductor memory device and control method thereof

Abstract

To provide a semiconductor memory device capable of suppressing an increase in the manufacturing cost of an external device, and a control method thereof.SOLUTION: The semiconductor memory device 1 includes a calibration circuit 11 that executes a ZQ calibration operation, and a resistance unit 12 that is used as a reference resistance in the ZQ calibration operation. In addition, the control method of the semiconductor memory device 1 including the resistance unit 12 used as the reference resistance in the ZQ calibration operation includes a step in which the calibration circuit 11 of the semiconductor memory device 1 executes the ZQ calibration operation using the resistance unit 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] In conventional semiconductor memory devices, a resistor (external resistor) provided outside the semiconductor memory device is connected to the ZQ terminal of the semiconductor memory device to perform ZQ calibration in order to match the impedance of the transmission path with the output impedance of the output circuit (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123987 Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional technology, an external resistor needs to be connected to the ZQ terminal, which may increase the manufacturing cost of the external device (external system) including the external resistor. Furthermore, when a semiconductor memory device has multiple silicon dies (memory dies) such as a DDP (Dual Die Package), a different external resistor needs to be connected to each of the multiple silicon dies, which may further increase the manufacturing cost of the external device (external system) including the external resistor.

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a semiconductor memory device and a control method thereof that can suppress an increase in the manufacturing costs of an external device. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a semiconductor memory device including a calibration circuit that performs a ZQ calibration operation, and a resistor section that is used as a reference resistor in the ZQ calibration operation.

[0007] According to this invention, it is possible to perform ZQ calibration using a resistor portion provided in a semiconductor memory device, which eliminates the need to provide an external resistor for ZQ calibration in an external device, thereby suppressing the increase in manufacturing costs of the external device that would otherwise be caused by providing an external resistor.

[0008] The present invention also provides a method for controlling a semiconductor memory device, wherein the semiconductor memory device has a resistor section used as a reference resistor in a ZQ calibration operation, and the method includes a step in which a calibration circuit of the semiconductor memory device performs the ZQ calibration operation using the resistor section. [Effects of the Invention]

[0009] According to the semiconductor memory device and the control method thereof of the present invention, it is possible to suppress an increase in the manufacturing costs of the external device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a diagram illustrating a configuration example of a resistor unit. [Figure 3] FIG. 1A is a diagram showing an example of a configuration for adjusting the resistance value of a resistor unit, and FIG. 1B is a diagram showing an example of a timing chart of voltage values ​​corresponding to the resistance value of the resistor unit. [Figure 4] FIG. 10 is a diagram showing an example of a timing chart of the output voltage of the calibration circuit in the calibration operation. DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device 1 according to an embodiment of the present invention. The semiconductor memory device 1 according to this embodiment is, for example, a DRAM such as a DDR4 SDRAM (Double-Data-Rate 4 Synchronous Dynamic Random Access Memory) and includes one or more memory dies (chips) 10. In this embodiment, the semiconductor memory device 1 is provided with one ZQ terminal 20 for each of the one or more memory dies 10. Note that while FIG. 1 illustrates a case in which one memory die 10 is provided within the semiconductor memory device 1, the semiconductor memory device 1 may include multiple memory dies 10. In addition, for the sake of simplicity, other well-known components of the semiconductor memory device 1 (e.g., a power supply circuit, a command decoder, an address decoder, a clock generator, etc.) are not shown here.

[0012] In this embodiment, the memory die 10 includes a calibration circuit 11 and a resistor section 12 .

[0013] The calibration circuit 11 includes a plurality of P-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) P1 to Pi (i is an integer equal to or greater than 2), and is configured to perform ZQ calibration operations. A source terminal of each of the P-channel MOSFETs P1 to Pi is connected to an operating voltage VDD, and a drain terminal of each of the P-channel MOSFETs P1 to Pi is connected to a resistor unit 12 via a node N. A control signal for controlling the on / off of each of the P-channel MOSFETs P1 to Pi is input to a gate terminal of each of the P-channel MOSFETs P1 to Pi.

[0014] In this embodiment, the case where the calibration circuit 11 includes a plurality of P-channel MOSFETs P1 to Pi will be described as an example, but the calibration circuit 11 may include a plurality of N-channel MOSFETs, a plurality of other transistors, or a plurality of switch circuits instead of the plurality of P-channel MOSFETs P1 to Pi. The calibration operation performed in the calibration circuit 11 will be described later.

[0015] The resistance section 12 is configured to be used as a reference resistance in the ZQ calibration operation. In this embodiment, the resistance section 12 includes a plurality of resistance units U1 to Uj (j is an integer equal to or greater than 2) connected in parallel to the calibration circuit 11, as shown in Fig. 2. This makes it possible to configure a reference resistance in the ZQ calibration operation using the plurality of resistance units U1 to Uj.

[0016] In this embodiment, each of the plurality of resistor units U1 to Uj includes a plurality of (four in the example shown in FIG. 2) resistors 12a, 12b, R1, and R2 connected in series, and a plurality of (three in the example shown in FIG. 2) switch sections SW1, SW2, and SW3. Each of the plurality of resistor units U1 to Uj is configured such that one end of the Nth (N is an integer equal to or greater than 1) switch section SWN is connected to one end of the Nth resistor RN, one end of the (N+1) switch section SW(N+1) is connected to the other end of the Nth resistor, and the other ends of the Nth switch section SWN and the (N+1) switch section SW(N+1) are connected to each other. 2, one end of the first (N=1) switch section SW1 is connected to one end of the first resistor R1, one end of the second switch section SW2 is connected to the other end of the first resistor R1, and the other ends of the first switch section SW1 and the second switch section SW2 are connected to each other. Also, one end of the second (N=2) switch section SW2 is connected to one end of the second resistor R2, and one end of the third switch section SW3 is connected to the other end of the second resistor R2, and the other ends of the second switch section SW2 and the third switch section SW3 are connected to each other.

[0017] In this embodiment, the case where three switch sections SW1, SW2, SW3 are provided in each of the plurality of resistor units U1 to Uj has been described as an example, but the number of switch sections provided in each of the plurality of resistor units U1 to Uj may be two or less, or may be four or more. Furthermore, the number of switch sections provided in each of the plurality of resistor units U1 to Uj may be the same for each of the plurality of resistor units U1 to Uj, or may be different for each of the plurality of resistor units U1 to Uj.

[0018] Furthermore, in this embodiment, the case where four resistors 12a, 12b, R1, and R2 are provided in each of the plurality of resistor units U1 to Uj has been described as an example, but the number of resistors provided in each of the plurality of resistor units U1 to Uj may be three or less, or may be five or more. Furthermore, the number of resistors provided in each of the plurality of resistor units U1 to Uj may be the same for each of the plurality of resistor units U1 to Uj, or may be different for each of the plurality of resistor units U1 to Uj.

[0019] In this embodiment, each of the multiple resistor units U1 to Uj is configured to have a resistance value corresponding to the switch unit in the ON state when any of the multiple switch units SW1, SW2, and SW3 is turned on. Specifically, each of the multiple resistor units U1 to Uj is controlled so that only one of the multiple switch units SW1, SW2, and SW3 is turned on. For example, when the first switch unit SW1 of the resistor unit U1 is turned on and the second switch unit SW2 and the third switch unit SW3 are turned off, the resistance value of the resistor unit U1 is represented by the sum of the resistance values ​​of the resistors 12a and 12b. Furthermore, when the second switch unit SW2 of the resistor unit U1 is turned on and the first switch unit SW1 and the third switch unit SW3 are turned off, the resistance value of the resistor unit U1 is represented by the sum of the resistance values ​​of the resistors 12a, 12b, and the first resistor R1. Furthermore, when the third switch section SW3 of the resistor unit U1 is in an ON state and the first switch section SW1 and the second switch section SW2 are in an OFF state, the resistance value of the resistor unit U1 is expressed as the sum of the resistance values ​​of the resistors 12a, 12b, the first resistor R1, and the second resistor R2. In this way, each of the multiple resistor units U1 to Uj can have a different resistance value depending on the ON state of the switch section.

[0020] In this embodiment, each of the multiple switch sections SW1, SW2, and SW3 is configured to include a transfer transistor. This makes it possible to easily turn on the transfer transistor by turning on either a P-channel MOSFET or an N-channel MOSFET that constitutes the transfer transistor. Note that, although the case where each of the multiple switch sections SW1, SW2, and SW3 is configured to include a transfer transistor is described here as an example, at least one of the multiple switch sections SW1, SW2, and SW3 may be configured to include a switch circuit other than a transfer transistor (for example, a P-channel MOSFET or an N-channel MOSFET).

[0021] Each of the resistor units U1 to Uj may have the same resistance value. This makes it possible to easily configure a reference resistor for the ZQ calibration operation using resistor units U1 to Uj having the same resistance value. For example, if the resistance value of the resistor section 12 is 240Ω and there are 10 resistor units, the resistance value of each resistor unit may be set to 2400Ω.

[0022] Here, an example of a method for adjusting the resistance value of each of the plurality of resistor units U1 to Uj will be described with reference to FIG. 3. In the example shown in FIG. 3(a), a predetermined voltage V1 is applied to the resistor unit U1, and the other end of each of the switches SW1, SW2, and SW3 is connected to one (+) input terminal of a comparator C. A predetermined reference voltage Vref is input to the other (-) input terminal of the comparator C. Furthermore, the comparator C is configured to compare a voltage Vin input to the one (+) input terminal with a reference voltage Vref input to the other (-) input terminal, and output the comparison result as an output voltage Vout. In this embodiment, a case will be described in which the resistance value of the resistor unit U1 is adjusted, assuming that the resistor unit U1 has a desired resistance value when its output voltage (i.e., voltage Vin) is equal to the reference voltage Vref.

[0023] As shown in Fig. 3(b), in resistor unit U1, first switch section SW1 is set to the ON state, then second switch section SW2 is set to the ON state, and then third switch section SW3 is set to the ON state. Then, among the multiple switch sections SW1, SW2, and SW3, a switch section (second switch section SW2 in the example shown in Fig. 3(b)) that makes voltage Vin and reference voltage Vref equal when set to the ON state is identified, and the identified switch section is set to the ON state, thereby adjusting the resistance value of resistor unit U1. Furthermore, the resistance values ​​of other resistor units U2 to Uj may be adjusted in a similar manner.

[0024] Note that, since the resistance values ​​of the resistors 12a, 12b, R1, and R2 provided in the plurality of resistor units U1-Uj may differ for each of the plurality of resistor units U1-Uj depending on characteristics such as process and temperature, the switch unit that, when set to the ON state, makes the voltage Vin equal to the reference voltage Vref may be different for each of the plurality of resistor units U1-Uj. Also, in the example shown in Fig. 3(b), a case is described as an example in which the first switch unit SW1 is set to the ON state first, then the second switch unit SW2 is set to the ON state, and then the third switch unit SW3 is set to the ON state, but the order in which the switch units are set to the ON state may be determined arbitrarily (for example, the third switch unit SW3 may be set to the ON state first, then the second switch unit SW2 may be set to the ON state, and then the first switch unit SW1 may be set to the ON state).

[0025] 1, the ZQ terminal 20 is a terminal that can be connected to an external resistor for the ZQ calibration operation. Note that, since the resistor section 12 used as a reference resistor in the ZQ calibration operation is provided within the semiconductor memory device 1, the ZQ terminal 20 does not need to have the same configuration as in the prior art (i.e., a configuration that is provided so as to be connectable to both the calibration circuit 11 and the external resistor). In this embodiment, the ZQ terminal 20 is provided in a state that is not connected to the calibration circuit 11 or the resistor section 12.

[0026] Incidentally, conventional semiconductor memory devices are provided with terminals for data input / output (e.g., DQ terminals) in addition to the ZQ terminal 20. Here, the data input / output terminals (pads) must be formed to a size that allows contact with probe pins (probe needles, probe needles) of a probe card during wafer testing. However, if the size of the data input / output terminals (pad size) increases, the charge / discharge current at the data input / output terminals increases, which may increase the power consumption of the semiconductor memory device. Also, it is conceivable to provide a data output terminal dedicated to wafer testing in the semiconductor memory device in addition to the data output terminal used during normal operation of the semiconductor memory device. However, in this case, it is necessary to newly provide a data output terminal dedicated to wafer testing in the semiconductor memory device (memory die), which may increase the size of the semiconductor memory device (memory die).

[0027] Therefore, in this embodiment, the ZQ terminal 20 is configured to be used for inputting and outputting data during wafer testing. This eliminates the need to increase the size (pad size) of the data output terminal (DQ terminal) used during normal operation of the semiconductor memory device 1, making it possible to suppress an increase in power consumption of the semiconductor memory device 1. Furthermore, since there is no need to provide a data output terminal dedicated to wafer testing, it is possible to suppress an increase in the size of the semiconductor memory device 1 (memory die 10).

[0028] In this embodiment, the ZQ terminal 20 may be connected to a data input / output circuit (not shown) for transmitting and receiving, for example, a data signal (DQ) or a data strobe signal (DQS, / DQS) to and from an external device. The ZQ terminal 20 may also be formed to a size that allows contact with a probe pin of a probe card during wafer testing. This allows the data input / output circuit of the semiconductor memory device 1 to transmit and receive data to and from a probe card via the ZQ terminal 20 during wafer testing, and to transmit and receive data to and from an external device via a data output terminal (DQ terminal) during normal operation. The terminal used for transmitting and receiving data may be switched using, for example, a switch circuit or the like.

[0029] Note that Figure 1 shows a case where one ZQ terminal 20 is provided for one memory die 10, but if the semiconductor memory device 1 has multiple memory dies 10, one ZQ terminal 20 may be provided for each of the multiple memory dies 10, or one common ZQ terminal 20 may be provided for the multiple memory dies 10.

[0030] 4, a calibration operation performed in the calibration circuit 11 of the semiconductor memory device 1 of this embodiment will be described. In this embodiment, the calibration circuit 11 performs the calibration operation using the resistance section 12. Note that, here, a case where the calibration operation is performed in the calibration circuit 11 will be described, assuming that impedance matching is achieved between the resistance section 12 and the voltage V of the node N in FIG. 1 when the voltage V is equal to a predetermined voltage (for example, VDD / 2).

[0031] At the start of the calibration operation, each of the multiple P-channel MOSFETs P1 to Pi is in the OFF state. First, when the P-channel MOSFET P1 is set to the ON state, the voltage V at the node N rises. Next, when the P-channel MOSFET P2 is set to the ON state while the P-channel MOSFET P1 is on, the voltage V at the node N rises further. Furthermore, when the P-channel MOSFETs P1 and P2 are on and the P-channel MOSFET P3 is set to the ON state, the voltage V at the node N rises further. In this way, the calibration operation is performed by sequentially setting each of the multiple P-channel MOSFETs P1 to Pi to the ON state until the voltage V at the node N becomes equal to a predetermined voltage (for example, VDD / 2). Although FIG. 4 shows a case where the calibration operation is performed so that the voltage V of the node N rises to a predetermined voltage (for example, VDD / 2), the calibration operation may also be performed so that the voltage V of the node N falls to the predetermined voltage (for example, VDD / 2) (that is, each of the multiple P-channel MOSFETs P1 to Pi may be set to an ON state at the start of the calibration operation, and may be set to an OFF state in turn until the voltage V of the node N becomes equal to the predetermined voltage (for example, VDD / 2)).

[0032] Furthermore, the node N of the calibration circuit 11 may be connected to, for example, a terminal (pad) (not shown) for a data signal (DQ) or a terminal (pad) (not shown) for a data strobe signal (DQS, / DQS). This makes it possible to set the resistance obtained in the calibration operation (i.e., the combined resistance of the on-resistances of at least one P-channel MOSFET set to be in the on state among the multiple P-channel MOSFETs P1 to Pi) as the output impedance.

[0033] As described above, the semiconductor memory device 1 and the control method thereof according to this embodiment make it possible to perform the ZQ calibration operation using the resistor unit 12 provided in the semiconductor memory device 1, thereby eliminating the need to provide an external resistor for ZQ calibration in the external device, thereby preventing the manufacturing costs of the external device from increasing due to the provision of an external resistor.

[0034] The above-described embodiments have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, each element disclosed in the above embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0035] For example, in the above-described embodiment, the semiconductor memory device is a DRAM, but the present invention is not limited to this. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a pSRAM (Pseudo-Static Random Access Memory), a flash memory, or another semiconductor memory device.

[0036] Furthermore, the configurations of the calibration circuit 11 and the resistance section 12 shown in FIGS. 1 and 2 are merely examples, and may be changed as appropriate, or well-known configurations or various other configurations may be adopted. [Explanation of symbols]

[0037] 1...Semiconductor memory device 10...Memory die 11...Calibration circuit 12...Resistance part 20...ZQ terminal R1…1st resistor R2…Second resistor SW1: First switch SW2: Second switch section SW3: Third switch section U1, U2, Uj...Resistor units

Claims

1. a calibration circuit that performs a ZQ calibration operation; a resistor unit used as a reference resistor in the ZQ calibration operation; Semiconductor memory device.

2. a terminal that can be connected to an external resistor for the ZQ calibration operation and is used for inputting and outputting data in a wafer test; 2. The semiconductor memory device according to claim 1.

3. the terminal is not connected to the calibration circuit and the resistor section; 3. The semiconductor memory device according to claim 2.

4. a plurality of memory dies; the resistor portion is provided for each of the plurality of memory dies, 2. The semiconductor memory device according to claim 1.

5. The resistor section includes a plurality of resistor units connected in parallel.

2. The semiconductor memory device according to claim 1.

6. Each of the plurality of resistor units has the same resistance value.

6. The semiconductor memory device according to claim 5.

7. At least one of the plurality of resistor units includes a plurality of switch units, and is configured to have a resistance value corresponding to the switch unit in the on state when any one of the plurality of switch units is in the on state.

6. The semiconductor memory device according to claim 5.

8. At least one switch unit among the plurality of switch units includes a transfer transistor.

8. The semiconductor memory device according to claim 7.

9. The at least one resistance unit comprises: a plurality of resistors connected in series; an Nth switch unit having one end connected to one end of an Nth resistor (N is an integer equal to or greater than 1) among the plurality of resistors; an (N+1)th switch unit having one end connected to the other end of the Nth resistor; The other end of the Nth switch unit is connected to the other end of the (N+1)th switch unit.

8. The semiconductor memory device according to claim 7.

10. The semiconductor memory device is a dynamic random access memory.

2. The semiconductor memory device according to claim 1.

11. A method for controlling a semiconductor memory device, comprising: the semiconductor memory device includes a resistor unit used as a reference resistor in a ZQ calibration operation; a calibration circuit of the semiconductor memory device performing the ZQ calibration operation using the resistor unit; A method for controlling a semiconductor memory device.

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