Power conversion device and control method

Abstract

To suppress fluctuation of neutral point potential in a wide operation region.SOLUTION: A power conversion device according to an embodiment of the present invention includes two power converters and a control unit. In each of the two power converters, a DC-side terminal is connected to a connection point between the first DC capacitor and the second DC capacitor connected in series, and an AC-side terminal is connectable to a three phase system. The control unit superimposes a predetermined first zero phase voltage value in one power converter of the two power converters on a voltage command value of each phase of the one power converter, imposes a limitation on a superimposition amount of the zero phase voltage value, and superimposes an exceeding first zero phase voltage value based on a first voltage value that cannot be superimposed due to the limitation on a voltage command value of each phase of the other power converter of the two power converters to obtain a voltage command value of each phase of the other power converter.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a power conversion device and a control method. [Background technology]

[0002] A power conversion device is known in which an AC system is connected to one side of a plurality of power converters using switching elements, and a plurality of DC capacitors are connected in series to the DC section on the other side. In such a power conversion device, fluctuations in the neutral point potential of one of the power converters are suppressed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6900759 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there exists an operating region where fluctuations cannot be suppressed completely.

[0005] The embodiments of the present invention have been made in consideration of the above circumstances, and provide a power conversion device and a control method that can suppress fluctuations in neutral point potential over a wide operating range. [Means for solving the problem]

[0006] A power conversion device according to an embodiment of the present invention includes two power converters and a control unit. The two power converters each have a DC-side terminal connected to a junction between a first DC capacitor and a second DC capacitor connected in series, and an AC-side terminal connectable to a three-phase system. The control unit superimposes a predetermined zero-phase voltage value of one of the two power converters on a voltage command value for each phase of the one power converter, limits the amount of superimposition of the zero-phase voltage value, and superimposes an excess first zero-phase voltage value based on the first voltage value that could not be superimposed due to the limit on a voltage command value for each phase of the other power converter, thereby setting the voltage command value for each phase of the other power converter. [Effects of the Invention]

[0007] According to the present invention, fluctuations in the neutral point potential can be suppressed over a wide operating range. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a power conversion device. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a circuit for suppressing fluctuations in neutral point potential by a control device. [Figure 3] 4 is a state diagram showing an example of the operation of the first power converter and the second power converter. [Figure 4] FIG. 5 is a state diagram showing an example of operation of the first power converter and the second power converter according to the comparative example. [Figure 5] FIG. 10 is a diagram showing an example of the configuration of a fluctuation suppression circuit according to a second embodiment. [Figure 6] FIG. 10 is a diagram showing an example of the configuration of a fluctuation suppression circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, a power conversion device and a control method according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that the embodiment described below is an example of an embodiment of the present invention, and the present invention should not be interpreted as being limited to these embodiments. Furthermore, in the drawings referred to in this embodiment, identical parts or parts having similar functions are given the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, part of the configuration may be omitted from the drawings.

[0010] FIG. 1 is a diagram showing an example of the configuration of a power conversion device 1 according to this embodiment. The power generation system 1 includes a first power converter 10, a second power converter 20, and a control unit 100. The first power converter 10 is, for example, an example of the circuit configuration of a neutral-point-clamped (NPC) converter, and the second power converter 20 is, for example, an example of the circuit configuration of a neutral-point-clamped inverter. Note that in this embodiment, an NPC inverter is used as an example of a neutral-point-clamped power converter, but this is not limiting. For example, the neutral point clamp may be a T-type neutral point clamp, or may be another type.

[0011] The control unit 100 controls the first power converter 10 and the second power converter 20. The control unit 100 executes control to suppress fluctuations in the zero-phase voltage Vnp of the first power converter 10 and the second power converter 20. For example, the control unit 100 executes control of the first power converter 10 using a first voltage command value obtained by superimposing a predetermined zero-phase voltage of the first power converter 10 on a voltage command value for each phase. Furthermore, the control unit 100 according to this embodiment executes control of the second power converter 20 using a second voltage command value obtained by superimposing an excessive first zero-phase voltage that could not be superimposed on a voltage command value for each phase of the second power converter 20. Details of the control unit 100 will be described later.

[0012] 1, in the DC link section, the AC terminals of a UVW-phase converter including a U-phase first power converter 10 are connected to a load in which a high-potential-side capacitor C1 and a low-potential-side capacitor C2 are connected in series, and the AC power source is connected to the AC terminals of a UVW-phase inverter including a u-phase second power converter 20. The zero-phase voltage Vnp is a potential obtained by subtracting the potential Vdc2 of the low-potential-side capacitor C2 from the potential Vdc1 of the high-potential-side capacitor C1 and dividing the result by 2.

[0013] The first power converter 10 includes four switching elements SW_C1, SW_C2, SW_C3, and SW_C4 connected in series from the high-potential side to the low-potential side to form legs; four freewheeling diodes D_C1, D_C2, D_C3, and D_C4 connected in anti-parallel with each switching element in a one-to-one relationship; two switching elements SW_C5 and SW_C6 connected in series from the interconnection point of the switching elements SW_C1 and SW_C2 to the interconnection point of the switching elements SW_C3 and SW_C4; and two diodes D_C5 and D_C6 connected in anti-parallel with the switching elements SW_C5 and SW_C6 in a one-to-one relationship. Capacitor C1 stores a DC voltage vdc1, and capacitor C2 stores a DC voltage vdc2. The collector of each switching element is the high-potential side, and the emitter is the low-potential side. Each diode has a cathode as the high-potential side and an anode as the low-potential side.

[0014] A current iuc is output from the interconnection point of the switching elements SW_C2 and SW_C3 to the outside of the first power converter 10. The interconnection point of the switching elements SW_C5 and SW_C6 is connected to the neutral point NP (potential is vn), which is the interconnection point of the capacitors C1 and C2, and a current inc flows through it. The configuration of the V-phase and W-phase converters is the same as that of the U-phase first power converter 10.

[0015] The u-phase second power converter 20 also has four switching elements SW_I1, SW_I2, SW_I3, and SW_I4 connected in series from the high potential side to the low potential side to form legs, four freewheeling diodes D_I1, D_I2, D_I3, and D_I4 connected in anti-parallel to each switching element in a one-to-one relationship, two switching elements SW_I5 and SW_I6 connected in series from the interconnection point of the switching elements SW_I1 and SW_I2 to the interconnection point of the switching elements SW_I3 and SW_I4, and two diodes D_I5 and D_I6 connected in anti-parallel to the switching elements SW_I5 and SW_I6 in a one-to-one relationship.

[0016] A current iui is output from the interconnection point of the switching elements SW_I2 and SW_I3 to the outside of the second power converter 20. The interconnection point of the switching elements SW_I5 and SW_I6 is connected to the neutral point NP, and a current ini flows through it. The configuration of the v-phase and w-phase inverters is the same as that of the u-phase second power converter 20.

[0017] The fluctuation suppression circuit 110 will be described using Fig. 2 with reference to Fig. 3. Fig. 2 is a diagram showing an example of the configuration of the neutral point potential fluctuation suppression circuit 110 controlled by the control unit 100. As shown in Fig. 2, the fluctuation suppression circuit 110 has a first calculation unit 30, an adder circuit 31, a first modulation factor limiting circuit 32, a subtractor circuit 33, a multiplier circuit 34, an adder circuit 35, and a second modulation factor limiting circuit 36. In the following description, when the processing of the u phase, v phase, and w phase, or the processing of the U phase, V phase, and W phase are equivalent, u, v, and w may be represented as x or X. In other words, x may be represented as u, v, and w, or X may be represented as U, V, and W.

[0018] 3 is a state diagram showing an example of the operation of the first power converter 10 and the second power converter 20. The horizontal axis represents time, and the vertical axis represents the final voltage command value v' of the first power converter 10 from the top. 1x0 (v' 1u0 , v' 1v0 , v' 1w0 ) and the first zero-phase voltage v 10 , the output current i of the first power converter 10 1x (i 1u , i 1v, i 1w ), the final voltage command value v' of the second power converter 21u0 (v' 21u0 , v' 21v0 , v' 21w0 ) and excess first zero-phase voltage v' 10 ×K 12 , the output current i of the second power converter 20 2x (i 2u , i 2v , i 2w ), capacitor voltage v po ,v pn , neutral point potential v np Shows.

[0019] First, the first calculation unit 30 calculates the zero-phase voltage v 10 is calculated using equation (1). 1x is the voltage command value of each phase leg before the zero-sequence voltage is superimposed. 1x represents the current output from the leg of each phase of the first power converter 10. sign represents the sign function.

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[0020] Next, the adder circuit 31 calculates the voltage command value v before voltage superposition according to equation (2). 1x The first zero-phase voltage v 10 The value of is added to the voltage command value v 1x0 Generate.

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[0021] Next, the final voltage command value v' in Fig. 3 1x0 and the first zero-phase voltage v 10 As shown in the figure, the first modulation rate limiting circuit 32 limits the added voltage command value v 1x0 The amplitude of the added voltage command value v is set to, for example, a range of 1 pu. 1x0 The final voltage command value v' is obtained by limiting the modulation rate to a fixed upper or lower limit value, for example, in the range exceeding 1 pu. 1x0 Generate.

[0022] Next, the subtraction circuit 33 subtracts the voltage command value v before the first zero-phase voltage is superimposed. 1x0 to the final voltage command value v' 1x0 is subtracted, and the final voltage command value v' is obtained. 1x0 The first voltage v' that could not be superimposed on 10 is generated according to equation (3).

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[0023] Next, the multiplication circuit 34 multiplies the coefficient K 12 The first voltage v' 10 Multiplying by this gives the first voltage v' 10 The excess first zero-phase voltage v' is a factor of 10 ×K 12 Generate the coefficient K 12 is the excess first zero-phase voltage v' 10 The zero-phase voltage v' of the second power converter 21x This is a coefficient for converting to

[0024] Next, the adder circuit 35 calculates the voltage command value v of the second power converter 20 according to equation (4). 2x The first zero-phase voltage v' exceeds 10 ×K 12 is superimposed to obtain the added voltage command value v 21x0 Generate.

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[0025] Next, the final voltage command value v' of the second power converter in FIG. 21x0 and excess first zero-phase voltage v' 10 ×K 12 As shown in the figure, the second modulation rate limiting circuit 36 ​​limits the added voltage command value v 21x0 The amplitude of the added voltage command value v is set to, for example, a range of 1 pu. 1x0 The final voltage command value v' is obtained by limiting the modulation rate to a fixed upper or lower limit value, for example, in the range exceeding 1 pu. 21x0Generate.

[0026] FIG. 4 shows a comparative example in which the voltage command value v 2x In other words, the final voltage command value v of the second power converter 20 is 2x The first zero-phase voltage v' exceeds 10 ×K 12 This differs from Figure 3 in that it is not superimposed.

[0027] The horizontal axis represents time, and the vertical axis represents the final voltage command value v′ of the first power converter 10 from the top. 1u0 , v' 1v0 , v' 1w0 and the first zero-phase voltage v 10 , the output current i of the first power converter 10 1u , i 1v , i 1w , the final voltage command value v of the second power converter 2x , the output current i of the second power converter 20 2u , i 2v , i 2w , capacitor voltage v po ,v pn , neutral point potential v np Shows.

[0028] The neutral point potential v np The amplitude of the neutral point potential v in the comparative example of FIG. np The amplitude of the voltage command value v of each phase of the second power converter 20 is in the range of 0.1 to −0.1. 2x , the excess first zero-phase voltage v' 10 ×K 12 The final voltage command value v' 21x0 By controlling the second power converter 20 in accordance with the above, the neutral point potential v np Therefore, the amplitude fluctuation can be suppressed.

[0029] As described above, according to this embodiment, the voltage command value v 2x , the excess first zero-phase voltage v' 10 ×K 12The final voltage command value v' 21x0 As a result, the zero-phase voltage v 10 Even for the operating region where the addition of the neutral point potential v np In this way, the amplitude fluctuation of the zero-phase voltage v 10 For the operating region where the addition of the voltage command value v 2x The first zero-phase voltage v on the first power converter 10 side that could not be added 10 Excessive first zero-phase voltage v' based on 10 ×K 12 , the voltage command value v of each phase of the second power converter 20. 2x By adding to the neutral point potential v np Therefore, the amplitude fluctuation can be further suppressed.

[0030] (Second embodiment) The power conversion device 1 according to the second embodiment has a voltage command value v 2x , the second zero-phase voltage v of the second power converter 20 20 The power conversion device 1 of the first embodiment differs from the power conversion device 1 of the first embodiment in that the power conversion device 1 of the first embodiment is superimposed in advance. The following describes the differences from the power conversion device 1 of the first embodiment.

[0031] 5 is a diagram showing an example of the configuration of a fluctuation suppression circuit 110 according to the second embodiment. As shown in FIG. 4, the fluctuation suppression circuit 110 further includes a second calculation unit 37, an addition circuit 38, and a third modulation factor limiting circuit 39. With this configuration, the fluctuation suppression circuit 110 according to the second embodiment can suppress the voltage command value v 2x , the second power converter 20 zero-phase voltage v 20 The difference from the fluctuation suppression circuit 110 according to the first embodiment is that the fluctuation suppression circuit 110 is subjected to superimposition processing.

[0032] The second calculation unit 37 calculates the second zero-phase voltage v 20 is calculated using equation (5). 2x is the voltage command value of each phase leg before the zero-sequence voltage is superimposed. 2xrepresents the current output from the leg of each phase of the second power converter 20. sign represents the sign function.

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[0033] Next, the adder circuit 38 calculates the voltage command value v before voltage superposition according to equation (6). 2x The second zero-phase voltage v 20 The value of is added to the voltage command value v 2x0 Generate.

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[0034] Next, the third modulation rate limiting circuit 39 limits the added voltage command value v 2x0 The amplitude of the added voltage command value v is set to, for example, a range of 1 pu. 2x0 For example, the adjusted voltage command value v' is set by limiting the range exceeding 1 pu to a fixed upper or lower limit. 2x0 Generate.

[0035] Next, the adder circuit 35 calculates the adjusted voltage command value v′ of the second power converter 20 according to equation (7). 2x0 The first zero-phase voltage v' exceeds 10 ×K 12 is superimposed to obtain the added voltage command value v 21x0 Generate.

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[0036] As described above, according to this embodiment, the voltage command value v 2x , the second zero-phase voltage v of the second power converter 20 20 After superimposing and limiting, the excess first zero-phase voltage v' 10 ×K 12 The final voltage command value v' is obtained by superimposing 21x0As a result, the neutral point potential v np Therefore, the amplitude fluctuation can be further suppressed.

[0037] (Third embodiment) The power conversion device 1 according to the third embodiment differs from the power conversion device 1 according to the second embodiment in that the excess second zero-phase voltage that could not be superimposed on the second power converter 20 side is superimposed on the first voltage command value for each phase of the first power converter 10. The differences from the power conversion device 1 according to the second embodiment will be described below.

[0038] 6 is a diagram showing an example of the configuration of a fluctuation suppression circuit 110 according to the third embodiment. As shown in FIG. 6, the fluctuation suppression circuit 110 according to the third embodiment further includes a subtraction circuit 40, a multiplication circuit 41, an addition circuit 42, and a fourth modulation factor limiting circuit 43. With this configuration, the fluctuation suppression circuit 110 according to the third embodiment can suppress the excessive second zero-phase voltage v' that could not be superimposed on the second power converter 20 side. 20 is the first voltage command value v' 1x0 The fluctuation suppression circuit 110 according to the second embodiment differs from the fluctuation suppression circuit 110 according to the second embodiment in that the fluctuation suppression circuit 110 is superimposed on the fluctuation suppression circuit 110.

[0039] As shown in FIG. 6, the subtraction circuit 40 calculates the voltage command value v before the second zero-phase voltage is superimposed. 2x0 to the adjusted voltage command value v' 2x0 is subtracted and the adjusted voltage command value v' is obtained. 2x0 The second voltage v' that could not be superimposed on 20 is generated according to equation (8).

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[0040] Next, the multiplication circuit 41 multiplies the coefficient K 21 The second voltage v' 20 Multiplying by this gives the second voltage v' 20 The excess second zero-phase voltage v' is a factor of 20 ×K 21 Generate the coefficient K 21 is the excess second zero-phase voltage v' 20is a coefficient for converting the voltage Vout into a zero-phase sequence voltage for addition of the first power converter 10.

[0041] Next, the adder circuit 42 calculates the adjusted voltage command value v′ of the first power converter 10 according to equation (9). 1x0 The second zero-phase voltage V' exceeds 20 ×K 21 is superimposed to obtain the added voltage command value v 12x0 Generate.

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[0042] Next, the fourth modulation rate limiting circuit 43 limits the added voltage command value v 12x0 The amplitude of the added voltage command value v is set to, for example, a range of 1 pu. 21x0 The final voltage command value v' is obtained by limiting the range exceeding 1 pu to a fixed upper or lower limit. 12x0 The subsequent processing is the same as that of the fluctuation suppressor circuit 110 according to the second embodiment.

[0043] Furthermore, the coefficient K 12 can be calculated using, for example, equation (10), and the coefficient K 21 can be calculated using, for example, equation (11).

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[0044] As a result, the zero-phase voltage v 20 Even for the operating region where the addition of the neutral point potential v np Therefore, the amplitude fluctuation can be further suppressed. [Explanation of symbols]

[0045] 1: power conversion device, 10: first power converter, 20: second power converter, 30: first calculation unit, 31: adder circuit, 32: first modulation factor limiting circuit, 33: subtraction circuit, 34: multiplication circuit, 35: adder circuit, 36: second modulation factor limiting circuit, 37: second calculation unit, 38: adder circuit, 39: third modulation factor limiting circuit, 40: subtraction circuit, 41: multiplication circuit, 42: adder circuit, 43: fourth modulation factor limiting circuit, 100: control unit, 110: fluctuation suppression circuit

Claims

1. two power converters each having a DC side terminal connected to a junction point of the first DC capacitor and the second DC capacitor connected in series and each having an AC side terminal connectable to a three-phase system; superimposing a predetermined first zero-phase voltage value in one of the two power converters on voltage command values ​​for each phase of the one power converter; limiting an amount of superimposition of the first zero-phase-sequence voltage value, and superimposing an excess first zero-phase-sequence voltage value based on the first voltage value that could not be superimposed due to the limit on a voltage command value for each phase of the other power converter of the two power converters; a control unit that sets the voltage command values ​​for each phase of the other power converter; A power conversion device comprising:

2. The power conversion device according to claim 1 , wherein the control unit multiplies the first voltage value by a predetermined coefficient to obtain the excessive first zero-phase voltage value.

3. The power conversion device according to claim 1 , wherein the control unit calculates the first zero-phase voltage value using a predetermined calculation formula.

4. 4. The power conversion device according to claim 3, wherein the control unit calculates the first zero-phase voltage value based on a voltage command value before superimposing the first zero-phase voltage value of the leg of each phase and a current value output from the leg of each phase of the one power converter.

5. The power conversion device according to claim 1 , wherein the control unit limits the amount of superimposition of the first zero-phase-sequence voltage value so that a modulation factor does not exceed a predetermined value.

6. 3. The power conversion device according to claim 1, wherein the control unit superimposes a second zero-phase-sequence voltage value corresponding to the other power converter on a voltage command value in the other power converter, limits an amount of superimposition of the second zero-phase-sequence voltage value, and then superimposes the excessive first zero-phase-sequence voltage value on the voltage command values ​​for each phase of the other power converter.

7. The control unit The power conversion device according to claim 6 , wherein the second zero-phase-sequence voltage value is not superimposed, and the excessive first zero-phase-sequence voltage value is superimposed on a voltage command value for each phase of the other power converter.

8. The control unit superimposing a second zero-phase-sequence voltage value corresponding to the other power converter on a voltage command value for the other power converter, and limiting the amount of superimposition of the second zero-phase-sequence voltage value; 3. The power conversion device according to claim 1, wherein a second excessive zero-phase voltage value based on the second voltage value that could not be superimposed due to the restriction is superimposed on the voltage command values ​​for each phase of the one power converter to set the voltage command values ​​for each phase of the one power converter.

9. The power conversion device according to claim 2 , wherein the magnitude of the coefficient is a ratio between an output voltage value and a current value of the one power converter and an output voltage value and a current value of the other power converter.

10. A control method for a power conversion device having two power converters, each having a DC side terminal connected to a junction point of a first DC capacitor and a second DC capacitor connected in series, and each having an AC side terminal connectable to a three-phase system, comprising: superimposing a predetermined first zero-phase voltage value in one of the two power converters on voltage command values ​​for each phase of the one power converter; limiting an amount of superimposition of the first zero-phase-sequence voltage value, and superimposing an excess first zero-phase-sequence voltage value based on the first voltage value that could not be superimposed due to the limit on a voltage command value for each phase of the other power converter of the two power converters; a control method for a power conversion device, wherein the voltage command values ​​for each phase of the other power converter are set as voltage command values ​​for each phase of the other power converter.

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