Neural network apparatus and method of operating the same

Abstract

To provide a neural network device that performs an operation on data having a higher number of bits than a limited bit resolution of a digital-to-analog converter, and an operation method thereof.SOLUTION: The neural network device includes a digital-analog converter that converts a digital input into an analog input of either a voltage or a current, a cell array 2 that includes a plurality of memory cells that are arranged in a plurality of bit lines and a plurality of word lines and store neural network weights, performs an operation on the analog input input via the word lines, and outputs an analog output of either a current or a voltage via the bit lines, an analog-digital converter that converts the analog output into a digital output, and at least one processor that is electrically connected to the digital-analog converter and the analog-digital converter and executes control on the digital input and the digital output.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to neural network devices and methods of operation thereof, and more particularly to methods of performing more precise bit operations using neural network devices having relatively small bit resolution. [Background technology]

[0002] Artificial neural networks mimic biological neural networks, can be trained by inputting a large amount of data, and are used to estimate or approximate results that are difficult to derive using conventional techniques. Artificial neural networks contain layers of interconnected neurons that exchange signals, and synapses have weights determined based on learning or experience.

[0003] On the other hand, CIM (Computing in Memory) devices that perform analog calculations process data within the memory, minimizing data transfer between the memory and the processor and improving calculation speed. However, when implemented in edge computing devices, there is a problem that precise calculations are difficult due to size constraints.

[0004] The above-mentioned background art is technical information that the inventor possessed for the purpose of deriving the present invention or that he acquired in the process of deriving the present invention, and is not necessarily publicly known art that was made public to the general public prior to the filing of the present invention. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a neural network device and an operating method thereof. The problems to be solved by the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present invention and will be more clearly understood by the embodiments of the present disclosure. Furthermore, it will be understood that the problems and advantages to be solved by the present disclosure can be achieved by the means and combinations thereof set forth in the claims. [Means for solving the problem]

[0006] As a means for solving the above technical problems, a first aspect of the present disclosure can provide a neural network device including: a digital-to-analog converter that converts a digital input into an analog input of either a voltage or a current; a cell array that is arranged on a plurality of bit lines and a plurality of word lines and includes a plurality of memory cells that store neural network weights, and that performs an operation on the analog input input via the word lines and outputs an analog output of either a current or a voltage via the bit lines; an analog-to-digital converter that converts the analog output into a digital output; and at least one processor that is electrically connected to the digital-to-analog converter and the analog-to-digital converter and that executes control over the digital input and the digital output, wherein the at least one processor inputs one or more digital inputs including at least a portion of the input signal to the digital-to-analog converter based on the number of bits of the input signal and a DAC bit resolution of the digital-to-analog converter, and generates the output signal using at least one of the digital outputs corresponding to the output of the bit line based on the number of bits of the input signal and the cell bit resolution of the plurality of memory cells.

[0007] A second aspect of the present disclosure may provide a method for operating a neural network device, including: generating one or more digital inputs including at least a portion of an input signal based on the number of bits of the input signal and a DAC bit resolution of a digital-to-analog converter; obtaining one or more digital outputs corresponding to the one or more digital inputs using a cell array including a plurality of memory cells that store weights of a neural network; and generating the output signal using at least one of the digital outputs based on the number of bits of the input signal and the cell bit resolution of the plurality of memory cells.

[0008] A third aspect of the present disclosure can provide a computer-readable recording medium having recorded thereon a program for causing a computer to execute the method of the second aspect.

[0009] In addition, other methods and devices for realizing the present invention, and computer-readable recording media having recorded thereon programs for executing the methods can also be provided.

[0010] Other aspects, features, and advantages beyond those described above will become apparent from the following drawings, claims, and detailed description of the invention. [Effects of the Invention]

[0011] According to the above-described means for solving the problems of the present disclosure, it is possible to perform operations on data having a higher number of bits than the limited bit resolution of a digital-to-analog converter.

[0012] Furthermore, according to the means for solving the problems of the present disclosure, it is possible to generate an output having a number of bits higher than the bit resolution of the limited memory cells.

[0013] The effects of the embodiments are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the present invention. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram illustrating the implementation of a neural network system according to an embodiment. [Figure 2] 1 is an exemplary diagram for comparing a Von Neumann architecture and a CIM (computing in memory) architecture according to an embodiment of the present invention. [Figure 3] 1 is an exemplary diagram for comparing a Von Neumann architecture and a CIM (computing in memory) architecture according to an embodiment of the present invention. [Figure 4] FIG. 1 illustrates a neural network device according to an embodiment of the present invention. [Figure 5A] 10A and 10B are diagrams illustrating an operation method of a cell array according to an embodiment; [Figure 5B] 10A and 10B are diagrams illustrating an operation method of a cell array according to an embodiment; [Figure 6A] FIG. 10 is a diagram for comparing a matrix-vector multiplication with operations performed in a cell array, according to one embodiment. [Figure 6B] FIG. 10 is a diagram for comparing a matrix-vector multiplication with operations performed in a cell array, according to one embodiment. [Figure 7] 10A and 10B are diagrams illustrating an example in which a convolution operation is performed in a cell array according to an embodiment. [Figure 8] 1 is a diagram illustrating an operation method of a neural network device according to an embodiment of the present invention. [Figure 9] FIG. 2 is a diagram illustrating a digital input according to an embodiment of the present invention. [Figure 10] 10A and 10B are diagrams illustrating a method for generating an output signal according to an embodiment of the present invention. [Figure 11] FIG. 10 is a diagram illustrating a digital input according to another embodiment of the present invention. [Figure 12] 10A and 10B are diagrams illustrating a method for generating an output signal according to another embodiment of the present invention. [Figure 13] 10A and 10B are diagrams illustrating an operation method of a neural network device according to another embodiment of the present invention. [Figure 14] 10A and 10B are diagrams illustrating a method for generating an output signal according to another embodiment of the present invention. [Figure 15] 10A and 10B are diagrams illustrating a method for generating an output signal according to another embodiment of the present invention. [Figure 16] 3 is a flowchart of a method for operating a neural network device according to an embodiment of the present invention. [Figure 17] FIG. 10 is a block diagram of a neural network device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] When describing the present invention, if it is determined that a specific description of related publicly known technology would obscure the gist of the present invention, that detailed description may be omitted, and unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by a person having ordinary skill in the art to which the present invention belongs.

[0016] Appearances of phrases such as "in one embodiment," "related to one embodiment," or "in accordance with the implementation of one embodiment" in this specification do not necessarily all refer to the same embodiment.

[0017] Since the embodiments can be modified in various ways and can have various forms, some embodiments are shown in the drawings and described in detail. However, this is not intended to limit the embodiments to the particular disclosed form, but should be understood to include all modifications, equivalents, or alternatives falling within the spirit and technical scope of the embodiments. The terms used in the specification are used merely to describe the embodiments and are not intended to limit the embodiments.

[0018] The terms used in the embodiments are currently commonly used general terms that have been selected as much as possible while taking into consideration the functions of the embodiments, but these may change depending on the intentions of engineers engaged in the technical field to which the embodiments belong, precedents, the emergence of new technologies, etc. In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, the meanings thereof will be described in detail in the relevant section. Therefore, the terms used in the embodiments should be defined based on the meanings of the terms and the overall content of the embodiments, rather than simply the names of the terms.

[0019] Some embodiments of the present disclosure may be represented by functional blocks and various processing steps. Some or all of these functional blocks may be implemented by various hardware and / or software components that perform specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors or by circuitry for a given function.

[0020] Also, for example, the functional blocks of the present disclosure may be implemented in various programming or scripting languages, or may be implemented in algorithms executed on one or more processors, and the present disclosure may employ conventional techniques for electronic configuration, signal processing, and / or data processing, etc.

[0021] Terms such as "database," "element," "means," and "configuration" can be used broadly and are not limited to mechanical and physical configurations. Furthermore, terms such as "module" and "unit" used in the specification refer to a unit that processes at least one function or operation, and may be realized by hardware or software, or a combination of hardware and software.

[0022] Furthermore, the connecting lines or members between components shown in the figures are merely exemplary functional and / or physical or circuit connections, and in an actual device the connections between components may be represented by various alternative or additional functional, physical, or circuit connections.

[0023] Furthermore, terms including ordinal numbers such as "first" or "second" used herein may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another.

[0024] In addition, the size and proportion of some components in the drawings may be slightly exaggerated. Furthermore, components shown in one drawing may not be shown in another drawing.

[0025] Throughout the specification, the term "embodiment" is an arbitrary category for easily describing the invention in the present disclosure, and the embodiments are not necessarily mutually exclusive. For example, a configuration disclosed in one embodiment may be applied and / or implemented in other embodiments, and may be modified and applied and / or implemented without departing from the scope of the present disclosure.

[0026] Furthermore, the terms used in this disclosure are for the purpose of describing the embodiments and are not intended to limit the embodiments. In this disclosure, the singular forms "a," "an," and "the" also include the plural forms unless otherwise specified.

[0027]

[0033] The present disclosure will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein.

[0028] The invention will be explained in more detail below on this basis with reference to the drawings.

[0029] FIG. 1 is a diagram for explaining the implementation of a neural network system according to an embodiment.

[0030] Referring to FIG. 1, a trained neural network 10 and a device 20 in which the neural network 10 is implemented can be seen.

[0031] The term "trained" for neural network 10 means that the weights of each layer of neural network 10 have been determined based on a large amount of training data. If the weights resulting from the training of neural network 10 are stored in a central cloud server, a cloud computing device using neural network 10 can communicate with the central cloud server to send input values ​​to neural network 10 and receive output values. In this case, even if neural network 10 is very complex or large-scale, the cloud computing device can use the output values ​​without any problems.

[0032] However, if the device 20 is an edge computing device that processes data from the device itself without communicating with a central cloud server, the weights of the neural network 10 determined by learning are stored in the device 20, which is actual hardware, specifically in memory cells that make up the cell array of the device 20. In this case, the device 20 may be a neuromorphic chip.

[0033] Neuromorphic chips are hardware that mimic the functions of the human brain by creating circuits that mimic the morphology of neurons. In other words, neuromorphic chips are computer chips that mimic the structure of the nervous system. Because neuromorphic chips are composed only of the circuits necessary for neural network calculations, they offer hundreds of times the benefits in terms of power, area, and speed. Neuromorphic chips mimic the way the brain works by configuring the neuron-synapse connections in parallel, and by connecting and disconnecting when not processing data, they conserve energy. For example, conventional computers, such as the von Neumann architecture, process input data sequentially, making them excellent for executing precisely written programs. However, they suffer from limitations in power consumption and inefficiencies in pattern recognition and real-time recognition. In contrast, neuromorphic chips use analog operations, where data gradually changes between states, rather than digital ones like 0 and 1. In other words, parallel-configured artificial neurons operate in an event-driven manner without a clock. This allows them to efficiently process atypical characters, sounds, and images that conventional computers find difficult to intuitively recognize.

[0034] In one embodiment, when input data such as an image, sound, or electromagnetic wave is input to the neuromorphic chip, the input data can be processed within the neuromorphic chip to output predetermined output data. In this case, the data input to the neuromorphic chip is not limited to the above-mentioned image, sound, or electromagnetic wave, but can include various types of data such as video and text.

[0035] According to one embodiment, a neuromorphic device can be implemented using an Edge AI Chip. Edge AI refers to a technology that executes AI algorithms on hardware devices using edge computing based on data generated by the system. AI processing is primarily performed in cloud-based data centers, which require massive computing capacity and are highly dependent on servers. On the other hand, Edge AI allows AI algorithm operations to be performed locally, reducing dependency on the cloud (server), thereby reducing communication costs and protecting privacy by preventing sensitive personal information from being sent to the cloud. Therefore, configuring a neuromorphic device with an Edge AI Chip not only reduces costs and improves security, but also enables highly responsive systems to be realized by immediately executing operations within the same hardware.

[0036] Meanwhile, in neural network 10, the state values ​​of each weight can be very diverse (e.g., 128 states), and the memory cells of the cell array realized in device 20 are formed of multi-bit (e.g., 8-bit) memory cells to store the weight state values. Meanwhile, in order to perform operations on data input from device 20, the cell array of the neural network must be composed of memory cells having state values ​​equal to or greater than the resolution of the input data, i.e., the number of bits of the input data, and the digital-to-analog converter of device 20 must also have a resolution equal to or greater than the number of bits of the input data.

[0037] However, implementing a neural network with high-resolution memory cells can be excessively costly, and high-resolution digital-to-analog converters can occupy a large area and unnecessarily increase the size of device 20. Therefore, when considering the size and cost of device 20, a high-precision (i.e., processing data with a large number of bits) computational method is necessary even if device 20 is composed of low-resolution components.

[0038] As used herein, "cell bit resolution" refers to the number of distinct state values ​​that a memory cell can represent, expressed in bits. For example, a cell bit resolution of 7 bits for a memory cell may indicate that the memory cell stores any of 128 distinct state values.

[0039] In the following description, the device 20 according to an embodiment of the present invention, i.e., the neural network device, may be the neuromorphic device described above, i.e., the neuromorphic device described above may function as a neural network device according to an embodiment of the present invention.

[0040] 2 and 3 are exemplary diagrams for comparing a Von Neumann architecture and a computing in memory (CIM) architecture according to an embodiment of the present invention.

[0041] Referring to Figure 2, the von Neumann architecture is a computer architecture proposed by John von Neumann. It is a stored-program computer architecture consisting of a typical three-layer architecture of main memory, central processing unit, and input / output units.

[0042] The von Neumann architecture has the advantage of being highly versatile, since when changing from one computing device to another, only the software (program) needs to be changed without the need to rearrange the hardware (wires, etc.). However, because it requires sequential execution of a list of instructions, each of which changes the value of a specific memory location, it causes a serious problem in the design of high-speed computers, known as the von Neumann bottleneck.

[0043] To solve the von Neumann bottleneck, alternatives that have been proposed include the Harvard architecture, which divides memory into areas where instructions are stored and areas where data is stored; the CIM architecture, which not only stores data but also performs data calculations from memory; and neuromorphic computing, an artificial neural network-type integrated circuit that mimics the brain structure of higher animals, in which many units with integrated calculation and memory functions are connected in parallel like a network, and each unit operates in an event-driven manner.

[0044] Referring to Figure 3, it can be seen that the CIM architecture consists of a processor and memory with computing capabilities.

[0045] Unlike the conventional von Neumann architecture, in which all data in memory is moved to the processor for calculation, the CIM architecture performs calculations in memory when a processor instruction is passed, and only the result data is transferred to the processor, eliminating the need to move large amounts of data, effectively resolving the von Neumann bottleneck mentioned above. Another advantage is significantly lower power consumption.

[0046] A neural network device according to an embodiment of the present invention can perform operations using only on-chip memory without using external memory. For example, the neural network can perform operations without memory updates during input signal processing by performing operations for each layer on a CIM basis using only on-chip memory without using external memory (e.g., off-chip memory). Specifically, the neural network device can perform CIM-based operations in which each memory cell is directly connected to a processor.

[0047] However, CIM-based AI chips perform calculations directly within their internal memory without transferring data to external memory, eliminating the bottleneck caused by data movement between the memory and the calculation device. This allows CIM-based AI chips to fundamentally solve the memory bandwidth problem. Furthermore, this structure offers the advantages of reducing power consumption and minimizing heat generation. The cell array of a neural network device according to one embodiment of the present invention can be configured with multi-bit realizable memory to maximize the calculation speed of such a CIM architecture. For example, a neural network device can be configured with 7-bit (128 analog memory states) realizable memory. By configuring a neural network with a large capacity, it can process large amounts of data with low power consumption and high performance, even over long periods of use, unlike conventional CIM chips, which suffer from issues such as heat generation and performance degradation.

[0048] On the other hand, on-chip memory can be realized by a cell array. That is, the cell array can receive instructions from a processor and perform operations, and CIM operations can be achieved by integrating memory cells of the cell array into the on-chip memory. For example, the processor can receive an input signal and drive a neural network device trained based on predetermined training data to obtain an output signal.

[0049] FIG. 4 is a diagram illustrating a neural network device according to an embodiment of the present invention.

[0050] The neural network device can be realized in various types of devices such as a personal computer (PC), a server device, a mobile device, and an embedded device, and specific examples thereof include, but are not limited to, smartphones, tablet devices, augmented reality (AR) devices, Internet of Things (IoT) devices, self-driving cars, robotics, medical equipment, etc. that perform speech recognition, image recognition, image classification, etc. using a neural network. Furthermore, the neural network device can correspond to a dedicated hardware accelerator (HW accelerator) installed in such devices, and the neural network device can be, but is not limited to, a hardware accelerator such as an NPU (neural processing unit), a TPU (tensor processing unit), or a Neural Engine, which is a dedicated module for driving a neural network.

[0051] The neural network device may include a digital-to-analog converter 1, a cell array 2, an analog-to-digital converter 3, and a processor 4. The neural network device shown in Fig. 4 only includes components related to this embodiment, and it will be obvious to one of ordinary skill in the art that the neural network device may further include other general-purpose components in addition to the components shown in Fig. 4.

[0052] A neural network device according to one embodiment may include a digital-to-analog converter 1.

[0053] A digital-to-analog converter 1 according to one embodiment can convert an input signal having a digital value into an analog signal. For example, the analog signal can be a voltage or a current. That is, the digital-to-analog converter 1 can convert a digital input into an analog input of either a voltage or a current. For example, the digital-to-analog converter 1 can receive a digital voltage composed of multiple bits, convert it into an analog voltage corresponding to the number of bit lines, and apply the analog voltages to multiple bit lines.

[0054] The neural network device according to one embodiment may include a cell array 2 including a plurality of memory cells arranged on a plurality of bit lines and a plurality of word lines.

[0055] A plurality of word lines of the cell array 2 according to an embodiment are connected to the digital-to-analog converter 1 and can receive an analog input converted from the digital input from the digital-to-analog converter 1.

[0056] As described above, the memory cells can store the weights of a neural network. For example, when an analog input is input via each of the word lines of the cell array 2, a MAC (multiply and accumulate) operation is performed with the weights of the neural network stored in the memory cells, and an analog output can be output via each of the bit lines. In this case, similar to the analog input, the analog output can be either a current or voltage signal.

[0057] The neural network device according to one embodiment may include an analog-to-digital converter 3 .

[0058] An analog-to-digital converter 3 according to one embodiment is connected to a plurality of bit lines of the cell array 2 and is capable of receiving an analog output.

[0059] The analog-to-digital converter 3 according to one embodiment can convert an analog output into a digital output having a digital value. That is, the analog-to-digital converter 3 can convert either a voltage or a current analog output into a digital output. As an example, the analog-to-digital converter 3 can receive analog voltages output from multiple bit lines and convert them into a digital output having a predetermined number of bits.

[0060] In one embodiment, the processor 4 is electrically connected to the digital-to-analog converter 1 and the analog-to-digital converter 3, and can perform control over the digital input and digital output. Specifically, the processor 4 can control the digital input based on the input signal, and can control the output signal based on the digital output.

[0061] 5A and 5B are diagrams illustrating a method of operating a cell array according to an embodiment.

[0062] 5A, the cell array may include a plurality of memory cells 530. Here, the memory cells 530 may be elements whose electrical conductance or weight changes depending on an electrical pulse, for example, a voltage or a current, applied across them. For example, each memory cell 530 may be a resistive crossbar memory array (RCA), or may be a multi-level memory such as a resistive RAM (ReRAM), a ferroelectric RAM (FeRAM), a phase-change RAM (PRAM), a magnetic RAM (MRAM), or a NAND / NOR flash memory.

[0063] In one embodiment, the cell array may provide wiring 512 extending in a first direction (e.g., horizontal direction) and wiring 522 extending in a second direction (e.g., vertical direction) intersecting the first direction. For convenience of explanation, the wiring 512 extending in the first direction will be referred to as row lines, and the wiring 522 extending in the second direction will be referred to as column lines. A plurality of memory cells 530 are arranged at each intersection of the row wiring 512 and the column wiring 522, and can connect corresponding row wiring 512 and corresponding column wiring 522.

[0064] The memory cell 530 can be implemented to have various characteristics, such as exhibiting analog behavior in which the conductivity changes gradually depending on the number of input electrical pulses rather than an abrupt change in resistance during the set and reset operations. Specifically, the processor of the neural network device can apply a varying voltage to the memory cell 530. This can gradually change the resistance or weight of the memory cell 530.

[0065] The operation of the above cell array will be explained below with reference to Fig. 5B. For convenience of explanation, the row wirings 512 can be referred to as the first row wiring 512A, the second row wiring 512B, the third row wiring 512C, and the fourth row wiring 512D from top to bottom, and the column wirings 522 can be referred to as the first column wiring 522A, the second column wiring 522B, the third column wiring 522C, and the fourth column wiring 522D from left to right.

[0066] 5B , in an initial state, all of the memory cells 530 may be in a relatively low conductivity state, i.e., a high resistance state. If at least some of the memory cells 530 are in a low resistance state, an initialization operation may be required to set them to a high resistance state. Each of the memory cells 530 may have a predetermined threshold required for a change in resistance and / or conductivity. More specifically, when a voltage or current less than the predetermined threshold is applied across each memory cell 530, the conductivity of the memory cell 530 remains unchanged, whereas when a voltage or current greater than the predetermined threshold is applied to the memory cell 530, the conductivity of the memory cell 530 may change.

[0067] In this state, an input signal (or an analog input into which the input signal is converted) corresponding to the particular data can be input to the row wires 512 to operate to output the particular data as a result of the particular column wires 522. For example, the input signal can appear as the application of an electrical pulse to each of the row wires 512. Furthermore, the column wires 522 can be driven with an appropriate voltage or current for output.

[0068] For convenience of explanation, the following description will be given taking a single-bit (1-bit) operation as an example. In one example, when a column wiring 522 that outputs specific data is already determined, the column wiring 522 may be driven to apply a voltage of a magnitude equal to or greater than a voltage required for a set operation (hereinafter, referred to as a set voltage) to a memory cell 530 located at an intersection with a row wiring 512 corresponding to “1,” and the remaining column wirings 522 may be driven to apply a voltage of a magnitude smaller than the set voltage to the remaining memory cells 530. For example, when the set voltage has a magnitude of Vset and the column wiring 522 that outputs data “0011” is determined to be the third column wiring 522C, the magnitude of the electrical pulse applied to the third and fourth row wirings 512C and 512D may be equal to or greater than Vset, and the voltage applied to the third column wiring 522C may be 0V, so that the first and second memory cells 530A and 530B located at the intersection of the third column wiring 522C and the third and fourth row wirings 512C and 512D are applied with a voltage of Vset or greater. Therefore, the first and second memory cells 530A and 530B can be placed in a low resistance state. The conductivity of the first and second memory cells 530A and 530B in the low resistance state can gradually increase as the number of electrical pulses increases. The size and width of the applied electrical pulses can be substantially constant. The voltages applied to the remaining column wirings, i.e., the first, second, and fourth column wirings 522A, 522B, and 522D, can have a value between 0 V and Vset, for example, ½ Vset, so that the remaining memory cells 530, excluding the first and second memory cells 530A and 530B, are applied with a voltage less than Vset. Therefore, the resistance states of the remaining memory cells 530, excluding the first and second memory cells 530A and 530B, may not change.

[0069] As another example, the column wiring 522 that outputs the specific data may not be determined. In this case, the current flowing through each column wiring 522 is measured while an electrical pulse corresponding to the specific data is applied to the row wiring 512, and the column wiring 522 that first reaches a predetermined threshold current, for example, the third column wiring 522C, can be the column wiring 522 that outputs the specific data.

[0070] In this manner, different data can be output to different column wirings 522, respectively.

[0071] Meanwhile, the row wiring 512 of the cell array may refer to a word line, and the column wiring 522 of the cell array may refer to a bit line.

[0072] 6A-6B are diagrams for comparing a matrix-vector multiplication with operations performed in a cell array, according to one embodiment.

[0073] 6A, the convolution operation between the input data and the kernel can be performed using a vector-matrix multiplication. For example, the input data can be represented by matrix X 610, and the weight values ​​can be represented as a kernel by matrix W 611. The output data can be represented by matrix Y 612, which is the result of the multiplication of matrix X 610 and matrix W 611.

[0074] Referring to Figure 6B, a vector multiplication operation can be performed using multiple memory cells of a cell array. Compared to Figure 6A, input data can be received as an input value of a memory cell, which can be a voltage 620. Furthermore, a weight value can be stored in a synapse of the core, i.e., a memory cell, which can be a conductance 621. Therefore, the output value of the memory cell can be represented by a current 622, which is a result of the multiplication operation between the voltage 620 and the conductance 621.

[0075] FIG. 7 is a diagram illustrating an example in which a convolution operation is performed in a cell array according to an embodiment.

[0076] In one embodiment, the neural network device may receive an input signal 710. Here, the input signal 710 may be a digital input having a digital value. The input signal 710 may be converted to an analog input 701 via a digital-to-analog converter 720. The converted analog input 701 may then be input to a plurality of word lines of a core 700 implemented as at least a portion of a cell array.

[0077] Additionally, the core 700 may store learned kernel values ​​in multiple memory cells. For example, the kernel values ​​stored in the multiple memory cells may be conductances 702. In this case, the cell array may calculate an output value by performing a vector multiplication operation between an analog input 701 and the conductance 702, and the output value may be represented as an analog output 703 (e.g., a current value).

[0078] Because the analog output 703 (e.g., current) output from the core 700 is an analog signal, the analog output 703 can be converted to a digital input via an analog-to-digital converter 730 for use as input data for other cores 750 in the cell array. The cell array can convert the analog output 703 to a digital signal using the analog-to-digital converter 730. In one embodiment, the neural network device can use the analog-to-digital converter 730 to convert the analog output 703 to a digital signal having the same bit resolution as the number of bits of the input signal 710. For example, if the number of bits of the input signal 710 is 1-bit resolution, the neural network device can use the analog-to-digital converter 730 to convert the analog output 703 to a digital signal with 1-bit resolution.

[0079] The neural network device can use the activation unit 740 to apply an activation function to the digital signal converted by the analog-to-digital converter 730. The activation function can be a Sigmoid function, a Tanh function, or a ReLU (Rectified Linear Unit) function, but is not limited to these. The digital signal to which the activation function has been applied can be used as an input value of another core 750. When the digital signal to which the activation function has been applied is used as an input value of another core 750, the above-described process can be similarly applied to the other core 750.

[0080] On the other hand, the core 700 and the other core 750 are not physically separated, but rather the weight values ​​of the memory cells included in the cell array are changed according to the weight and / or bias values ​​of each core 700, 750.

[0081] Meanwhile, the number of bits of the input signal 710 can have various bit resolution values, such as 1-bit, 4-bit, and 8-bit resolution. In this case, the number of bits of the input signal 710 may be higher than the resolution of the memory cells included in the cell array 700. In this case, calculation can be performed by setting the number of bits of the input signal 710 to be equal to or lower than the resolution of the memory cells included in the cell array 700, but this poses a problem in that calculations with higher accuracy cannot be performed. Therefore, a calculation method for solving this problem will be described with reference to FIG. 8 and subsequent figures.

[0082] FIG. 8 is a diagram illustrating a method of operating a neural network device according to an embodiment of the present invention.

[0083] 8 shows an environment in which a processor of a neural network device generates an output signal based on an input signal. That is, while FIG. 8 shows only components (e.g., cell array 2) for explaining the execution process of the processor, the environment is not limited thereto and may include additional omitted components.

[0084] Alternatively, the processor may be a component of control logic (not shown) included in the neural network device, or may be a component provided separately from the control logic (not shown).

[0085] In one embodiment, the processor may generate one or more digital inputs 811, 812 based on the input signal 800. As an example, the processor may input one or more digital inputs including at least a portion of the input signal 800 to a digital-to-analog converter (not shown) based on the number of bits of the input signal 800 and the bit resolution (hereinafter referred to as "DAC bit resolution") of the digital-to-analog converter (not shown).

[0086] For example, the processor can input the input signal 800 as digital inputs 811, 812 to a digital-to-analog converter (not shown) based on the number of bits of the input signal 800 and the DAC bit resolution, and can also generate multiple digital inputs 811, 812 including at least a portion of the input signal 800 based on the number of bits of the input signal 800 and the DAC bit resolution, and input the generated multiple digital inputs 811, 812 to the digital-to-analog converter (not shown).

[0087] FIG. 9 is a diagram for explaining a digital input according to an embodiment of the present invention.

[0088] 9, in response to the number of bits of input signal 900 exceeding the DAC bit resolution, the processor may input two or more digital inputs including at least a portion of input signal 900 to the digital-to-analog converter. For example, in response to the number of bits of input signal 900 being 16 bits and the DAC bit resolution being 8 bits, the processor may input two or more digital inputs including at least a portion of input signal 900 to the digital-to-analog converter.

[0089] In one embodiment, the two or more digital inputs may include an upper bit sequence 931 corresponding to the upper bits 921 of the input signal 900 and a lower bit sequence 932 corresponding to the lower bits 922 of the input signal 900. For example, if the input signal 900 is 16-bit data, the upper bit sequence 931 may be a bit sequence corresponding to the upper 8 bits of the input signal 900, and the lower bit sequence 932 may be a bit sequence corresponding to the lower 8 bits of the input signal 900. As another example, if the input signal 900 is 16-bit data, the upper bit sequence 931 may be a bit sequence corresponding to the upper 10 bits of the input signal 900, and the lower bit sequence 932 may be a bit sequence corresponding to the lower 6 bits of the input signal 900. In this case, however, the DAC bit resolution must be 10 bits or greater, as described below.

[0090] On the other hand, the multiple bits constituting the most significant bits 921 of the input signal 900 have values ​​that are higher on average than the multiple bits constituting the least significant bits 922 in the input signal 900. In one embodiment, the most significant bits 921 of the input signal 900 can be a bit string from a first bit positioned higher than the reference bit 901 to the reference bit 901, and the least significant bits 922 can be a bit string from the multiple bits of the most significant bits 921 and one of the bits 902 next to the reference bit 901 to a second bit positioned lower than the bit 902 next to the reference bit 901.

[0091] In one embodiment, if the DAC bit resolution is n and the most significant bit of the input signal 900 is referred to as the first-placed bit, the reference bit 901 may be the n-th placed bit of the input signal 900. In another embodiment, the reference bit 901 may be either the most significant bit or the n-th placed bit of the input signal 900.

[0092] In one embodiment, the upper bit string 931 may be the upper bits 921 of the input signal 900 shifted to the right by the first bit length 910 so that the least significant bit (LSB) of the upper bit string 931 is aligned with the least significant bit of the input signal 900.

[0093] Here, the least significant bit refers to the bit located at the lowest position in a bit string. For example, the least significant bit of a bit string (1, 1, 1, 1, 1, 1, 1, 0) may be 0. Furthermore, aligning the least significant bit of the upper bit string 931 with the least significant bit of the input signal 900 may mean removing the remaining bits of the input signal 900 except for the upper bit 921 so that the least significant bit of the upper bit string 931 is at the same position as the least significant bit of the input signal 900.

[0094] In one embodiment, the upper bit sequence 931 can be a bit sequence from the most significant bit (MSB) of the input signal 900 to the reference bit 901, and the lower bit sequence 932 can be a bit sequence from multiple bits of the upper bit 921 of the input signal 900 and one of the bits 902 next to the reference bit 901 to the least significant bit of the input signal 900.

[0095] Here, the most significant bit means the bit located highest in a bit string. For example, in a bit string (1, 0, 0, 0, 0, 0, 0, 0), the most significant bit may be 1.

[0096] As an example, if the lower bit sequence 932 is a bit sequence from the bit 902 next to the reference bit 901 to the least significant bit of the input signal 900, the first bit length 910 may be the number of bits of the lower bit sequence 932. In other words, if the lower bit sequence 932 is a bit sequence from the bit 902 next to the reference bit 901 to the least significant bit of the input signal 900, the input signal 900 is divided into the upper bit sequence 931 and the lower bit sequence 932 without any overlapping bits, so the first bit length 910 may be the number of bits of the lower bit sequence 932. While FIG. 9 shows a case where the input signal 900 is divided in half to generate the upper bit sequence 931 and the lower bit sequence 932, the numbers of bits of the upper bit sequence 931 and the lower bit sequence 932 may vary depending on the position of the reference bit 901.

[0097] For example, if the input signal 900 has 16 bits (1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0), and the reference bit is the 9th digit 1, the upper bit sequence 931 is (1, 1, 0, 1, 0, 0, 0, 1), in which the remaining bits (1, 1, 1, 1, 0, 0, 1, 0) excluding the upper bit portion of the input signal 900 have been removed, and the lower bit sequence 932 can be (1, 1, 1, 1, 0, 0, 1, 0), which is the bit sequence from 1, the bit next to the reference bit, to the least significant bit.

[0098] On the other hand, the number of bits of the digital input may be equal to or less than the DAC bit resolution. That is, according to one embodiment of the present invention, even if an input signal having a number of bits higher than the DAC bit resolution is input, the processor can generate two or more digital inputs (e.g., 931, 932) having a number of bits equal to or less than the DAC bit resolution, and input them to the digital-to-analog converter.

[0099] Returning to FIG. 8 , one or more digital inputs 811, 812 can be input to a plurality of word lines 821 of the cell array 2 via a digital-to-analog converter (not shown). The one or more digital inputs 811, 812 input to the plurality of word lines 821 of the cell array 2 can be output as analog outputs through operations with neural network weights stored in a plurality of memory cells 823. This analog output can be output via a bit line 822 of the cell array 2. That is, the processor can obtain digital outputs 831, 832 corresponding to the output of the bit line 822. At this time, digital outputs 831, 832 corresponding to the digital inputs 811, 812, respectively, can be obtained. For example, the digital output 831 corresponding to the digital input 811 can be obtained, and then the digital output 832 corresponding to the digital input 812 can be obtained sequentially.

[0100] As an example, a first analog output previously output via bit line 822 may be converted via an analog-to-digital converter to digital output 831, and a second analog output subsequently output via bit line 822 may be converted via an analog-to-digital converter to digital output 832. The processor may sequentially obtain digital output 831 and digital output 832 output via the analog-to-digital converter.

[0101] In one embodiment, when digital input 811 is a high-order bit string according to the above-described embodiment and digital input 812 is a low-order bit string according to the above-described embodiment, the processor inputs the high-order bit string 811 and the low-order bit string 812 to a digital-to-analog converter (not shown), and receives digital output 831 corresponding to the high-order bit string 811 and digital output 832 corresponding to the low-order bit string 812 output via an analog-to-digital converter (not shown). In this case, in the following description, digital output 831 corresponding to the high-order bit string 811 can be defined as a high-order bit output, and digital output 832 corresponding to the low-order bit string 812 can be defined as a low-order bit output.

[0102] In one embodiment, the processor can generate an output signal 840 using at least one of the digital outputs 831, 832 corresponding to the output of the bit line 822 based on the number of bits of the input signal 800 to be acquired and the bit resolution of the multiple memory cells 823 (hereinafter referred to as "cell bit resolution").

[0103] FIG. 10 is a diagram illustrating a method for generating an output signal according to an embodiment of the present invention.

[0104] 10 , an upper bit output 1021 and a lower bit output 1022 according to one embodiment are shown. In one embodiment, the processor can shift the upper bit output 1021 to the left by a first bit length 1010. For example, if the upper bit output 1021 is (1, 1, 0, 1, 0, 0, 0, 1), the upper bit output 1031 shifted to the left by the first bit length 1010 may be (1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0). Here, the “0” in the lower 8 bits can represent an actual value of 0, but can also be replaced with a meaningless value or a null value.

[0105] In one embodiment, the processor can generate the output signal 1000 based on the shifted upper bit output 1031 and the lower bit output 1032. For example, if the shifted upper bit output 1031 is (1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0) and the lower bit output 1032 is (1, 1, 1, 1, 0, 0, 1, 0), the processor can combine the upper bit output 1031 and the lower bit output 1032 to generate (1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0) as the output signal 1000. That is, the output signal 1000 can be generated by embedding the lower bit output 1032 corresponding to the first bit length 1010 into the lower bits of the upper bit output 1031 corresponding to the first bit length 1010.

[0106] 9 , as an example, if the lower bit sequence 932 is a bit sequence from the bit 902 next to the reference bit 901 to the least significant bit of the input signal 900, the first bit length 910 may be the number of bits in the lower bit sequence 932. In other words, if the lower bit sequence 932 is a bit sequence from the bit 902 next to the reference bit 901 to the least significant bit of the input signal 900, the input signal 900 is divided into the upper bit sequence 931 and the lower bit sequence 932 without any overlapping bits, so the first bit length 910 may be the number of bits in the lower bit sequence 932.

[0107] FIG. 9 shows a case where an input signal 900 is divided in half to generate an upper bit sequence 931 and a lower bit sequence 932, but the number of bits in the upper bit sequence 931 and the lower bit sequence 932 may differ depending on the position of the reference bit 901.

[0108] FIG. 11 is a diagram illustrating a digital input according to another embodiment of the present invention.

[0109] In one embodiment, when the lower bit sequence 1132 is a bit sequence from one of the plurality of bits of the upper bits 1121 of the input signal 1100 to the least significant bit of the input signal 1100, the first bit length 1110 can be the number of bits of the lower bit sequence 1132 minus the number of overlapping bits 1111 between the upper bit sequence 1131 and the lower bit sequence 1132.

[0110] As an example, in order to prevent the upper bit sequence 1131 and the lower bit sequence 1132 from overlapping with each other, the processor must determine the bit sequence from the bit 1102 next to the reference bit 1101 to the least significant bit of the input signal 1100 as the lower bit sequence 1132. Conversely, the processor can determine the upper bit sequence 1131 and the lower bit sequence 1132 so that they overlap with each other.

[0111] For example, if the upper bit sequence 1131 is a bit sequence from the most significant bit of the input signal 1100 to the reference bit 1101, and the lower bit sequence 1132 is a bit sequence from one of the multiple bits of the upper bit 1121 of the input signal 1100 to the least significant bit of the input signal 1100, the upper bit sequence 1131 and the lower bit sequence 1132 can have overlapping bits 1111. Specifically, as shown in FIG. 11 , if the lower bit sequence 1132 is a bit sequence from the bit before the reference bit 1101 to the least significant bit of the input signal 1100, the upper bit sequence 1131 and the lower bit sequence 1132 can have two overlapping bits 1111.

[0112] FIG. 12 is a diagram illustrating a method for generating an output signal according to another embodiment of the present invention.

[0113] Referring to FIG. 12, when the upper and lower bit strings have overlapping bits as in FIG. 11, an embodiment is shown in which a processor generates an output signal 1200 based on an upper bit output 1221 corresponding to the upper bit string and a lower bit output 1222 corresponding to the lower bit string.

[0114] In one embodiment, the processor may shift the upper bit output 1221 corresponding to the upper bit string to the left by the first bit length 1210. As described above, the first bit length 1210 may be the number of bits in the lower bit string minus the number of overlapping bits between the upper bit string and the lower bit string.

[0115] In one embodiment, the processor may generate the output signal 1200 based on the shifted upper bit output 1231 and lower bit output 1232. The specific manner in which the processor generates the output signal 1200 based on the shifted upper bit output 1231 and lower bit output 1232 is the same as in Figure 10, but there may be a problem with how the processor handles the overlapping bits 1211 when combining the upper bit output 1221 and lower bit output 1222 in this embodiment.

[0116] In one embodiment, the overlapping bits 1211 of the upper bit output 1221 and the overlapping bits 1211 of the lower bit output 1222 may not have the same value. As a result of the cell array's operation on specific data, errors in certain lower bits tend to be ignored. However, in the case of the upper bit output 1221, since it becomes the upper bit of the output signal 1200 when generating the output signal 1200, the lower bits of the upper bit output 1221 must be preserved. Therefore, as described with reference to FIG. 11 , the processor generates upper bit examples and lower bit examples so that there are overlapping bits between the upper bit examples and the lower bit examples, and replaces the overlapping bits 1211 of the upper bit output 1221 corresponding to the upper bit string with the value of the overlapping bits 1211 of the lower bit output 1222 corresponding to the lower bit string, thereby preserving the lower bits of the upper bit output 1221 as described above.

[0117] However, the method of processing the overlapping bits 1211 is not limited to this, and the output signal 1200 can also be determined based on the difference between the overlapping bits 1211 of the upper bit output 1221 and the overlapping bits 1211 of the lower bit output 1222. For example, the corresponding portion of the output signal 1200 can be determined by the average value of the overlapping bits 1211 of the upper bit output 1221 and the overlapping bits 1211 of the lower bit output 1222.

[0118] FIG. 13 is a diagram illustrating a method of operating a neural network device according to another embodiment of the present invention.

[0119] 13 shows an environment in which a processor of a neural network device generates an output signal 1350 based on an input signal 1300. That is, while FIG. 13 shows only components (e.g., cell array 2) for explaining the execution process of the processor, the environment is not limited thereto and may include additional omitted components.

[0120] In one embodiment, the processor can combine two or more combinations of any of the digital outputs 1331, 1332 generated based on the input signal 1300 to generate the output signal 1350. Specifically, in response to the number of bits of the input signal 1300 exceeding the cell bit resolution, the processor can combine two or more combinations of any of the digital outputs 1331, 1332 corresponding to the outputs of the bit lines 1310A, 1310B, 1320A, and 1320B to generate the output signal 1350. That is, in response to the number of bits of the input signal 1300 and the DAC bit resolution being 16 bits and the cell bit resolution being 8 bits, the processor can combine two or more combinations of any of the digital outputs 1331, 1332 corresponding to the outputs of the bit lines 1310A, 1310B, 1320A, and 1320B to generate the output signal 1350.

[0121] On the other hand, the number of bits of the digital outputs 1331, 1332 may be the same as or lower than the cell bit resolution. That is, according to one embodiment of the present invention, the processor can combine two or more combinations of digital outputs 1331, 1332 having a number of bits equal to or lower than the cell bit resolution to generate an output signal having a number of bits higher than the cell bit resolution.

[0122] In one embodiment, the cell array 2 may be configured in pairs: a first bit line 1310A connected to a first memory cell that stores a weight corresponding to a higher-order bit of the output signal 1350; and a second bit line 1310B connected to a second memory cell that stores a weight corresponding to a lower-order bit of the output signal 1350. Furthermore, in one embodiment, the digital outputs 1331 and 1332 corresponding to the outputs of the bit lines 1310A and 1310B may include a higher-order bit output 1331 corresponding to the output of the first bit line 1310A and a lower-order bit output 1332 corresponding to the output of the second bit line 1310B. Thus, the processor can generate the output signal 1350 based on the digital output 1331 output by the first bit line 1310A and the digital output 1332 output by the second bit line 1310B.

[0123] FIG. 14 is a diagram illustrating a method for generating an output signal according to another embodiment of the present invention.

[0124] 14, an upper bit output 1421 and a lower bit output 1422 according to one embodiment are shown. In one embodiment, the processor may shift the upper bit output 1421 to the left by a second bit length 1410. For example, the embodiment in which the processor shifts the upper bit output 1421 to the left by the second bit length 1410 can be applied in the same manner as the embodiment in which the processor shifts the upper bit output to the left by a first bit length, as described above with reference to FIG.

[0125] Specifically, the processor may shift the upper bit output 1421 to the left by the second bit length 1410 so that the most significant bit of the upper bit output 1421 is aligned with the most significant bit of the output signal 1400, and generate the output signal 1400 based on the shifted upper bit output 1431 and lower bit output 1432. For example, the processor may combine the shifted upper bit output 1431 and lower bit output 1432 to generate the output signal 1400.

[0126] 13, in one embodiment, the first bit line 1310A can store a higher bit weight from the most significant bit of the output signal 1350 to a reference bit (not shown), and the second bit line 1310B can store a lower bit weight from any of the more significant bits of the output signal 1350 and the bit (not shown) next to the reference bit (not shown) to the least significant bit of the output signal 1350. Thus, the output of the first bit line 1310A can be a higher bit output (e.g., digital output 1331), and the output of the second bit line 1310B can be a lower bit output (e.g., digital output 1332).

[0127] 14, in one embodiment, when the second bit line stores the lower bit weights from the bit next to the reference bit (not shown) to the least significant bit of the output signal 1400, the second bit length 1410 may be the number of bits of the lower bit output 1422. In this regard, the principles described above with reference to FIG.

[0128] FIG. 15 is a diagram illustrating a method for generating an output signal according to another embodiment of the present invention.

[0129] In one embodiment, when the second bit line stores the lower bit weight from one of the most significant bits of the output signal 1500 to the least significant bit of the output signal 1500, the second bit length 1510 may be the number of bits of the lower bit output 1522 minus the number of overlapping bits 1511 between the upper bit output 1521 and the lower bit output 1522.

[0130] In one embodiment, the processor can calculate a result of an operation (hereinafter referred to as a "correct output") between the upper bit string and neural network weights stored in a plurality of memory cells of the cell array. The processor can define the difference between the correct output and the upper bit output 1521 as a residual error, and reflect the residual error in the weight of the second bit line that outputs the lower bit output 1522. That is, the processor can preserve the duplicated bit 1511 of the upper bit output 1521 by replacing the value of the duplicated bit 1511 of the upper bit output 1521 with the value of the duplicated bit 1511 of the lower bit output 1522.

[0131] The method of generating the output signal 1500 by combining the upper bit output 1531 and the lower bit output 1532 transferred by the processor can be based on the same principles as the method described above with reference to FIG. 14, and details thereof will be omitted.

[0132] FIG. 16 is a flowchart of a method of operating a neural network device according to one embodiment of the present invention.

[0133] Referring to FIG. 16, in step 1610, the neural network device may generate one or more digital inputs comprising at least a portion of the input signal based on the number of bits of the input signal and the DAC bit resolution of the digital-to-analog converter.

[0134] In one embodiment, the neural network device may generate two or more digital inputs comprising at least a portion of the input signal and input them to the digital-to-analog converter in response to the number of bits of the input signal exceeding the DAC bit resolution of the digital-to-analog converter.

[0135] In one embodiment, the number of bits of the digital input may be the same as or higher than the DAC bit resolution.

[0136] In one embodiment, the two or more digital inputs may include a high-order bit string corresponding to the most significant bits of the input signal and a low-order bit string corresponding to the least significant bits of the input signal.

[0137] In one embodiment, the most significant bit string may be the most significant bits of the input signal shifted to the right by a first bit length so that the least significant bit of the most significant bit string is aligned with the least significant bit of the input signal.

[0138] In one embodiment, the neural network device can input the upper bit string and the lower bit string into a digital-to-analog converter.

[0139] In one embodiment, the upper bit sequence may be a bit sequence from the most significant bit of the input signal to the reference bit, and the lower bit sequence may be a bit sequence from any of the upper bits of the input signal and the bit next to the reference bit to the least significant bit of the input signal.

[0140] In one embodiment, when the lower bit string is a bit string from the bit next to the reference bit to the least significant bit of the input signal, the first bit length may be the number of bits in the lower bit string.

[0141] In one embodiment, when the lower bit string is a bit string from one of a plurality of most significant bits of the input signal to the least significant bit of the input signal, the first bit length may be a value obtained by subtracting the number of overlapping bits between the most significant bit string and the lower bit string from the number of bits in the lower bit string.

[0142] In step 1620, the neural network device may obtain one or more digital outputs corresponding to one or more digital inputs using a cell array including a plurality of memory cells that store neural network weights.

[0143] In step 1630, the neural network device may generate an output signal using at least one of the digital outputs based on the number of bits of the input signal and the cell bit resolution of the plurality of memory cells.

[0144] In one embodiment, the neural network device can receive a higher-order bit output corresponding to the higher-order bit string and a lower-order bit output corresponding to the lower-order bit string output via the analog-to-digital converter, shift the higher-order bit output to the left by a first bit length, and generate an output signal based on the shifted higher-order bit output and lower-order bit output.

[0145] In one embodiment, in response to the number of bits of the input signal exceeding the cell bit resolution of the plurality of memory cells, the neural network device may generate an output signal by combining any two or more combinations of digital outputs corresponding to the outputs of the bit lines, where the number of bits of the digital outputs may be equal to or less than the cell bit resolution.

[0146] In one embodiment, the cell array of the neural network device may be configured in pairs of a first bit line that stores a weight corresponding to the most significant bit of the output signal and a second bit line that stores a weight corresponding to the least significant bit of the output signal.

[0147] In one embodiment, the digital outputs corresponding to the output of the bit lines may include a most significant bit output corresponding to the output of a first bit line and a least significant bit output corresponding to the output of a second bit line.

[0148] In one embodiment, the neural network device can shift the upper bit output to the left by a second bit length so that the most significant bit of the upper bit output is aligned with the most significant bit of the output signal, and generate an output signal based on the shifted upper bit output and lower bit output.

[0149] In one embodiment, the first bit line can store the significant bit weights of the output signal from the most significant bit to the reference bit.

[0150] In one embodiment, the second bit line can store a lower bit weight from any of the most significant bits of the output signal and the bit next to the reference bit to the least significant bit of the output signal.

[0151] In one embodiment, if the second bit line stores the lower bit weight from the bit next to the reference bit to the least significant bit of the output signal, the second bit length may be equal to the number of bits of the lower bit output.

[0152] In one embodiment, when the second bit line stores a lower bit weight from one of a plurality of bits of the most significant bits of the output signal to the least significant bit of the output signal, the second bit length can be the number of bits of the less significant bit output minus the number of overlapping bits of the most significant bit output and the less significant bit output.

[0153] FIG. 17 is a block diagram of a neural network device according to another embodiment of the present invention.

[0154] 17, a neural network device (hereinafter referred to as "device") 1700 can include a communication unit 1710, a processor 1720, and a DB 1730. Only components related to the embodiment are shown in device 1700 in Fig. 17. Therefore, it can be understood by a person of ordinary skill in the art that other general-purpose components can be further included in addition to the components shown in Fig. 17.

[0155] The communication unit 1710 may include one or more components that enable wired / wireless communication with an external server or device. For example, the communication unit 1710 may include at least one of a short-range communication unit (not shown), a mobile communication unit (not shown), and a broadcast receiving unit (not shown). In one embodiment, the communication unit 1710 may use at least one communication protocol of a serial peripheral interface (SPI) and a universal asynchronous receiver / transmitter (UART). Furthermore, in one embodiment, the communication unit 1710 may communicate with sensors, external memory, and external control devices.

[0156] The DB 1730 is hardware that stores various data to be processed within the device 1700, and can store programs for processing and control of the processor 1720.

[0157] DB1730 may include random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM, Blu-ray or other optical disk storage, hard disk drive (HDD), solid state drive (SSD), or flash memory.

[0158] Processor 1720 controls the overall operation of device 1700. For example, processor 1720 can generally control an input unit (not shown), a display (not shown), communication unit 1710, DB 1730, etc. by executing a program stored in DB 1730. Processor 1720 can control the operation of device 1700 by executing a program stored in DB 1730.

[0159] The processor 1720 may control at least some of the operations of the components of the device 1700 described above in FIGS.

[0160] The processor 1720 may be implemented using at least one of application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, and other electrical units for performing functions.

[0161] In one embodiment, device 1700 may be a server. A server may be implemented as a computing device or multiple computing devices that communicate over a network and provide instructions, code, files, content, services, etc. As an example, a server may receive input signals and generate output signals.

[0162] Meanwhile, embodiments of the present invention may be realized in the form of a computer program executable by various components on a computer, and such a computer program may be recorded on a computer-readable medium, which may include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program instructions, such as ROMs, RAMs, and flash memories.

[0163] Meanwhile, the computer program may be specially designed and constructed for the present invention, or may be one that is well known and available to those skilled in the art of computer software. Examples of the computer program include not only machine language code such as that produced by a compiler, but also high-level language code that can be executed by a computer using an interpreter, etc.

[0164] According to one embodiment, methods according to various embodiments of the present disclosure may be provided in a computer program product. The computer program product may be traded between sellers and buyers as a commodity. The computer program product may be distributed in the form of a device-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)) or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices. In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily generated in a device-readable storage medium, such as the memory of a manufacturer's server, an application store server, or an intermediary server.

[0165] Unless otherwise clearly stated or contrary to the order of steps constituting the method of the present invention, the steps may be performed in any suitable order. The present invention is not necessarily limited to the order of the steps described above. The use of all examples or exemplary terms in the present invention is merely for the purpose of explaining the present invention in detail, and the scope of the present invention is not limited by the examples or exemplary terms unless otherwise limited by the claims. Furthermore, those skilled in the art will understand that various modifications, combinations, and variations can be made depending on design conditions and factors within the scope of the appended claims or their equivalents.

[0166] Therefore, the concept of the present invention should not be limited to the above-described embodiments, and all scopes equivalent to or modified equivalently from the scope of the claims, as well as the scope of the claims described below, can be said to fall within the scope of the concept of the present invention.

Claims

1. a digital-to-analog converter that converts a digital input into an analog input of either voltage or current; a cell array arranged on a plurality of bit lines and a plurality of word lines, including a plurality of memory cells for storing weights of a neural network, performing an operation on the analog input inputted via the word lines, and outputting an analog output of either a current or a voltage via the bit lines; an analog-to-digital converter that converts the analog output into a digital output; at least one processor electrically connected to the digital-to-analog converter and the analog-to-digital converter and performing control over the digital inputs and the digital outputs; The at least one processor inputting one or more digital inputs to the digital-to-analog converter, the digital-to-analog converter comprising at least a portion of the input signal, based on the number of bits of the input signal and the DAC bit resolution of the digital-to-analog converter; A neural network device that generates an output signal using at least one of the digital outputs corresponding to the output of the bit line based on the number of bits of the input signal and the cell bit resolution of the plurality of memory cells.

2. The at least one processor responsive to the number of bits of the input signal exceeding a DAC bit resolution of the digital-to-analog converter, inputting two or more digital inputs to the digital-to-analog converter, the two or more digital inputs comprising at least a portion of the input signal; The number of bits of the digital input is 2. The neural network device of claim 1, wherein the bit resolution is equal to or lower than the DAC bit resolution.

3. The two or more digital inputs are: a high-order bit string corresponding to the high-order bits of the input signal and a low-order bit string corresponding to the low-order bits of the input signal, The upper bit string is 3. The neural network device according to claim 2, wherein the most significant bit of the input signal is shifted to the right by a first bit length so that the least significant bit (LSB) of the most significant bit string is aligned with the least significant bit of the input signal.

4. The at least one processor inputting the upper bit string and the lower bit string to the digital-to-analog converter; receiving a higher-order bit output corresponding to the higher-order bit string and a lower-order bit output corresponding to the lower-order bit string outputted via the analog-to-digital converter; Shifting the most significant bit output to the left by the first bit length; 4. The neural network device according to claim 3, wherein the output signal is generated based on the shifted higher-order bit output and the lower-order bit output.

5. The upper bit string is a bit string from the most significant bit (MSB) of the input signal to a reference bit, The lower bit string is 4. The neural network device according to claim 3, wherein the input signal is a bit string from either a plurality of most significant bits of the input signal or the bit next to the reference bit to the least significant bit of the input signal.

6. 6. The neural network device according to claim 5, wherein when the lower bit string is a bit string from the bit next to the reference bit to the least significant bit of the input signal, the first bit length is the number of bits in the lower bit string.

7. 6. The neural network device according to claim 5, wherein when the lower bit string is a bit string from one of a plurality of most significant bits of the input signal to the least significant bit of the input signal, the first bit length is a value obtained by subtracting the number of overlapping bits between the most significant bit string and the lower bit string from the number of bits of the lower bit string.

8. The at least one processor generating the output signal by combining any two or more combinations of digital outputs corresponding to outputs of the bit lines in response to the number of bits of the input signal exceeding the cell bit resolution of the plurality of memory cells; The number of bits of the digital output is 2. The neural network device of claim 1, wherein the cell bit resolution is equal to or lower than the cell bit resolution.

9. The cell array includes: a first bit line for storing a weight corresponding to a high-order bit of the output signal and a second bit line for storing a weight corresponding to a low-order bit of the output signal are configured in pairs; The digital output corresponding to the output of the bit line is 9. The neural network device according to claim 8, further comprising a higher-order bit output corresponding to the output of said first bit line, and a lower-order bit output corresponding to the output of said second bit line.

10. The at least one processor shifting the most significant bit of the most significant bit output to the left by a second bit length so that the most significant bit of the most significant bit of the output signal is aligned; 10. The neural network device according to claim 9, wherein the output signal is generated based on the shifted higher-order bit output and the lower-order bit output.

11. The first bit line is storing the weights of the most significant bits of the output signal from the most significant bit to the reference bit; The second bit line is 11. The neural network device according to claim 10, wherein lower bit weights are stored from a plurality of higher order bits of the output signal and the bit next to the reference bit to the least significant bit of the output signal.

12. 12. The neural network device of claim 11, wherein when the second bit line stores lower bit weights from the bit next to the reference bit to the least significant bit of the output signal, the second bit length is the number of bits of the lower bit output.

13. 12. The neural network device of claim 11, wherein when the second bit line stores lower bit weights from any of a plurality of upper bits of the output signal to the least significant bit of the output signal, the second bit length is a value obtained by subtracting the number of overlapping bits of the upper bit output and the lower bit output from the number of bits of the lower bit output.

14. generating one or more digital inputs comprising at least a portion of the input signal based on the number of bits of the input signal and a DAC bit resolution of a digital-to-analog converter; obtaining one or more digital outputs corresponding to the one or more digital inputs using a cell array including a plurality of memory cells that store neural network weights; and generating the output signal using at least one of the digital outputs based on the number of bits of an input signal and the cell bit resolution of the plurality of memory cells.

15. A computer-readable recording medium having recorded thereon a program for causing a computer to execute the method according to claim 14.

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