Dix to DIF conversion using HMB buffer management

Abstract

To provide a storage device capable of supporting either a data integrity extension (DIX) format or a data integrity field (DIF) format using the same address mapping for data and metadata.SOLUTION: In the storage system 100, the data storage device comprises a memory device and a controller coupled to the memory device. A controller stores data and metadata stored in a data integrity field (DIF) format in a host memory buffer (HMB), determines whether a host device operates in a DIF format or a data integrity extension (DIX) format, and delivers to the host device one or more scatter gather lists (SGLs) corresponding to the format in which the host device operates.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present disclosure generally relate to supporting data integrity extension (DIX) and data integrity field (DIF) formats in a host memory buffer (HMB). [Background technology]

[0002] There are two different formats for organizing data in the buffer. One format is Data Integrity Extension (DIX). The other format is Data Integrity Field (DIF). The DIX format involves organizing data and metadata separately. The DIF format involves interleaving metadata with data. Metadata is an extension of user data. User data operates at logical block addresses (LBAs), such as 512 bytes or 4K per LBA. Metadata is usually in multiples of 4 bytes, starting at 8 bytes.

[0003] Typically, a host device can operate in one format, and the data storage device must adapt to the format of the host device. Interaction between the data storage device and the host device is challenging from a performance standpoint.

[0004] Therefore, there is a need in the art for improved host and data storage device interaction when using the DIF and DIX formats. Summary of the Invention

[0005] Using the same address mapping for data and metadata, either the Data Integrity Extension (DIX) format or the Data Integrity Field (DIF) format can be supported. To do so, the data storage device is responsible for generating and maintaining a scatter gather list (SGL). The data storage device maintains either the DIX format or the DIF format in a host memory buffer (HMB) and can then convert from the DIX format to the DIF format if the host device uses the DIF format. Conversely, if the host device uses the DIX format, the data storage device can convert from the DIF format to the DIX format. Extending DIF capabilities to DIX capabilities and vice versa is possible without any changes to the data flow.

[0006] In one embodiment, a data storage device includes a memory device and a controller coupled to the memory device, the controller configured to store data and metadata in an HMB, where the data and metadata are stored in a DIF format, determine whether a host device operates in the DIF format or the DIX format, and deliver one or more SGLs to the host device that correspond to the format in which the host device operates.

[0007] In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device, the controller configured to store data and metadata in an HMB, where the data and metadata are stored in a DIX format, determine whether a host device operates in the DIX format or the DIF format, and deliver one or more SGLs to the host device that correspond to the format in which the host device operates.

[0008] In another embodiment, a data storage device comprises means for storing data and a controller coupled to the means for storing data, the controller configured to write data to the HMB, where the data is written in either DIX format or DIF format, utilize the same address mapping for the data, and report the data to the host device as either DIF or DIX, and the controller configured to convert the DIX format to the DIF format or from the DIF format to the DIX format. [Brief explanation of the drawings]

[0009] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments. [Figure 1] 1 is a schematic block diagram illustrating a storage system in which a data storage device may function as a storage device for a host device, according to certain embodiments. [Figure 2] 1 is a schematic diagram of both the DIF and DIX formats. [Figure 3] FIG. 1 is a schematic diagram of a system having a DIX buffer. [Figure 4] FIG. 1 is a schematic diagram of an internal DIX format. [Figure 5] FIG. 1 is a schematic diagram of an internal DIF format. [Figure 6] 1 is a flowchart showing the use of the DIX format in HMB. [Figure 7] 1 is a flowchart showing the use of the DIF format in HMB.

[0010] For ease of understanding, wherever possible, the same reference numbers have been used to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. DETAILED DESCRIPTION OF THE INVENTION

[0011] Reference will be made below to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specific described embodiments. Instead, any combination of the following features and elements, whether associated with different embodiments or not, is contemplated for implementing and practicing the present disclosure. Furthermore, embodiments of the present disclosure may achieve other possible solutions and / or advantages over the prior art, but whether or not a particular advantage is achieved by a given embodiment does not limit the present disclosure. Accordingly, the following aspects, features, embodiments, and advantages are merely exemplary and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein, and should not be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0012] Using the same address mapping for data and metadata, either the Data Integrity Extension (DIX) format or the Data Integrity Field (DIF) format can be supported. To do so, the data storage device is responsible for creating and maintaining a Scatter Gather List (SGL). The data storage device maintains either the DIX format or the DIF format in the Host Memory Buffer (HMB) and can then convert from the DIX format to the DIF format if the host device uses the DIF format. Conversely, if the host device uses the DIX format, the data storage device can convert from the DIF format to the DIX format. Extending DIF capabilities to DIX capabilities and vice versa is possible without any changes to the data flow.

[0013] 1 is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that may function as a storage device for a host device 104, according to certain embodiments. For example, the host device 104 may store and retrieve data using non-volatile memory (NVM) 110 included in the data storage device 106. The host device 104 includes host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, that may operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID) that collectively function as a mass storage device for the host device 104.

[0014] 1, host device 104 may store data on and / or retrieve data from one or more storage devices, such as data storage device 106. As shown in FIG. 1, host device 104 may communicate with data storage device 106 via interface 114. Host device 104 may include any of a wide range of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" pad, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or any other device capable of sending or receiving data from a data storage device.

[0015] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 allocated to the data storage device 106 for exclusive use by the controller 108 of the data storage device 106. For example, the controller 108 may store mapping data, buffered commands, logical to physical (L2P) tables, metadata, etc. in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would normally be stored in the controller 108's internal memory, such as the volatile memory 112, the buffer 116, static random access memory (SRAM), etc. In examples where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.

[0016] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, write buffer 116, and optional DRAM 118. In some examples, data storage device 106 may include additional components not shown in FIG. 1 for clarity. For example, data storage device 106 may include a printed circuit board (PCB) to which the components of data storage device 106 are mechanically attached and which includes conductive traces that electrically interconnect components such as data storage device 106. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5-inch data storage device (e.g., HDD or SSD), a 2.5-inch data storage device, a 1.8-inch data storage device, a peripheral component interconnect (PCI), a PCI-extended (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled to the motherboard of the host device 104 (e.g., soldered directly or plugged into a connector).

[0017] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108 and provides an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, as shown in FIG. 1, the power supply 111 may receive power from the host device 104 via the interface 114.

[0018] The NVM 110 may include multiple memory devices or memory units. The NVM 110 may be configured to store and / or retrieve data. For example, a memory unit of the NVM 110 may receive data and a message from the controller 108 instructing the memory unit to store the data. Similarly, the memory unit may receive a message from the controller 108 instructing the memory unit to retrieve the data. In some examples, each of the memory units may be referred to as a die. In some examples, the NVM 110 may include multiple dies (i.e., multiple memory units). In some examples, each memory unit may be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0019] In some examples, each memory unit may include any type of non-volatile memory device, such as a flash memory device, a phase-change memory (PCM) device, a resistive random-access memory (ReRAM) device, a magneto-resistive random-access memory (MRAM) device, a ferroelectric random-access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0020] The NVM 110 may include multiple flash memory devices or memory units. The NVM flash memory devices may include NAND or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor in each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, each of which may include multiple physical or logical blocks, and the multiple physical or logical blocks may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define one of multiple pages. Each cell in each of the multiple pages may be electrically connected to a respective bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) device. The controller 108 can write data to the NVM flash memory device at the page level, read data from the NVM flash memory device, and erase data from the NVM flash memory device at the block level.

[0021] The power supply 111 may provide power to one or more components of the data storage device 106. When operating in a standard mode, the power supply 111 may provide power to one or more components using power provided by an external device, such as the host device 104. For example, the power supply 111 may provide power to one or more components using power received from the host device 104 via the interface 114. In some examples, the power supply 111 may include one or more power storage components configured to provide power to one or more components when operating in a shutdown mode, such as when power is no longer received from an external device. In this manner, the power supply 111 may function as an on-board backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of power that can be stored by the one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increase.

[0022] The volatile memory 112 may be used by the controller 108 to store information. The volatile memory 112 may include one or more volatile memory devices. In some examples, the controller 108 may use the volatile memory 112 as a cache. For example, the controller 108 may store cached information in the volatile memory 112 until the cached information is written to the NVM 110. As shown in FIG. 1 , the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, the optional DRAM 118 may be utilized to store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, and the like. In some examples, the data storage device 106 is DRAM-less, as it does not include the optional DRAM 118. In other examples, the data storage device 106 includes the optional DRAM 118.

[0023] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate the data storage command to store the data in the NVM 110 and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110. The controller 108 may include a circuit or processor configured to execute a program for operating the data storage device 106.

[0024] The controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be similar to the volatile memory 112. For example, the optional second volatile memory 120 may be an SRAM. The controller 108 may allocate a portion of the optional second volatile memory to the host device 104 as a controller memory buffer (CMB) 122. The CMB 122 may be directly accessed by the host device 104. For example, rather than maintaining one or more transmit queues within the host device 104, the host device 104 may utilize the CMB 122 to store one or more transmit queues that are normally maintained within the host device 104. In other words, the host device 104 may generate commands and store the generated commands, with or without associated data, in the CMB 122, and the controller 108 accesses the CMB 122 to retrieve the stored generated commands and / or associated data.

[0025] 2 is a schematic diagram 200 of both the DIF and DIX formats. The DIF format is managed by a single list of pointers, while the DIX format has two separate lists. Some devices support DIF formatting, such as when data and metadata are stored on the same page of a memory device (e.g., NAND), while some host devices operate in the DIX format.

[0026] In the DIF format, the data resides in a single buffer with a set of pointers to the data and metadata. The data and metadata are not necessarily contiguous or sequential as shown. The data and metadata are interleaved with each other in the DIF format.

[0027] The DIX format has two pointers: one for data and one for metadata. There can be multiple entries in each set. For example, there can be multiple entries for a dataset. Similarly, there can be multiple entries for a metadata set. In one embodiment, the number of entries in the pointer to the dataset is equal to the number of entries in the pointer to the metadata set. Essentially, there is one head queue that points to the data and one head queue that points to the metadata.

[0028] If the data storage device operates in DIF format but the host device operates in DIX format (or vice versa), some conversion is required to process read or write commands. In one example, the DIX information is put into a DIX buffer in the host device, then the data is read, followed by all the LBA portions of the DIX. Essentially, the metadata is read from the host device first, then the data. After, say, 512 bytes, the data has been fetched. At that point, both the data and the metadata have been fetched and are stored in the DIF buffer on the data storage device. The reverse is done for read commands. After all the data has been sent, the metadata is sent separately.

[0029] FIG. 3 is a schematic diagram 300 of a system with a DIX buffer. FIG. 3 shows the host DRAM with ranges for commands and data. FIG. 3 also shows the NAND where data is read (or written). FIG. 3 also shows the data storage device, including a PCIe interface, a control path (used for command fetching and parsing), and a data path triggered by the control path. The data path includes several engines before finally reaching the DMA, which is responsible for sending data from the local SRAM to the host DRAM.

[0030] A DIX buffer is added to allow a device to operate in DIF mode internally and DIX mode externally (similar mechanisms are required for DIX internally and DIF externally). During a write command, when a data storage device reads data from a host device, the DMA operates according to the following flow. This flow assumes (to simplify the example): a 512-byte LBS (LBA size), an 8-byte MDS (metadata size), and a 128-byte MPS (optimized TLP size). Each read from the host device is expected to be of this size if the required bandwidth can be sustained, and the NLB (number of LBAs in the command) is 32 LBAs.

[0031] The flow is as follows: 2nd time [NLB * MDS / MPS=32 * 8 / 128] times, fetch DIX information for a TLP from the host (for example, 128 bytes), store the DIX information in the DIX buffer, and repeat 16 times [MPS / MDS=128 / 8] (per LBA) (read user data from the host (512 bytes)), and pass the LBA + related DIX information (8 bytes out of 128) to the rest of the data path engine.

[0032] The DIX buffer flow shows how DIX data is prefetched so it can be interleaved within the data stream destined for other hardware (HW) engines. For the DIF flow, having to organize the data in a DIF destined for the host device means that each LBA that is currently perfectly aligned to 512 bytes (and PCIe TLP size) now becomes (as an example) 512+8 or 4k+16 and is no longer aligned. This complicates DMA and breaks TLP alignment.

[0033] This disclosure proposes a way to support DIF mode with minimal changes to the device. Previously, there were different data flows for DIF and DIX formats. As described herein, a data storage device can always use the same address mapping for data and metadata and report the address mapping as either DIF or DIX format. This is possible if the device is responsible for the SGL list.

[0034] In the SGL, all entries can be different sizes. An entry can be, for example, 1 byte, but it should be understood that the SGL can be any size. The SGL is much more distributed and dynamic than a physical region page (PRP). The idea is that instead of the host device telling the data storage device where to put data, the data storage device decides where to put the data. The only location where the data storage device can decide to place the data is within the HMB, because the HMB is a storage area dedicated by the host device that the data storage device uses as it sees fit. The HMB typically has an L2P table, for example.

[0035] Thus, the data storage device can control the location within the HMB and therefore can decide to place data within the HMB in either DIX or DIF format without input from the host device. If the HMB is in DIX format and the host device wants to operate in DIF format, the data storage device can generate an SGL list that looks like the list shown in Figure 4.

[0036] Figure 4 is a schematic diagram 400 using the internal DIX format. Figure 4 shows the actual layout of data in HMB memory, which is identical for both DIF and DIX modes. In this example, the data in the HMB is organized as DIX. This is used to simplify DMA for TLP optimization (no need to break TLPs to MAC based on local buffer breakdown). However, when the data storage device (i.e., the data storage device's controller) generates an SGL list for commands, the controller generates a six-entry list (often called a pointer or set) if the NS is formatted to operate in DIF format, or two lists of one entry each if the NS is configured for DIX format.

[0037] Thus, 0-512 are the first entries in the DIF SGL list for data, and 1535-1543 are the second entries for metadata. The list alternates between data and metadata as shown in Figure 4. If the host device operates in DIX mode, there will be two lists: one for the data SGL starting at 0 and having a size of 1536, and a second for the metadata starting at 1536 and having a size of 24. By creating an SGL structure with the data storage device, the host device is tricked into operating in DIX or DIF format, while the data storage device operates in the DIX format of Figure 4.

[0038] FIG. 5 is a schematic diagram 500 using the internal DIF format. In this case, data is arranged in the HMB in a DIF layout. The SGL list for the DIX format contains two lists of three entries each, and the SGL list for the DIF format contains one entry. FIG. 5 shows the reverse method compared to FIG. 4, where the data storage device operates in the DIF format and the host device can operate in either the DIX format or the DIF format. The HMB operates in the DIF format. When the host device operates in the DIF format, there is one buffer starting from 0 and having a size of 1560. When the host device operates in DIX mode, there are two lists, one for data and one for metadata.

[0039] 4 and 5, a host device can operate in either the DIF format or the DIX format, and a data storage device can also operate in either the DIF format or the DIX format. Converting between formats is straightforward due to the fact that the data storage device creates an SGL because the data and metadata are in the HMB and their location is controlled by the controller.

[0040] 6 is a flowchart 600 illustrating the use of the DIX format in an HMB. Initially, a data storage device determines, at block 602, to store data and metadata in the HMB using the DIX format. Then, at block 604, a determination is made as to whether the host device is using the DIX format. If the host device is using the DIX format, at block 606, an SGL in DIX format is generated, and at block 608, the SGL is delivered to the host device. If the host device is not using the DIX format, the host device is using the DIF format. Thus, at block 610, the DIX format is converted to the DIF format by generating an SGL in DIF format, and then at block 608, delivering the SGL to the host device.

[0041] 7 is a flowchart 700 illustrating the use of the DIF format in an HMB. Initially, a data storage device determines, at block 702, to store data and metadata in the HMB using the DIF format. Then, at block 704, a determination is made as to whether the host device is using the DIF format. If the host device is using the DIF format, at block 706, an SGL in the DIF format is generated, and at block 708, the SGL is delivered to the host device. If the host device is not using the DIF format, the host device is using the DIX format. Therefore, at block 710, the DIF format is converted to the DIX format by generating an SGL in the DIX format, and then at block 708, delivering the SGL to the host device.

[0042] By allowing the data storage device to handle buffer allocation for the destination of a read command, the data storage device can support both DIF and DIX formats using the same data structures in the HMB, thereby enabling DIX capabilities to be extended to DIF capabilities without changing the data flow.

[0043] In one embodiment, a data storage device includes a memory device and a controller coupled to the memory device, the controller being configured to: store data and metadata in a host memory buffer (HMB), where the data and metadata are stored in a DIF format; determine whether the host device operates in a DIFX format or a DIX format; and deliver one or more scatter gather lists (SGLs) to the host device corresponding to the format in which the host device operates. The controller is configured to convert the data and metadata from the DIF format to the DIX format. The delivering includes delivering a data SGL and a separate, distinct metadata SGL to the host device. The data SGL has a plurality of data entries. The plurality of data entries are non-sequential. The metadata SGL has a plurality of metadata entries. The plurality of metadata entries are non-sequential. A first metadata entry of the plurality of metadata entries is sequential with a first data entry of the plurality of data entries. The data SGL and the metadata SGL are sequential and each include a single entry. The controller is configured to generate the SGL.

[0044] In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to: store data and metadata in a host memory buffer (HMB), where the data and metadata are stored in a DIX format; determine whether the host device operates in the DIX format or the DIF format; and deliver one or more scatter gather lists (SGLs) to the host device corresponding to the format in which the host device operates. The controller is configured to convert the data and metadata from the DIX format to the DIF format. The delivering includes delivering a single SGL covering both the data and the metadata. The controller is configured to deliver the data SGL and a separate, distinct metadata SGL to the host device for operation in the DIF format. The data SGL has a plurality of data entries, and the metadata SGL has a plurality of metadata entries. The plurality of data entries are non-sequential, and the plurality of metadata entries are non-sequential. A first data entry and a first metadata entry of the plurality of metadata entries are sequential.

[0045] In another embodiment, a data storage device comprises: means for storing data; and a controller coupled to the means for storing data, the controller configured to write the data to a host memory buffer (HMB), where the data is written in either a Data Integrity Extended (DIX) format or a Data Integrity Field (DIF) format; utilize a uniform address mapping for the data; and report the data to the host device as either DIF or DIX; the controller configured to convert the DIX format to the DIF format or from the DIF format to the DIX format. The controller is configured to generate at least one scatter gather list (SGL) for the data and the metadata. The generated at least one SGL includes generating separate SGL lists for the data and the metadata.

[0046] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A data storage device comprising: a memory device; a controller coupled to the memory device, the controller comprising: storing data and metadata in a host memory buffer (HMB), said data and metadata being stored in a Data Integrity Field (DIF) format; determining whether the host device operates in the DIF format or the Data Integrity Extension (DIX) format; A data storage device configured to deliver to the host device one or more scatter gather lists (SGLs) corresponding to the format in which the host device operates.

2. 10. The data storage device of claim 1, wherein the controller is configured to convert the data and metadata from a DIF format to a DIX format.

3. The data storage device of claim 1 , wherein said delivering comprises delivering a data SGL and a separate and distinct metadata SGL to said host device.

4. 4. The data storage device of claim 3, wherein the data SGL has a plurality of data entries.

5. 5. The data storage device of claim 4, wherein the plurality of data entries are non-sequential.

6. The data storage device of claim 5 , wherein the metadata SGL comprises a plurality of metadata entries.

7. The data storage device of claim 6 , wherein the plurality of metadata entries are non-sequential.

8. 8. The data storage device of claim 7, wherein a first metadata entry of said plurality of metadata entries is sequential with a first data entry of said plurality of data entries.

9. 4. The data storage device of claim 3, wherein the data SGL and the metadata SGL are sequential and each contain a single entry.

10. The data storage device of claim 1 , wherein the controller is configured to generate the SGL.

11. 1. A data storage device comprising: a memory device; a controller coupled to the memory device, the controller comprising: storing data and metadata in a host memory buffer (HMB), wherein the data and metadata are stored in a Data Integrity Extension (DIX) format; determining whether the host device operates in a DIX format or a Data Integrity Field (DIF) format; A data storage device configured to deliver to the host device one or more scatter gather lists (SGLs) corresponding to the format in which the host device operates.

12. 12. The data storage device of claim 11, wherein the controller is configured to convert the data and metadata from a DIX format to a DIF format.

13. 12. The data storage device of claim 11, wherein said distributing comprises distributing a single SGL that covers both data and metadata.

14. 12. The data storage device of claim 11, wherein the controller is configured to deliver a data SGL and a separate and distinct metadata SGL to the host device for the host device to operate in the DIF format.

15. 15. The data storage device of claim 14, wherein the data SGL has a plurality of data entries and the metadata SGL has a plurality of metadata entries.

16. 16. The data storage device of claim 15, wherein the plurality of data entries are non-sequential and the plurality of metadata entries are non-sequential.

17. 17. The data storage device of claim 16, wherein the first data entry of the plurality of metadata entries and the first metadata entry are sequential.

18. 1. A data storage device comprising: means for storing data; a controller coupled to the means for storing the data, the controller comprising: writing data to a host memory buffer (HMB), the data being written in either a Data Integrity Extension (DIX) format or a Data Integrity Field (DIF) format; A data storage device configured to utilize the same address mapping for the data and report the data to a host device as either DIF or DIX, and the controller configured to convert DIX format to DIF format or from DIF format to DIX format.

19. 20. The data storage device of claim 18, wherein the controller is configured to generate at least one scatter gather list (SGL) for data and metadata.

20. 20. The data storage device of claim 19, wherein the at least one SGL generated includes generating separate SGL lists for data and metadata.

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