Printed circuit board

Abstract

To provide a printed circuit board in which adhesion between a conductor pattern and an insulating layer can be ensured, signal loss can be improved through roughness free surface treatment, and interlayer short circuit or migration due to a foreign substance / flaw / scratch can be improved.SOLUTION: A printed circuit board includes a first conductor pattern, a first insulating film covering at least a portion of the first conductor pattern along a shape of a surface of the first conductor pattern, and an insulating layer disposed on the first insulating film, wherein the first insulating film includes a first inorganic layer and a first organic layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Recently, the thickness of insulating layers has been steadily decreasing in order to form fine circuits and fine vias, which has increased the impact of foreign matter, scratches, etc., which may cause problems such as interlayer shorts between circuits and migration. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the various objects of the present disclosure is to provide a printed circuit board that can ensure adhesion between a conductor pattern and an insulating layer.

[0004] Another of the various objects of the present disclosure is to provide a printed circuit board that can improve signal loss through a non-roughness surface treatment.

[0005] Another of the various objects of the present disclosure is to provide a printed circuit board that can improve interlayer shorts and migration caused by foreign matter, flaws, scratches, etc. [Means for solving the problem]

[0006] One of the various solutions provided by the present disclosure is to form an insulating film including an inorganic layer and an organic layer on the surface of a conductor pattern in a printed circuit board in which the conductor pattern is embedded in an insulating layer.

[0007] For example, a printed circuit board may include a first conductor pattern, a first insulating film covering at least a portion of the first conductor pattern along the surface shape of the first conductor pattern, and an insulating layer disposed on the first insulating film, wherein the first insulating film may include a first inorganic layer and a first organic layer.

[0008] Another of the various solutions provided through the present disclosure is to form an insulating film not only on the surface of the conductor pattern but also between the multiple insulating layers in a printed circuit board in which the conductor pattern is embedded in multiple insulating layers.

[0009] For example, a printed circuit board may include a first insulating layer, a first conductor pattern embedded under the first insulating layer with at least a portion of its lower surface exposed from the lower surface of the first insulating layer, a first insulating film that covers at least a portion of each of the upper and side surfaces of the first conductor pattern along the shape of the first conductor pattern and extends over the lower surface of the first insulating layer, a second insulating layer arranged on the upper surface of the first insulating layer, a second insulating film that is arranged between the first and second insulating layers and has a thickness thinner than each of the first and second insulating layers, and a second conductor pattern arranged on the upper surface of the second insulating layer. [Effects of the Invention]

[0010] One of the various effects of the present disclosure is that it is possible to provide a printed circuit board that can ensure adhesion between the conductor pattern and the insulating layer.

[0011] Another advantage of the present disclosure is that it provides a printed circuit board that can improve signal loss through a non-roughness surface treatment.

[0012] Another effect of the present disclosure, among other effects, is that it is possible to provide a printed circuit board that can improve interlayer short circuits and migration caused by foreign matter, flaws, scratches, etc. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3]FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 4] 4 is a schematic enlarged cross-sectional view of area A of the printed circuit board of FIG. 3. [Figure 5] 4A to 4C are schematic cross-sectional views illustrating steps in an example of manufacturing the printed circuit board of FIG. 3. [Figure 6] FIG. 10 is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 7] 7 is a schematic enlarged cross-sectional view of area B of the printed circuit board of FIG. 6. [Figure 8] 7A to 7C are schematic cross-sectional views illustrating steps in an example of manufacturing the printed circuit board of FIG. 6. [Figure 9] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 10] 10 is a schematic enlarged cross-sectional view of area C of the printed circuit board of FIG. 9. [Figure 11] 10A to 10C are schematic cross-sectional views illustrating steps in an example of manufacturing the printed circuit board of FIG. 9. [Figure 12] 1 is a cross-sectional image diagram illustrating a schematic layer structure of an insulating film formed between a conductor pattern and an insulating material. [Figure 13] FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor package. [Figure 14] FIG. 10 is a cross-sectional view schematically showing another example of a semiconductor package. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present disclosure will be described below with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for clarity.

[0015] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0016] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also coupled to other electronic components (described later) to form various signal lines 1090.

[0017] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with one another. The chip-related components 1020 can also be in the form of a package including the above-mentioned chips and electronic components.

[0018] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020.

[0019] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, they are not limited to these and may also include passive elements in the form of chip components used for various other applications. In addition, the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0020] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0021] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0022] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0023] Referring to the drawing, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Furthermore, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-described chip-related components, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0024] printed circuit board FIG. 3 is a cross-sectional view that schematically shows an example of a printed circuit board, and FIG. 4 is an enlarged cross-sectional view that schematically shows an area A of the printed circuit board of FIG.

[0025] Referring to the drawings, a printed circuit board 100A according to an example may include a first insulating layer 111, a first conductor pattern 121 disposed on an upper surface of the first insulating layer 111, a second insulating layer 112 disposed on the upper surface of the first insulating layer 111 and embedding the first conductor pattern 121, a second conductor pattern 122 disposed on an upper surface of the second insulating layer 112, a first insulating layer 151 covering at least a portion of the upper surface and side surfaces of the first conductor pattern 121 and extending on a lower surface of the second insulating layer 112, a second insulating layer 152 covering at least a portion of the upper surface and side surfaces of the second conductor pattern 122 and extending on the upper surface of the second insulating layer 112, and a via pattern 131 penetrating the second insulating layer 112 and the first insulating layer 151 to connect the first and second conductor patterns 121 and 122 to each other. There may be a plurality of the first and second conductor patterns 121 and 122 and the via pattern 131.

[0026] In this case, at least a portion of the first insulating film 151 may be disposed between the first conductive pattern 121 and the second insulating layer 112. For example, the first insulating film 151 may cover at least a portion of the first conductive pattern 121 along the shape of the surface of the first conductive pattern 121. For example, the first insulating film 151 may be conformally disposed on the first conductive pattern 121 and extend onto the lower surface of the second insulating layer 112. When there are multiple first conductive patterns 121, the first insulating film 151 may be continuously disposed on the lower surface of the second insulating layer 112 between the multiple first conductive patterns 121. The first insulating film 151 may be composed of multiple layers, and may include, for example, a first inorganic layer 151a and a first organic layer 151b. On the surface of the first conductive pattern 121, the first inorganic layer 151a may be in contact with the first conductive pattern 121, and the first organic layer 151b may be in contact with the second insulating layer 112.

[0027] As described above, in the printed circuit board 100A according to one embodiment, the surface of the first conductor pattern 121 may be covered with the first insulating film 151. The first insulating film 151 may be formed by a dry surface treatment, as described below, and may include a first inorganic layer 151a and a first organic layer 151b. Therefore, sufficient adhesion with the second insulating layer 112 may be ensured without a wet surface treatment, such as a CZ treatment, and signal loss may be effectively reduced by reducing surface roughness. Furthermore, a non-etching process may be performed to ensure sufficient design margin. Furthermore, the first insulating film 151, including the first inorganic layer 151a and the first organic layer 151b arranged in the above-described manner, may effectively prevent interlayer shorts due to foreign matter, scratches, or the like, as well as migration, sparks, and shorts between the plurality of first conductor patterns 121. For example, even when the thickness of the second insulating layer 112 is as thin as 10 μm or less, the above-described problems may be effectively resolved. Therefore, yield may be improved.

[0028] On the other hand, if the first insulating film 151 includes only the first inorganic layer 151a, problems such as voids and peeling may occur at the interface with the second insulating layer 112. Furthermore, if the first insulating film 151 includes only the first organic layer 151b, it may be difficult to improve interlayer short circuits, migration, sparks, short circuits, etc. caused by foreign matter, flaws, scratches, etc.

[0029] Meanwhile, in the first insulating film 151, the first inorganic layer 151a may be thicker than the first organic layer 151b. For example, the first inorganic layer 151a may have a thickness of about 1 nm to 50 nm or about 5 nm to 30 nm, and the first organic layer 151b may have a thickness of about 0.1 nm to 10 nm or about 0.5 nm to 5 nm. If the thickness is not uniform, the thickness here may be an average thickness, for example, an average value of thickness values ​​measured at any five points on a cross-sectional image of the first insulating film 151 including the first inorganic layer 151a and the first organic layer 151b. The cross-sectional image may be taken using a TEM (Transmission Electron Microscopy) or the like. This thickness relationship allows the first insulating film 151 to exhibit the above-described effects.

[0030] In addition, in the first insulating film 151, the first inorganic layer 151a may include a metal oxide, and the first organic layer 151b may include a silane-based compound. The metal oxide may be, for example, Al2O3, TiO2, TaO2, and / or SiN x The silane-based compound may include, for example, an aminosilane compound and / or an imidazole silane compound, and preferably includes, for example, an aminosilane compound such as, for example, 3-Aminopropyltriethoxysilane (APTES), but is not limited thereto. The material of the first organic layer 151b may be analyzed using, but is not limited to, XPS (X-ray Photoelectron Spectroscopy). By selecting such a material, the above-described effects of the first insulating film 151 can be more excellent.

[0031] Meanwhile, at least a portion of the second insulating film 152 may be disposed on the second conductive pattern 122. For example, the second insulating film 152 may cover at least a portion of the second conductive pattern 122 along the surface shape of the second conductive pattern 122. For example, the second insulating film 152 may be conformally disposed on the second conductive pattern 122 and extend onto the upper surface of the second insulating layer 112. When there are multiple second conductive patterns 122, the second insulating film 152 may be continuously disposed on the upper surface of the second insulating layer 112 between the multiple second conductive patterns 122. The second insulating film 152 may include a second inorganic layer 152a and / or a second organic layer 152b. The second insulating film 152 may also be composed of multiple layers, for example, may include a second inorganic layer 152a and a second organic layer 152b substantially similar to the first insulating film 151. On the surface of the second conductive pattern 122, the second inorganic layer 152a may be in contact with the second conductive pattern 122, and the second organic layer 152b may be spaced apart from the second conductive pattern 122. Through this second insulating film 152, the technical effects described above for the first insulating film 151 can be similarly achieved.

[0032] Meanwhile, the second inorganic layer 152a may be thicker than the second organic layer 152b. For example, the second inorganic layer 152a may have a thickness of about 1 nm to 50 nm or about 5 nm to 30 nm, and the second organic layer 152b may have a thickness of about 0.1 nm to 10 nm or about 0.5 nm to 5 nm. If the thickness is not uniform, the thickness here may be an average thickness, for example, an average value of thickness values ​​measured at any five points on a cross-sectional image photograph of the second insulating film 152 including the second inorganic layer 152a and the second organic layer 152b. The cross-sectional image photograph may be taken using a transmission electron microscope (TEM) or the like. This thickness relationship allows the second insulating film 152 to have the above-described effects.

[0033] The second inorganic layer 152a may include a metal oxide, and the second organic layer 152b may include a silane-based compound. The metal oxide may be, for example, Al2O3, TiO2, TaO2, and / or SiN. x The second organic layer 152b may include, for example, an aminosilane compound and / or an imidazole silane compound, and preferably includes, but is not limited to, an aminosilane compound such as, for example, 3-aminopropyltriethoxysilane (APTES). The material of the second organic layer 152b may be analyzed using, but is not limited to, XPS (X-ray Photoelectron Spectroscopy). By selecting such a material, the above-described effects of the second insulating film 152 can be more excellent.

[0034] The components of the printed circuit board 100A according to an example will be described in more detail below with reference to the drawings.

[0035] The first and second insulating layers 111 and 112 may each include an insulating material. The insulating material may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, or glass fabric). For example, the organic insulating material may be a non-photosensitive insulating material such as copper clad laminate (CCL), Ajinomoto build-up film (ABF), or prepreg (PPG), but is not limited thereto. Other polymer materials may also be used. The organic insulating material may also be a photosensitive insulating material such as a photoimageable dielectric (PID). Preferably, the first and second insulating layers 111 and 112 may each be ABF. ABFs of various compositions may be used, such as ABF with a low coefficient of thermal expansion (CTE), ABF containing nanofillers, and ABF with a low dielectric constant (Df). If necessary, the first insulating layer 111 may be omitted, but is not limited thereto.

[0036] The first and second conductor patterns 121 and 122 may each include a metal material. The metal material may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include, but is not limited to, copper (Cu). The first and second conductor patterns 121 and 122 may each include a signal pattern, a power pattern, and / or a ground pattern. These patterns may each have a line, pad, and / or plane shape. The first and second conductor patterns 121 and 122 may each include an electroless plating layer (e.g., chemical copper) and an electrolytic plating layer (e.g., electrolytic copper). A sputtering layer may be included instead of the electroless plating layer, or both may be included if necessary. For example, the first conductive pattern 121 may include a first seed layer 121a and a first metal layer 121b, and the second conductive pattern 122 may include a second seed layer 122a and a second metal layer 122b. The first and second seed layers 121a and 122a may each be an electroless plating layer and / or a sputtering layer, and may each include, for example, a copper (Cu) layer or a titanium (Ti) / copper (Cu) layer. The first and second metal layers 121b and 122b may each be an electrolytic plating layer, and may each include, for example, a copper (Cu) layer. The first and second insulating films 151 and 152 may not be formed on the lower surfaces of the first and second conductive patterns 121 and 122, respectively, but are not limited thereto.

[0037] The via pattern 131 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but is not limited to this. The via pattern 131 may include a signal via, a power via, and / or a ground via. The via pattern 131 may have a tapered cross section in which the width of the upper end is wider than the width of the lower end, but is not limited to this. The via pattern 131 may include an electroless plating layer (e.g., chemical copper) and an electrolytic plating layer (e.g., electrolytic copper). A sputtering layer may be included instead of the electroless plating layer, or both may be included if necessary. For example, the via pattern 131 may include a third seed layer 131a and a third metal layer 131b. The third seed layer 131a may be an electroless plating layer and / or a sputtering layer, and may include, for example, a copper (Cu) layer or a titanium (Ti) / copper (Cu) layer. The third metal layer 131b may be an electrolytic plating layer, and may include, for example, a copper (Cu) layer. The via pattern 131 may be integrated with the second conductor pattern 122, and, for example, the second and third seed layers 122a and 131a may be integrally connected to each other, and the second and third metal layers 122b and 131b may be integrally connected to each other.

[0038] The first and second insulating films 151 and 152 may each include an insulating material. The insulating material may be an organic insulating material and / or an inorganic insulating material. For example, the first and second insulating films 151 and 152 may each be a combination of an inorganic layer and an organic layer. The inorganic layer and the organic layer may each be a thin film coating layer that can be formed by sputtering, CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), ALD (Atomic Layer Deposition), etc. Preferably, the inorganic layer is formed by ALD in view of high step coverage and thickness uniformity, but is not limited thereto. The inorganic layer may be formed by, for example, Al2O3, TiO2, TaO2, and / or SiN x The organic layer may include, for example, an aminosilane compound and / or an imidazole silane compound, and preferably, may include, but is not limited to, an aminosilane compound, such as, but not limited to, APTES (3-Aminopropyltriethoxysilane). If necessary, the second insulating film 152 may be omitted, but is not limited to this.

[0039] 5A to 5C are schematic cross-sectional views illustrating steps in an example of manufacturing the printed circuit board of FIG.

[0040] Referring to the drawing, first, a first conductive pattern 121 may be formed on the upper surface of a first insulating layer 111. The first insulating layer 111 may be formed by laminating ABF or the like. The first conductive pattern 121 may be formed through a circuit process such as tenting (TT), additive process (AP), semi-additive process (SAP), or modified semi-additive process (MSAP). Next, a first insulating film 151 may be formed to continuously and conformally cover the upper surface of the first insulating layer 111 and the surface of the first conductive pattern 121. The first insulating film 151 may be formed by a dry pretreatment process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, a two-layer structure of a first inorganic layer 151a and a first organic layer 151b may be continuously formed by deposition and / or coating processes in a vacuum chamber. Next, a second insulating layer 112 can be formed on the first insulating layer 111, embedding the first conductive pattern 121 and the first insulating film 151. The second insulating layer 112 can be formed by laminating ABF or the like. Next, a via hole v can be formed penetrating the second insulating layer 112 and the first insulating film 151. The via hole v can be formed by a laser drill or the like. Next, a via pattern 131 filling the via hole v and a second conductive pattern 122 disposed on the upper surface of the second insulating layer 112 can be formed. The via pattern 131 and the second conductive pattern 122 can be formed by a circuit process such as tenting (TT), additive process (AP), semi-additive process (SAP), or modified semi-additive process (MSAP). Next, a second insulating film 152 can be formed to continuously and conformally cover the upper surface of the second insulating layer 112 and the surface of the second conductive pattern 122.The second insulating film 152 may be formed by a dry pretreatment process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. For example, a two-layer structure of the second inorganic layer 152a and the second organic layer 152b may be formed successively by a deposition and / or coating process in a vacuum chamber.

[0041] The printed circuit board 100A according to the above-described example can be manufactured through a series of processes. The other details can be substantially the same as those described above, and therefore, a redundant description thereof will be omitted.

[0042] FIG. 6 is a cross-sectional view schematically showing another example of a printed circuit board, and FIG. 7 is a schematic enlarged cross-sectional view of region B of the printed circuit board of FIG.

[0043] Referring to the drawings, a printed circuit board 100B according to another example may further include a third insulating film 153, at least a portion of which is disposed between the upper surface of the second insulating layer 112 and the lower surface of the second conductive pattern 122 in the printed circuit board 100A according to the above example. The via pattern 131 may further penetrate the third insulating film 153. An inner side surface of the third insulating film 153 may be in contact with the via pattern 131, and an outer side surface of the third insulating film 153 may be in contact with the second insulating film 152. The third insulating film 153 may include a third inorganic layer 153a and / or a third organic layer 153b, similar to the first and second insulating films 151 and 152. Between the second insulating layer 112 and the second conductive pattern 122, the third inorganic layer 153a may be in contact with the second insulating layer 112, and the third organic layer 153b may be in contact with the second conductive pattern 122. More specific details regarding the third inorganic layer 153a and the third organic layer 153b may be substantially the same as those described above for the first and second inorganic layers 151a and 152a and the first and second organic layers 151b and 152b. The third insulating film 153 may further improve adhesion between the second insulating layer 112 and the second conductive pattern 122, and more effectively prevent interlayer shorts due to foreign matter, flaws, scratches, etc.

[0044] The other contents may be substantially the same as those described above, and therefore, a duplicated description thereof will be omitted.

[0045] 8A to 8C are schematic cross-sectional views showing steps in an example of manufacturing the printed circuit board of FIG.

[0046] Referring to the drawing, first, a first conductive pattern 121 may be formed on the upper surface of a first insulating layer 111. The first insulating layer 111 may be formed by laminating ABF or the like. The first conductive pattern 121 may be formed through a circuit process such as tenting (TT), additive process (AP), semi-additive process (SAP), or modified semi-additive process (MSAP). Next, a first insulating film 151 may be formed to continuously and conformally cover the upper surface of the first insulating layer 111 and the surface of the first conductive pattern 121. The first insulating film 151 may be formed by a dry pretreatment process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, a two-layer structure of a first inorganic layer 151a and a first organic layer 151b may be continuously formed by deposition and / or coating processes in a vacuum chamber. Next, a second insulating layer 112 may be formed on the first insulating layer 111, embedding the first conductive pattern 121 and the first insulating film 151. The second insulating layer 112 may be formed by laminating ABF or the like. Next, a third insulating film 153 may be formed to continuously and conformally cover the upper surface of the second insulating layer 112. The third insulating film 153 may be formed by a dry pretreatment process such as CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), or ALD (Atomic Layer Deposition). For example, a two-layer structure of a third inorganic layer 153a and a third organic layer 153b may be continuously formed by a deposition and / or coating process in a vacuum chamber. Next, a via hole v may be formed penetrating the second insulating layer 112, the first insulating film 151, and the third insulating film 153. The via hole v may be formed by a laser drill or the like. Next, a via pattern 131 that fills the via hole v and a second conductor pattern 122 that is disposed on the upper surface of the third insulating film 153 can be formed.The via pattern 131 and the second conductor pattern 122 may be formed by a circuit process such as tenting (TT), additive process (AP), semi-additive process (SAP), or modified semi-additive process (MSAP). If necessary, the third insulating film 153 remaining on the upper surface of the second insulating layer 112 in areas other than the area where the second conductor pattern 122 is formed may be removed. Next, the second insulating film 152 may be formed to continuously and conformally cover the upper surface of the second insulating layer 112 and the surface of the second conductor pattern 122. The second insulating film 152 may be formed by a dry pretreatment process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, a two-layer structure of the second inorganic layer 152a and the second organic layer 152b may be continuously formed by deposition and / or coating processes in a vacuum chamber.

[0047] The printed circuit board 100B according to the other example described above can be manufactured through a series of processes. The other details may be substantially the same as those described above, and therefore, a redundant description thereof will be omitted.

[0048] FIG. 9 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 10 is a schematic enlarged cross-sectional view of region C of the printed circuit board of FIG.

[0049] Referring to the drawings, a printed circuit board 100C according to another example may further include a fourth insulating film 154 disposed within the second insulating layer 112 of the printed circuit board 100A according to the above example. The fourth insulating film 154 divides the second insulating layer 112 into a plurality of regions 112-1 and 112-2, e.g., a first region 112-1 adjacent to the first conductor pattern 121 and a second region 112-2 adjacent to the second conductor pattern 122. The via pattern 131 may further penetrate the fourth insulating film 154. An inner side surface of the fourth insulating film 154 may contact the via pattern 131. The fourth insulating film 154 may be thinner than the first and second regions 112-1 and 112-2. If the thickness is not uniform, the magnitude relationship may be compared using an average thickness. Here, the average thickness may be an average of thickness values ​​measured at any five points. For example, the average thickness of the fourth insulating film 154 in a cross section may be thinner than the average thickness of each of the first and second regions 112-1 and 112-2. The fourth insulating film 154 may include a fourth inorganic layer 154a and / or a fourth organic layer 154b, similar to the first and second insulating films 151 and 152. Between the first and second regions 112-1 and 112-2, the fourth inorganic layer 154a may contact the first region 112-1, and the fourth organic layer 154b may contact the second region 112-2. The details of the fourth inorganic layer 154a and the fourth organic layer 154b may be substantially the same as those described above for the first and second inorganic layers 151a and 152a and the first and second organic layers 151b and 152b. Even when the second insulating layer 112 is made up of multiple layers with the fourth insulating film 154 interposed therebetween, it can have excellent adhesion and can more effectively prevent interlayer shorts caused by foreign matter, scratches, etc. For example, defects caused by foreign material (FM), dents, voids, etc. can be improved.

[0050] The other contents may be substantially the same as those described above, and therefore, a duplicated description thereof will be omitted.

[0051] 11A to 11C are schematic cross-sectional views illustrating steps in an example of manufacturing the printed circuit board of FIG.

[0052] Referring to the drawing, first, a first conductive pattern 121 may be formed on the upper surface of a first insulating layer 111. The first insulating layer 111 may be formed by laminating ABF or the like. The first conductive pattern 121 may be formed through a circuit process such as tenting (TT), additive process (AP), semi-additive process (SAP), or modified semi-additive process (MSAP). Next, a first insulating film 151 may be formed to continuously and conformally cover the upper surface of the first insulating layer 111 and the surface of the first conductive pattern 121. The first insulating film 151 may be formed by a dry pretreatment process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, a two-layer structure of a first inorganic layer 151a and a first organic layer 151b may be continuously formed by deposition and / or coating processes in a vacuum chamber. Next, a second insulating layer 112-1 may be formed on the first insulating layer 111, embedding the first conductive pattern 121 and the first insulating film 151. The second insulating layer 112-1 may correspond to the first region 112-1 described above. The second insulating layer 112-1 may be formed by laminating ABF or the like. Next, a fourth insulating film 154 may be formed to continuously and conformally cover the upper surface of the second insulating layer 112-1. The fourth insulating film 154 may be formed by a dry pretreatment process such as CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), or ALD (Atomic Layer Deposition). For example, a two-layer structure of a fourth inorganic layer 154a and a fourth organic layer 154b may be continuously formed by deposition and / or coating processes in a vacuum chamber. Next, a second insulating layer 112-2 may be formed on the fourth insulating film 154. The second-second insulating layer 112-2 may correspond to the second region 112-2 described above. The second-second insulating layer 112-2 may be formed by laminating ABF or the like.Next, a via hole v may be formed that penetrates the 2-1 insulating layer 112-1, the 2-2 insulating layer 112-2, the first insulating film 151, and the fourth insulating film 154. The via hole v may be formed by a laser drill or the like. Next, a via pattern 131 that fills the via hole v and a second conductor pattern 122 disposed on the upper surface of the 2-2 insulating layer 112-2 may be formed. The via pattern 131 and the second conductor pattern 122 may be formed by a circuit process such as tenting (TT), an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP). Next, a second insulating film 152 may be formed that continuously and conformally covers the upper surface of the 2-2 insulating layer 112-2 and the surface of the second conductor pattern 122. The second insulating film 152 may be formed by a dry pretreatment process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. For example, a two-layer structure of the second inorganic layer 152a and the second organic layer 152b may be formed successively by a deposition and / or coating process in a vacuum chamber.

[0053] The printed circuit board 100C according to the above-described further example can be manufactured through a series of processes. The other details may be substantially the same as those described above, and therefore, a duplicated description thereof will be omitted.

[0054] FIG. 12 is a cross-sectional image diagram that schematically shows the layer structure of an insulating film formed between a conductor pattern and an insulating material.

[0055] Referring to the drawings, an insulating film having a double-layer structure, which is a mixed structure of a metal oxide film and an organic film, may be disposed between a conductor pattern (e.g., Cu) and an insulating material (e.g., ABF). The insulating film may have a thickness of several to several tens of nanometers. This insulating film may be used as at least one of the first to fourth insulating films described above. The arrangement of this insulating film may ensure adhesion between the conductor pattern and the insulating material, improve signal loss through a non-roughness surface treatment, and reduce interlayer shorts and migration caused by foreign matter, scratches, etc.

[0056] FIG. 13 is a cross-sectional view schematically showing an example of a semiconductor package.

[0057] Referring to the drawing, a semiconductor package 500 according to an example embodiment may include a package substrate 200 and first and second semiconductor chips 410 and 420 mounted on the package substrate 200. The package substrate 200 may include a bridge substrate 210 including fine wiring interconnecting the first and second semiconductor chips 410 and 420. The bridge substrate 210 may have an internal structure that includes at least one of the printed circuit boards 100A, 100B, and 100C described above. For example, the bridge substrate 210 may have a wiring structure including a plurality of insulating layers, a plurality of wiring layers disposed on or within the plurality of insulating layers, and a plurality of via layers penetrating at least one of the plurality of insulating layers. In this case, the plurality of insulating layers may include the first and / or second insulating layers described above, the plurality of wiring layers may include the first and / or second conductor patterns described above, the plurality of wiring layers may include the via patterns described above, and may further include the first, second, third, and / or fourth insulating layers described above. The package substrate 200 may be a conventional multilayer printed circuit board, and its specific structure is not particularly limited. If necessary, the internal structure of the package substrate 200 may include at least one of the printed circuit boards 100A, 100B, and 100C described above. The first and second semiconductor chips 410 and 420 may be memory chips, application processor chips, and / or logic chips, respectively. The first and second semiconductor chips 410 and 420 may be the same type of chip or different types of chips.

[0058] The other contents are substantially the same as those described above, and therefore, a duplicated description thereof will be omitted.

[0059] FIG. 14 is a cross-sectional view schematically showing another example of a semiconductor package.

[0060] Referring to the drawing, a semiconductor package 600 according to another example may include a package substrate 300 and first and second semiconductor chips 410 and 420 mounted on the package substrate 300. A fine wiring layer 310 including fine wiring interconnecting the first and second semiconductor chips 410 and 420 may be disposed on the outermost surface of the package substrate 300. The fine wiring layer 310 may include at least one of the printed circuit boards 100A, 100B, and 100C described above. For example, the fine wiring layer 310 may have a wiring structure including a plurality of insulating layers, a plurality of wiring layers disposed on or within the plurality of insulating layers, and a plurality of via layers penetrating at least one of the plurality of insulating layers. In this case, the plurality of insulating layers may include the first and / or second insulating layers described above, the plurality of wiring layers may include the first and / or second conductor patterns described above, the plurality of wiring layers may include the via patterns described above, and may further include the first, second, third, and / or fourth insulating layers described above. The package substrate 300 may be a conventional multilayer printed circuit board, and its specific structure is not particularly limited. If necessary, the internal structure of the package substrate 300 may include at least one of the above-described printed circuit boards 100A, 100B, and 100C. The first and second semiconductor chips 410 and 420 may be memory chips, application processor chips, and / or logic chips, respectively. The first and second semiconductor chips 410 and 420 may be the same type of chip or different types of chips.

[0061] The other contents are substantially the same as those described above, and therefore, a duplicated description thereof will be omitted.

[0062] In the present disclosure, the term "cover" may include not only completely covering but also at least partially covering, and may also include not only directly covering but also indirectly covering. Furthermore, the term "fill" may include not only completely filling but also at least partially filling, and may also include roughly filling. Furthermore, the term "surround" may include not only completely surrounding but also partially surrounding and roughly surrounding. Furthermore, "expose" may include not only completely exposing but also partially exposing, and may mean exposing a corresponding component from something that embeds it.

[0063] In the present disclosure, "substantially" can be determined to include process errors, positional deviations, measurement errors, etc. that occur during the manufacturing process. For example, "substantially constant thickness" can include not only cases where the thickness is completely constant, but also cases where the thickness is roughly constant. Furthermore, "substantially coplanar" can include not only cases where the thickness is completely in the same plane, but also cases where the thickness is roughly in the same plane.

[0064] In the present disclosure, the term "cross section" can refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the term "planar" can refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0065] In this disclosure, for convenience, terms such as bottom, lower part, and bottom surface are used to refer to the downward direction based on the cross section of the drawing, and terms such as top, upper part, and top surface are used to refer to the opposite direction. However, this is a definition of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of these directions, and the concepts of top and bottom may change at any time.

[0066] In this disclosure, the term "connected" encompasses not only direct connection but also indirect connection via an adhesive layer, etc. Furthermore, the term "electrically connected" encompasses both physical connection and non-physical connection. Furthermore, terms such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0067] In the present disclosure, thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness, etc. can be measured using a scanning microscope or optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical or horizontal section, and each value can be measured based on the required cut section. For example, the width of the upper and / or lower ends of a via can be measured on a cross section cut along the central axis of the via. In this case, if the value is not constant, the value can be determined as the average of values ​​measured at any five points.

[0068] The term "one example" used in this disclosure does not mean the same embodiment as the other examples, but is provided to emphasize and describe the unique features that are different from each other. However, the above-described one example does not exclude being realized in combination with the features of another example. For example, even if a matter described in a particular example is not described in another example, it can be understood as being related to the other example unless there is a contrary or contradictory description with that matter in the other example.

[0069] The terms used in this disclosure are merely used to describe an example and are not intended to limit the disclosure. In this case, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0070] 1000 electronic equipment 1010 mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 camera 1060 Antenna 1070 display 1080 battery 1090 signal line 1100 smartphone 1110 motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 Speaker 100A, 100B, 100C Printed Circuit Boards 111, 112 Insulating layer 121, 122 Conductor pattern 121a, 122a, 131a seed layer 121b, 122b, 131b metal layer 131 via pattern 151, 152, 153, 154 Insulating film 151a, 152a, 153a, 154a Inorganic layer 151b, 152b, 153b, 154b organic layer 500, 600 semiconductor packages 410, 420 semiconductor chips 200, 300 package substrate 210 Bridge board 310 Fine wiring layer

Claims

1. a first conductor pattern; a first insulating film covering at least a portion of the first conductor pattern along the shape of a surface of the first conductor pattern; an insulating layer disposed on the first insulating film; The first insulating film includes a first inorganic layer and a first organic layer.

2. The printed circuit board according to claim 1 , wherein, on a surface of the first conductor pattern, the first inorganic layer contacts the first conductor pattern and the first organic layer contacts the insulating layer.

3. The printed circuit board of claim 1 , wherein the first inorganic layer is thicker than the first organic layer.

4. the first inorganic layer has a thickness of 1 nm to 50 nm; The printed circuit board of claim 3 , wherein the first organic layer has a thickness of 0.1 nm to 10 nm.

5. the first inorganic layer includes a metal oxide; The printed circuit board of claim 1 , wherein the first organic layer comprises a silane-based compound.

6. The metal oxide is Al ２ O ３ , TiO ２ , TaO ２ and SiN ｘ one or more of The printed circuit board according to claim 5 , wherein the silane-based compound is at least one of an aminosilane compound and an imidazole silane compound.

7. The printed circuit board of claim 1 , wherein the first insulating film extends onto a lower surface of the insulating layer.

8. the first conductor pattern is a plurality of first conductor patterns, the first insulating film covers at least a portion of each of the first conductor patterns along the shape of a surface of each of the first conductor patterns; The printed circuit board according to claim 7 , wherein the first insulating film is disposed continuously on the lower surface of the insulating layer between the plurality of first conductor patterns.

9. a second conductor pattern disposed on the insulating layer; The printed circuit board of claim 1 , further comprising a via pattern that penetrates the insulating layer and the first insulating film and connects the first and second conductor patterns to each other.

10. the first conductor pattern includes a first seed layer and a first metal layer; the second conductor pattern includes a second seed layer and a second metal layer; the via pattern includes a third seed layer and a third metal layer; the second and third seed layers are integrally connected to each other; The printed circuit board of claim 9 , wherein the second and third metal layers are integrally connected to one another.

11. a second insulating film covering at least a portion of the second conductor pattern along a surface shape of the second conductor pattern; the second insulating film extends onto an upper surface of the insulating layer; The printed circuit board of claim 9 , wherein the second insulating film comprises at least one of a second inorganic layer and a second organic layer.

12. a third insulating film at least partially disposed between the upper surface of the insulating layer and the lower surface of the second conductor pattern; the via pattern further penetrates the third insulating film, The printed circuit board of claim 9 , wherein the third insulating film comprises at least one of a third inorganic layer and a third organic layer.

13. further comprising a fourth insulating film disposed within the insulating layer; the fourth insulating film divides the insulating layer into a first region adjacent to the first conductor pattern and a second region adjacent to the second conductor pattern; the via pattern further penetrates the fourth insulating film, The printed circuit board of claim 9 , wherein the fourth insulating film includes at least one of a fourth inorganic layer and a fourth organic layer.

14. The printed circuit board of claim 1 , wherein the insulating layer comprises an Ajinomoto Build-up Film (ABF).

15. a first insulating layer; a first conductor pattern embedded under the first insulating layer, at least a portion of a lower surface of which is exposed from the lower surface of the first insulating layer; a first insulating film that covers at least a portion of each of an upper surface and a side surface of the first conductor pattern along the shape of the first conductor pattern and extends onto a lower surface of the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second insulating film disposed between the first and second insulating layers and having a thickness thinner than that of each of the first and second insulating layers; a second conductor pattern disposed on the top surface of the second insulating layer.

16. The printed circuit board of claim 15 , further comprising a via pattern that penetrates the first and second insulating layers and the first and second insulating films and connects the first and second conductor patterns to each other.

Images