Imaging device and electronic apparatus

Abstract

To provide an imaging apparatus having an image processing function.SOLUTION: An imaging device with an additional function such as image processing can hold analog data obtained by imaging operation in a pixel and take out data obtained by multiplying the analog data by a given weight coefficient. In the pixel, difference data between adjacent light-receiving devices can be obtained, and data on a luminance gradient can be obtained. When the information is taken into a neural network or the like, distance information or the like can be inferred. In addition, an enormous amount of image data can be retained in a pixel as analog data, so that processing can be performed efficiently.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using oxide semiconductor thin films formed on substrates has been attracting attention. For example, a transistor having an oxide semiconductor and extremely low off-state current is used in a pixel circuit. An imaging device having such a configuration is disclosed in Patent Document 1.

[0005] Furthermore, Patent Document 2 discloses a technique for adding a calculation function to an imaging device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-123087 Summary of the Invention [Problem to be solved by the invention]

[0007] The ability to capture high-resolution images has become common in imaging devices installed in mobile devices. In the next generation, imaging devices will be required to have even more intelligent functions. .

[0008] The image data (analog data) acquired by the imaging device is converted into digital data and sent to an external device. After the image is extracted, image processing is performed as necessary. If possible, cooperation with external devices will be faster, and user convenience will be improved. The load and power consumption of peripheral devices can also be reduced. If complex data processing can be performed in a single step, the time required for data conversion can also be reduced.

[0009] For example, the brightness gradient is calculated from the difference information of the data between adjacent pixels, and the brightness gradient is used as the data. By using DNN (deep neural network) as the data, distance information The calculation of the difference data between pixels and the calculation of part of the DNN are performed by the imaging device. By performing this on-site, high-speed inference with low power consumption becomes possible.

[0010] In addition, mobile information terminals such as smartphones can acquire information on the distance of the captured subject. The captured image can be processed (such as blurring the front and back of the target subject). The distance information is acquired using parallax from multiple cameras. If we could obtain this information, we could combine cameras into one, reducing manufacturing costs. can be done.

[0011] Therefore, one aspect of the present invention is to provide an imaging device capable of image processing. Another object of the present invention is to provide an imaging device capable of acquiring distance information. Alternatively, an imaging device capable of acquiring information on the luminance gradient between adjacent pixels is provided. One of the purposes is to function as a part of a neural network. One of the objects is to provide an imaging device. Alternatively, to provide an imaging device with low power consumption. Another object of the present invention is to provide a highly reliable imaging device. Another object is to provide a novel imaging device. It is one of the objects to provide a method for driving an image device. One of the aims is to provide

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention relates to an imaging device having an image processing function.

[0014] One embodiment of the present invention includes a pixel and a readout circuit, and the pixel includes a first light receiving circuit and a second light receiving circuit. The amplifier circuit is held in the first light receiving circuit. and a potential corresponding to the difference between the first data stored in the second light receiving circuit and the second data stored in the second light receiving circuit. and outputting the signal to an arithmetic circuit, the arithmetic circuit having a first node and a second node. When the first data and the second data are the same value, the amplifier circuit outputs A first potential corresponding to the first data is written to the second node, and the first data and the second data are written to the second node. When the second potential is generated by the electric conversion, the second potential output by the amplifier circuit is written to the first node. A third potential can be added to each of the first node and the second node, and a read circuit is the current that flows according to the potential of the first node and the current that flows according to the potential of the second node. An imaging device capable of extracting the product of the second potential and the third potential by calculation using be.

[0015] The readout circuit includes a current mirror circuit and a correlated double sampling circuit. The mirror circuit includes a first transistor and a second transistor. The source or drain of the transistor and the gate are electrically connected to the first node. , one of the source or drain of the second transistor is connected to the second node and the correlated double The amplifier circuit can be electrically connected to the amplifier.

[0016] Another embodiment of the present invention includes a pixel and a readout circuit, and the pixel includes a first light receiving circuit. a first input terminal, a second light receiving circuit, an amplifier circuit, and an arithmetic circuit; and a second input terminal, and the arithmetic circuit has a first node, a second node, and a first a capacitor, a second capacitor, a first transistor, a second transistor, The first node is connected to one electrode of the first capacitor and one electrode of the first transistor. The gate is electrically connected to the second node, and one electrode of the second capacitor and the second The gates of the second transistor are electrically connected, and the source or drain of the first transistor is One of the inputs of the first transistor and one of the source or drain of the second transistor are connected to a read circuit. The first light receiving circuit is electrically connected to the first input terminal, and the second The light receiving circuit is electrically connected to the second input terminal, and the first node is connected to the first input terminal and The first potential output by the amplifier circuit when the same potential is input to the first and second input terminals is written as The second node receives the data generated by the first light receiving circuit and the data generated by the second light receiving circuit. The second potential output by the amplifier circuit is written in accordance with the difference between the data to be written and the first node and the second node is connected to the first capacitor or the second capacitor. , a third potential can be added, and the readout circuitry can measure the current flowing through the first transistor. and a calculation using the current flowing through the second transistor determines the difference between the second potential and the third potential. It is an imaging device that can extract the product.

[0017] The readout circuit includes a current mirror circuit and a correlated double sampling circuit. The mirror circuit includes a third transistor and a fourth transistor. The source or drain and gate of the first transistor are connected to the source or drain of the second transistor. is electrically connected to one of the drains of the fourth transistor and is connected to one of the source or drain of the fourth transistor. On the other hand, one of the source or drain of the second transistor and the correlated double sampling circuit The circuit can be electrically connected to the

[0018] Each of the first and second light receiving circuits includes a photoelectric conversion device and a fifth transistor. a sixth transistor, a third capacitor, and a third capacitor; The other electrode is electrically connected to one of the source and drain of the fifth transistor. The other of the source or drain of the fifth transistor is connected to the source or drain of the sixth transistor. The first light receiving element is electrically connected to one of the drains and one of the electrodes of the third capacitor. The other of the source and the drain of the sixth transistor included in the circuit is connected to the first input terminal. the source or drain of the sixth transistor of the second light receiving circuit. The other can be electrically connected to the second input terminal.

[0019] The fifth transistor and the sixth transistor each have a metal oxide in a channel formation region. The metal oxides are In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, and one or more of La, Ce, Nd or Hf).

[0020] Each of the first and second light receiving circuits further includes a seventh transistor and an eighth transistor. a gate of the seventh transistor is connected to one of the third capacitors; The seventh transistor is electrically connected to the source or drain of the eighth transistor. It is preferable that the gate electrode is electrically connected to either the source or the drain of the transistor.

[0021] The amplifier circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and , and one of the source and drain of the ninth transistor is connected to the first light receiving circuit. the source or the second electrode of the ninth transistor; The other of the drains is electrically connected to the first input terminal, and the source of the tenth transistor is One of the source and drain of the second light receiving circuit is connected to one electrode of a third capacitor of the second light receiving circuit. The other of the source and drain of the tenth transistor is electrically connected to the second input terminal The eleventh transistor is electrically connected to the first transistor, and one of the source and the drain of the eleventh transistor is electrically connected to the first transistor. The other of the source and the drain of the eleventh transistor is electrically connected to the input terminal. It can be electrically connected to the second input terminal.

[0022] The ninth to eleventh transistors each have a metal oxide in a channel formation region. The metal oxides are In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, and one or more of La, Ce, Nd or Hf).

[0023] In the above, a plurality of pixels can be electrically connected to one readout circuit. Cut.

[0024] Another aspect of the present invention is a method for analyzing an image captured by the imaging device and an image analyzed by the imaging device. This is an electronic device that processes a part of an image based on distance information of the subject in the image. [Effects of the Invention]

[0025] By using one embodiment of the present invention, an imaging device capable of image processing can be provided. Alternatively, an imaging device capable of acquiring distance information can be provided. It is possible to provide an imaging device that can acquire information on the luminance gradient between adjacent pixels. It is possible to provide an imaging device that functions as a part of a neural network. Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, a novel imaging device or the like can be provided. Furthermore, a method for driving the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device. [Figure 2] FIG. 2 is a diagram illustrating a pixel block 200 and a circuit 240. As shown in FIG. [Figure 3] FIG. 3 is a diagram illustrating the pixel 100. [Figure 4] Fig. 4A is a diagram illustrating a light receiving circuit, and Fig. 4B is a diagram illustrating a differential amplifier circuit. [Figure 5] 5A and 5B are diagrams illustrating a current source circuit. [Figure 6] FIG. 6 is a timing chart illustrating the operation of the pixel block 200. As shown in FIG. [Figure 7] 7A and 7B are diagrams illustrating the circuit 301 and the circuit 302. FIG. [Figure 8] FIG. 8 is a diagram illustrating a memory cell. [Figure 9] 9A and 9B are diagrams showing examples of the configuration of a neural network. [Figure 10] 10A to 10D are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 11] 11A to 11C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 12] FIG. 12 is a cross-sectional view illustrating a pixel. [Figure 13] 13A to 13C are diagrams illustrating a Si transistor. [Figure 14] FIG. 14 is a cross-sectional view illustrating a pixel. [Figure 15] FIG. 15 is a cross-sectional view illustrating a pixel. [Figure 16] FIG. 16 is a cross-sectional view illustrating a pixel. [Figure 17] 17A to 17D illustrate an OS transistor. [Figure 18] FIG. 18 is a cross-sectional view illustrating a pixel. [Figure 19] 19A to 19C are perspective views (cross-sectional views) illustrating pixels. [Figure 20] 20A1 to 20A3 and 20B1 to 20B3 are perspective views of a package and a module that house an imaging device. [Figure 21] 21A to 21F are diagrams illustrating an electronic device. [Figure 22] FIG. 22 is a diagram illustrating an automobile. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0028] In addition, even if a circuit diagram shows a single element, there may be functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, a transistor that operates as a switch may be used. In some cases, multiple resistors may be connected in series or in parallel. In some cases, the sensor may be divided and placed in multiple positions.

[0029] In addition, when one conductor has multiple functions such as wiring, electrode, and terminal, In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, The elements may be connected via one or more conductors, and This type of configuration is also included in the category of direct connection.

[0030] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0031] One aspect of the present invention is an imaging device having additional functions such as image processing. The analog data (image data) acquired during the imaging operation is stored in the pixels, and the analog data and an arbitrary weighting coefficient can be multiplied to extract data.

[0032] In addition, the pixel can obtain differential data between adjacent light receiving devices, and the brightness gradient By incorporating this information into a neural network, It is possible to infer distance information and other information. It is also possible to convert a huge amount of image data into analog data. Since the pixel can be held in this state, processing can be performed efficiently.

[0033] By obtaining distance information from images, robots can perform picking operations and automatic operation of moving objects. It can also support distance measurement and other tasks. Previously, multiple cameras were used to acquire information, but now distance information can be obtained with a single camera. The manufacturing cost can be reduced.

[0034] <Imaging device> FIG. 1 is a block diagram illustrating an imaging device according to one embodiment of the present invention. Circuit 300, circuit 301, circuit 302, circuit 303, circuit 304, and circuit 305 Note that each of the circuits 301 to 305 is not limited to a single circuit configuration, but may be a plurality of circuits. It may be composed of a combination of the above circuits. Or, it may be composed of an integrated circuit of any of the above circuits. In addition, circuits other than those described above may be connected.

[0035] The pixel array 300 has an imaging function and a calculation function. The circuit 301 has a calculation function. The circuit 302 has a calculation function or a data conversion function. The circuits 303 and 304 are The circuit 305 has a function of supplying a potential for product-sum calculation to the pixel. The circuit having the function may be a shift register or a decoder. The circuits 301 and 302 may be provided externally.

[0036] The pixel array 300 includes a plurality of pixel blocks 200. The pixel blocks 200 are shown in FIG. As shown, the pixel array 210 and the circuit 220 are included.

[0037] The pixel array 210 has a plurality of pixels 100 arranged in a matrix. The element 100 is electrically connected to the wiring 151 and the wiring 152. 52 are electrically connected to the circuit 220, respectively.

[0038] The circuit 220 is a readout circuit and includes a circuit 230 and a circuit 240. The circuit 230 is It is a current source circuit and has the function of controlling the current flowing through the pixel array 210 and the circuit 240. The circuit 240 is a differential extraction circuit, for example, a correlated double sampling circuit (CDS circuit) can be used.

[0039] Any two or more of the circuit 230, the circuit 240, and the pixel array 210 overlap each other. It is preferable that the pixel block 2 is formed to have a region. The area of ​​the pixel 240 can be reduced, and the resolution can be increased. , it can also be provided outside the pixel block 200.

[0040] In FIG. 2, the number of pixels in the pixel array 210 is 3×3 as an example. However, it is not limited to this. For example, it can be 2x2, 4x4, etc. Or, the horizontal direction The number of pixels in the horizontal and vertical directions may be different. A switch or the like may be provided between each of the lines 152 to change the number of pixels. The pixel may be shared by adjacent pixel blocks 200. A path or a gain adjustment circuit may be electrically connected to the amplifier.

[0041] The pixel 100 acquires image data, generates calculation data using the image data, and performs the calculation. The above-mentioned configuration can also be used to generate data by adding the calculated data and a weighting factor. The pixel block 200 can be operated as a multiply-accumulate circuit.

[0042] <Pixel circuit> 3 shows a configuration example of a pixel 100. The pixel 100 includes circuits 10a and 10b, a circuit 20, and a circuit It has 30.

[0043] The circuits 10a and 10b are light receiving circuits, and generate image data using a photoelectric conversion device. The circuit 20 is a differential amplifier circuit, and receives the signals from the circuits 10a and 10b. The circuit 30 has a function of outputting a data potential amplified according to the difference between the received data. The circuit has a function of holding the data potential output from the circuit 20 and a function of detecting the data potential. It has the function of giving weights (potentials equivalent to weighting coefficients).

[0044] <Light receiving circuit> The circuits 10a and 10b may have the same configuration, and the photoelectric conversion device 101 (photoelectric conversion devices 101a and 101b) and transistor 102 (transistors 102a and 102 b), transistor 103 (transistors 103a and 103b), and capacitor 106 (capacitors 106a, 106b).

[0045] One electrode of the photoelectric conversion device 101 is connected to the source or drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to the One of the source or drain of the transistor 103 and one electrode of the capacitor 106 are electrically connected.

[0046] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 114. The other of the source and drain of the transistor 103 is electrically connected to the wiring 115. The gate of the transistor 102 is electrically connected to the wiring 116. is electrically connected to the wiring 117.

[0047] Here, the other of the source or drain of the transistor 102 and the source of the transistor 103 The electrical connection point between one of the source or drain and one electrode of the capacitor 106 is Let node FD be node FD (node ​​FDa, node FDb).

[0048] The wirings 114 and 115 can function as power supply lines. The wiring 11 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. 6 and 117 can function as signal lines that control the conduction of each transistor.

[0049] The photoelectric conversion device 101 may be a photodiode. Regardless of the type of diode, Si photodiodes with silicon in the photoelectric conversion layer, organic photoconductors An organic photodiode having a conductive film as a photoelectric conversion layer can be used. If you want to increase the light detection sensitivity during measurement, it is preferable to use an avalanche photodiode. It's nice.

[0050] The transistor 102 can have a function of controlling the potential of the node FD. The resistor 103 can have a function of initializing the potential of the node FD.

[0051] When an avalanche photodiode is used as the photoelectric conversion device 101, a high voltage is applied. The transistor connected to the photoelectric conversion device 101 may be a high-voltage transistor. For example, a high-voltage transistor may be used in a channel forming region. A transistor using metal oxide (hereinafter referred to as OS transistor) or the like can be used for the Specifically, the transistor 102 is preferably an OS transistor.

[0052] The OS transistor also has an extremely low off-state current. By using an OS transistor in 103, the period during which the charge can be held at node FD can be shortened. Therefore, the circuit configuration and operation method can be made extremely long. A global shutter system can be applied, in which charge accumulation is performed simultaneously in all pixels. In addition, while the image data is stored in the node FD, multiple calculations using the image data are performed. It is also possible to do the following.

[0053] On the other hand, when high speed operation is desired, high mobility semiconductors using silicon for the channel formation region are used. It is preferable to use a high-power transistor (hereinafter referred to as a Si transistor). The transistors 102 and 103 may be Si transistors.

[0054] The present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. As the Si transistor, a transistor having amorphous silicon may be used. , crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystal silicon) Transistors and the like.

[0055] The above is an example of the circuit configuration of the circuits 10a and 10b, and the photoelectric conversion operation may be different from other circuits. This can also be done by circuit configuration.

[0056] Also, as shown in FIG. 4A, the circuits 10a and 10b include a transistor 175 (transistor 175a, 175b), and transistor 176 (transistors 176a, 176b) The configuration may also include the following.

[0057] The gate of the transistor 175 is electrically connected to the node FD. One of the source and the drain of the transistor 17 is electrically connected to the wiring 118. The other of the source or drain of transistor 176 is connected to the other of the source or drain of transistor 176. The other of the source and the drain of the transistor 176 is electrically connected to the wiring OU The wiring 118 can function as a power supply line, and the wiring 115 can be electrically connected to the may be connected to

[0058] The transistor 175 is a source follower that outputs data according to the potential of the node FD. The transistor 176 is a selection transistor for selecting the light receiving circuit to be read out. Therefore, by using the circuits 10a and 10b having the configuration shown in FIG. Image data can be read out from each light receiving circuit to the wiring OUT. It is also possible to read out image data in parallel with the operation of the circuit 20.

[0059] <Differential amplifier circuit> The circuit 20 includes a transistor 104 (transistors 104a and 104b) and a transistor 105 (transistors 105a and 105b), transistor 107, and transistor 1 08 and a transistor 131 (transistors 131a and 131b). This can be done.

[0060] One of the source and drain of transistor 104a is connected to the gate of transistor 105a. and is electrically connected to one of the source and drain of the transistor 107. One of the source and drain of transistor 104b is connected to the gate of transistor 105b and The transistor 107 is electrically connected to the other of the source and the drain. One of the source or drain of 105a is connected to the source or drain of transistor 131a. The source or drain of the transistor 105b is electrically connected to one of the terminals and the gate of the transistor 105b. One of the inputs is electrically connected to one of the source or drain of the transistor 131b and the gate. The other of the source and drain of the transistor 105a is connected to the The other of the source or drain of transistor 105b and the source or drain of transistor 108 The terminals are electrically connected to one of the terminals.

[0061] The other of the source and the drain of the transistor 131 is electrically connected to the wiring 124. The other of the source and drain of the transistor 108 is connected to a reference potential line such as a GND line. The gate of the transistor 104a is electrically connected to the wiring 121. The gate of the transistor 104b is electrically connected to the wiring 122. The gate of the transistor 107 is electrically connected to the wiring 123.

[0062] The wiring 124 can function as, for example, a power supply line that supplies high potential power. The wiring 121, wiring 122, and wiring 123 are signal lines that control the conduction of each transistor. It can have all the functions.

[0063] The transistor 104 functions as a switch. The other drain is electrically connected to a node FDa of the circuit 10a. The other of the source and drain of 104b is electrically connected to node FDb of circuit 10b. Therefore, the transistor 104 is an element of the circuits 10a and 10b. It is also possible.

[0064] The transistor 105 functions as a differential transistor pair in the differential amplifier circuit. The gate of the transistor 105a functions as a first input terminal of the circuit 20. The gate of 105b serves as the second input terminal of the circuit 20. The data generated by the circuit 10a can be input to the input terminal. The child can receive data generated by circuit 10b.

[0065] The transistor 107 functions as a switch, connecting the first input terminal and the second input terminal to the same The switch can be used when acquiring reference data.

[0066] The transistor 108 functions as a current source, and a suitable potential (Bias) is supplied to the gate. Note that a resistor may be used instead of the transistor 108.

[0067] The transistor 131 functions as a voltage conversion circuit. 31 is shown as a diode-connected p-channel transistor, Alternatively, a diode may be used instead of the transistor 131. A diode element, a resistor element, or a cascode circuit may be used.

[0068] In addition, one of the source or drain of the transistor 105b and the source of the transistor 131b The part of the wiring that connects either the source or drain also functions as the output terminal. The output terminal (node ​​N) is connected to the output data of the circuit 10a and the output data of the circuit 10b. 10b, a data potential amplified according to the difference in the output data can be output.

[0069] As shown in FIG. 4B, the circuit 20 includes a transistor 104 and a transistor 107. The transistor 104 and the transistor 107 may be configured to have a first input. The second input terminal and the second input terminal are provided to have the same potential. By using the potential (reset potential) of the wiring 115 supplied from the transistor 103, The transistor 104 and the transistor 107 can be omitted.

[0070] <Arithmetic circuit> The circuit 30 includes a transistor 132, a transistor 133, a transistor 134, and a transistor a transistor 142, a transistor 143, a transistor 144, and a capacitor 135 and a capacitor 145.

[0071] One of the source and drain of the transistor 132 is connected to one electrode of the capacitor 135 and and the gate of the transistor 133. The other electrode of the capacitor 135 is electrically connected to one of the source and drain of the transistor 134. One of the source or drain of transistor 142 is connected to one electrode of capacitor 145 and transistor 146. The other electrode of the capacitor 145 is electrically connected to the gate of the transistor 143. It is electrically connected to either the source or the drain of the transistor 144 .

[0072] The gate of the transistor 132 is electrically connected to the wiring 125. The gate of the transistor 134 is electrically connected to the wiring 126. The gate of the transistor 144 is electrically connected to the wiring 127. The other of the source or drain of transistor 142 is The other of the source and drain of the transistor 134 is electrically connected to the node N. The other of the source and the drain of the transistor 144 is electrically connected to the wiring 128. do.

[0073] One of the source and the drain of the transistor 133 is electrically connected to the wiring 151. One of the source and the drain of the transistor 143 is electrically connected to a wiring 152. do. The other of the source or drain of the transistor 133 and the other of the source or drain of the transistor 143 The other end of the drain is electrically connected to a reference potential line such as a GND line or a low potential power supply line. will be done.

[0074] The wiring 125, the wiring 126, and the wiring 127 are used as signal lines for controlling the conduction of each transistor. The wiring 128 can have the function of, for example, transmitting a weighting coefficient (filter for convolution processing). The wiring is capable of supplying a potential corresponding to the circuit 305 (see FIG. 1). The wiring 151 is electrically connected to the circuit 230 and the circuit 240. The wiring 152 is a wiring electrically connected to the circuit 230 (see FIG. 2).

[0075] Here, one of the source or drain of the transistor 132 and one of the capacitors 135 The point (wiring) where the electrode and the gate of the transistor 133 are connected is referred to as node P1. In addition, one of the source and drain of the transistor 142 and one of the voltages of the capacitor 145 The point (wiring) where the electrode and the gate of the transistor 143 are connected is referred to as node P2.

[0076] The data output by the circuit 20 can be stored in the nodes P1 and P2. Also, nodes P1 and P2 can be floating. The data held in the nodes P1 and P2 are supplied with a potential (heavy) from the wiring 128. The capacitance coefficient can be given by the capacitive coupling of capacitor 135 or capacitor 145.

[0077] <Readout circuit> Next, the configuration of the read circuit 220 will be described. The read circuit 220 includes a current source circuit and a circuit 240 that functions as a difference extraction circuit.

[0078] <Current source circuit> The circuit 230 can apply a current according to the data stored in the pixel 100. For example, The circuit 230 may have a configuration shown in FIG. 5A. The configuration may include a lens section 226.

[0079] FIG. 5A shows a configuration using n-ch transistors. The configuration may include the first and second inputs 222 and 252, and the second and third inputs 223 and 253.

[0080] One of the source and drain of the transistor 222 is electrically connected to the signal line FG. The other of the source and drain of the transistor 222 is connected to the gate of the transistor 223. One of the source and drain of the transistor 252 is electrically connected to the signal line FG The other of the source and drain of the transistor 252 is electrically connected to REF. The gate of the transistor 222 is electrically connected to the gate of the transistor 253. A gate of the transistor 252 is electrically connected to the wiring 213.

[0081] One of the source and the drain of the transistor 223 is electrically connected to the wiring 151 . One of the source and the drain of the transistor 253 is electrically connected to the wiring 152 . The other of the source or drain of the transistor 223 and the source of the transistor 253 Alternatively, the other of the drains is electrically connected to the high potential power supply line (VDD).

[0082] In the current supply unit 225, an appropriate signal potential is supplied to the signal lines FG and FGREF, and the wiring 2 By supplying a high potential ("H") to 13, transistors 222, 252 and The resistors 223 and 253 are conductive, and current can be supplied to the wiring 151 and the wiring 152. Cut.

[0083] The current mirror section 226 has a structure including a transistor 254 and a transistor 224. The gate and one of the source and drain of the transistor 254 may be is electrically connected to the wiring 152. is electrically connected to the wiring 151. The other of the source and drain of the transistor 224 The other of the source and drain of the transistor 254 is connected to the low potential power line (VSS). The gate of transistor 224 is electrically connected to the gate of transistor 254. The transistor 224 is electrically connected to the transistor 254, and the same current (ICM) flows through the transistor 224. It is possible.

[0084] The current supply unit 225 is configured using a p-ch transistor as shown in FIG. 5B. The output side of the transistor 262 is connected to the wiring 152 and the gate of the transistor 261. It is electrically connected to the port.

[0085] <Difference extraction circuit> The circuit 240 is a differential extraction circuit, and uses the currents flowing through the pixel 100 and the circuit 230 to: The product of the data and the weighting coefficient (product-sum operation result) can be extracted. As shown in Figure 2, The pixels 100 are electrically connected to each other by wiring 151. The circuit 240 The calculation can be performed using the sum of the currents flowing through the transistors 133.

[0086] The circuit 240 includes a capacitor 202, a transistor 203, a transistor 204, and a transistor A transistor 205, a transistor 206, and a transistor 207 as a voltage conversion circuit. A suitable analog potential (Bias) is applied to the gate of the transistor 207. do.

[0087] One electrode of the capacitor 202 is connected to one of the source and drain of the transistor 203. and electrically connected to the gate of the transistor 204. The source or drain of the transistor 205 is connected to the source or drain of the transistor 206. The capacitor 20 is electrically connected to either the source or the drain of the transistor 206. The other electrode of the transistor 207 is connected to the wiring 151 and one of the source and drain of the transistor 207. and electrically connected to each other.

[0088] Here, one electrode of the capacitor 202, the source or drain of the transistor 203 The point where the gate of the transistor 204 is connected to the other side is referred to as node C.

[0089] The other of the source and the drain of the transistor 203 is electrically connected to the wiring 218. The other of the source and the drain of the transistor 204 is electrically connected to a wiring 219. The other of the source and drain of the transistor 205 is connected to a reference power supply line such as a GND line. The other of the source and the drain of the transistor 206 is electrically connected to the wiring 21. The other of the source and drain of the transistor 207 is electrically connected to GND. The gate of the transistor 203 is electrically connected to a reference power supply line such as a wiring. The gate of the transistor 205 is electrically connected to a wiring 215. The gate of the transistor 206 is electrically connected to a wiring 214.

[0090] The wirings 218 and 219 can function as power supply lines. can function as a wiring for supplying a reset potential (Vr) for readout. The wiring 219 can function as a high-potential power supply line. The wiring 216 can function as a signal line that controls the conduction of each transistor. 212 is an output line, which can be electrically connected to, for example, the circuit 301 shown in FIG. .

[0091] The transistor 203 has a function of resetting the potential of the node C to the potential of the wiring 218. The transistors 204 and 205 function as a source follower circuit. The transistor 206 can have a function of controlling the readout. The circuit 240 functions as a correlated double sampling circuit (CDS circuit), It is also possible to replace it with a circuit having another configuration that has the function.

[0092] <Operation> Next, the operation of the imaging device according to one embodiment of the present invention will be described. 00, the data (reference data) when there is no difference between the outputs of the circuits 10a and 10b is Next, in each of the circuits 10a and 10b, image data is obtained by photoelectric conversion. The data is acquired, and the difference data is acquired.

[0093] Next, the current flowing from the circuit 230 to the circuit 240 based on the reference data and the difference data is calculated. When weights are assigned to the voltage-converted data, the reference data, and the difference data, the circuit 230 The current flowing through the circuit 240 is converted into voltage data, and the differential potential between the data and the voltage data is extracted by the circuit 240.

[0094] The differential potential corresponds to data obtained by removing various offset components from the current flowing through the circuit 220. The current expressed as the product of the difference data and the weighting coefficient is converted into voltage data. That is, the product of the difference data and the weighting coefficient can be extracted.

[0095] To explain the overall flow of extracting the product of the differential data and the weighting coefficient, The operation of 100 is omitted, and the node P1 receives the differential data of the circuit 10a and the circuit 10b. The data potential X corresponding to (the difference between the data obtained by photoelectric conversion) is stored, and the node P 2, the data potential ( The explanation will be given assuming that the reference data, ideally 0, is stored in the pixel 100. The operation will be described later.

[0096] In the pixel block 200, the off-state potentials other than the product of the differential data (potential X) and the weighting coefficient (potential W) are The set components can be removed and the target WX can be extracted. The flow of WX extraction when using the circuit is as follows.

[0097] First, in the circuit 240, the transistor 203 is turned on, and a line is connected from the wiring 218 to the node A potential Vr is written to C. Here, the potential Vr is the reset potential used for the read operation. .

[0098] At this time, the differential data (potential X) is written to the node P1 of the circuit 30 of the pixel 100. Also, it is assumed that reference data 0 is written in node P2. In addition, the weighting coefficient written from the wiring 128 is set to 0.

[0099] At this time, the total current flowing from the circuit 230 to the transistor 133 of each pixel 100 is k Σ(XV th ) 2 In addition, the circuit 230 outputs a signal to the transistor 143 of each pixel 100. The total current flowing is kΣ(0-V th ) 2 where k is a constant, V th Each is the threshold voltage of each transistor.

[0100] In the circuit 230, the total current flowing through the transistor 223 is IC, the total current flowing through the transistor 25 The sum of the currents flowing through transistors 224 and 254 is ICFEF. The current flowing through the capacitor is defined as ICM (see Figure 5A).

[0101] In this case, ICREF0 (ICREF when weight is 0) = ICM0 + kΣ(0-V th ) 2 Therefore, ICM0=ICREF0-kΣ(0-V th ) 2 This becomes:

[0102] Here, the current IR0 (IR when the weight is 0) flowing through the transistor 207 of the circuit 240 is , IR0=IC-ICM0-kΣ(XV th ) 2 That is, IR0 = IC-I CREF0+kΣ(0-V th ) 2 -kΣ(XV th ) 2 This becomes:

[0103] Then, the transistor 203 of the circuit 240 is turned off, and the potential Vr is maintained at the node C. do.

[0104] Next, a potential corresponding to the weighting coefficient (W) is applied to the wiring 128, and the nodes P1 and P2 are connected by capacitive coupling. A weighting factor (W) is assigned to code P2.

[0105] At this time, the total current flowing from the circuit 230 to the transistor 133 of each pixel 100 is k Σ(X+WV th ) 2 In addition, the transistor 14 of each pixel 100 is connected to the circuit 230. The total current flowing through 3 is kΣ(WV th ) 2 This becomes:

[0106] Therefore, the current IR flowing through the transistor 207 of the circuit 240 is IR=IC-ICM -kΣ(X+WV th ) 2 That is, IR=IC-ICREF+kΣ(WV th ) 2 -kΣ(X+WV th ) 2 This becomes:

[0107] Here, the difference between IR0 and IR is IR0-IR=kΣ(Vth 2 -(X-Vth) 2 -(W-Vth) 2 +(W+X-Vth) 2 )=kΣ(2WX). The offset component is removed and the term consisting of WX can be extracted.

[0108] The difference can be extracted by the circuit 240. IR0 is initially set as the potential Vr of the node C. When node C is floating, the potential of the wiring 151 is Since the state changes to the state of the weighting coefficient W, the difference Y of the potential (the difference between IR0 and IR) ) is added to node C by the capacitive coupling of capacitor 202. Here, node C is V r+Y, and if we consider the potential Vr=0, Y is the potential obtained by converting the difference between IR0 and IR into a voltage. That is, WX can be extracted.

[0109] Next, the operation of the pixel 100 and the pixel block 2 will be described according to the timing chart shown in FIG. The operation of the pixel 100 will be described below. The pixel 100 described here has the configuration shown in FIG. In addition, it is assumed that a predetermined potential is supplied to the power supply line, etc.

[0110] <Operation of pixel 100> At time T1, the potential of the wiring 116 is set to "H", the potential of the wiring 117 is set to "H", and the potential of the wiring 121 is set to "H". is "H", the potential of the wiring 122 is "H", and the potential of the wiring 123 is "L". In the circuit 10b, the transistors 102 and 103 are turned on, and the node The potential of FDa and the potential of the node FDb become the reset potential (the potential of the wiring 115).

[0111] At time T2, the potential of the wiring 116 is set to "L", the potential of the wiring 117 is set to "L", and the potential of the wiring 121 is set to "L". is "L", the potential of the wiring 122 is "L", and the potential of the wiring 123 is "L". The transistor 102, the transistor 103, and the transistor 104 are turned off, and the nodes FDa and A reset potential is held at node FDb and node FDb. The storage operation begins.

[0112] At time T3, the potential of the wiring 116 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "H". When the voltage is set to "H", the transistor 102 becomes conductive, and the voltage stored in the photoelectric conversion device 101 The electric charge is transferred to the node FDa and the node FDb. " and the potentials of the nodes FDa and FDb are maintained.

[0113] Furthermore, the transistor 104b and the transistor 107 are turned on, and the potential of the node FDb rises to the 20 (the gate of transistor 105a) and the second input terminal (the gate of transistor 105b). The output of the input terminal 105 is input to the gate of register 105b.

[0114] At this time, the output terminal (node ​​N) of the circuit 20 receives the data input to the first input terminal and The data potential amplified according to the difference between the data input to the second input terminal is output. Here, the data potential output to the output terminal (node ​​N) of the circuit 20 is called reference data. The reference data is the data input to the first input terminal and the data input to the second input terminal. This is the data that is output when there is no difference between the input data and the output data.

[0115] When the configuration of FIG. 4B is used for the circuit 20, the nodes FDa and FDb are reset. The reference data can be output when the reference potential is set to the reference potential.

[0116] At time T4, when the potential of the wiring 126 is set to “H”, the output voltage of the circuit 20 is applied to the node P2 of the circuit 30. The potential of the input terminal (node ​​N) is written. After that, the potential of the wiring 126 is set to "L" and the The potential of the line 127 is set to "H" before time T4. The potential of the other electrodes of the capacitors 135 and 145 is set to the potential of the wiring 128 (for example, 0). .

[0117] At time T5, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "H". When the level is set to "L", the transistor 104a is turned on and the transistor 107 is turned off. The potential of the node FDa is written to the first input terminal of the circuit 20. The potential of the node FDb is written to the second input terminal.

[0118] Therefore, the output terminal (node ​​N) of the circuit 20 has the difference between the node FDa and the node FDb. The data potential amplified according to the time is output. ) is the image data acquired by the circuit 10a and the data potential acquired by the circuit 10b. This is a potential amplified according to the difference in image data, and can be called differential data. , image data, or imaging data.

[0119] At time T6, when the potential of the wiring 125 is set to “H”, the output voltage of the circuit 20 is applied to the node P1 of the circuit 30. The potential of the input terminal (node ​​N) is written. After that, the potential of the wiring 125 is set to "L" and the The potential of node P1 is maintained.

[0120] At time T7, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 127 is set to "L". When the transistor 104, the transistor 134, and the transistor 144 are turned off, Conduction occurs, and the series of operations of the circuit 10a, the circuit 10b, and the circuit 20 ends.

[0121] <Operations of Circuit 220 and Circuit 230> At time T7, when the potential of the wiring 213 is set to “H”, the transistor The gates of transistors 222 and 252 are supplied with appropriate bias, turning on transistor 222. A current IC flows through 23, and a current ICREF flows through transistor 253 (see FIG. 5A). Then, the potential of the wiring 213 is set to "L".

[0122] where ICREF is the current through transistor 254 (ICM) and the transistor The current IC flows through the transistor 224. The current (ICM) flowing through the transistor 133 of the circuit 30 and the current flowing through the transistor 134 of the circuit 240 are This is the sum of the current flowing through the resistor 207.

[0123] In addition, when the potential of the wiring 151 is determined in the above state, the potential of the wiring 216 is set to "H". , the potential "Vr" of the wiring 218 is written to the node C. Then, the potential of the wiring 216 is set to "L". Then, node C is left floating and held at potential "Vr".

[0124] At time T8, the potential of the wiring 127 is set to “H” to turn on the transistors 134 and 144. When a potential W corresponding to the weighting coefficient is supplied to the wiring 128, the nodes P1 and P The potential W is applied to the potential held at 2 by capacitive coupling. Since the state of the weighting coefficient W changes from the state of the weighting coefficient W, the current flows through the transistor 207 of the circuit 230. The current changes.

[0125] At this time, the potential change "Y" of the wiring 151 is applied to the node C by the capacitive coupling of the capacitor 202. Here, the potential of node C becomes "Vr+Y", and the potential "Vr" can be considered as 0. For example, the potential of the node C is a potential “Y” obtained by converting the difference in the current flowing through the transistor 207 into a voltage. That is, WX can be extracted according to the current equation described above.

[0126] At time T9, when the potential of the wiring 214 is set to "H" and an appropriate bias is applied to the wiring 215, The circuit 240 outputs a signal potential corresponding to WX to the wiring 212 by a source follower operation. This can be done.

[0127] At time T10, the potential of the wiring 127 is set to "L", the potential of the wiring 213 is set to "L", and the potential of the wiring 214 is set to "L". The potential of the line 215 is set to "L", and the read operation is completed.

[0128] The WX output from the circuit 240 through the above operation can be input to the circuit 301. .

[0129] In the above example, data is written simultaneously to node P1 and node P2. The example shows how to extract data according to the time difference between the data of node P1 and node P2. For example, if the first frame of data is written to node P1 and the second frame is written to node P2, By writing the data of the frame to node P2, information including motion parallax can be extracted. Depth (distance) information can be obtained from motion parallax, making it possible to create a 3D image. Cut.

[0130] <Circuits 301, 302> 7A is a diagram illustrating circuits 301 and 302 connected to circuit 240. The data of the product-sum operation results output from 240 are input sequentially to circuit 301. The circuit 301 may have various computational functions. Alternatively, the functions of the circuit 301 may be implemented by software processing. It may be replaced by theory.

[0131] For example, the circuit 301 may include a circuit for calculating an activation function. For example, a comparator circuit can be used. The result of comparing the data with the set threshold is output as binary data. , the pixel block 200 and the circuit 301 are used as elements of a neural network. It can work.

[0132] The circuit 301 may also have an A / D converter. When outputting data to the outside, the analog data is converted to digital data by the circuit 301. For example, the circuit 10a and the circuit 10b shown in FIG. 4A can be connected via the wiring OUT. The circuit 301 can be electrically connected to the circuit 301 through the above.

[0133] The data output by the pixel block 200 corresponds to multi-bit image data. If the path 301 can convert the image data into binary data, it can be said that the image data is compressed.

[0134] The data output from the circuit 301 is sequentially input to the circuit 302. The circuit 302 is, for example, For example, the configuration may include a latch circuit and a shift register. This allows parallel-to-serial conversion to be performed, and data input in parallel is transmitted via the wiring 311 The connection destination of the wiring 311 is not limited. For example, it can be connected to a neural network, a storage device, a communication device, and the like.

[0135] Also, as shown in FIG. 7B, the circuit 302 may include a neural network. The neural network has memory cells arranged in a matrix, and each memory The cell holds a weighting factor. The data output from the circuit 301 is stored in the memory cell 32. 0, and a multiplication and accumulation operation can be performed. The numbers are just examples and are not limiting.

[0136] The neural network shown in FIG. 7B is composed of memory cells 320 and and reference memory cell 325, circuit 330, circuit 350, circuit 360, and circuit 370. It has.

[0137] FIG. 8 shows an example of a memory cell 320 and a reference memory cell 325. 5 are arranged in any one row. The memory cells 320 and the reference memory cells 325 are similar The transistor 161, the transistor 162, and the capacitor 163 are included. do.

[0138] The source or drain of the transistor 161 is connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, either the source or the drain of the transistor 161 is electrically connected. The point where the gate of the transistor 162 and one electrode of the capacitor 163 are connected is called a node NM. do.

[0139] The gate of the transistor 161 is electrically connected to the wiring WL. The other electrode is electrically connected to the wiring RW. One of the terminals is electrically connected to a reference potential wiring such as a GND wiring.

[0140] In the memory cell 320, the other of the source and drain of the transistor 161 is connected to a wiring The other of the source and drain of the transistor 162 is electrically connected to the wiring WD. It is electrically connected to BL.

[0141] In the reference memory cell 325, the other of the source or drain of the transistor 161 is The source or drain of the transistor 162 is electrically connected to the wiring WDref. The other end is electrically connected to the wiring BLref.

[0142] The wiring WL is electrically connected to the circuit 330. The circuit 330 includes a decoder or a shift register. A resistor or the like can be used.

[0143] The wiring RW is electrically connected to the circuit 301. Each memory cell receives an output from the circuit 301. The binary data thus obtained is written. Note that a shift register is provided between the circuit 301 and each memory cell. It may also have a sequential circuit such as a register.

[0144] The wiring WD and the wiring WDref are electrically connected to the circuit 350. The circuit 350 includes: A decoder or a shift register can be used. The circuit 350 may include a converter and an SRAM. It is possible to output the weighting coefficients.

[0145] The wiring BL and the wiring BLref are electrically connected to the circuit 360. The circuit 360 can be configured in the same way as the circuit 240. A signal with the red component removed can be obtained.

[0146] The circuit 360 is electrically connected to the circuit 370. The circuit 370 can also be referred to as an activation function circuit. The activation function circuit converts the signal input from the circuit 360 into a predefined It has the function of performing calculations to convert according to activation functions. For example, activation functions are For example, sigmoid function, tanh function, softmax function, ReLU function, threshold function The signal converted by the activation function circuit is used as output data. and output to the outside.

[0147] As shown in Figure 9A, the neural network NN consists of an input layer IL, an output layer OL, and a hidden layer The input layer IL, output layer OL, and hidden layer HL are Each layer has one or more neurons (units). There may be one or more hidden layers HL. The network can also be called a DNN (Deep Neural Network). Learning using a neural network can also be called deep learning.

[0148] Input data is input to each neuron in the input layer IL. The output signal of the neurons in the previous or next layer is input to each neuron in the output layer OL. The output signal of the neuron in the previous layer is input to each neuron. It can be connected to all neurons (fully connected), or it can be connected to only some neurons ( Good too.

[0149] Figure 9B shows an example of a neuron operation. Here, we consider two neurons, N and N. The figure shows two neurons in the front layer that output signals to the neuron N. The output of the neuron N is input to the input. In this case, the multiplication result of output x1 and weight w1 (x1w1) and the multiplication result of output x2 and weight w2 After the sum x1w1+x2w2 of (x2w2) is calculated, a bias b is added if necessary. Then, the value a is calculated by the activation function h. The neuron N outputs an output signal y=ah.

[0150] In this way, the operation of a neuron involves adding the product of the output of the previous layer neuron and the weight. This multiplication and addition operation is called multiplication and addition (x1w1+x2w2 above). This may be done on software using a program, or on hardware. Good too.

[0151] In one embodiment of the present invention, a product-sum operation is performed using an analog circuit as hardware. When using analog circuits for the calculation circuit, it is necessary to reduce the circuit scale of the product-sum calculation circuit or to transfer the circuit to memory. This reduces the number of accesses, thereby improving processing speed and reducing power consumption.

[0152] The multiply-accumulate circuit preferably includes an OS transistor. Since the off-state current of the transistor is extremely small, it can be used as a transistor that constitutes the analog memory of the product-sum operation circuit. It is also possible to use both Si transistors and OS transistors for multiply-and-add operations. A calculation circuit may be configured.

[0153] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0154] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0155] <Structure example> FIG. 10A is a diagram showing an example of the structure of a pixel of an imaging device, and shows the stack of layers 561 and 563. It may be a layered structure.

[0156] Layer 561 includes photovoltaic device 101. Photovoltaic device 101 is shown in FIG. As shown, it may have layers 565a and 565b. It can also be called an area.

[0157] The photoelectric conversion device 101 shown in FIG. 11A is a pn junction photodiode, for example, The layer 565a may be made of a p-type semiconductor, and the layer 565b may be made of an n-type semiconductor. Alternatively, an n-type semiconductor may be used for the layer 65a and a p-type semiconductor for the layer 565b.

[0158] The pn junction photodiode is typically formed using single crystal silicon. Photodiodes that use single-crystal silicon as a photoelectric conversion layer can detect light ranging from ultraviolet to near-infrared. It has a relatively wide spectral sensitivity characteristic, and when combined with the optical conversion layer described later, it can It can detect long wavelength light.

[0159] In addition, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode. Examples of the compound semiconductor include gallium-arsenic-phosphide (GaAsP), Gallium phosphide (GaP), indium gallium arsenide (InGaAs) , lead-sulfur compounds (PbS), lead-selenium compounds (PbSe), indium-arsenic compounds (InAs), indium-antimonide (InSb), mercury-cadmium-tellurium Compounds such as HgCdTe can be used.

[0160] Compound semiconductors include group 13 elements (aluminum, gallium, indium, etc.) and Compound semiconductors containing group 15 elements (nitrogen, phosphorus, arsenic, antimony, etc.) semiconductors), or group 12 elements (magnesium, zinc, cadmium, mercury, etc.) ) and compound semiconductors containing group 16 elements (oxygen, sulfur, selenium, tellurium, etc.) (2-6 It is preferable that the semiconductor is a group compound semiconductor.

[0161] Compound semiconductors change their band gap depending on the combination of constituent elements and their atomic ratio. This allows the production of photosensitive materials with sensitivity to a wide range of wavelengths from ultraviolet to infrared. A diode can be formed.

[0162] The wavelength of ultraviolet light is around 0.01 μm to around 0.38 μm, and the wavelength of visible light is around 0. The wavelength of near infrared light is from about 0.75 μm to about 2.5 μm. The wavelength of mid-infrared light is around 2.5 μm to 4 μm, and the wavelength of far-infrared light is around 4 μm. It can be generally defined as being in the vicinity of 1000 μm to 1000 μm.

[0163] For example, to form a photodiode that is sensitive to light ranging from ultraviolet light to visible light, GaP can be used for the electric conversion layer. Also, it has high photosensitivity from ultraviolet light to near-infrared light. To form a photodiode having a photoelectric conversion layer, the above-mentioned silicon or GaAs In addition, a photosensitive material having a photosensitivity from visible light to mid-infrared light can be used. To form a photodiode, InGaAs or the like can be used for the photoelectric conversion layer. In addition, to form a photodiode that is sensitive to light from near infrared light to mid-infrared light, PbS or InAs can be used for the electric conversion layer. To form a photodiode that is sensitive to light, the photoelectric conversion layer is made of PbSe and I nSb or HgCdTe or the like can be used.

[0164] Photodiodes using the above compound semiconductors can be used with pin junctions as well as pn junctions. The pn junction and pin junction are not limited to a homojunction structure, but may be a heterojunction. It may be a composite structure.

[0165] For example, in a heterojunction, a first compound semiconductor is used in one layer of a pn junction structure, and the other The layer can be made of a second compound semiconductor different from the first compound semiconductor. The first compound semiconductor is used in one or two layers of the in-junction structure, and the other layers are A second compound semiconductor different from the first compound semiconductor can be used. Either the compound semiconductor or the second compound semiconductor may be a semiconductor of an element such as silicon. stomach.

[0166] The photoelectric conversion layer of the photodiode may be formed using a different material for each pixel. By using this configuration, it is possible to detect ultraviolet light, visible light, and infrared light. An imaging device having two or three types of pixels, such as a pixel having a It is possible.

[0167] As shown in FIG. 11B, the photoelectric conversion device 101 included in the layer 561 is The layer 566b, the layer 566c, and the layer 566d may be stacked. The photoelectric conversion device 101 is an example of an avalanche photodiode, and includes a layer 566a, a layer 566b, and a layer 566c. 66d corresponds to an electrode, and layers 566b and 566c correspond to a photoelectric conversion portion.

[0168] The layer 566a is preferably a low resistance metal layer, such as aluminum or titanium. It is possible to use tungsten, tantalum, silver or a laminate thereof.

[0169] The layer 566d is preferably formed using a conductive layer that has high transparency to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide oxide, indium-gallium-zinc oxide, or graphene can be used. The layer 566d may be omitted.

[0170] The layers 566b and 566c of the photoelectric conversion section are pn junctions in which a selenium-based material is used as the photoelectric conversion layer. The layer 566b is made of selenium, which is a p-type semiconductor. For the layer 566c, an n-type semiconductor such as gallium oxide can be used. preferable.

[0171] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, the incident light is multiplied by using avalanche multiplication. The electron amplification relative to the amount of light can be increased. In addition, selenium-based materials have a light absorption coefficient This has the advantage in terms of production, as it allows the photoelectric conversion layer to be made into a thin film. The thin film can be formed by vacuum deposition or sputtering.

[0172] Selenium-based materials include crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium. These have photosensitivity from ultraviolet light to visible light. Indium and selenium compounds (CIS) or copper, indium, gallium, and selenium Compounds such as CIGS can be used. These emit light from ultraviolet to near-infrared. It has light sensitivity.

[0173] The n-type semiconductor is formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or These materials can be used for hole injection. It also functions as a blocking layer and can reduce dark current.

[0174] As shown in FIG. 11C, the photoelectric conversion device 101 included in the layer 561 is Alternatively, the layer 567b, the layer 567c, the layer 567d, and the layer 567e may be stacked. The photovoltaic device 101 shown in FIG. 11C is an example of an organic photoconductive film, and the layer 567a is a bottom electrode. The layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d are light-transmitting layers. It corresponds to the electric conversion unit.

[0175] One of the layers 567b and 567d of the photoelectric conversion portion is a hole transport layer, and the other is an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0176] The hole transport layer may be made of, for example, molybdenum oxide. For example, C 60 , C 70 or derivatives thereof. It is possible.

[0177] The photoelectric conversion layer is a mixed layer of n-type organic semiconductor and p-type organic semiconductor (bulk heterojunction). There are various types of organic semiconductors, and they can be photosensitive to the desired wavelength. A material having such a property may be selected for the photoelectric conversion layer.

[0178] The layer 563 shown in FIG. 10A may be, for example, a silicon substrate. The capacitor substrate has a silicon transistor and the like. The silicon transistor is used to form the pixel circuit. Other circuits include circuits that drive the pixel circuits, image signal readout circuits, image processing circuits, neural networks, etc. It can be used to form networks, communication circuits, etc. Random Access Memory (RDMA) and other memory circuits, Processing Unit), MCU (Micro Controller U) In this embodiment, the above circuits except for the pixel circuit are This is called a functional circuit.

[0179] For example, the pixel circuit (pixel 100) and the functional circuit (circuit 220, 301, 302, 303, 304, 305, etc.) Part or all of the layer 563 may be provided.

[0180] Alternatively, layer 563 may be a stack of multiple layers as shown in Figure 10B. Although three layers, 563a, 563b, and 563c, are shown as an example, two layers may be used. Alternatively, layer 563 may be a stack of four or more layers. These layers may be formed by, for example, a lamination process. By using such a configuration, pixel circuits and functional circuits can be stacked on multiple layers. The pixel circuits and functional circuits can be stacked on top of each other, making it possible to realize a compact, high-performance image capture device. An imaging device can be fabricated.

[0181] Also, the pixel has a stacked structure of layers 561, 562, and 563 as shown in FIG. 10C. It may be possible.

[0182] Layer 562 can include OS transistors. Alternatively, the layer 563 may be formed of a Si transistor and the layer 56 One or more functional circuits may be formed using the OS transistors included in the semiconductor device 2. The layer 563 is a support substrate such as a glass substrate, and the layer 562 is an OS transistor that functions as a functional circuit. A path may be formed.

[0183] For example, a normally-off CPU (" It is possible to realize a non-off-CPU (also called a "Noff-CPU"). Normally-off type, which is in a non-conducting state (also called an off state) even when the gate voltage is 0V It is an integrated circuit that includes transistors.

[0184] The Noff-CPU stops supplying power to circuits that are not required to operate, The circuit can be put into standby mode. The power supply is stopped and the circuit in standby mode No power is consumed. Therefore, the Noff-CPU can minimize power consumption. In addition, the Noff-CPU maintains the necessary information for operation, such as the settings, even if the power supply is cut off. When the device returns from standby mode, the power supply to the circuit is restarted. There is no need to rewrite the settings etc. That is, high-speed In this way, the Noff-CPU can recover without significantly slowing down its operation speed. Power consumption can be reduced.

[0185] Alternatively, layer 562 may be a stack of multiple layers, as shown in Figure 10D. Although two layers, 562a and 563b, are shown as an example, three or more layers may be laminated. These layers can be formed, for example, stacked on top of layer 563. Alternatively, a layer formed on the layer 561 may be bonded to a layer formed on the layer 3.

[0186] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0187] Since the energy gap of the semiconductor layer of an OS transistor is large, the current is several yA / μm (channel The OS transistor exhibits extremely low off-state current characteristics (current value per 1 μm of transistor width). The stan- dard is free from impact ionization, avalanche breakdown, and short channel effects. These features differ from those of Si transistors, allowing for the creation of highly reliable circuits with high voltage resistance. In addition, the electrical characteristics caused by the non-uniformity of the crystallinity, which is a problem in Si transistors, can be improved. OS transistors are also less likely to experience variations in performance.

[0188] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In containing one or more metals selected from the group consisting of tin, neodymium, and hafnium The In-M-Zn oxide can be used as a film. Typically, it can be formed by sputtering. Alternatively, the insulating layer may be formed by a layer deposition method.

[0189] Sputtering tube used to form In-M-Zn oxide by sputtering method The atomic ratio of the metal elements in the get preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in the sputtering target is In:M:Zn=1:1:1. , In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4 :2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M: Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferred. The atomic ratio of each layer is the atomic ratio of the metal elements contained in the sputtering target. This includes a variation of plus or minus 40% in the ratio.

[0190] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or This oxide semiconductor has a low density of defect states and is stable. It can be said that this oxide semiconductor has stable characteristics.

[0191] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be controlled. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0192] In the oxide semiconductor that constitutes the semiconductor layer, silicon or carbon, which is one of the group 14 elements, is If silicon is included, oxygen vacancies increase, causing the semiconductor layer to become n-type. The silicon or carbon concentration (obtained by secondary ion mass spectrometry) was 2 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0193] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0194] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0195] In addition, if hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the oxide that bonds with the metal atoms Since the oxygen reacts with oxygen to form water, oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally on. Furthermore, defects in which hydrogen has entered the oxygen vacancies act as donors, In addition, some of the hydrogen atoms bond with the metal atoms, resulting in the generation of carrier electrons. It may combine with hydrogen to generate electrons, which are carriers. A transistor including an oxide semiconductor having such a structure tends to be normally on.

[0196] A defect in which hydrogen is inserted into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the acid As a parameter of the compound semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "donor concentration."

[0197] Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0198] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0199] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0200] The semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC region, or a crystalline structure region. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0201] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This article explains the structure of the .NET composite OS.

[0202] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0203] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0204] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0205] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0206] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0207] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0208] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0209] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0210] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0211] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0212] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0213] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction measurement, It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0214] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphor) is formed. The electron diffraction pattern is Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It can be seen that it has a nano-crystal structure.

[0215] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2, or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0216] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0217] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0218] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X It is a region with high insulation compared to the region where 1 is the main component. That is, GaO X3 etc. By distributing the region where it is the main component in the oxide semiconductor, the leakage current can be suppressed, and a good etching operation can be realized.

[0219] Therefore, when CAC-OS is used in a semiconductor device, the insulation X3 caused by etc. such as GaO and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily to achieve a high on-current (I on ) and a high field-effect mobility (μ). This can be achieved.

[0220] In addition, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0221] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as required. This can be achieved.

[0222] FIG. 12 is an example of a cross-sectional view of a laminate having layers 560, 561, and layer 563, and having a bonding surface between layer 563a and layer 56 3b that constitute layer 563.

[0223] <Layer 563b> Layer 563b can have a functional circuit provided on the silicon substrate 611. Here The transistors 105 and 108 included in the circuit 20 are included as part of the functional circuit. and transistor 131.

[0224] The layer 563b includes a silicon substrate 611, insulating layers 612, 613, 614, 616, and 617. , 618 are provided. The insulating layer 612 functions as a protective film. The insulating layer 61 functions as an interlayer insulating film and a planarizing film. The conductive layer 619 functions as a bonding layer. It is electrically connected to the gate of the resistor 105 .

[0225] Examples of the protective film include a silicon nitride film, a silicon oxide film, and an aluminum oxide film. As the interlayer insulating film and the planarizing film, for example, a silicon oxide film can be used. Inorganic insulating films such as those made of acrylic resins and polyimide resins can be used. The dielectric layer of the capacitor may be a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The bonding layer will be described later.

[0226] It can also be used as wiring, electrodes, and plugs for electrical connections between devices. Conductors that can be used include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Nesium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from the group consisting of thium, lanthanum, etc., or alloys containing the above-mentioned metal elements Alternatively, an alloy or the like combining the above-mentioned metal elements may be appropriately selected and used. It is not limited to a single layer, but may be a plurality of layers made of different materials.

[0227] <Layer 563a> Layer 563a includes elements of pixel 100 and may also include elements of functional circuitry. Here, a transistor 102 is shown as part of the elements of the pixel 100. The transistor 104 included in the circuit 20 is shown as an element of the functional circuit.

[0228] The layer 563a includes a silicon substrate 632, insulating layers 631, 633, 634, 635, and 637. , 638 are provided. Conductive layers 636, 639 are also provided.

[0229] The insulating layer 631 and the conductive layer 639 function as bonding layers. , 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 638 serves as a protective film. The insulating layer 638 has an insulating function. The insulating layer 638 can be formed of the same material as the other insulating layers. The insulating layer 638 may be formed using the same material as the insulating layer 631.

[0230] The conductive layer 639 is connected to the other of the source and drain of the transistor 105 and the conductive layer 619 The conductive layer 636 is electrically connected to the wiring 114 (see FIG. 3). will be done.

[0231] The Si transistor shown in FIG. 12 has a channel in a silicon substrate (silicon substrates 611 and 632). The cross section in the channel width direction (shown in layer 563a in FIG. 12) is a fin type having a hole forming region. The cross section of the Si transistor is shown in FIG. 13A. It may also be of a planar type.

[0232] Alternatively, as shown in FIG. 13C, a transistor having a semiconductor layer 545 of a silicon thin film may be used. The semiconductor layer 545 may be formed on an insulating layer 546 on a silicon substrate 611, for example. The silicon-on-insulator (SOI) It is possible.

[0233] <layer 561> The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 includes the layer 563a. In FIG. 12, the photoelectric conversion device 101 can be formed on the substrate shown in FIG. The photoelectric conversion layer 567a is made of an organic photoconductive film. the cathode, and layer 567e the anode.

[0234] Layer 561 is provided with insulating layers 651, 652, 653, 654 and conductive layer 655. do.

[0235] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. In addition, the insulating layer 654 is provided to cover the edge of the photoelectric conversion device 101, and the layer 567e and the layer 567f are The insulating layer 652 also functions as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0236] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is a transistor included in the layer 563a. The photoelectric conversion device 1 is electrically connected to either the source or the drain of the transistor 102. The layer 567e corresponding to the anode of O1 is connected to the conductive layer 655 via the conductive layer 655. The electrode layer 636 is electrically connected to the electrode layer 636 .

[0237] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and and a microlens array 673.

[0238] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used. A dielectric film having a function as an anti-reflection film may be laminated.

[0239] When the photoelectric conversion device 101 is sensitive to visible light, a color filter is applied to the optical conversion layer 672. The color filters are red, green, blue, yellow, and C. A color image can be obtained by assigning colors such as C (cyan) and M (magenta) to each pixel. For example, as shown in the perspective view (including the cross section) of FIG. 19A, Color filter 672R (red), color filter 672G (green), color filter 672B (blue) Each of these can be assigned to a different pixel.

[0240] In addition, in a suitable combination of the photoelectric conversion device 101 and the optical conversion layer 672, If a wavelength cut filter is used in the conversion layer 672, images in various wavelength regions can be obtained. It may be an imaging device.

[0241] For example, if an infrared filter that blocks light having wavelengths shorter than visible light is used for the optical conversion layer 672, The optical conversion layer 672 can be used as an infrared imaging device. If a filter that blocks infrared rays is used, it can be used as a far-infrared imaging device. If an ultraviolet filter that blocks light with wavelengths longer than visible light is used in 72, it can be used as an ultraviolet imaging device. It is possible.

[0242] It is also possible to arrange a plurality of different optical conversion layers in one imaging device. For example, in FIG. As shown, color filter 672R (red), color filter 672G (green), The blue filter 672B and the infrared filter 672IR can be assigned to different pixels. In this configuration, visible light images and infrared light images can be acquired simultaneously. .

[0243] Alternatively, as shown in FIG. 19C, a color filter 672R (red), a color filter 672 G (green), color filter 672B (blue), ultraviolet filter 672UV In this configuration, visible light images and ultraviolet light images can be captured simultaneously. You can gain.

[0244] In addition, if a scintillator is used for the optical conversion layer 672, the radiation used in an X-ray imaging device, etc. It can be used as an imaging device to obtain an image that visualizes the intensity of radiation such as X-rays that has passed through the subject. When radiation strikes the scintillator, it emits visible or ultraviolet light due to the photoluminescence phenomenon. The light is converted into light (fluorescence) such as external light. The light is then detected by the photoelectric conversion device 101. Image data is acquired by installing an imaging device having this configuration in a radiation detector or the like. It may be used.

[0245] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. It includes materials that absorb and emit visible or ultraviolet light. For example, Gd2O2S:Tb, Gd2O 2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, Ba F2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0246] By taking images using infrared or ultraviolet light, it is possible to perform inspection, security, and sensor functions. For example, by taking an image using infrared light, Non-destructive testing of objects, sorting of agricultural products (such as sugar content meter functions), vein authentication, medical testing, etc. In addition, by taking an image using ultraviolet light, it is possible to detect the ultraviolet light emitted from the light source or flame. This allows for the management of light sources, heat sources, production equipment, etc.

[0247] A microlens array 673 is provided on the optical conversion layer 672. The light passing through each lens of the lens 673 passes through the optical conversion layer 672 directly below, and By providing the microlens array 673, Since the collected light can be incident on the photoelectric conversion device 101, photoelectric conversion can be performed efficiently. The microlens array 673 has high transparency to light of a target wavelength. It is preferable to form the substrate from a thin resin or glass.

[0248] <Laminating> Next, the bonding of the layer 563b and the layer 563a will be described.

[0249] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 is an insulating The insulating layer 618 and the conductive layer 619 have a buried region. They are flattened to match the height.

[0250] The layer 563a includes an insulating layer 631 and a conductive layer 639. The conductive layer 639 is an insulating The insulating layer 631 and the conductive layer 639 have a buried region. They are flattened to match the height.

[0251] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as the main component. In addition, it is preferable that the insulating layer 618 and the insulating layer 631 are made of the same component. I wish.

[0252] For example, the conductive layers 619 and 639 may be made of Cu, Al, Sn, Zn, W, Ag, Pt, or A. In view of ease of bonding, Cu, Al, W, or The insulating layers 618 and 631 are made of silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, titanium nitride, etc. can be used.

[0253] That is, the conductive layer 619 and the conductive layer 639 are made of the same metal material as described above. In addition, it is preferable that the insulating layer 618 and the insulating layer 631 are made of the above-described material. It is preferable to use the same insulating material. The bonding can be performed with the boundary of a as the joining position.

[0254] The conductive layer 619 and the conductive layer 639 may have a multilayer structure. The insulating layer 618 and the insulating layer 619 may be made of the same metal material as long as the surface layers (bonding surfaces) are made of the same metal material. 31 may also be a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) are made of the same insulating material. It's fine as long as it's free.

[0255] By this bonding, electrical connection between the conductive layer 619 and the conductive layer 639 can be obtained. Furthermore, it is possible to obtain a connection having mechanical strength between the insulating layer 618 and the insulating layer 631. can be done.

[0256] To bond metal layers together, the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or other methods. The surface activated bonding method is used to bond the cleaned and activated surfaces together. Alternatively, a diffusion bonding method can be used, which uses a combination of temperature and pressure to bond surfaces together. Both of these bond at the atomic level, so they can be used not only electrically but also mechanically. Mechanically excellent bonding can also be obtained.

[0257] In addition, to bond the insulating layers together, after obtaining high flatness by polishing, etc., oxygen plasma etc. The hydrophilic treated surfaces are brought into contact with each other to temporarily bond them together, and then the final bonding is performed by dehydrating them through heat treatment. Aqueous bonding methods can be used. Hydrophilic bonding also occurs at the atomic level, so , and mechanically excellent bonding can be obtained.

[0258] When the layer 563b and the layer 563a are bonded together, an insulating layer and a metal layer are mixed on each bonding surface. Therefore, for example, the surface activated bonding method and the hydrophilic bonding method may be combined.

[0259] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then to a hydrophilic treatment. Alternatively, the surface of the metal layer may be treated with a hard metal such as Au. It is also possible to use an oxidized metal and then subject it to hydrophilic treatment. That's fine.

[0260] By the above-mentioned bonding, the circuit of the layer 563b and the pixel 100 of the layer 563a are The elements can be electrically connected.

[0261] <Modification of laminate structure 1> FIG. 14 shows a modified example of the laminated structure shown in FIG. 12, in which the layer 561 has a photoelectric conversion device 1 The structure of layer 561 and the structure of part of layer 563a are different, and there is also a layer 561 and a layer 563a between them. It has a mating surface.

[0262] The layer 561 includes the photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers. The conductive layers 685 and 686 are provided.

[0263] The photoelectric conversion device 101 is a pn junction photodiode, and the layer corresponding to the p-type region 565b and a layer 565a corresponding to an n-type region. This shows an example in which a photodiode is formed on a silicon substrate. It is a built-in photodiode, and is provided on the surface side (current extraction side) of the layer 565a. The thin p-type region (part of the layer 565b) can suppress dark current and reduce noise. Cut.

[0264] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 664 functions as an interlayer insulating film and a planarizing film. It has the function as.

[0265] The silicon substrate has grooves for separating pixels, and an insulating layer 665 is formed on the top surface of the silicon substrate and The insulating layer 665 is provided in the groove. This can prevent carriers generated in the insulating layer from flowing to adjacent pixels. The insulating layer 665 also has a function of suppressing the intrusion of stray light. In addition, an anti-reflection film is formed between the upper surface of the silicon substrate and the insulating layer 665. may be provided.

[0266] The insulating layer 664 is formed by LOCOS (LOCal Oxidation of Silicon) Alternatively, the STI (Shallow Trench Ionization) method can be used. The insulating layer 665 may be formed by, for example, an acid isolation method. Inorganic insulating films such as silicon dioxide and silicon nitride, and organic insulating films such as polyimide resin and acrylic resin An insulating film can be used. The insulating layer 665 may have a multi-layer structure. A space may be provided in a portion of the edge layer 665. The space may be filled with a gas such as air or an inert gas. The space may be in a reduced pressure state.

[0267] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions buried in the insulating layer 661. In addition, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are aligned to the same height. It is flattened.

[0268] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. a conductive layer 683 electrically connected to one of the source and drain of the transistor 102; A conductive layer 684 is formed that is electrically connected to the conductive layer 636 .

[0269] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. 83, 684 have regions buried in the insulating layer 638. Also, the insulating layer 638 and the conductive The surfaces of the conductive layers 683 and 684 are flattened so that they are at the same height.

[0270] Here, the conductive layers 683, 684, 685, and 686 are the same as the conductive layers 619 and 639 described above. The insulating layers 638 and 661 are the same as the insulating layers 618 and 631. It is the same lamination layer as

[0271] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, the photoelectric conversion device 10 The first layer 565a (n-type region, corresponding to the cathode) and the source or drain of the transistor 102 In addition, the conductive layer 684 and the conductive layer 686 can be attached to each other. By combining them, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 is formed. The wiring 114 (see FIG. 3) can be electrically connected. By bonding 661, the layer 561 and the layer 563a are electrically and mechanically bonded. This can be done.

[0272] FIG. 15 shows a modified example different from the above, in which the transistor 102 is provided on the layer 561. In this configuration, one of the source and drain of the transistor 102 is The other of the source and drain is directly connected to the electric conversion device 101 and is formed as a node FD. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred. This makes it possible to provide an imaging device with less noise.

[0273] Here, the other of the source and the drain of the transistor 102 included in the layer 561 is a conductive layer 692. The layer 563 is electrically connected to the source or One of the drains is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are This is the same bonding layer as the conductive layers 619 and 639 described above.

[0274] <Laminated structure 2> FIG. 16 shows a laminate having layers 560, 561, 562, and 563 and no bonding surface. 5 is an example of a cross-sectional view. Layer 563 is provided with a Si transistor. Layer 562 is provided with an O The layers 563, 561, and 560 are configured as shown in FIG. 2, so the explanation will be omitted here.

[0275] <layer 562> Layer 562 is formed on layer 563. Layer 562 includes an OS transistor. shows the transistor 102 and the transistor 104. In the cross-sectional view shown in FIG. The electrical connection between them is not shown.

[0276] The layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, and 628. In addition, a conductive layer 627 is provided. The conductive layer 627 is connected to the wiring 114 (see FIG. 3). Electrical connection can be made.

[0277] The insulating layer 621 functions as a blocking layer. , 626, and 628 function as an interlayer insulating film and a planarizing film. , and has a function as a protective film.

[0278] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In Si devices, hydrogen is needed to terminate dangling bonds, Hydrogen near the OS transistor is one of the factors that generate carriers in the oxide semiconductor layer. Therefore, the layer where the Si device is formed and the OS transistor It is preferable that a hydrogen blocking film is provided between the layer on which the transistor is formed and the layer on which the transistor is formed.

[0279] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, or oxide. Gallium, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide Examples of usable materials include hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc. do.

[0280] The other of the source or drain of the transistor 104 is connected to the transistor 10 The conductive layer 627 is electrically connected to the gate of the gate electrode 5. The conductive layer 627 is also electrically connected to the wiring 114 (see FIG. 3A). are electrically connected.

[0281] One of the source and drain of the transistor 102 is a photoelectric conversion device included in the layer 561. The conductive layer 627 is electrically connected to the cathode of the photoelectric conversion layer 561. It is electrically connected to the anode of the device 101 .

[0282] FIG. 17A shows the details of an OS transistor. The OS transistor shown in FIG. An insulating layer is provided over a stack of a semiconductor layer and a conductive layer, and an opening reaching the oxide semiconductor layer is provided. A self-aligned structure in which a source electrode 705 and a drain electrode 706 are formed by It is completed.

[0283] The OS transistor has a channel formation region 708 and a source region 709 formed in the oxide semiconductor layer. 703 and drain region 704, as well as a gate electrode 701 and a gate insulating film 702. In the opening, at least the gate insulating film 702 and the gate An electrode 701 is provided. An oxide semiconductor layer 707 is further provided in the opening. That's fine.

[0284] As shown in FIG. 17B, the OS transistor is formed by forming a semiconductor layer 701 using the gate electrode 701 as a mask. As a self-aligned structure in which a source region 703 and a drain region 704 are formed in Good too.

[0285] Alternatively, as shown in FIG. 17C, the source electrode 705 or the drain electrode 706 and the gate electrode A non-self-aligned top-gate transistor having an area overlapping with the electrode 701. It's okay to have it.

[0286] The OS transistor has a structure having a back gate 735. The back gate 735 may be a transistor channel as shown in FIG. As shown in the cross section in the panel width direction, the front gate and the electric 17D is an example of a cross section of the transistor shown in FIG. 17A taken along line B1-B2. However, the same applies to transistors with other structures. 35 may be configured to be supplied with a fixed potential different from that of the front gate.

[0287] <Modification of laminate structure 2> FIG. 18 shows a modified example of the laminated structure shown in FIG. 17, in which the layer 561 has a photoelectric conversion device 1 The structure of layer 561 and the structure of part of layer 562 are different, and the layer 561 and the layer 562 are bonded together. It has a surface.

[0288] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode. The configuration is the same as that shown in 14.

[0289] In layer 562, insulating layer 648 is formed on insulating layer 628. a conductive layer 688 electrically connected to one of the source and drain of the capacitor 102; A conductive layer 689 is formed that is electrically connected to layer 627 .

[0290] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. 88, 689 have regions buried in the insulating layer 648. Also, the insulating layer 648 and the conductive The surfaces of the conductive layers 683 and 684 are flattened so that they are at the same height.

[0291] Here, the conductive layers 688 and 689 are the same laminating layers as the conductive layers 619 and 639 described above. The insulating layer 648 is a laminated layer similar to the insulating layers 618 and 631 described above. .

[0292] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, the layer of the photoelectric conversion device 565a (n-type region, corresponding to the cathode) and the source or drain of the transistor 102 One of the conductive layers 689 and 686 can be electrically connected. By this, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 114 ( 3) can be electrically connected. By joining the layers 561 and 562a together, electrical and mechanical bonding can be achieved. can.

[0293] When multiple Si devices are stacked, the polishing and bonding processes are required multiple times. Therefore, there are issues such as the large number of processes, the need for dedicated equipment, and low yields, which increases manufacturing costs. The OS transistor is formed by stacking it on a semiconductor substrate on which other devices are formed. This allows the bonding process to be reduced.

[0294] Note that the structure in which the transistor 102 is provided in the layer 561 shown in FIG. 15 is applied to this structure. Good too.

[0295] <Package, Module> FIG. 20A1 is a perspective view showing the appearance of the upper surface side of a package containing an image sensor chip. The package is a package that fixes the image sensor chip 450 (see FIG. 20A3). The substrate 410, the cover glass 420, and the adhesive 430 that bonds the two together are included.

[0296] 20A2 is a perspective view of the bottom surface of the package. It has a BGA (Ball grid array) with rice balls as bumps 440. Not just BGA, but also LGA (Land grid array) or PGA (Pin Grid Array) may also be included.

[0297] FIG. 20A3 shows the package with the cover glass 420 and adhesive 430 partially removed. Electrode pads 460 are formed on a package substrate 410. The electrode pad 460 and the bump 440 are electrically connected via a through hole. The electrode 460 is electrically connected to the image sensor chip 450 by a wire 470. do.

[0298] FIG. 20B1 shows a camera in which an image sensor chip is housed in a lens-integrated package. This is a perspective view of the top surface of the module. 20B3, a package substrate 411 for fixing the lens cover 421, and a lens cover 422. The package substrate 411 and the image sensor chip 451 are also included. Between them is an IC chip 490 ( Figure 20B3 is also provided, and shows the SiP (System in Package) It has the following structure.

[0299] 20B2 is a perspective view of the appearance of the lower surface side of the camera module. The bottom and side surfaces of the package 1 are provided with lands 441 for mounting. The structure is an example only. QFP (Quad flat package) or the BGA mentioned above is provided. Good too.

[0300] FIG. 20B3 shows the module with the lens cover 421 and part of the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 4 61 is electrically connected to the image sensor chip 451 or IC chip 490 by wires 471 are actively connected.

[0301] By housing the image sensor chip in the package of the above type, it is possible to This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible.

[0302] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0303] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines, etc. Specific examples of these electronic devices are shown in Figures 21A to 21F.

[0304] FIG. 21A shows an example of a portable information terminal, which includes a housing 981, a display unit 982, and an operation button 983. , an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The portable information terminal has a touch sensor on the display unit 982. Any operation, such as inputting, can be performed by touching the display 982 with a finger or a stylus. The imaging device of one embodiment of the present invention and its operating method are provided in the portable information terminal. The law can be applied.

[0305] The camera 987 has an imaging device according to one embodiment of the present invention, and the object is captured from the image acquired by the camera 987. Based on the distance information, the camera 987 can acquire the distance information of the body. For example, you can blur the front and back of the main subject. This can be done.

[0306] FIG. 21B shows an information terminal, which includes a housing 911, a display unit 912, a speaker 913, and a camera 919. The display unit 912 has a touch panel function that allows input and output of information. In addition, characters and the like can be recognized from an image acquired by the camera 919, and the corresponding characters can be played back through the speaker 913. The portable data terminal can output the characters as voice. The method of operation can be applied.

[0307] FIG. 21C shows a surveillance camera, which includes a support base 951, a camera unit 952, and a protective cover 953. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling. The present invention relates to the elements for image acquisition in the camera unit. The imaging device and the operation method thereof according to the above embodiment can be applied to a surveillance camera. This is a common name and does not limit its use. For example, it can be used as a surveillance camera. The device is also called a camera or video camera.

[0308] FIG. 21D shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, and an operation unit. It has a key 974, a lens 975, a connection part 976, a speaker 977, a microphone 978, etc. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display unit 973 is The video camera is provided in a second housing 972. The video camera is provided with an imaging device according to one embodiment of the present invention and The method of operation can be applied.

[0309] FIG. 21E shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 963. , a light emitting unit 967, a lens 965, etc. The digital camera is The device and its method of operation can be applied.

[0310] FIG. 21F shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera, The display unit 932 has a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operation method thereof according to one embodiment of the present invention are applied to the information terminal. can be done.

[0311] FIG. 22A illustrates an external view of an automobile as an example of a moving object. The vehicle 890 has a camera 891 and other cameras, and can acquire information on the front, rear, left, right and above the vehicle 890. The imaging device and its operation method according to one embodiment of the present invention can be applied to the camera 891. In addition, the car 890 can be equipped with infrared radar, millimeter wave radar, and laser radar. The automobile 890 is equipped with various sensors (not shown) such as the above. The image captured by the camera 891 is analyzed and the presence or absence of guardrails and pedestrians is determined. It can judge the surrounding traffic conditions and perform autonomous driving. It can also provide road guidance, hazard prediction, etc. The present invention can be used in a system that performs the above.

[0312] In the imaging device according to one aspect of the present invention, the obtained image data is subjected to a computation such as a neural network. By performing computational processing, for example, it is possible to increase the resolution of images, reduce image noise, and perform facial recognition (for crime prevention purposes). etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (wide dynamic range image restoration, positioning, character recognition, and reflection reduction for lensless image sensors. Which processing can be performed?

[0313] In the above description, an automobile is used as an example of a moving body. The vehicle may be any of a vehicle with a fuel cell, an electric vehicle, a hydrogen vehicle, etc. For example, the mobile object is not limited to a car. Other examples include helicopters, unmanned aerial vehicles (drones), airplanes, and rockets. By applying the computer of one aspect of the present invention to these moving bodies, a system using artificial intelligence can be realized. can be granted.

[0314] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. [Explanation of symbols]

[0315] 10a: circuit, 10b: circuit, 20: circuit, 30: circuit, 100: pixel, 101: photoelectric conversion conversion device, 101a: photoelectric conversion device, 101b: photoelectric conversion device, 102: transistor transistor, 102a: transistor, 102b: transistor, 103: transistor, 103a: transistor, 103b: transistor, 104: transistor, 104a: Transistor, 104b: transistor, 105: transistor, 105a: transistor 105b: transistor, 106: capacitor, 106a: capacitor, 106b: Capacitor, 107: transistor, 108: transistor, 114: wiring, 115: wiring Wire, 116: Wiring, 117: Wiring, 118: Wiring, 121: Wiring, 122: Wiring, 123 : wiring, 124: wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 1 31: transistor, 131a: transistor, 131b: transistor, 132: transistor 133: transistor, 134: transistor, 135: capacitor, 142 : transistor, 143: transistor, 144: transistor, 145: capacitor, 151: Wiring, 152: Wiring, 161: Transistor, 162: Transistor, 163: Capacitor, 175: transistor, 175a: transistor, 175b: transistor , 176: transistor, 176a: transistor, 176b: transistor, 200: Pixel block, 202: capacitor, 203: transistor, 204: transistor, 2 05: Transistor, 206: Transistor, 207: Transistor, 210: Pixel array I, 212: Wiring, 213: Wiring, 214: Wiring, 215: Wiring, 216: Wiring, 218 : wiring, 219: wiring, 220: circuit, 222: transistor, 223: transistor, 224: transistor, 225: current supply unit, 226: current mirror unit, 230: circuit , 240: circuit, 252: transistor, 253: transistor, 254: transistor ,261: transistor, 262: transistor, 300: pixel array, 301: circuit, 302: Circuit, 303: Circuit, 304: Circuit, 305: Circuit, 311: Wiring, 320: memory cell, 325: reference memory cell, 330: circuit, 350: circuit, 360: circuit, 37 0: circuit, 410: package substrate, 411: package substrate, 420: cover glass, 421: Lens cover, 430: Adhesive, 435: Lens, 440: Bump, 441: La 450: image sensor chip; 451: image sensor chip; 460: electrode pad pad, 461: electrode pad, 470: wire, 471: wire, 490: IC chip, 5 45: Semiconductor layer, 546: Insulating layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer , 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567 b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: Insulating layer, 613: insulating layer, 614: insulating layer, 616: insulating layer, 617: insulating layer, 618: Insulating layer, 619: Conductive layer, 621: Insulating layer, 622: Insulating layer, 623: Insulating layer, 624: Insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer, 631: Insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 6 36: Conductive layer, 637: Insulating layer, 638: Insulating layer, 639: Conductive layer, 648: Insulating layer, 6 51: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 6 61: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 6 72: Optical conversion layer, 672B: Color filter, 672G: Color filter, 672IR : Infrared filter, 672R: Color filter, 672UV: Ultraviolet filter, 673: Microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer 688: Conductive layer, 689: Conductive layer, 691: Conductive layer, 692: Conductive layer, 701: Gel gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705 : Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 708: Channel formation Area, 735: back gate, 890: car, 891: camera, 892: imaging direction, 9 11: Housing, 912: Display unit, 913: Speaker, 919: Camera, 932: Display unit, 9 33: Housing and wristband, 939: Camera, 951: Support stand, 952: Camera unit ,953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 9 65: Lens, 967: Light-emitting unit, 971: Housing, 972: Housing, 973: Display unit, 974 : Operation keys, 975: Lens, 976: Connection part, 977: Speaker, 978: Microphone, 9 81: Housing, 982: Display unit, 983: Operation buttons, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera

Claims

1. having pixels, the pixel includes a first light receiving circuit, a second light receiving circuit, an amplifier circuit, and an arithmetic circuit; the arithmetic circuit includes first to sixth transistors and first and second capacitors; the first data output from the first light receiving circuit is input to a first terminal of the amplifier circuit; the second data output from the second light receiving circuit is input to a second terminal of the amplifier circuit; a third terminal of the amplifier circuit electrically connected to one of the source and the drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor element; the other electrode of the first capacitor element is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor electrically connected to a gate of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor element; the other electrode of the second capacitance element is electrically connected to one of the source and the drain of the fifth transistor; the other electrode of the second capacitance element is electrically connected to the gate of the sixth transistor; The other of the source and the drain of the fifth transistor is electrically connected to a fourth terminal of the amplifier circuit.

2. The imaging device according to claim 1, An electronic device that processes a part of an image captured by the imaging device based on distance information of a subject in the image analyzed by the imaging device.

Images