Image sensor with germanium photoelectric conversion layer

Abstract

To bond a germanium (Ge) photosensor and a silicon (Si) drive circuit layer. Due to the difference in lattice constant of 4.18% between Ge and Si, positional displacement (dislocation) of Ge and Si atoms occurs at the Ge / Si interface, which causes large dark current noise.SOLUTION: The lattice constants of Ge and Si are 0. 5658nm and 0. 5431nm, respectively. The reason why the number of digits is four is that the lattice constants of Ge reported in recent years are all 0. 5658nm in the range of four significant figures. An insulating layer having a large number of openings is interposed between the Ge layer and the Si layer. When there are 24 Ge atoms and 25 Si atoms between adjacent openings, 24 * 0. 5658nm = 13. 5792nm, 25 * 0. 5431nm = 13. 5775nm. Since the number of significant figures is four, dislocation does not occur if the Ge crystal and the Si crystal are bonded by forming openings in the insulating layer at a pitch of 13. 58nm.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to an image sensor that uses germanium (hereinafter referred to as "Ge") as a photoelectric conversion means and silicon (hereinafter referred to as "Si") as a peripheral circuit. [Background technology] Wavelength and penetration depth of incident light into Ge

[0002] Ge photoelectric conversion layers are used for light of 800nm ​​to 1500nm. As shown in Figure 1, the average penetration depth of 800nm ​​light into Ge is approximately 0.2um. Hereinafter, "um" will represent microns. The average penetration depth of 1500nm light is approximately 2.3um. The thickness of the photoelectric conversion layer is 1 to 3 times the average penetration depth of light of the target wavelength. Therefore, Ge layers with a thickness of 1um to several um are used according to the imaging wavelength. Lattice constants of Ge and Si

[0003] The value of the lattice constant varies slightly depending on the literature. However, in recent literature, the lattice constant of Ge is 0.5658 nm when rounded to the four most significant digits. In this patent, the ratio of the lattice constants of Ge and Si plays a fundamental role. Therefore, the lattice constant of Si is also 0.5431 nm when rounded to the four most significant digits.

[0004] Therefore, the lattice constant of Ge is 4.18% longer than that of Si.

[0005] When a small amount of Ge or carbon (C) is introduced into a Si crystal, the lattice constant of Si increases or decreases slightly. Also, when a small amount of tin (hereinafter referred to as "Sn") or Si is introduced into a Ge crystal, the lattice constant of Ge increases or decreases slightly. Therefore, the lattice constant can be finely adjusted by introducing these elements. The lattice constant of C is 0.3567 nm. Non-Patent Document 1 states that the lattice constant of Sn is 0.6493 nm. Dislocations at the interface between Si and Ge

[0006] The interface between Si and Ge is a crystalline mismatch layer due to the difference in lattice constants between Si and Ge, which causes numerous crystalline defects called dislocations, mainly on the Ge side, with an average spacing of about 10 nm, along the interface.

[0007] The thickness of this dislocation layer is several tens of nanometers.

[0008] Furthermore, large-scale oblique defects grow in the Ge layer from the interface between Si and Ge. These defects penetrate the Ge layer with a pitch of less than 1 μm. Therefore, they are called threading dislocations. These defects become a source of noise such as large dark current.

[0009] This patent relates to a technique for suppressing defects originating at the interface between Ge and Si. Over the past 40 years, various techniques have been applied to suppress these defects.

[0010] The first attempt was to insert an intermediate layer between the Si and Ge layers, with the ratio of Si to Ge gradually changing. From the Si layer to the Ge layer, the ratio of Ge gradually increases, and then the layer is connected to the Ge layer.

[0011] The final technology remaining is the two-stage temperature growth method. First, a Ge layer is grown over a long period of time at a low temperature of 250 to 350°C, just above the Si layer, to a thickness that encompasses the normal dislocation layer but does not penetrate the silicon. The temperature is then raised to a high temperature of over 700°C, and the Ge layer is grown. Other techniques that have been attempted include changing the temperature between these low and high temperatures several times to aggregate large-scale dislocations or move them to the surrounding area.

[0012] However, despite many years of efforts by many researchers and engineers, these methods have not been able to completely suppress the threading dislocations.

[0013] Figure 2 is taken from a 2005 paper by Li et al. (Non-Patent Document 2). The surface of a Si crystal was oxidized to form a SiO2 layer several atomic layers thick, and then the SiO2 layer was randomly removed. A Ge layer was grown on top of it. The figure shows a TEM image of one of the openings in the SiO2 layer.

[0014] The size of the aperture is about 7 nm.

[0015] At least in the approximately 2 nm section of the Ge / Si interface near the center of the aperture, no significant disorder in the atomic arrangement is observed. In this junction direction, atoms are arranged in groups of about six.

[0016] Since the (001) plane is a typical plane of a diamond crystal structure such as a Si crystal or a Ge crystal, the following description will be given for the case where the junction plane between Si and Ge is the (001) plane.

[0017] Hereafter, we will refer to a large number of atoms connected in one direction as an "atomic chain." On the (001) surface, a 2 nm atomic chain, when divided by the lattice constant of Si, 0.5431 μm, corresponds to just under four atoms.

[0018] With technological advances over the past 20 years since Non-Patent Document 2, it is expected that covalent bonding will be possible for openings wider than 2 nm. The upper limit is unknown, but in the following it is assumed to be 5 nm. Even if the opening is narrower than 5 nm, the following description basically holds. Current state of fine processing

[0019] TSMC has established a new foundry in Kumamoto Prefecture, aiming to operate a multi-nm process.

[0020] Fine electron beam lithography equipment has been introduced at several universities in Japan.

[0021] For example, a 5 nm electron beam lithography system was introduced at Osaka University (Non-Patent Document 3).

[0022] In this way, processes on the order of a few nanometers have become possible in both industry and research institutes such as universities.

[0023] Patent Document 1 discloses a pixel structure 100 of a multi-framing image sensor shown in Figure 3. A high voltage is sequentially applied to eight horizontal transfer gates 101. This allows eight consecutive image signals to be sequentially transferred at extremely short time intervals via output gates 102 to eight image signal storage areas (horizontal transfer gates) arranged on the circumference, and stored on the spot, making it possible to capture eight consecutive images at ultra-high speed.

[0024] The inventors of the present invention developed a multi-framing image sensor equipped with six horizontal transfer gates in 2017, and in 2018 achieved continuous shooting of 10 images at a shooting speed of 100 million images per second, becoming the first in the world to successfully capture continuous shooting of flying light using an image sensor (Non-Patent Document 4). In this case, one of the six horizontal transfer gates in each pixel was used as a drain, and the two adjacent pixels were used as macro pixels, resulting in a continuous shooting number of 10 (= (6 - 1) × 2).

[0025] Figure 4 shows a horizontal cross-sectional view 103 and a vertical cross-sectional view 104 of the pixel structure of a multi-framing image sensor disclosed in Non-Patent Document 5. Instead of horizontal transfer gates, 16 vertical transfer gates 106 are provided around a Si photoelectric conversion layer 105. In this case, signal electrons are transferred directly and sequentially in the horizontal direction from the central Si photoelectric conversion layer. The contour lines indicate equipotential lines when a high voltage is applied to one vertical transfer gate 107.

[0026] When Ge is used as the photoelectric conversion layer, the Si photoelectric conversion layer area in Figure 4 is used only for transfer purposes, and the Ge photoelectric conversion layer is placed on top of it. Image sensor with Ge photoelectric conversion layer and Si avalanche multiplication layer

[0027] Non-Patent Document 6 discloses a SPAD (Single-Photon Avalanche-Diode) image sensor that includes a Ge photoelectric conversion layer and an avalanche multiplication layer in which a high voltage is applied to a Si layer.

[0028] The interface between a normal Ge photoelectric conversion layer and a Si layer is a dislocation layer, resulting in low transfer efficiency and generating very large noise.

[0029] In Non-Patent Document 6, the dislocation layer is buried in a very high concentration p-type layer to suppress the activity of dislocations. As a result, signal electrons pass through these layers mainly by the diffusion effect. This sacrifices transfer efficiency and transfer speed, but in exchange, a single signal electron that once reaches the Si layer is amplified to thousands to tens of thousands of electrons by an electron avalanche. As a result, the output signal has a number of signal electrons that far exceeds the number of electrons corresponding to the large noise generated by the dislocation layer and the dense p-type layer. This makes it possible to detect a single electron generated by the incidence of a single photon. Photoelectric conversion materials and insulating materials

[0030] FIG. 13 shows the lattice constants, thermal expansion coefficients, and melting points of materials commonly used for photoelectric conversion, and the thermal expansion coefficients and melting points of materials used for insulation.

[0031] For example, the thermal expansion coefficient of Si is about five times that of SiO2 (2.556×10 -6 K -1 / 0.55×10 -6 K -1 The thermal expansion coefficient of Ge is about 10 times larger than that of SiO2 (5.79 × 10 -6 K -1 / 0.55×10 -6 K -1 ) Therefore, when Si or Ge is grown on SiO2 at several hundred degrees Celsius and then returned to room temperature, a strong tensile force acts on the Si or Ge layer. This can cause microcracks to form in the Si or Ge layer during this process. Care must be taken in the process to prevent this.

[0032] By stacking an Al2O3 layer on the SiO2 layer, the tensile force acting between the Ge layer and the insulating layer can be alleviated. This is because the thermal expansion coefficient of Al2O3 is 8.2 × 10 -6 K -1 is about 20% larger than that of Ge.

[0033] The melting point is also important in the process. For example, when stacking Si, Ge, and InSb, the relationship between their melting points becomes important. The melting points are 1414°C, 938°C, and 524°C, respectively. These process temperatures are much lower than the melting points, but usually follow the order of the melting points.

[0034] In fact, the process temperature for Si is in a wide range centered around 900°C (depending on the process), while that for Ge is around 500°C. Conversely, when processing in the reverse order, technical ingenuity is required. [Prior art documents] [Patent documents]

[0035] [Patent Document 1] Title of invention: Solid-state imaging device, Patent No. 6188679, Registration date: August 10, 2017, Patent holder: Goji Eto, Inventors: Goji Eto, Tetsuo Yamada, Vu Truong Son Dao [Non-patent literature]

[0036] [Non-Patent Document 1] Ishimaru, M., Nakamura, R., "Behavior of Sn during crystallization of amorphous GeSn," Materia, 59(12), 662-668, 2020. [Non-patent document 2] Q. Li, et al., Morphological evaluation and strain relaxation of Ge island grown on chemically oxidized Si(100) by molecular-beam epitaxy, J. of Appl. Phys., 98(7), 073504-8, 2005. [Non-patent document 3] OS-104(N10) Automatically Transferred Electron Beam Writer | (osaka-u.ac.jp) [Non-patent document 4] TGEtoh,et al.,Light-in-Flight Imaging by a Silicon Image Sensor:Toward the Theoretical Highest Frame Rate,Sensors,19(10),2247,15 May 2019. [Non-Patent Document 5] Eto, G. et al., Ge-on-Si Stone Circle Image Sensor, ITE Technical Report, 47(27), 2023. [Non-patent document 6] P. Vines,et al,High performance planar Germanium-on-Silicon Single-photon avalanche-diode detector,Nature Communications,10,1086,2019. Summary of the Invention [Problem to be solved by the invention]

[0037] The frequency of crystal defects occurring at the interface between Si crystals and Ge crystals is suppressed.

[0038] First, the solution to the problem according to the present invention will be explained using an easy-to-understand example.

[0039] Assume that a Si crystal layer is the bottom layer and a Ge crystal layer is the top layer, with a thin insulating layer between them. In this insulating layer, there are a first opening and a second opening, each with a diameter larger than the lattice constant. These two openings are located in one crystal direction of the Si crystal. Assume that there are K Ge atoms and (K+1) Si atoms between the center of the first opening and the center of the second opening.

[0040] The distance between adjacent Ge atoms in the above crystal direction is defined as A, and that between adjacent Si atoms is defined as B. In this case, the following formula represents the condition for the shortest distance when the positions of the Si and Ge atoms exactly coincide near the centers of the above two openings.

[0041] KA=(K+1)B, or K=B / (AB)

[0042] This condition specifies the minimum distance between adjacent openings. When the Ge and Si atoms are located at the center of the first opening and K is not an integer, the positions of the Ge and Si atoms in the adjacent second opening are slightly shifted from the center. This shift can be up to half the lattice constant.

[0043] At this time, the relative displacement between the Ge atoms and the Si atoms in the second opening is small enough to be ignored.

[0044] When A = 0.5658 nm and B = 0.5431 nm, K = B / (AB) = 23.93, K × A = (K + 1) × B = 13.54 nm, and 2 × K × A = 27.07 nm.

[0045] Therefore, if the openings are made at a pitch of 13.54 nm or 27.07 nm, no dislocations will occur.

[0046] However, at this stage, there is no mass production process that can provide position control on the sub-nanometer order. In reality, we will search for an opening interval that is an integer value close to these values. In other words, the values ​​obtained in the above study will be an easy-to-understand guideline for solving the problem. Means for solving the problem and their effects

[0047] Hereinafter, the substantial incident direction of light will be referred to as the vertical direction, and the direction perpendicular thereto will be referred to as the horizontal direction or radiation direction.

[0048] The surface that the incident light reaches relatively first is called the top, and the surface that the light reaches later is called the bottom.

[0049] The first solution of the present invention is an imaging device equipped with an image sensor, wherein each pixel of the image sensor comprises a photoelectric conversion means made mainly of crystalline germanium that converts the incident light into an electric charge, an insulating means connected to the lower surface of the photoelectric conversion means, and the charge transfer means made mainly of crystalline silicon that is connected to the lower surface of the insulating means, and wherein the plane formed by the insulating means is provided with two or more openings made mainly of crystalline germanium or crystalline silicon and surrounded by the insulating means, and when any one of the openings is called a first opening and the nearest opening having its center on a single crystal direction passing through the center of the first opening is called a second opening, when one atom in the bottom layer of the photoelectric conversion means and one atom in the top layer of the transfer means are substantially connected at the substantial center of the first opening, one atom in the bottom layer of the photoelectric conversion means and one atom in the top layer of the transfer means are substantially connected at the substantial center of the second opening.

[0050] This technology effectively bonds Ge atoms and Si atoms at the openings, effectively suppressing the generation of dislocation layers that occur when a Ge layer is bonded onto a Si layer.

[0051] The imaging device is characterized in that, when the average interatomic distance of the bottom layer of the photoelectric conversion means between the substantial centers of the adjacent openings is A and the average interatomic distance of the top layer of the transfer means is B, and K satisfies K×A=(K+1)×B, the distance between the adjacent openings is substantially an integer multiple of K×A.

[0052] However, the interatomic distance depends on the temperature, so ideally the pitch of the openings should be determined so as to maintain the above criteria in the early stage of the growth of the germanium layer after the opening opening process.

[0053] This technology can maximize the transfer efficiency of signal electrons from the Ge layer to the Si layer. In other words, this technology minimizes the inter-aperture distance K × A by connecting Si and Ge atoms at the atomic level in each aperture. For the same aperture size, the shorter the inter-aperture distance, the easier it is to transfer signal electrons from the Ge layer to the Si layer. In the stage of technological development toward this direction, setting the inter-aperture distance to an integer multiple of K × A will allow us to clearly understand the direction of technological development.

[0054] Furthermore, by adding trace amounts of carbon, Si, Ge, Sn, or other homologous elements to crystalline Ge and crystalline Si, the distance at which the positions of Ge and Si atoms coincide in a certain crystal direction can be adjusted.

[0055] Furthermore, by providing the insulating means with a layer having a fixed charge, such as an aluminum oxide layer or a hafnium oxide layer, it is possible to prevent signal electrons from approaching defect layers, such as the interface between the insulating means and the Ge layer and the insulating means, and the interface between the insulating means and the Si layer. [Brief explanation of the drawings]

[0056] [Figure 1] Incident wavelength (abscissa), absorptance (left ordinate), and penetration depth (right ordinate) of a photoelectric conversion material such as Ge [Figure 2] An example of a TEM image described in Non-Patent Document 2. A thin SiO2 layer on a Si crystal layer was roughened to expose the Si layer, and Ge crystals were grown on it. [Figure 3] An example of a plan view of a pixel of a multi-framing image sensor described in Patent Document 1 [Figure 4] An example of a pixel structure of a multi-framing image sensor with a vertical transfer gate described in Non-Patent Document 4 [Figure 5] Plan view and cross section of one pixel of a multi-framing image sensor [Figure 6] Apertures with a diameter of 5 nm at a pitch of 25 nm are formed in the Al2O3 thin layer 119 and the SiO2 thin layer between the Ge photoelectric conversion layer 111 and the Si transfer means 112. [Figure 7] Gate operation diagram [Figure 8] Overall view of the imaging device [Figure 9] Drive voltage generation circuit [Figure 10] Image sensor plan view [Figure 11] Relationship between electron velocity and electric field in Si layers [Figure 12] Additional n-doping for accelerating electrons in Ge layers [Figure 13] Lattice constants and thermal properties of materials used in photovoltaic conversion DETAILED DESCRIPTION OF THE INVENTION Overview of the structure of the first embodiment

[0057] The present invention mainly relates to the structure of an insulating layer between a Ge layer and a Si layer in a sensor chip of an image sensor of an imaging device.

[0058] The image sensor of the present invention is constructed by stacking a sensor chip and a transfer circuit chip.

[0059] 5 shows a planar structure 108 and a cross-sectional view 109 of one pixel according to the first embodiment of the present invention. This planar structure is similar to that shown in FIG. 3. However, the wiring structure shown in FIG. 3 is omitted. That is, only one of the eight external circuits of the output gate 102 is shown.

[0060] The difference is that the image sensor of the present invention adds one transfer gate 110 to the center of the pixel. The advantage is that it makes horizontal transfer of signal electrons easier. Therefore, this change does not change the basic structure or driving method. The only difference is that one step of gate operation at the center of the pixel is added to the gate operation during shooting.

[0061] Therefore, in this specification, the structure of the sensor chip will be mainly described, with a particular section describing the insulating layer 113 between the Ge photoelectric conversion layer 111 and the Si transfer circuit layer 112.

[0062] First, the structure of the sensor chip of the first embodiment will be described below. Next, the structure and function of the insulating layer between the Ge layer and the Si layer will be described. After that, the function and operation of the sensor chip will be described. Structure of the Sensor Chip

[0063] As shown in cross section 109, the image sensor of the present invention is made by joining two chips in the vertical direction.

[0064] The upper stage is a sensor chip 114. The lower stage is a drive circuit chip 115.

[0065] The sensor chip and driver circuit chip are physically separated by a plastic insulating layer, but are electrically connected by bumps 125. On the other hand, the sensor chip is made up of multiple semiconductor layers, but the bonding between the layers is direct, with no physical space between them.

[0066] As mentioned above, the following mainly describes the structure of the sensor chip.

[0067] As shown in cross-sectional view 109, incident light 116 is collected by an on-chip microlens (not shown) provided on each pixel and enters photoelectric conversion layer 111. The photoelectric conversion layer is made of a semiconductor containing Ge as its main component.

[0068] On the surface of the Ge layer is placed a high-pass filter 117, which blocks light with wavelengths of 1000 nm or less and transmits light with wavelengths longer than that, and is 50 nm thick.

[0069] The high-pass filter is covered with a 20-nm-thick SiO2 protective layer 118. Beneath that is a 1.5-um-thick Ge photoelectric conversion layer 111. Beneath the Ge layer is a 14-nm-thick insulating layer 113. This insulating layer consists of a 10-nm Al2O3 layer 119 and a 4-nm SiO2 layer 120. Beneath that is a 500-nm-thick Si transfer circuit layer 112. Beneath that is a 7-nm-thick SiO2 insulating layer 121. Beneath that are horizontal transfer electrodes 122. The horizontal transfer electrodes are made of 100-nm-thick polysilicon. Beneath that is an insulating layer 124 coated with an anti-reflection layer 123 for SWIR light. The sensor chip and driver circuit chip are electrically connected by copper bumps 125.

[0070] The flat surfaces of both the Ge layer and the Si layer are (001) planes.

[0071] Next, we will explain the planar structure of the sensor chip. An octagonal transfer electrode is provided at the center of the pixel. The transfer gate that includes this electrode is the center gate (CG) 110. Eight horizontal transfer electrodes 126 are provided around the CG. These electrodes extend in radial directions from the CG. Therefore, the transfer gates that include these electrodes will be called "radial transfer gates (RTG) 126."

[0072] The horizontal size of one pixel is a square with one side measuring 4 um.

[0073] The planar shape of the Ge layer is an octagon with a side length of 1 μm, so the diameter is (1 + 2 × 0.707) μm = 2.414 μm.

[0074] The width of the CG 110 is 0.814 μm. This width includes half the width of the insulating layer between it and the RTG 126. Therefore, these gaps are not shown. The gap width is 100 nm.

[0075] The outside of each RTG is provided with a floating diffusion (FD) 127. The signal electron packets sent from each RTG are converted into voltage by the FD.

[0076] The FD is connected to a source follower (SF) 128. The SF converts the voltage change of the FD into a current and amplifies it. The amplified image signal is temporarily stored in memory. In this embodiment, the FD is also used as a memory. Therefore, the memory is not shown in this diagram.

[0077] The image signals stored in the in-pixel memory are read out from the image sensor after the image capture is completed, and successive images are constructed using the read image signals.

[0078] The surface layers other than the surface of the Ge layer are covered with a light-shielding layer 129 .

[0079] The sides of the Ge layer are insulating walls 130 made of SiO2 with a thickness of 50 nm, and the outside is a Si layer 131.

[0080] The pixels are separated by a 100 nm thick SiO2 layer 132 in the vertical direction at the pixel boundary.

[0081] The insulating layer is made up of a laminate of Al2O3 and SiO2 layers.

[0082] The SiO2 layer is a defect layer because there are no Si or Ge crystal atoms to connect to above or below it. The fixed charges in the Al2O3 layer act as a repulsive force against the signal electrons, suppressing the trapping of signal electrons and the generation of noise.

[0083] In this embodiment, the openings in the insulating layer are oriented in the directions of

[0010] and

[0100] , and the junction surfaces of Ge and Si are both (001).

[0084] Consider the case where the number of atoms in the Si atomic chain is 46 and the number of atoms in the Ge atomic chain is 44.

[0085] In this case, the atomic chain length of Ge is 44 × 0.5658 nm = 24.90 nm.

[0086] That is, it is 0.10 nm shorter than 25 nm. The lattice constant of Sn is 0.6493 nm. The difference in lattice constant between Sn and Ge is 0.0818 nm (= (0.6493 - 0.5658) nm). In this case, (36 × 0.5658 + 0.6493) / 37 × 44 nm = 24.99 nm.

[0087] In other words, substituting one of the 37 Ge atom chains with Sn results in an aperture pitch of 24.99 nm. In an actual process, if the ratio of Sn atoms is increased slightly, the length of the 44 Ge atom chain can be made exactly 25 nm.

[0088] On the other hand, the length of the Si atomic chain is 46 × 0.5431 = 24.98 nm. Therefore, by adding a trace amount of Ge, the length of the atomic chain between the openings in the Si layer can be made 25 nm.

[0089] The first embodiment shown in Figure 6 includes a photoelectric conversion layer, a transfer layer, and an insulating layer made of a laminate of Al2O3 and SiO2 with 5 nm openings at a 25 nm pitch.

[0090] The SWIR light that has passed through a 1000 nm high-pass filter 117 generates pairs of holes and signal electrons in a Ge photoelectric conversion layer 111 having a thickness of 1.5 μm.

[0091] The light that is filtered by the 1000 nm high-pass filter and remains without being photoelectrically converted in the Ge layer is substantially transmitted through the Si layer 112 .

[0092] Furthermore, the light transmitted through the layer 122 of the transfer electrode RTG is absorbed by the SWIR light absorption layer 124 below.

[0093] The voltage of the hole contact 135 at the top end of the Ge layer is constant at −4 V. Holes are discharged to the outside of the device through the hole contact. Hole contact wiring is not shown.

[0094] The CG 110 and the eight RTGs 126 are driven between a low voltage VL of -2.5 V and a high voltage VH of -1 V. The potential of the output gate (OG) 102 is constant at -2 V.

[0095] Since -2V is 0.5V higher than the VL of the RTG, when the RTG changes from VH to VL, the electrons in the RTG cross the OG and flow into the FD127.

[0096] The potential of the reset drain (RD) 136 is the ground voltage 0 V. The reset gate (RS) 137 is driven between −1 V and 0.2 V.

[0097] The drive method for the CG, RTG, and RS is shown in Figure 7. This drive method consists of four phases. The time resolution is 200 ps for the RTG pulse width 138. The pulse width 139 of the CG 110 is half that, at 100 ps. The CG takes VH simultaneously with each RTG pulse and returns to VL before the RTG.

[0098] In the reset phase 140 before shooting, the voltage of all RTGs is first raised to VH and then lowered to VL. This causes the accumulated electrons to move to FD127. At this time, the voltage of all reset gates RS137 is raised to 0.2V. Therefore, the FD and RD (reset drain) are connected at ground voltage. Therefore, the potential of the FD becomes 0V. Immediately afterwards, the potential of RS is lowered to -1V. This sets the potential of all FDs to 0V.

[0099] Next is the FD pre-potential detection phase 141. In this embodiment, the signal charge amount, that is, the potential change in the FD, is detected by digital CDS (Correlated Double Sampling). First, the potential of the FD is detected and recorded as a digital signal.

[0100] CDS is usually performed in an analog manner. Digital CDS has slightly larger conversion noise than analog CDS. In this embodiment, the FD is used as memory, and the frame interval is very short, so CDS reading cannot be performed during that time. For this reason, the amount of electrons in the FD is recorded as a digital value before and after shooting, and the amount of charge is detected from the difference.

[0101] After the image capture, the potentials of the eight FDs are detected, and the difference between this and the data obtained in the preliminary potential detection phase is saved as eight image signals.

[0102] The pre-potential detection phase 141 is not shown in Figure 7. The reason for not showing it and its operation will be explained below.

[0103] It is not possible to show on the same diagram the time pattern of the RTG voltage in the imaging phase 142 and the time step of the selection transistor 181 that determines the readout order from the FD in the pre-potential detection phase 141. The time step of the RTG is 100 ps, ​​while the shortest time step of the selection transistor is 1 us.

[0104] By sequentially applying a high voltage to each of the selection transistors 181 connected to the address line, the voltage (potential) of the FD is sequentially read out. The time operation pattern of this selection transistor is the same as the time operation pattern of the horizontal transfer transistor shown next in the image capture phase 142. The voltage applied to the selection transistor is from 0V to 1V.

[0105] The time operation pattern of the select transistor in the read phase 145 is the same as that in the pre-potential detection phase 141, and is therefore not shown.

[0106] In the pre-potential detection phase 141 before the image capture phase 142, the potential of the FD is first measured and then converted into digital data and recorded. In the signal detection after the end of the image capture phase, the potential difference of the FD before and after capture in one of the eight time steps is calculated. By repeating this process, continuous image signals for each pixel of eight images are detected.

[0107] Next is the shooting phase 142. VH is sequentially applied to the eight RTGs and CGs. The signal electrons pass through the CG and are collected in one RTG 143 that has VH applied. The CG voltage returns to VL first. Then the RTG voltage is returned to VL. The signal electrons pass through OG 144 and enter FD 127. This is repeated eight times to store the image signals for eight consecutive frames in the FD.

[0108] Next is the signal detection phase 145. The potentials of the eight FDs are detected in sequence and digitized, and at the same time, the difference from the digital data obtained in the preliminary potential detection phase is saved as eight image signals.

[0109] In this way, eight consecutive image signals captured with a time resolution of 200 ps are stored in the digital memory area of ​​the driver circuit chip 115.

[0110] The image signal is read out of the element at a sufficiently slow speed after the eight consecutive images have been taken.

[0111] 8 shows a configuration diagram 150 of an image capturing apparatus according to the first embodiment of the present invention. Incident light 151 passes through a filter 152, a lens 153, an aperture 154, and a shutter 155 and enters an image sensor 156.

[0112] The image sensor is attached to the tip of the camera unit 157. The image sensor is controlled by an imaging control circuit 158 ​​and a signal readout circuit 159. However, the initial imaging control circuit (drive circuit) and memory are built into the drive circuit chip in each pixel. A buffer memory 160 for temporarily storing digital image signals is connected to the signal readout circuit. The buffer memory is connected to a communication circuit 161 and further to an image processing device 162 in the control computer. The control computer also incorporates a control circuit 163 and an internal recording device 164 for controlling the entire system. The control computer is also connected to an external recording device 165, a display 166, a console 167, a mouse 168, a trigger device 169 for starting and stopping imaging in synchronization with the occurrence of the phenomenon being photographed, and a lighting device 170.

[0113] 9 shows the imaging control circuit 158. A signal waveform generated by an FPGA 171 and a constant voltage generated by a constant voltage generating device 172 are combined to generate a dynamic voltage waveform by a voltage generating device 173, which is output from a wiring 174.

[0114] Control is performed according to the program embedded in the FPGA. The FPGA also controls the signal readout circuit. Sensor chip

[0115] FIG. 10 shows a top view 175 of the sensor chip.

[0116] The sensor chip has a light receiving surface 176 consisting of 1024 x 1024 pixels in the center thereof, and a pad area 177 and a multiplexer area 178 around it.

[0117] The size of one pixel is 4um x 4um. Therefore, the light receiving surface is 4.096mm x 4.096mm. The chip size is 7mm x 7mm. Second and third embodiments

[0118] The difference between the first and second embodiments and the first embodiment is that Sn is not used.

[0119] In the first embodiment, the opening pitch is substantially an integer of 25 nm, and the numbers of Ge and Si atoms between the openings are also substantially integers of 44 and 46. Therefore, the positions of the Ge atoms and Si atoms in the openings are substantially located at the centers of the openings. However, in this process, the Ge crystal contains approximately 3.6% Sn.

[0120] In the second and third embodiments, Sn is not used, but the pitch between the openings or the number of Ge atoms and / or Sn atoms between the openings is not an integer. When K is an integer, the pair of Ge atoms and Si atoms is not necessarily located at the center of the opening. Conversely, when the opening pitch is an integer, the number of Ge or Si atoms between the openings is not necessarily an integer.

[0121] In the second embodiment, we assume K = 24. This value is close to the K value of 23.93 obtained when the minimum aperture spacing of 13.54 nm is determined for the case where both Ge and Si are intrinsic semiconductors. In this case, the Ge atomic chain length is 13.58 nm (= 24 × 0.5658 nm), and the Si atomic chain length is also 13.58 nm (= 25 × 0.5431 nm). Therefore, to four significant digits, the positions of the Ge atoms and the Si atoms in each aperture match.

[0122] The minimum opening pitch is K=B / (AB)=13.54 nm, and therefore, in the third embodiment, it is assumed that the opening pitch is set to 14 nm, which is the integer closest to this value.

[0123] The aperture pitch is adjusted by adding Si to the Ge layer. Although several empirical formulas are available for the lattice constant of SiGe, as a first approximation, we assume that there is a linear relationship between the ratio of Ge added to Si.

[0124] The average lattice constant of SiGe is C, which is an unknown quantity.

[0125] Since K is also an unknown, we solve K×C=14.00nm and K=S / (CS) simultaneously. The results are C=0.5650nm and K=24.78.

[0126] C = 0.5650 nm is 0.0008 nm shorter than the lattice constant of Ge, which is 0.5658 nm. Dividing this by the lattice constant difference between Ge and Si, 0.0227 nm, gives us 3.5%.

[0127] In this case, it is only necessary to add a small amount of Si to the Ge photoelectric conversion layer, which is a very realistic solution. The actual concentration adjustment is performed experimentally.

[0128] The junction surface between Ge and Si is the (001) plane, and the direction of the opening is the

[0110] direction. In this case, the interatomic distance is 1 / SQRT(2) times the lattice constant, where SQRT stands for square root.

[0129] The aperture pitch is basically the result of the calculation in the

[0010] direction already described multiplied by 1 / SQRT(2) as a proportionality constant.

[0130] The aperture pitch can be calculated for other surfaces and directions using the same procedure.

[0131] Instead of the insulating layer Al2O3 between the Si layer and the Ge layer, a layer having a fixed charge such as hafnium oxide may be used.

[0132] A large potential difference may be applied between the hole contact 135 and the CG and RTG to add an amplification function by impact ionization. When the electric field is increased, an avalanche (electron avalanche) type is generated. Seventh embodiment

[0133] 12 shows a Ge photovoltaic layer 111, an insulating layer consisting of stacked Al2O3 layer 119 and SiO2 layer 120, and a Si transport layer 112. This embodiment primarily comprises a semicircular n-negative impurity doped region 179 around an opening in the Ge layer.

[0134] At this time, as shown by the arrows around the doping region in the figure, the electrons generated in the Ge layer move toward the n-negative region, which effectively prevents them from approaching the interface between the Ge layer and the insulating layer, which is a defect region.

[0135] This technique has two effects: (1) together with the Al2O3 fixed negative charge layer, it suppresses trapping of signal electrons at the interface, and (2) it shortens the transit time of electrons towards the opening in the Ge layer.

[0136] The memory chip may be bonded below the drive circuit chip 115 in Fig. 5. This will increase the number of images captured by about one order of magnitude. However, the imaging speed will be reduced by about one order of magnitude.

[0137] In the above embodiments, the horizontal crystal planes of Si and Ge are assumed to be (001) planes. The horizontal crystal planes are not limited to (001). Furthermore, the horizontal crystal planes of Ge and Si do not need to be the same crystal plane. The orientation of the openings is also not limited to

[0010] .

[0138] In commercially available image sensors, adjacent pixels share readout circuits, etc. In the present invention, adjacent pixels may also share some of the functions.

[0139] In addition, although this patent considers the combination of Ge and Si, there are other combinations of compounds where dislocations caused by differences in lattice constants can be a problem. In these cases as well, the concept of this invention is expected to function effectively.

[0140] It is ideal for ultra-fast NIR and SWIR imaging, and in particular for imaging explosions and high-speed combustion phenomena, it allows simultaneous measurement of not only deformation but also temperature. [Explanation of symbols]

[0141] 100 Pixel structure of multi-framing image sensor 101 Horizontal transfer gate 102 Output Gate (OG) 103 Horizontal cross section of pixel structure of multi-framing image sensor 104 Vertical cross section of the same 105 Si photoelectric conversion layer 106 16 vertical transfer gates 107 Vertical Transfer Gate 108 Planar structure of one pixel in the first embodiment 109 Same cross section 110 One transfer gate (CG) at the center of the pixel 111 Ge photoelectric conversion layer 112 Si transfer circuit layer 113 Insulating layer 114 Sensor Chip 115 Driver circuit chip 116 Incident light 117 1000nm high pass filter 118 SiO2 protective layer 119 Al2O3 layer 120 SiO2 layer 121 SiO2 insulating layer 122 Horizontal transfer electrode group 123 SWIR anti-reflection layer 124 Insulating layer coated with anti-reflection layer 125 Copper Bump 126 Horizontal transfer electrode (RTG) 127 Floating Diffusion (FD) 128 Source Follower (SF) 129 Light blocking layer 130 SiO2 insulating wall Si layer outside the 131Ge photoelectric conversion layer 132 SiO2 layer at pixel boundaries 133 Pitch of thin insulating SiO2 layer between Ge and Si (25nm) 5 nm opening in a thin SiO2 layer between 134 Ge and Si Hole contact on top of 135 Ge layer 136 Reset Drain (RD) 137 Reset Gate (RS) 138 RTG Pulse Width 139 CG pulse width 140 Reset Phase 141 Pre-potential detection phase 142 Shooting Phase 1 RTG with 143 VH 144 Output Gate (OG) 145 Signal Detection Phase 150 Configuration diagram of the imaging device of the first embodiment 151 Incident light 152 filters 153 Lens 154 Aperture 155 Shutter 156 Image Sensor 157 Camera Club 158 Shooting control circuit 159 Signal readout circuit 160 buffer memory 161 Communication Circuit 162 Image processing device 163 Control circuit for controlling the entire system 164 Internal Recording Device 165 External Recording Device 166 displays 167 Console 168 Mouse 169 Trigger Device 170 Lighting equipment 171 FPGA 172 Constant voltage generating device 173 Voltage generating devices 174 Wiring 175 Top view of the sensor chip 176 Photosensitive surface 177 Pad Area 178 Multiplexer Area n-negative doping around an opening in a 179 Ge layer 180 Second Transfer Gate 181 Source follower select transistor after FD

Claims

1. An apparatus comprising: a means for collecting incident electromagnetic waves or incident charged particles (hereinafter referred to as "incident light"); a semiconductor device (hereinafter referred to as "image sensor") for receiving the collected incident light; a means for controlling the image sensor; and a means for processing a signal output from the image sensor, wherein the image sensor has pixels arranged in M ​​rows and N columns (where M and N are positive integers), and when the substantial incident direction of the incident light is defined as a vertical direction, with the side closer to the incident surface defined as the top and the side farther from the incident surface defined as the bottom, Each of the pixels includes a photoelectric conversion means, the photoelectric conversion means being mainly made of crystalline germanium and converting the incident light into an electric charge, an insulating means connected to a lower surface of the photoelectric conversion means, and a charge transfer means, the photoelectric conversion means being mainly made of crystalline silicon and connected to a lower surface of the insulating means, When two or more regions (hereinafter referred to as "apertures") made mainly of crystalline germanium or crystalline silicon and surrounded by the insulating means are provided within the plane formed by the insulating means, and when any one of the apertures is called a first aperture and the nearest aperture having its center in one crystal direction passing through the center of the first aperture is called a second aperture, and when one atom in the bottom layer of the photoelectric conversion means and one atom in the top layer of the transfer means are substantially connected at the substantial center of the first aperture, One atom in the bottom layer of the photoelectric conversion means and one atom in the top layer of the transfer means are substantially connected at the substantial center of the second opening.

2. 2. The device according to claim 1, wherein the image sensor is characterized in that, when an average interatomic distance in the lowermost layer of the photoelectric conversion means between the substantial centers of the first and second openings is A, an average interatomic distance in the uppermost layer of the transfer means is B, and K satisfies K×A=(K+1)×B, the distance between the adjacent openings is substantially an integer multiple of K×A.

3. The device according to claim 1 or claim 2, wherein the photoelectric conversion means contains a trace amount of silicon or tin, and simultaneously, or the transfer means contains a trace amount of carbon or germanium.

4. The device according to any one of claims 1 to 3, wherein the insulating means comprises a layer having a fixed charge, such as an aluminum oxide layer or a hafnium oxide layer.

Images