Amplifier circuit

Abstract

To provide an amplifier circuit having a high gain while maintaining power consumption.SOLUTION: The amplifier circuit 1 includes an input-terminal 101, an output-terminal 102, a side FET11 having a gate-terminal g1, a drain-terminal d1, and a source-terminal s1, a side FET12 having a gate-terminal g2, a drain-terminal d2, and a source-terminal s2, a side g3 having a gate-terminal, a drain-terminal, and a source-terminal, and LC parallel resonant circuits 20 and 40, wherein the gate-terminal is connected to the input-terminal 101, and the drain-terminal is connected to the source-terminal. s2 d3 d1 s3 g1 FET31, the source node s1 is connected to the ground, the gate node g2 is connected to the drain node d3 and the C parallel resonance circuit 40, the drain node d2 is connected to the input node 102 and the LC parallel resonance circuit 20, the gate node g3 is connected to the source node s2, and the source node s3 is connected to the ground.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit. [Background technology]

[0002] Patent Document 1 discloses a low-noise amplifier circuit having two cascode-connected amplifier elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2008-512926 Summary of the Invention [Problem to be solved by the invention]

[0004] In the amplifier circuit disclosed in Patent Document 1, methods for further increasing the gain include increasing the current consumption (drain current or collector) to increase the mutual conductance, and increasing the output resistance by configuring the amplifier elements in a multi-stage configuration of three or more stages. However, these methods increase the current consumption or power supply voltage, making it impossible to achieve high gain while maintaining low power consumption.

[0005] SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an amplifier circuit that has a high gain while maintaining power consumption. [Means for solving the problem]

[0006] In order to achieve the above object, an amplifier circuit according to one embodiment of the present invention includes a first input terminal and a first output terminal, a first amplifier element having a first control terminal, a first terminal, and a second terminal, a second amplifier element having a second control terminal, a third terminal, and a fourth terminal, a third amplifier element having a third control terminal, a fifth terminal, and a sixth terminal, a first LC parallel resonant circuit, and a second LC parallel resonant circuit, wherein the first control terminal is connected to the first input terminal, the first terminal is connected to the fourth terminal, the second terminal is connected to ground, the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit, the third terminal is connected to the first output terminal and the first LC parallel resonant circuit, the third control terminal is connected to the fourth terminal, and the sixth terminal is connected to ground. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide an amplifier circuit that has a high gain while maintaining low power consumption. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit configuration diagram of an amplifier circuit according to an embodiment; [Figure 2A] FIG. 1 is a circuit configuration diagram of an amplifier circuit according to a comparative example. [Figure 2B] FIG. 10 is a diagram showing current-voltage characteristics of amplifying elements according to an embodiment and a comparative example. [Figure 3] FIG. 10 is a circuit configuration diagram of an amplifier circuit according to a first modified example of the embodiment. [Figure 4A] FIG. 10 is a circuit state diagram of the amplifier circuit according to the first modification of the embodiment when the gain is high. [Figure 4B] FIG. 10 is a circuit state diagram of the amplifier circuit according to the first modification of the embodiment when the gain is low. [Figure 5] FIG. 10 is a circuit configuration diagram of an amplifier circuit according to a second modification of the embodiment. [Figure 6] FIG. 10 is a circuit configuration diagram of an amplifier circuit according to a third modification of the embodiment. [Figure 7] FIG. 10 is a circuit configuration diagram of an amplifier circuit according to a fourth modified example of the embodiment. [Figure 8A]FIG. 10 is a circuit state diagram of the amplifier circuit according to the fourth modification of the embodiment when the first amplifier is operating. [Figure 8B] FIG. 10 is a circuit state diagram of the amplifier circuit according to the fourth modification of the embodiment when the second amplifier is operating. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0010] It should be noted that the drawings are schematic diagrams in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present invention, and are not necessarily strictly illustrated, and may differ from the actual shapes, positional relationships, and proportions. In the drawings, the same reference numerals are used to denote substantially the same components, and redundant explanations may be omitted or simplified.

[0011] In the circuit configuration of the present disclosure, "connected" includes not only direct connection by connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Connected between A and B" means connected to both A and B between A and B.

[0012] In addition, in this disclosure, a "path" means a transmission line composed of a wiring through which a high-frequency signal propagates, an electrode directly connected to the wiring, and a terminal directly connected to the wiring or the electrode.

[0013] In addition, in this disclosure, "component A is arranged in series with path B" means that both the signal input terminal and the signal output terminal of component A are connected to the wiring, electrode, or terminal that constitutes path B.

[0014] In the present invention, the terms "terminal," "input end," and "output end" refer to the points at which conductors within elements terminate. However, if the impedance of the conductor between elements is sufficiently low, a terminal is interpreted as any point on the conductor between elements or the entire conductor, not just a single point.

[0015] (Embodiment) [1 Circuit configuration of amplifier circuit 1] The circuit configuration of an amplifier circuit 1 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit configuration diagram of the amplifier circuit 1 according to this embodiment. As shown in the figure, the amplifier circuit 1 includes an amplifier 10 and an auxiliary amplifier 30. The amplifier 10 includes an input terminal 101, an output terminal 102, FETs 11 and 12, an LC parallel resonant circuit 20, capacitors 23 and 24, and an inductor 25. The auxiliary amplifier 30 includes an FET 31 and an LC parallel resonant circuit 40.

[0016] The input terminal 101 is an example of a first input terminal and is a terminal for inputting a high-frequency signal. The output terminal 102 is an example of a first output terminal and is a terminal for outputting a high-frequency signal.

[0017] FET11 is an example of a first amplifying element and is an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having a gate terminal g1 (first control terminal), a drain terminal d1 (first terminal), and a source terminal s1 (second terminal). FET12 is an example of a second amplifying element and is an n-channel MOSFET having a gate terminal g2 (second control terminal), a drain terminal d2 (third terminal), and a source terminal s2 (fourth terminal). FET31 is an example of a third amplifying element and is an n-channel MOSFET having a gate terminal g3 (third control terminal), a drain terminal d3 (fifth terminal), and a source terminal s3 (sixth terminal).

[0018] Each of FETs 11, 12, and 31 may be a p-channel MOSFET or another FET. If each of FETs 11, 12, and 31 is a p-channel MOSFET, the drain terminal and the source terminal are reversed. Also, each of FETs 11, 12, and 31 may be a bipolar transistor. If each of FETs 11, 12, and 31 is a bipolar transistor, the gate terminal of the FET becomes the base terminal, the drain terminal of the FET becomes the collector terminal, and the source terminal of the FET becomes the emitter terminal.

[0019] The LC parallel resonant circuit 20 is an example of a first LC parallel resonant circuit, and has a configuration in which a variable inductor 21 and a variable capacitor 22 are connected in parallel. The LC parallel resonant circuit 20 varies its resonant frequency in accordance with the frequency of a high-frequency signal input to the input terminal 101. The LC parallel resonant circuit 40 is an example of a second LC parallel resonant circuit, and has a configuration in which a variable inductor 41 and a variable capacitor 42 are connected in parallel. The LC parallel resonant circuit 40 varies its resonant frequency in accordance with the frequency of a high-frequency signal input to the input terminal 101. Note that the LC parallel resonant circuits 20 and 40 do not necessarily have the function of varying their resonant frequencies.

[0020] The gate terminal g1 is connected to the input terminal 101 via a capacitor 23. The drain terminal d1 is connected to the source terminal s2. The source terminal s1 is connected to ground via an inductor 25. The gate terminal g2 is connected to the drain terminal d3 and the LC parallel resonant circuit 40. The drain terminal d2 is connected to the output terminal 102 via a capacitor 24, and is also connected to the LC parallel resonant circuit 20. The gate terminal g3 is connected to the source terminal s2. The source terminal s3 is connected to ground.

[0021] According to the above connection configuration, the FET 11 and the FET 12 are cascode-connected, so that the amplifier circuit 1 can function as an amplifier circuit with a high gain.

[0022] For comparison, a conventional cascode-connected amplifier circuit is illustrated. FIG. 2A is a circuit diagram of an amplifier circuit 500 according to a comparative example. As shown in the figure, the amplifier circuit 500 according to the comparative example is a conventional cascode-connected amplifier circuit, and includes an input terminal 101, an output terminal 102, a bias terminal 105, FETs 11 and 12, an LC parallel resonant circuit 520, capacitors 23, 24, and 27, an inductor 25, and a resistive element 26. The amplifier circuit 500 according to the comparative example differs in configuration from the amplifier circuit 1 according to the embodiment in that the auxiliary amplifier 30 is not provided.

[0023] The FETs 11 and 12 are cascode-connected to each other. Generally, a low-noise amplifier circuit uses a cascode structure to obtain a high gain. In the amplifier circuit 500, the gain A is defined by Equation 1.

[0024] A=gm1×Rout (Formula 1)

[0025] gm1 is the mutual conductance of the FET 11, and Rout is the output resistance, as shown in Equation 2.

[0026] Rout=r_up / / r_down =r_up×r_down / (r_up+r_down) (Formula 2)

[0027] r_up is the impedance seen from the drain terminal of the FET 12 to the power supply side, and r_down is the impedance seen from the drain terminal of the FET 12 to the ground side. In other words, the output resistance Rout is the parallel impedance of r_up and r_down.

[0028] From equation 1, to increase the gain A, (1) Increase the current consumption (drain current Id) to increase gm1 (2) Use a multi-stage configuration of three or more FETs to increase the output resistance Rout. Examples include:

[0029] However, the above method (1) increases current consumption. Also, once gm1 saturates, further increasing the current does not increase the gain. Furthermore, the above method (2) does not allow the use of low-power supply voltage circuits when a multi-stage configuration is used. In other words, it is difficult to increase the gain while reducing power consumption using the above methods (1) and (2).

[0030] In contrast, the amplifier circuit 1 according to this embodiment can increase the output resistance Rout without increasing power consumption. Regarding r_up, the resonant frequency of the LC parallel resonant circuit 20 is adjusted so that high impedance is obtained at the frequency of the high-frequency signal. Meanwhile, regarding r_down, high impedance can be achieved by providing the auxiliary amplifier 30 and reducing the potential amplitude at point X (the connection point between the drain terminal d1 of FET 11 and the source terminal s2 of FET 12).

[0031] In the amplifier circuit 500 according to the comparative example, the potential Vg2 of the gate terminal of the FET 12 is fixed by the supply of a bias potential from the bias terminal 105. Therefore, in order to pass the drain current Id that oscillates at a high frequency, the gate-source voltage Vgs2 of the FET 12 fluctuates. If the potential at point X is Vx, the gate-source voltage Vgs2 is (Vg2-Vx), and therefore Vx also fluctuates in response to the oscillating behavior of the drain current Id.

[0032] In contrast to this, in the amplifier circuit 1 according to this embodiment, the potential Vg2 of the gate terminal g2 of the FET 12 fluctuates in response to the amplitude change of the drain current Id because the gate terminal g2 is connected to the drain terminal d3 of the auxiliary amplifier 30. Therefore, the gate-source voltage Vgs2 is (Vg2-Vx), and Vx is fixed in response to the amplitude change of the drain current Id.

[0033] FIG. 2B shows the current-voltage characteristics of the FET 12 according to the embodiment and the comparative example. In the amplifier circuit 500 according to the comparative example, the fluctuation of Vx is large, so the drain current Id also fluctuates in response to changes in the drain-source voltage Vds of the FET 12. In contrast, in the amplifier circuit 1 according to the embodiment, the fluctuation of Vx is small, so the drain-source voltage Vds of the FET 12 does not fluctuate, and the drain current Id fluctuates depending on the gate-source voltage Vgs. In this case, the drain current Id does not change with changes in the drain-source voltage Vds. This is equivalent to the drain-source resistance of the FET 12 being very large. This allows r_down to be increased. In other words, in the amplifier circuit 1 according to the embodiment, by passing a small current through the auxiliary amplifier 30, the output resistance Rout can be significantly increased, thereby increasing the gain A. This makes it possible to provide an amplifier circuit 1 with high gain while maintaining low power consumption.

[0034] [2. Circuit Configuration of Amplifier Circuit 2 According to Modification 1] 3 is a circuit configuration diagram of an amplifier circuit 2 according to a first modification of the embodiment. As shown in the figure, the amplifier circuit 2 according to this modification includes an amplifier 10A, an auxiliary amplifier 30, and switches 51 and 52. The amplifier circuit 2 according to this modification differs from the amplifier circuit 1 according to the embodiment in the configuration of the amplifier 10A and in the addition of switches 51 and 52. Therefore, in the following, a description of the amplifier circuit 2 according to this modification that is the same as that of the amplifier circuit 1 according to the embodiment will be omitted, and the description will focus on the different configurations.

[0035] The amplifier 10A includes an input terminal 101, an output terminal 102, FETs 11 and 12, an LC parallel resonant circuit 20, capacitors 23, 24 and 27, an inductor 25, a resistive element 26, and a switch 53.

[0036] The switch 53 is connected between the gate terminal g2 and the capacitor 27 and the resistive element 26. The capacitor 27 is connected between the switch 53 and the ground and functions as a grounded gate capacitance of the FET 12. The resistive element 26 is connected between the switch 53 and the bias terminal 105.

[0037] The switch 52 is an example of a first switch, connected between the source terminal s2 and the gate terminal g3, and switches between connection and disconnection of the source terminal s2 and the gate terminal g3. The switch 51 is an example of a second switch, connected between the gate terminal g2 and the drain terminal d3, and switches between connection and disconnection of the gate terminal g2 and the drain terminal d3.

[0038] 4A is a circuit state diagram of the amplifier circuit 2 according to the first modification of the embodiment when the gain is high. When the amplifier circuit 2 requires a gain higher than a predetermined value, the switches 51 and 52 are turned on. The switch 53 is turned off. This connects the auxiliary amplifier 30 to the amplifier 10A, and the amplifier circuit 2 can amplify the high-frequency signal input to the input terminal 101 with high gain while maintaining low power consumption.

[0039] 4B is a circuit state diagram of the amplifier circuit 2 according to the first modification of the embodiment when the gain is low. When the amplifier circuit 2 requires a gain equal to or less than a predetermined value, the switches 51 and 52 are in a non-conductive state. Also, the switch 53 is in a conductive state. As a result, the auxiliary amplifier 30 is not connected to the amplifier 10A, the gate terminal g2 is high-frequency grounded, and a bias voltage is supplied to the gate terminal g2 from the bias terminal 105. This enables the amplifier circuit 2 to amplify the high-frequency signal input to the input terminal 101 with low gain.

[0040] This allows the amplifier circuit 2 to control the switches 51 to 53 to appropriately select between a low gain mode and a high gain mode with reduced power consumption.

[0041] [3. Circuit Configuration of Amplifier Circuit 3 According to Modification 2] 5 is a circuit configuration diagram of an amplifier circuit 3 according to a second modification of the embodiment. As shown in the figure, the amplifier circuit 3 according to this modification includes an amplifier 10A, an auxiliary amplifier 30A, and switches 51, 52, and 54. The amplifier circuit 3 according to this modification differs from the amplifier circuit 2 according to the first modification in the configuration of the auxiliary amplifier 30A and in the addition of a switch 54. Therefore, in the following, a description of the amplifier circuit 3 according to this modification that is the same as that of the amplifier circuit 2 according to the first modification will be omitted, and the description will focus on the different configurations.

[0042] The auxiliary amplifier 30A includes FETs 31 and 32 and an LC parallel resonant circuit 40.

[0043] The FET 32 is an example of a fourth amplifying element, and is an n-channel MOSFET, and has a gate terminal g4 (fourth control terminal), a drain terminal d4 (seventh terminal), and a source terminal s4 (eighth terminal).

[0044] The FET 32 may be a p-channel MOSFET or other FETs. If the FET 32 is a p-channel MOSFET, the drain terminal and the source terminal are reversed. The FET 32 may also be a bipolar transistor. If the FET 32 is a bipolar transistor, the gate terminal of the FET 32 becomes the base terminal, the drain terminal of the FET 32 becomes the collector terminal, and the source terminal of the FET 32 becomes the emitter terminal.

[0045] The FET 32 is connected between the drain terminal d3 and the LC parallel resonant circuit 40. The gate terminal g4 is connected to the bias terminal 105 via the switch 54. The drain terminal d4 is connected to the LC parallel resonant circuit 40. The source terminal s4 is connected to the drain terminal d3. The gate terminal g2 is connected to the drain terminal d3 via the drain terminal d4 and the source terminal s4. The gate terminal g3 is connected to the source terminal s2 via the switch 52. The source terminal s3 is connected to ground.

[0046] According to the above-described connection configuration, the FET 31 and the FET 32 are cascode-connected, which makes it possible to provide an amplifier circuit 3 having a high gain with a lower current consumption. In addition, by suppressing the Miller effect in the auxiliary amplifier 30A, it is possible to improve reverse isolation and the K value.

[0047] [4. Circuit Configuration of Amplifier Circuit 4 According to Modification 3] 6 is a circuit configuration diagram of an amplifier circuit 4 according to a third modification of the embodiment. As shown in the figure, the amplifier circuit 4 according to this modification includes amplifiers 10 and 10B and FETs 31 and 31B. The amplifier circuit 4 according to this modification differs from the amplifier circuit 1 according to the embodiment in that it includes two amplifiers 10 and 10B, uses a portion of amplifier 10B as an auxiliary amplifier for amplifier 10, and uses a portion of amplifier 10 as an auxiliary amplifier for amplifier 10B. Therefore, in the following, the amplifier circuit 4 according to this modification will be described mainly with reference to the different configurations, and a description of the same configurations as those of the amplifier circuit 1 according to the embodiment will be omitted.

[0048] The amplifier 10 includes an input terminal 101, an output terminal 102, FETs 11 and 12, an LC parallel resonant circuit 20, capacitors 23 and 24, and an inductor 25. The amplifier 10 has the same configuration as the amplifier 10 of the amplifier circuit 1 according to the embodiment.

[0049] The amplifier 10B includes an input terminal 103, an output terminal 104, FETs 11B and 12B, an LC parallel resonant circuit 20B, capacitors 23B and 24B, and an inductor 25B.

[0050] Input terminal 103 is an example of a second input terminal, and is a terminal for inputting a high-frequency signal. Output terminal 104 is an example of a second output terminal, and is a terminal for outputting a high-frequency signal.

[0051] FET 11B is an example of a fifth amplifying element, an n-channel MOSFET, and has a gate terminal g5 (fifth control terminal), a drain terminal d5 (ninth terminal), and a source terminal s5 (tenth terminal). FET 12B is an example of a sixth amplifying element, an n-channel MOSFET, and has a gate terminal g6 (sixth control terminal), a drain terminal d6 (eleventh terminal), and a source terminal s6 (twelfth terminal).

[0052] Each of FETs 11B and 12B may be a p-channel MOSFET or other FET. If each of FETs 11B and 12B is a p-channel MOSFET, the drain terminal and the source terminal are reversed. Also, each of FETs 11B and 12B may be a bipolar transistor. If each of FETs 11B and 12B is a bipolar transistor, the gate terminal of the FET becomes the base terminal, the drain terminal of the FET becomes the collector terminal, and the source terminal of the FET becomes the emitter terminal.

[0053] The LC parallel resonant circuit 20B is an example of a second LC parallel resonant circuit, and has a configuration in which a variable inductor 21B and a variable capacitor 22B are connected in parallel. The LC parallel resonant circuit 20B varies its resonant frequency in accordance with the frequency of a high-frequency signal input to the input terminal 103. Note that the LC parallel resonant circuit 20B does not necessarily have the function of varying the resonant frequency.

[0054] The gate terminal g1 is connected to the input terminal 101 via a capacitor 23. The drain terminal d1 is connected to the source terminal s2. The source terminal s1 is connected to ground via an inductor 25. The gate terminal g2 is connected to the drain terminal d6 and the LC parallel resonant circuit 20B. The drain terminal d2 is connected to the output terminal 102 via a capacitor 24, and is also connected to the LC parallel resonant circuit 20.

[0055] The gate terminal g5 is connected to the input terminal 103 via a capacitor 23B. The drain terminal d5 is connected to the source terminal s6. The source terminal s5 is connected to ground via an inductor 25B. The gate terminal g6 is connected to the drain terminal d2 and the LC parallel resonant circuit 20. The drain terminal d6 is connected to the output terminal 104 via a capacitor 24B and is also connected to the LC parallel resonant circuit 20B.

[0056] FET31 is an example of a third amplifying element, an n-channel MOSFET, and has a gate terminal g3 (third control terminal), a drain terminal d3 (fifth terminal), and a source terminal s3 (sixth terminal). FET31B is an example of a seventh amplifying element, an n-channel MOSFET, and has a gate terminal g7 (seventh control terminal), a drain terminal d7 (thirteenth terminal), and a source terminal s7 (fourteenth terminal).

[0057] The gate terminal g3 is connected to the source terminal s2. The drain terminal d3 is connected to the gate terminal g2 and the LC parallel resonant circuit 20B. The source terminal s3 is connected to ground. The gate terminal g7 is connected to the source terminal s6. The drain terminal d7 is connected to the gate terminal g6 and the LC parallel resonant circuit 20B. The source terminal s7 is connected to ground.

[0058] According to the above connection configuration, FET11 and FET12 are cascode-connected, and FET11B and FET12B are cascode-connected.

[0059] In the above circuit configuration, for example, when a high-frequency signal is input to input terminal 101, amplified by amplifier 10, and output from output terminal 102, FETs 11B, 12B, and 31B are turned off, and FET 31 and LC parallel resonant circuit 20B function as an auxiliary amplifier for amplifier 10. Furthermore, when a high-frequency signal is input to input terminal 103, amplified by amplifier 10B, and output from output terminal 104, FETs 11, 12, and 31 are turned off, and FET 31B and LC parallel resonant circuit 20 function as an auxiliary amplifier for amplifier 10B.

[0060] This allows a part of the amplifier (the LC parallel resonant circuit) that is in the off state to be used as an auxiliary amplifier, thereby providing an amplifier circuit 4 that has high gain and a small area while maintaining low power consumption.

[0061] [5. Circuit Configuration of Amplifier Circuit 5 According to Modification 4] 7 is a circuit diagram of an amplifier circuit 5 according to a fourth modification of the embodiment. As shown in the figure, the amplifier circuit 5 according to this modification includes amplifiers 10A and 10C, FETs 31 and 31B, and switches 51, 52, 55, and 56. The amplifier circuit 5 according to this modification differs from the amplifier circuit 3 according to the second modification in that it includes two amplifiers 10A and 10C, and uses a portion of amplifier 10C as an auxiliary amplifier for amplifier 10A, and a portion of amplifier 10A as an auxiliary amplifier for amplifier 10C. Therefore, the following description of the amplifier circuit 5 according to this modification will omit a description of the same configuration as the amplifier circuit 3 according to the second modification, and will focus on the different configuration.

[0062] The amplifier 10A includes an input terminal 101, an output terminal 102, FETs 11 and 12, an LC parallel resonant circuit 20, capacitors 23, 24, and 27, an inductor 25, a resistive element 26, and a switch 53. The amplifier 10A has the same configuration as the amplifier 10A of the amplifier circuit 2 according to the first modification and the amplifier 10A of the amplifier circuit 3 according to the second modification.

[0063] The amplifier 10C includes an input terminal 103, an output terminal 104, FETs 11C and 12C, an LC parallel resonant circuit 20C, capacitors 23C, 24C and 27C, an inductor 25C, a resistive element 26C, and a switch 57.

[0064] Input terminal 103 is an example of a second input terminal, and is a terminal for inputting a high-frequency signal. Output terminal 104 is an example of a second output terminal, and is a terminal for outputting a high-frequency signal.

[0065] FET11C is an example of a fifth amplifying element, an n-channel MOSFET, and has a gate terminal g5 (fifth control terminal), a drain terminal d5 (ninth terminal), and a source terminal s5 (tenth terminal). FET12C is an example of a sixth amplifying element, an n-channel MOSFET, and has a gate terminal g6 (sixth control terminal), a drain terminal d6 (eleventh terminal), and a source terminal s6 (twelfth terminal).

[0066] Each of FETs 11C and 12C may be a p-channel MOSFET or other FET. If each of FETs 11C and 12C is a p-channel MOSFET, the drain terminal and the source terminal are reversed. Also, each of FETs 11C and 12C may be a bipolar transistor. If each of FETs 11C and 12C is a bipolar transistor, the gate terminal of the FET becomes the base terminal, the drain terminal of the FET becomes the collector terminal, and the source terminal of the FET becomes the emitter terminal.

[0067] The LC parallel resonant circuit 20C is an example of a second LC parallel resonant circuit, and has a configuration in which a variable inductor 21C and a variable capacitor 22C are connected in parallel. The LC parallel resonant circuit 20C varies its resonant frequency in accordance with the frequency of a high-frequency signal input to the input terminal 103. Note that the LC parallel resonant circuit 20C does not necessarily have the function of varying the resonant frequency.

[0068] The switch 53 is connected between the gate terminal g2 and the capacitor 27 and the resistive element 26. The capacitor 27 is connected between the switch 53 and the ground and functions as a grounded gate capacitance of the FET 12. The resistive element 26 is connected between the switch 53 and the bias terminal 105.

[0069] The switch 57 is connected between the gate terminal g6 and the capacitor 27C and the resistor 26C. The capacitor 27C is connected between the switch 57 and the ground and functions as a grounded gate capacitance for the FET 12C. The resistor 26C is connected between the switch 57 and the bias terminal 106.

[0070] The switch 52 is an example of a third switch and is connected between the source terminal s2 and the gate terminal g3, switching between connection and disconnection of the source terminal s2 and the gate terminal g3. The switch 51 is an example of a fourth switch and is connected between the gate terminal g2 and the drain terminal d3, switching between connection and disconnection of the gate terminal g2 and the drain terminal d3. The switch 56 is an example of a fifth switch and is connected between the source terminal s6 and the gate terminal g7, switching between connection and disconnection of the source terminal s6 and the gate terminal g7. The switch 55 is an example of a sixth switch and is connected between the gate terminal g6 and the drain terminal d2, switching between connection and disconnection of the gate terminal g6 and the drain terminal d2.

[0071] The gate terminal g1 is connected to the input terminal 101 via a capacitor 23. The drain terminal d1 is connected to the source terminal s2. The source terminal s1 is connected to ground via an inductor 25. The gate terminal g2 is connected to the drain terminal d6 and the LC parallel resonant circuit 20C via a switch 51. The drain terminal d2 is connected to the output terminal 102 via a capacitor 24, and is also connected to the LC parallel resonant circuit 20.

[0072] The gate terminal g5 is connected to the input terminal 103 via a capacitor 23C. The drain terminal d5 is connected to the source terminal s6. The source terminal s5 is connected to ground via an inductor 25C. The gate terminal g6 is connected to the drain terminal d2 and the LC parallel resonant circuit 20 via a switch 55. The drain terminal d6 is connected to the output terminal 104 via a capacitor 24C and is also connected to the LC parallel resonant circuit 20C.

[0073] FET31 is an example of a third amplifying element, an n-channel MOSFET, and has a gate terminal g3 (third control terminal), a drain terminal d3 (fifth terminal), and a source terminal s3 (sixth terminal). FET31B is an example of a seventh amplifying element, an n-channel MOSFET, and has a gate terminal g7 (seventh control terminal), a drain terminal d7 (thirteenth terminal), and a source terminal s7 (fourteenth terminal).

[0074] The gate terminal g3 is connected to the source terminal s2 via a switch 52. The drain terminal d3 is connected to the gate terminal g2 via a switch 51 and is also connected to the LC parallel resonant circuit 20C. The source terminal s3 is connected to ground. The gate terminal g7 is connected to the source terminal s6 via a switch 56. The drain terminal d7 is connected to the gate terminal g6 via a switch 55 and is also connected to the LC parallel resonant circuit 20C. The source terminal s7 is connected to ground.

[0075] According to the above connection configuration, FET11 and FET12 are cascode-connected, and FET11C and FET12C are cascode-connected.

[0076] FIG. 8A is a circuit state diagram when the amplifier 10A of the amplifier circuit 5 according to the fourth modification of the embodiment is operating. When the amplifier 10A performs amplification with a gain higher than a predetermined value, the switches 51 and 52 are conductive. The switch 53 is non-conductive. The switches 55 and 56 are non-conductive. This results in the FET 31 and the LC parallel resonant circuit 20C being connected to the amplifier 10A. In other words, when the amplifier 10A performs amplification with a high gain, the FET 31 and the LC parallel resonant circuit 20C function as an auxiliary amplifier for the amplifier 10A. This allows the amplifier circuit 5 to amplify a high-frequency signal input to the input terminal 101 with high gain while maintaining low power consumption.

[0077] Although not shown, when amplifier 10A performs amplification with a gain equal to or less than a predetermined value, switches 51 and 52 are in a non-conductive state. Also, switch 53 is in a conductive state. As a result, the auxiliary amplifier is not connected to amplifier 10A, gate terminal g2 is high-frequency grounded, and a bias voltage is supplied to gate terminal g2 from bias terminal 105, enabling amplifier circuit 5 to amplify the high-frequency signal input to input terminal 101 with low gain.

[0078] FIG. 8B is a circuit state diagram when the amplifier 10C of the amplifier circuit 5 according to the fourth modification of the embodiment is operating. When the amplifier 10C performs amplification with a gain higher than a predetermined value, the switches 55 and 56 are conductive. The switch 57 is non-conductive. The switches 51 and 52 are non-conductive. As a result, the FET 31B and the LC parallel resonant circuit 20 are connected to the amplifier 10C. That is, when the amplifier 10C performs amplification with a high gain, the FET 31B and the LC parallel resonant circuit 20 function as an auxiliary amplifier for the amplifier 10C. This allows the amplifier circuit 5 to amplify a high-frequency signal input to the input terminal 103 with high gain while maintaining low power consumption.

[0079] Although not shown, when amplifier 10C performs amplification with a gain equal to or less than a predetermined value, switches 55 and 56 are turned off. Also, switch 57 is turned on. As a result, the auxiliary amplifier is not connected to amplifier 10C, gate terminal g6 is high-frequency grounded, and a bias voltage is supplied to gate terminal g6 from bias terminal 106. This enables amplifier circuit 5 to amplify the high-frequency signal input to input terminal 103 with low gain.

[0080] This allows the amplifier circuit 5 to appropriately select between a low-gain mode and a high-gain mode with reduced power consumption by controlling the switches 51, 52, 53, 55, 56, and 57. Furthermore, a part of the amplifier that is turned off (the LC parallel resonant circuit) can be used as an auxiliary amplifier. Therefore, it is possible to provide an amplifier circuit 5 that has high gain and a small area while maintaining low power consumption.

[0081] [6 Effects etc.] As described above, the amplifier circuit 1 according to this embodiment includes the input terminal 101 and the output terminal 102, the FET 11 having the gate terminal g1, the drain terminal d1, and the source terminal s1, the FET 12 having the gate terminal g2, the drain terminal d2, and the source terminal s2, the FET 31 having the gate terminal g3, the drain terminal d3, and the source terminal s3, and the LC parallel resonant circuits 20 and 40, in which the gate terminal g1 is connected to the input terminal 101, the drain terminal d1 is connected to the source terminal s2, the source terminal s1 is connected to ground, the gate terminal g2 is connected to the drain terminal d3 and the LC parallel resonant circuit 40, the drain terminal d2 is connected to the output terminal 102 and the LC parallel resonant circuit 20, the gate terminal g3 is connected to the source terminal s2, and the source terminal s3 is connected to ground.

[0082] According to this, since fluctuations at point X (the connection point of drain terminal d1 and source terminal s2) are small, the drain-source voltage Vds of FET 12 does not fluctuate, and the drain current Id varies depending on the gate-source voltage Vgs. In this case, since the drain current Id does not change with changes in the drain-source voltage Vds, the drain-source resistance of FET 12 becomes very large. In other words, by passing a small current through the auxiliary amplifier 30, the output resistance Rout can be significantly increased, and the gain A can be increased. Therefore, it is possible to provide an amplifier circuit 1 that has a high gain while maintaining low power consumption.

[0083] Furthermore, for example, in the amplifier circuit 1, the LC parallel resonant circuits 20 and 40 vary the resonant frequency in accordance with the frequency of the high-frequency signal input to the input terminal 101.

[0084] This makes it possible to increase the gain of a desired frequency and to allow unnecessary frequency components to escape to the power supply terminal side.

[0085] For example, the amplifier circuit 2 according to the first modification further includes a switch 52 that switches between connection and disconnection of the source terminal s2 and the gate terminal g3, and a switch 51 that switches between connection and disconnection of the gate terminal g2 and the drain terminal d3.

[0086] For example, in amplifier circuit 2, when the gain of amplifier circuit 2 is higher than a predetermined value, switches 51 and 52 are conductive, and when the gain of amplifier circuit 2 is equal to or lower than the predetermined value, switches 51 and 52 are non-conductive.

[0087] This allows the amplifier circuit 2 to appropriately select between a low gain mode and a high gain mode with reduced power consumption by switching the switches 51 and 52 between conductive and non-conductive states.

[0088] For example, the amplifier circuit 2 further includes a resistive element 26 connected between the gate terminal g2 and the bias terminal 105, and a capacitor 27 connected between the gate terminal g2 and ground.

[0089] This makes it possible to select between a high gain mode in which the gate terminal g2 is connected to the auxiliary amplifier 30 and a low gain mode in which the gate terminal g2 is connected to the bias terminal 105.

[0090] Also, for example, in the amplifier circuits 1 and 2, the FETs 11 and 12 are cascode-connected.

[0091] This makes it possible to provide the amplifier circuits 1 and 2 capable of high gain operation.

[0092] For example, the amplifier circuit 3 according to the second modification further includes an FET 32 having a gate terminal g4, ​​a drain terminal d4, and a source terminal s4, the FET 32 being connected between the drain terminal d3 and the LC parallel resonant circuit 40, the gate terminal g4 being connected to the bias terminal 105, the drain terminal d4 being connected to the LC parallel resonant circuit 40, the source terminal s4 being connected to the drain terminal d3, and the gate terminal g2 being connected to the drain terminal d3 via the drain terminal d4 and the source terminal s4.

[0093] This also makes it possible to improve reverse isolation by suppressing the Miller effect, thereby improving the K value.

[0094] Furthermore, for example, in the amplifier circuit 3, the FETs 31 and 32 are cascode-connected.

[0095] This makes it possible to provide an amplifier circuit 3 that consumes less current and has a high gain.

[0096] For example, the amplifier circuit 4 according to the third modification further includes an input terminal 103 and an output terminal 104, an FET 11B having a gate terminal g5, a drain terminal d5, and a source terminal s5, an FET 12B having a gate terminal g6, a drain terminal d6, and a source terminal s6, and an FET 31B having a gate terminal g7, a drain terminal d7, and a source terminal s7, and the gate terminal g1 is connected to the input terminal 101, the gate terminal g5 is connected to the input terminal 103, the drain terminal d1 is connected to the source terminal s2, and the drain terminal d5 is connected to the source terminal s3. The gate terminal g2 is connected to the drain terminal d3 and the LC parallel resonant circuit 20B, the gate terminal g6 is connected to the drain terminal d7 and the LC parallel resonant circuit 20B, the drain terminal d2 is connected to the output terminal 102 and the LC parallel resonant circuit 20B, the drain terminal d6 is connected to the output terminal 104 and the LC parallel resonant circuit 20B, the gate terminal g3 is connected to the source terminal s2, the gate terminal g7 is connected to the source terminal s6, and the source terminals s3 and s7 are connected to ground.

[0097] This allows a part of the amplifier (the LC parallel resonant circuit) that is in the off state to be used as an auxiliary amplifier, thereby providing an amplifier circuit 4 that has high gain and a small area while maintaining low power consumption.

[0098] For example, the amplifier circuit 5 according to variant example 4 further includes a switch 52 that switches between connection and disconnection of the source terminal s2 and the gate terminal g3, a switch 51 that switches between connection and disconnection of the gate terminal g2 and the drain terminal d3, a switch 56 that switches between connection and disconnection of the source terminal s6 and the gate terminal g7, and a switch 55 that switches between connection and disconnection of the gate terminal g6 and the drain terminal d7.

[0099] For example, in amplifier circuit 5, when FETs 11 and 12 are operated for amplification with a gain higher than a predetermined value, switches 51 and 52 are in a conductive state and switches 55 and 56 are in a non-conductive state, and when FETs 11C and 12C are operated for amplification with a gain higher than a predetermined value, switches 51 and 52 are in a non-conductive state and switches 55 and 56 are in a conductive state.

[0100] This allows the amplifier circuit 5 to appropriately select between a low-gain mode and a high-gain mode with reduced power consumption by controlling the switches 51, 52, 55, and 56. Furthermore, a portion of the amplifier (the LC parallel resonant circuit) that is turned off can be used as an auxiliary amplifier. Therefore, it is possible to provide an amplifier circuit 5 that has high gain and a small area while maintaining low power consumption.

[0101] Furthermore, for example, in the amplifier circuit 4, the FETs 11B and 12B are cascode-connected. Furthermore, for example, in the amplifier circuit 5, the FETs 11C and 12C are cascode-connected.

[0102] This makes it possible to provide the amplifier circuits 4 and 5 capable of high gain operation.

[0103] (Other embodiments) Although the amplifier circuit according to the present invention has been described above based on the embodiments and modifications, the amplifier circuit according to the present invention is not limited to the above embodiments and modifications. The present invention also includes other embodiments realized by combining any of the components in the above embodiments and modifications, modifications obtained by applying various modifications to the above embodiments and modifications that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above amplifier circuit.

[0104] For example, in the circuit configuration of the amplifier circuit according to the above-described embodiment and modification, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings.

[0105] The features of the amplifier circuits described based on the above-described embodiment and modifications will be described below.

[0106] <1> a first input terminal and a first output terminal; a first amplifying element having a first control terminal, a first terminal, and a second terminal; a second amplifying element having a second control terminal, a third terminal, and a fourth terminal; a third amplifying element having a third control terminal, a fifth terminal, and a sixth terminal; a first LC parallel resonant circuit and a second LC parallel resonant circuit, the first control terminal is connected to the first input terminal; the first terminal is connected to the fourth terminal; the second terminal is connected to ground; the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit; the third terminal is connected to the first output terminal and the first LC parallel resonant circuit; the third control terminal is connected to the fourth terminal; the sixth terminal is connected to ground,

[0107] <2> the first LC parallel resonant circuit and the second LC parallel resonant circuit vary their resonant frequencies in accordance with the frequency of a high-frequency signal input to the first input terminal; <1> The amplifier circuit according to claim 1.

[0108] <3> moreover, a first switch that switches between connection and disconnection of the fourth terminal and the third control terminal; a second switch that switches between connection and disconnection of the second control terminal and the fifth terminal; <1> or <2> The amplifier circuit according to claim 1.

[0109] <4> When the gain of the amplifier circuit is higher than a predetermined value, the first switch and the second switch are in a conductive state; When the gain of the amplifier circuit is equal to or less than a predetermined value, the first switch and the second switch are in a non-conductive state. <3> The amplifier circuit according to claim 1.

[0110] <5> moreover, a resistive element connected between the second control terminal and a bias terminal; a capacitor connected between the second control terminal and ground; <1> ~ <4> 10. The amplifier circuit according to claim 9,

[0111] <6> the first amplifying element and the second amplifying element are cascode-connected; <1> ~ <4> 10. The amplifier circuit according to claim 9,

[0112] <7> moreover, a fourth amplifying element having a fourth control terminal, a seventh terminal, and an eighth terminal; the fourth amplifying element is connected between the fifth terminal and the second LC parallel resonant circuit, the fourth control terminal is connected to a bias terminal; the seventh terminal is connected to the second LC parallel resonant circuit; the eighth terminal is connected to the fifth terminal, the second control terminal is connected to the fifth terminal via the seventh terminal and the eighth terminal; <1> ~ <6> 10. The amplifier circuit according to claim 9,

[0113] <8> the third amplifying element and the fourth amplifying element are cascode-connected. <7> The amplifier circuit according to claim 1.

[0114] <9> moreover a second input terminal and a second output terminal; a fifth amplifying element having a fifth control terminal, a ninth terminal, and a tenth terminal; a sixth amplifying element having a sixth control terminal, an eleventh terminal, and a twelfth terminal; a seventh amplifying element having a seventh control terminal, a thirteenth terminal, and a fourteenth terminal; the first control terminal is connected to the first input terminal; the fifth control terminal is connected to the second input terminal; the first terminal is connected to the fourth terminal; the ninth terminal is connected to the twelfth terminal; the second terminal is connected to ground; the tenth terminal is connected to ground; the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit; the sixth control terminal is connected to the thirteenth terminal and the first LC parallel resonant circuit; the third terminal is connected to the first output terminal and the first LC parallel resonant circuit; the eleventh terminal is connected to the second output terminal and the second LC parallel resonant circuit; the third control terminal is connected to the fourth terminal; the seventh control terminal is connected to the twelfth terminal; the sixth terminal is connected to ground; the fourteenth terminal is connected to ground; <1> or <2> The amplifier circuit according to claim 1.

[0115] <10> moreover, a third switch that switches between connection and disconnection of the fourth terminal and the third control terminal; a fourth switch that switches between connection and disconnection of the second control terminal and the fifth terminal; a fifth switch that switches between connection and disconnection of the twelfth terminal and the seventh control terminal; a sixth switch that switches between connection and disconnection of the sixth control terminal and the thirteenth terminal; <9> The amplifier circuit according to claim 1.

[0116] <11> When the first amplifying element and the second amplifying element are caused to perform an amplifying operation with a gain higher than a predetermined value, the third switch and the fourth switch are in a conductive state, and the fifth switch and the sixth switch are in a non-conductive state; When the fifth amplifying element and the sixth amplifying element are caused to perform an amplification operation with a gain higher than the predetermined value, the third switch and the fourth switch are brought into a non-conductive state, and the fifth switch and the sixth switch are brought into a conductive state. <10> The amplifier circuit according to claim 1.

[0117] <12> the fifth amplifying element and the sixth amplifying element are cascode-connected. <9> ~ <11> 10. The amplifier circuit according to claim 9, [Industrial Applicability]

[0118] The present invention can be widely used in communication devices such as mobile phones as a power amplifier circuit disposed in a multi-band front end section. [Explanation of symbols]

[0119] 1, 2, 3, 4, 5, 500 amplifier circuit 10, 10A, 10B, 10C amplifiers 11, 11B, 11C, 12, 12B, 12C, 31, 31B, 32 FET 20, 20B, 20C, 40, 520 LC parallel resonant circuit 21, 21B, 21C, 41 Variable inductors 22, 22B, 22C, 42 variable capacitors 23, 23B, 23C, 24, 24B, 24C, 27, 27C capacitors 25, 25B, 25C inductors 26, 26C resistor element 30, 30A auxiliary amplifier 51, 52, 53, 54, 55, 56, 57 Switches 101, 103 input terminals 102, 104 output terminals 105, 106 Bias terminals

Claims

1. a first input terminal and a first output terminal; a first amplifying element having a first control terminal, a first terminal, and a second terminal; a second amplifying element having a second control terminal, a third terminal, and a fourth terminal; a third amplifying element having a third control terminal, a fifth terminal, and a sixth terminal; a first LC parallel resonant circuit and a second LC parallel resonant circuit, the first control terminal is connected to the first input terminal; the first terminal is connected to the fourth terminal; the second terminal is connected to ground; the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit; the third terminal is connected to the first output terminal and the first LC parallel resonant circuit; the third control terminal is connected to the fourth terminal; The sixth terminal is connected to ground. Amplification circuit.

2. the first LC parallel resonant circuit and the second LC parallel resonant circuit vary their resonant frequencies in accordance with the frequency of a high-frequency signal input to the first input terminal; 2. The amplifier circuit according to claim 1.

3. moreover, a first switch that switches between connection and disconnection of the fourth terminal and the third control terminal; a second switch that switches between connection and disconnection of the second control terminal and the fifth terminal, 2. The amplifier circuit according to claim 1.

4. When the gain of the amplifier circuit is higher than a predetermined value, the first switch and the second switch are in a conductive state; When the gain of the amplifier circuit is equal to or less than a predetermined value, the first switch and the second switch are in a non-conductive state.

4. The amplifier circuit according to claim 3.

5. moreover, a resistive element connected between the second control terminal and a bias terminal; a capacitor connected between the second control terminal and ground.

4. The amplifier circuit according to claim 3.

6. the first amplifying element and the second amplifying element are cascode-connected.

2. The amplifier circuit according to claim 1.

7. moreover, a fourth amplifying element having a fourth control terminal, a seventh terminal, and an eighth terminal; the fourth amplifying element is connected between the fifth terminal and the second LC parallel resonant circuit, the fourth control terminal is connected to a bias terminal; the seventh terminal is connected to the second LC parallel resonant circuit; the eighth terminal is connected to the fifth terminal, the second control terminal is connected to the fifth terminal via the seventh terminal and the eighth terminal; The amplifier circuit according to any one of claims 1 to 6.

8. the third amplifying element and the fourth amplifying element are cascode-connected.

8. The amplifier circuit according to claim 7.

9. moreover a second input terminal and a second output terminal; a fifth amplifying element having a fifth control terminal, a ninth terminal, and a tenth terminal; a sixth amplifying element having a sixth control terminal, an eleventh terminal, and a twelfth terminal; a seventh amplifying element having a seventh control terminal, a thirteenth terminal, and a fourteenth terminal; the first control terminal is connected to the first input terminal; the fifth control terminal is connected to the second input terminal; the first terminal is connected to the fourth terminal; the ninth terminal is connected to the twelfth terminal; the second terminal is connected to ground; the tenth terminal is connected to ground; the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit; the sixth control terminal is connected to the thirteenth terminal and the first LC parallel resonant circuit; the third terminal is connected to the first output terminal and the first LC parallel resonant circuit; the eleventh terminal is connected to the second output terminal and the second LC parallel resonant circuit; the third control terminal is connected to the fourth terminal; the seventh control terminal is connected to the twelfth terminal; the sixth terminal is connected to ground; the fourteenth terminal is connected to ground; 2. The amplifier circuit according to claim 1.

10. moreover, a third switch that switches between connection and disconnection of the fourth terminal and the third control terminal; a fourth switch that switches between connection and disconnection of the second control terminal and the fifth terminal; a fifth switch that switches between connection and disconnection of the twelfth terminal and the seventh control terminal; a sixth switch that switches between connection and disconnection of the sixth control terminal and the thirteenth terminal, 10. The amplifier circuit according to claim 9.

11. When the first amplifying element and the second amplifying element are caused to perform an amplifying operation with a gain higher than a predetermined value, the third switch and the fourth switch are brought into a conductive state, and the fifth switch and the sixth switch are brought into a non-conductive state, When the fifth amplifying element and the sixth amplifying element are caused to perform an amplification operation with a gain higher than the predetermined value, the third switch and the fourth switch are brought into a non-conductive state, and the fifth switch and the sixth switch are brought into a conductive state. The amplifier circuit according to claim 10.

12. the fifth amplifying element and the sixth amplifying element are cascode-connected. The amplifier circuit according to any one of claims 9 to 11.

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