Differential signal output circuit and differential clock generation circuit

Abstract

To provide a differential signal output circuit which can be realized by a CMOS process and can output a differential output signal of a constant level regardless of the configuration of a termination circuit, and to provide a differential clock generation circuit to which the differential signal output circuit is applied.SOLUTION: The differential signal output circuit includes an output circuit including a pair of MOSFETs that output a differential output signal, a control circuit that generates a control voltage based on the differential output signal, and a drive circuit that drives the pair of MOSFETs based on a differential input signal so that a low level of the differential output signal becomes a level corresponding to the control voltage.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to a differential signal output circuit and a differential clock generation circuit. [Background technology]

[0002] The following techniques are known as techniques related to differential signal output circuits. For example, Patent Document 1 describes a vibrating device including an oscillator circuit that generates an oscillation signal by oscillating a vibrating element, and an output buffer circuit that outputs a clock signal based on the oscillation signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-84161 Summary of the Invention [Problem to be solved by the invention]

[0004] ECL (Emitter-Coupled Logic) is a method for implementing logic circuits that include differential amplifier circuits composed of bipolar transistors. ECL achieves high speeds by operating bipolar transistors in a non-saturated state. In ECL, the emitters of a pair of transistors that make up the input differential pair are coupled to each other and connected to a negative power supply through a constant current source. Because ECL requires a negative power supply, it is difficult to apply it to general applications. Subsequently, PECL (Positive ECL), which uses a positive power supply, and LVPECL (Low Voltage PECL), which can be driven at a lower voltage, were developed, and these are now used in high-performance computing applications such as mainframes and supercomputers, as well as in communications infrastructure.

[0005] A constant current output method is one way to realize an LVPECL differential signal output circuit using a more conventional CMOS process. However, this method has the problem that the level of the differential output signal changes depending on the configuration of the termination circuit.

[0006] The disclosed technology has been made in consideration of the above points, and aims to provide a differential signal output circuit that can be realized using a CMOS process and is capable of outputting a differential output signal of a constant level regardless of the configuration of the termination circuit, and a differential clock generation circuit that applies the same. [Means for solving the problem]

[0007] The differential signal output circuit according to the disclosed technology includes an output circuit including a pair of MOSFETs that output a differential output signal, a control circuit that generates a control voltage based on the differential output signal, and a drive circuit that drives the pair of MOSFETs based on a differential input signal so that the low level of the differential output signal becomes a level corresponding to the control voltage.

[0008] The pair of MOSFETs may form a source follower. Each of the pair of MOSFETs may be an n-channel type, with its drain connected to a power supply line, its source connected to an output terminal from which the differential output signal is output, and its gate connected to the output of the drive circuit.

[0009] The control circuit may generate the control voltage so that the level of the intermediate voltage of the differential output signal matches the level of a reference voltage.

[0010] The control circuit may include an operational amplifier circuit having an inverting input terminal to which the intermediate voltage is input and a non-inverting input terminal to which a reference voltage is input.

[0011] The differential clock generation circuit according to the disclosed technology includes the above-described differential signal output circuit, an oscillation circuit that outputs an oscillation signal having a constant frequency, and a conversion circuit that converts the oscillation signal into a differential signal and outputs the converted signal as the differential input signal. [Effects of the Invention]

[0012] According to the disclosed technology, a differential signal output circuit that can be realized by a CMOS process and can output a differential output signal of a constant level regardless of the configuration of the termination circuit, and a differential clock generation circuit that applies this circuit, are provided. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing an example of a configuration of a differential signal output circuit according to an embodiment of the disclosed technique; [Figure 2] 1 is an equivalent circuit diagram showing an example of a configuration of a differential signal output circuit and a termination circuit according to an embodiment of the disclosed technique; [Figure 3] 10 is a time chart showing an example of an operation waveform of each part of a differential signal output circuit according to an embodiment of the disclosed technique; [Figure 4A] FIG. 10 is an equivalent circuit diagram showing another example of the configuration of the termination circuit according to the embodiment of the disclosed technique. [Figure 4B] FIG. 10 is an equivalent circuit diagram showing another example of the configuration of the termination circuit according to the embodiment of the disclosed technique. [Figure 5] FIG. 1 is a diagram illustrating an example of a configuration of a differential signal output circuit according to a comparative example. [Figure 6] FIG. 10 is a block diagram illustrating an example of a configuration of a differential clock generation circuit according to another embodiment of the disclosed technology. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant description will be omitted.

[0015] [First embodiment] 1 is a block diagram showing an example of the configuration of a differential signal output circuit 10 according to an embodiment of the disclosed technique. The differential signal output circuit 10 receives a differential input signal S in_A , S in_B Differential output signal S according to out_A , S out_B The differential signal output circuit 10 includes a drive circuit 11, an output circuit 12, and a control circuit 13. The differential signal output circuit 10 may be formed on a semiconductor substrate. A termination circuit 60 is connected to output terminals 14A and 14B of the differential signal output circuit 10. A differential input signal S in_A and S in_B Similarly, the logic levels of the differential output signal S out_A and S out_B The logic levels of are opposite to each other.

[0016] The output circuit 12 outputs a differential output signal S out_A , S out_B The control circuit 13 has a pair of MOSFETs that output a differential output signal S out_A , S out_B Based on the control voltage V X The driver circuit 11 generates a differential output signal S out_A , S out_B The low level of the control voltage V X The differential input signal S in_A , S in_B A pair of MOSFETs constituting the output circuit 12 are driven based on the above.

[0017] 2 is an equivalent circuit diagram showing an example of the configuration of the differential signal output circuit 10 and the termination circuit 60. The drive circuit 11 has four CMOS inverters 21, 22, 23, and 24. The CMOS inverter 21 has a p-channel MOSFET (hereinafter referred to as p-MOS) 31 and an n-channel MOSFET (hereinafter referred to as n-MOS) 32. The p-MOS 31 has a source connected to a power supply line and a drain connected to the drain of the n-MOS 32. The n-MOS 32 has a source connected to a ground line. The gates of the p-MOS 31 and n-MOS 32 are connected to each other and serve as input terminals of the CMOS inverter 21. The drains of the p-MOS 31 and n-MOS 32 are connected to each other and serve as output terminals of the CMOS inverter 21. The CMOS inverter 21 receives a differential input signal S input to its input terminals. in_A The signal S is the inverted logic level of 1_A Output.

[0018] The CMOS inverter 22 has a p-MOS 33 and an n-MOS 34. The p-MOS 33 has a source connected to a power supply line and a drain connected to the drain of the n-MOS 34. The n-MOS 34 has a source connected to a ground line. The gates of the p-MOS 33 and n-MOS 34 are connected to each other and serve as input terminals of the CMOS inverter 22. The drains of the p-MOS 33 and n-MOS 34 are connected to each other and serve as output terminals of the CMOS inverter 22. The CMOS inverter 22 receives a differential input signal S in_B The signal S is the inverted logic level of 1_B Output.

[0019] The CMOS inverter 23 has a p-MOS 35 and an n-MOS 36. The source of the p-MOS 35 is connected to the power supply line, and the drain is connected to the drain of the n-MOS 36. The source of the n-MOS 36 is connected to a node n1. The gates of the p-MOS 35 and n-MOS 36 are connected to each other and serve as the input terminals of the CMOS inverter 23. The drains of the p-MOS 35 and n-MOS 36 are connected to each other and serve as the output terminals of the CMOS inverter 23. The CMOS inverter 23 receives a signal S 1_A The signal S is the inverted logic level of 2_A Output.

[0020] The CMOS inverter 24 has a p-MOS 37 and an n-MOS 38. The source of the p-MOS 37 is connected to the power supply line, and the drain is connected to the drain of the n-MOS 38. The source of the n-MOS 38 is connected to a node n1. The gates of the p-MOS 37 and n-MOS 38 are connected to each other and serve as the input terminal of the CMOS inverter 24. The drains of the p-MOS 37 and n-MOS 38 are connected to each other and serve as the output terminal of the CMOS inverter 24. The CMOS inverter 24 receives a signal S 1_B The signal S is the inverted logic level of 2_B Output.

[0021] The output circuit 12 has n-MOSs 41 and 42. The drain of the n-MOS 41 is connected to the power supply line, the source is connected to the output terminal 14A, and the gate is connected to the output terminal of the CMOS inverter 23. The n-MOS 41 receives the signal S 2_A A differential output signal S with a logic level according to out_A The differential output signal S out_A is output from output terminal 14A and transmitted to termination circuit 60.

[0022] The n-MOS 42 has a drain connected to the power supply line, a source connected to the output terminal 14B, and a gate connected to the output terminal of the CMOS inverter 24. The n-MOS 42 receives the signal S 2_B A differential output signal S with a logic level according to out_B The differential output signal S out_B is output from the output terminal 14B and transmitted to the termination circuit 60. The n-MOSs 41 and 42 form a source follower, and the signal S 2_A , S 2_B and the same phase differential output signal S out_A , S out_B Output.

[0023] The control circuit 13 includes resistor elements 51, 52, 53, 54, an operational amplifier circuit 55, capacitors 56, 57, and a p-MOS 58. One end of the resistor element 51 is connected to the output terminal 14B, and the other end is connected to one end of the resistor element 52. The other end of the resistor element 52 is connected to the output terminal 14A. The resistor elements 51 and 52 have the same resistance value, and a differential output signal S is output from the connection point between these elements. out_A and the differential output signal S out_B The intermediate voltage V C will be output.

[0024] The inverting input terminal of the operational amplifier circuit 55 is connected to the connection point between the resistor element 51 and the resistor element 52, and the inverting input terminal is supplied with an intermediate voltage V C A reference voltage V having a constant voltage level is input to the non-inverting input terminal of the operational amplifier circuit 55. REF is input. The output terminal of the operational amplifier circuit 55 is connected to one terminal of the resistor element 53. The other terminal of the resistor element 53 is connected to one terminal of the capacitor 56 and the gate of the p-MOS 58. The other terminal of the capacitor 56 is connected to the ground line. The drain of the p-MOS 58 is connected to the ground line, and the source is connected to one terminal of the resistor element 54, one terminal of the capacitor 57, and the node n1. The other terminal of the resistor element 54 is connected to the power supply line. The other terminal of the capacitor 57 is connected to the ground line. The control circuit 13 outputs the differential output signal S out_A , Sout_B The intermediate voltage V C The level of the reference voltage V REF The control voltage V X Generates a control voltage V X is output from the source of the p-MOS 58 and supplied to the node n1.

[0025] The termination circuit 60 has resistive elements 61 and 62 and a power supply 63. One end of the resistive element 61 is connected to the output terminal 14B, and the other end is connected to the positive electrode of the power supply 63. One end of the resistive element 62 is connected to the output terminal 14A, and the other end is connected to the positive electrode of the power supply 63. The negative electrode of the power supply 63 is connected to the ground line. When the differential signal output circuit 10 is of the LVPECL type, the voltage V supplied to the power supply line DD The level of the power supply voltage V is 3.3V, the resistance values ​​of the resistor elements 61 and 62 are 50Ω, and the output voltage level of the power supply 63 is DD The voltage is set to 1.3V, which is 2V less than the reference voltage.

[0026] 3 is a time chart showing an example of the operating waveforms of the components of the differential signal output circuit 10. The inverters 21 and 22 in the front stage of the drive circuit 11 respectively convert the differential input signal S in_A , S in_B The signal S is the inverted logic level of 1_A , S 1_B The signal S is output. 1_A , S 1_B The high level of DD is approximately the same as the level of the signal S 1_A , S 1_B The low level of is approximately the same as the level of the ground voltage supplied to the ground line.

[0027] The inverters 23 and 24 in the subsequent stages of the driving circuit 11 respectively convert the signal S 1_A , S 1_B The signal S is the inverted logic level of 2_A , S 2_B The signal S is output. 2_A , S 2_BThe high level of DD is approximately the same level as the signal S 2_A , S 2_B The low level of the control voltage V X It is roughly the same level as the

[0028] The n-MOSs 41 and 42 of the output circuit 12 receive the signal S 2_A , S 2_B and the same phase differential output signal S out_A , S out_B The output circuit 12 outputs a differential output signal S out_A , S out_B That is, the differential output signal S out_A , S out_B The high level of DD The gate-source voltage V GS_H The level is the level obtained by subtracting the level of the differential output signal S out_A , S out_B The low level of the control voltage V X The gate-source voltage V GS_L The control voltage V X The level of the differential output signal S out_A and S out_B The intermediate voltage V C The level is the reference voltage V REF That is, the differential output signal S out_A , S out_B The low level of the differential output signal S is set by feedback control by the control circuit 13. out_A , S out_B When the low level of is set, the differential output signal S out_A , S out_B The amplitude (difference between high and low levels) of the differential output signal S out_A , S out_B The low level and amplitude of the reference voltage V REFIt can be adjusted by the level of the reference voltage V REF The level of the differential output signal S out_A , S out_B The amplitude may be set to, for example, 0.75 V, which is the LVPECL standard.

[0029] 4A and 4B are equivalent circuit diagrams showing other examples of the configuration of the termination circuit. The termination circuit 60 shown in FIG. 2 can be replaced with the termination circuit 60A shown in FIG. 4A or the termination circuit 60B shown in FIG. 4B. The termination circuit 60A has resistive elements 64, 65, 66, and 67. One end of the resistive element 64 is connected to the power supply line, and the other end is connected to one end of the resistive element 66. The resistive element 65 has one end connected to the power supply line, and the other end is connected to one end of the resistive element 67. The other ends of the resistive elements 66 and 67 are each connected to the ground line. A node n A The output terminal 14A is connected to the resistor element 65, and the node n B The output terminal 14B is connected to the node n. The resistance values ​​of the resistor elements 64 and 65 are set to the same value, and the resistance values ​​of the resistor elements 66 and 67 are set to the same value. A and node n B The voltage of is the power supply voltage V DD The resistance values ​​of resistor elements 64 to 67 are determined so that the voltage is 2 V less than the reference voltage and a termination resistance of 50 Ω is achieved. Termination circuit 60A can achieve the same effect as termination circuit 60 shown in FIG. 2 without using a separate power supply.

[0030] The termination circuit 60B includes resistor elements 68 and 69. One end of the resistor element 68 is connected to the output terminal 14A and the other end is connected to the ground line. The resistor element 69 is connected to the output terminal 14B and the other end is connected to the ground line. For example, by setting the resistance values ​​of the resistor elements 68 and 69 to 150 Ω, it is possible to obtain substantially the same effect as when the resistance values ​​of the resistor elements 61 and 62 in the termination circuit 60 shown in FIG. 2 are set to 50 Ω and the output voltage of the power supply 63 is set to 1.3 V. The termination circuit 60B can be made smaller in circuit size than the termination circuit 60 shown in FIG. 2, thereby achieving cost reductions.

[0031] 5 is a diagram showing an example of the configuration of a differential signal output circuit 10X according to a comparative example. The differential signal output circuit 10X according to the comparative example outputs a differential output signal S out_A , S out_B is outputted by a constant current method. A differential signal output circuit 10X according to the comparative example includes a drive circuit 11A and an output circuit 12A.

[0032] The output circuit 12A has p-MOSs 71, 72, 73, 74, and 75. The p-MOSs 71, 72, and 73 each have a source connected to a power supply line and a gate connected to a bias voltage V BIAS is supplied. The drain of p-MOS 71 is connected to the sources of p-MOS 74 and 75. The drain of p-MOS 72 is connected to output terminal 14A. The drain of p-MOS 73 is connected to output terminal 14B. p-MOS 71, 72, and 73 each function as a constant current source.

[0033] The drain of p-MOS 74 is connected to output terminal 14 A, and the drain of p-MOS 75 is connected to output terminal 14 B. p-MOSs 74 and 75 are turned on and off complementarily in response to a drive signal supplied from drive circuit 11 A.

[0034] 5 illustrates a configuration in which a termination circuit 60 having resistive elements 61 and 62 and a power supply 63 is connected to output terminals 14A and 14B. The resistance values ​​of resistive elements 61 and 62 are, for example, 50 Ω each, and the output voltage level of power supply 63 is, for example, 1.3 V. The output current of p-MOS 71 is, for example, 15 mA, and the output currents of p-MOSs 72 and 73 are, for example, 6 mA each. For example, when p-MOS 74 is in the ON state and p-MOS 75 is in the OFF state, the differential output signal S out_A is high level, and the differential output signal S out_B In this case, a current (21 mA) that is the sum of the output current (15 mA) of p-MOS 71 and the output current (6 mA) of p-MOS 72 flows through resistor element 62 (50 Ω), and a differential output signal S of 2.35 V (high level) is output from output terminal 14A. out_A The output current (6 mA) of the p-MOS 73 flows through the resistor element 61 (50 Ω), and a differential output signal S of 1.6 V (low level) is output from the output terminal 14B. out_B will be output.

[0035] Now, consider the case where the termination circuit 60 is replaced with a simplified termination circuit 60B shown in FIG. 4B. In the termination circuit 60B, the resistance values ​​of the resistive elements 68 and 69 are assumed to be, for example, 150 Ω. In this case, the differential signal output circuit 10X according to the comparative example generates, for example, a differential output signal S out_A is high level, and the differential output signal S out_B When is low level, a current (21mA) that is the sum of the output current (15mA) of p-MOS 71 and the output current (6mA) of p-MOS 72 flows through resistor element 62 (150Ω), and a differential output signal S of 3.15V (high level) is output from output terminal 14A. out_A The output current (6 mA) of the p-MOS 73 flows through the resistor element 69 (150 Ω), and a differential output signal S of 0.9 V (low level) is output from the output terminal 14B. out_B In this way, the differential output signal S out_A , S out_B In the comparative example, the differential signal output circuit 10X outputs the differential output signal S out_A , Sout_B The level and amplitude of

[0036] On the other hand, according to the differential signal output circuit 10 according to the embodiment of the disclosed technique, the differential output signal S out_A , S out_B Since the differential signal output circuit 10 outputs the differential signals in a voltage format, it is possible to output differential output signals at a constant level regardless of the configuration of the termination circuit. Furthermore, the differential signal output circuit 10 can be realized using a more general CMOS process, and can be manufactured in a wider range of fabricators than when a bipolar process is used.

[0037] [Second embodiment] 6 is a block diagram showing an example of the configuration of a differential clock generation circuit 200 according to the second embodiment of the disclosed technology. The differential clock generation circuit 200 is configured to include the differential signal output circuit 10 according to the first embodiment described above. The differential clock generation circuit 200 has an oscillation circuit 201, a level shifter 202, a signal conversion circuit 203, and the differential signal output circuit 10.

[0038] A crystal oscillator 210 is connected to the oscillation circuit 201. The oscillation circuit 201 generates a sinusoidal oscillation signal S having a constant frequency. OSC The level shifter 202 outputs a sinusoidal oscillation signal S OSC is shaped into a square wave and the amplitude and signal level are adjusted. SQ The signal conversion circuit 203 outputs the single-ended signal S SQ The output signal of the signal conversion circuit 203 is converted into a differential signal and output. in_A , S in_B The differential signal output circuit 10 receives the differential input signal S in_A , S in_B Differential output signal S according to out_A , S out_B The differential output signal S out_A , S out_Bare terminated by a termination circuit (not shown) and supplied as differential clock signals to a subsequent circuit (not shown). Although the above description has been given of a configuration using a crystal oscillator 210, it is also possible to configure a differential clock generation circuit using a piezoelectric element or an oscillator element.

[0039] The following additional notes are further disclosed regarding the first and second embodiments. (Appendix 1) an output circuit including a pair of MOSFETs for outputting a differential output signal; a control circuit that generates a control voltage based on the differential output signal; a drive circuit that drives the pair of MOSFETs based on a differential input signal so that the low level of the differential output signal becomes a level corresponding to the control voltage; Contains Differential signal output circuit.

[0040] (Appendix 2) The pair of MOSFETs constitute a source follower. 2. A differential signal output circuit according to claim 1.

[0041] (Appendix 3) The pair of MOSFETs are each an n-channel type, with drains connected to power supply lines, sources connected to output terminals from which the differential output signals are output, and gates connected to the outputs of the drive circuits. 3. A differential signal output circuit according to claim 1 or 2.

[0042] (Appendix 4) The control circuit generates the control voltage so that the level of the intermediate voltage of the differential output signal matches the level of a reference voltage. 4. A differential signal output circuit according to claim 1.

[0043] (Appendix 5) The control circuit includes an operational amplifier circuit having an inverting input terminal to which the intermediate voltage is input and a non-inverting input terminal to which a reference voltage is input. 5. A differential signal output circuit according to claim 4.

[0044] (Appendix 6) A differential signal output circuit according to any one of Supplementary Note 1 to Supplementary Note 5; an oscillation circuit that outputs an oscillation signal having a constant frequency; a conversion circuit that converts the oscillation signal into a differential signal and outputs the converted signal as the differential input signal; 1. A differential clock generation circuit comprising: [Explanation of symbols]

[0045] 10, 10X differential signal output circuit 11, 11A drive circuit 12, 12A output circuit 13 Control circuit 14A, 14B output terminals 21, 22, 23, 24 Inverter 55 Operational amplifier circuit 60, 60A, 60B termination circuit 200 Differential Clock Generation Circuit 201 Oscillator Circuit 202 Level Shifter 203 Signal conversion circuit

Claims

1. an output circuit including a pair of MOSFETs that outputs a differential output signal; a control circuit that generates a control voltage based on the differential output signal; a drive circuit that drives the pair of MOSFETs based on a differential input signal so that the low level of the differential output signal becomes a level corresponding to the control voltage; Contains Differential signal output circuit.

2. The pair of MOSFETs constitute a source follower.

2. The differential signal output circuit according to claim 1.

3. The pair of MOSFETs are each an n-channel type, with drains connected to a power supply line, sources connected to output terminals from which the differential output signals are output, and gates connected to the output of the drive circuit.

2. The differential signal output circuit according to claim 1.

4. The control circuit generates the control voltage so that the level of the intermediate voltage of the differential output signal matches the level of a reference voltage.

2. The differential signal output circuit according to claim 1.

5. The control circuit includes an operational amplifier circuit having an inverting input terminal to which the intermediate voltage is input and a non-inverting input terminal to which a reference voltage is input.

5. The differential signal output circuit according to claim 4.

6. a differential signal output circuit according to any one of claims 1 to 5; an oscillation circuit that outputs an oscillation signal having a constant frequency; a conversion circuit that converts the oscillation signal into a differential signal and outputs the converted signal as the differential input signal; 1. A differential clock generation circuit comprising:

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