Device with low frequency noise rejection

Abstract

To provide a low noise transistor from which a ricker noise is removed.SOLUTION: In the transistor, a phase composite channel layer 130 in which quantum dots 131 are distributed in an amorphous matrix 132 and a surface stabilizing layer 140 in contact with the phase composite channel layer are formed. The passivation layer has a repeating structure of an inorganic insulating layer and an organic shielding layer. The surface passivation layer is formed in the space between the source electrode 150 and the drain electrode 160, and since the quantum dots of the phase composite channel layer have quantized states, carriers trapped in the quantum dots are limited, and even if a current is generated by a drain-source voltage in the phase composite channel layer, the carriers trapped in the quantum dots maintain a constant level. Accordingly, the drain-source current is constant even when the gate voltage increases, and the noise component of the gate voltage is not reflected in the drain-source current.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a device having a channel layer containing nanoparticles, and more particularly to a transistor having improved low-frequency noise characteristics and a device using the same. [Background technology]

[0002] Noise refers to electrical and electronic elements that interfere with the operation of devices. There are many different causes of noise, and noise can be divided into low-frequency noise and high-frequency noise depending on the frequency band. In particular, low-frequency noise refers to noise that usually occurs at frequencies below 100kHz. Low-frequency noise is not released or radiated outside the device where it is generated, but is included in the signal inside the device, causing the device to malfunction. Therefore, low-frequency noise is called device noise.

[0003] The above noise is mainly generated in a semiconductor FET (Field Effect Transistor) structure and is classified into thermal noise, flicker noise, and shot noise.

[0004] Thermal noise is generated by resistive elements within the device channel, and the generation of heat causes scattering of space charge within the device and random motion of electrons. The scattering and random motion create thermal noise, which appears across a wide frequency range.

[0005] Flicker noise, also known as 1 / f noise, is characterized by being inversely proportional to the frequency f. In transistors such as FETs, carriers move through the channel, are trapped at the interface of the gate dielectric film, and are detrapped again at an unspecified time and in an unspecified state. Flicker noise occurs during the process of trapping and detrapping at the interface. This is a variable that cannot be controlled externally and cannot be reduced by users.

[0006] FIG. 1 is a graph showing the characteristics of flicker noise according to the prior art.

[0007] Referring to Figure 1, the size of flicker noise is inversely proportional to the frequency. At high frequencies, flicker noise is hardly generated, and thermal noise accounts for the majority of device noise. Therefore, flicker noise is characterized by being prominent in the low frequency range, and dominates the low frequency range noise.

[0008] White noise is generated at a frequency higher than that at which flicker noise occurs, and occurs when the gate-source voltage of a transistor approaches the threshold voltage, so it has a negligible effect on the operation of the device.

[0009] As described above, in the low-frequency region, flicker noise significantly affects device operation, and is included in signals transmitted through transistors, significantly affecting device operation. Furthermore, as semiconductor design rules shrink and transistor operating voltages decrease, the channel size decreases, and the relative density of carriers trapped at the interface of the gate dielectric increases. In other words, unless the concentration of carriers trapped or detrapped at the interface of the gate dielectric is dramatically reduced compared to the low amount of charge flowing through the channel, low-frequency noise becomes an unavoidable problem.

[0010] In particular, there are many dangling bonds at the interface between the channel layer made of single-crystalline silicon and the amorphous gate dielectric film, which act as carrier trap sites. To solve this problem, the interface characteristics must be improved, but improving the interface characteristics between single-crystalline and amorphous is practically impossible. In other words, controlling the interface characteristics between two types of films with different materials and physical properties remains an unsolved problem. Summary of the Invention [Problem to be solved by the invention]

[0011] The technical problem to be solved by the present invention is to provide a low noise transistor in which flicker noise is eliminated. [Means for solving the problem]

[0012] In order to achieve the above technical objectives, the present invention provides a low-noise transistor comprising: a gate electrode formed on a substrate; a gate dielectric layer formed on the gate electrode; a phase composite channel layer formed on the gate dielectric layer and having quantum dots formed in an amorphous matrix; a surface passivation layer formed on the phase composite channel layer and for eliminating flicker noise; and a source electrode and a drain electrode formed on the phase composite channel layer, wherein the surface passivation layer is formed in direct contact with the phase composite channel layer in a space between the source electrode and the drain electrode.

[0013] The technical object of the present invention can also be achieved by providing a low-noise transistor comprising: a phase composite channel layer formed on a gate dielectric film, the phase composite channel layer having a single layer of quantum dots formed in an amorphous matrix; and a surface passivation layer in contact with the phase composite channel layer and having a superlattice structure of an inorganic insulating layer and an organic shielding layer, wherein the surface passivation layer has a higher bandgap than the phase composite channel layer and operates in the saturation region even at Vgs greater than Vds.

[0014] In order to achieve the above technical objective, the present invention provides a low-noise transistor including a source electrode grounded at a small signal level; a drain electrode opposite the source electrode; and a gate electrode to which a small-signal input voltage is applied, the low-noise transistor further including a gate dielectric layer formed on the gate electrode; a phase composite channel layer formed on the gate dielectric layer; and a surface passivation layer formed on the phase composite channel layer, the source electrode and the drain electrode being formed opposite to each other in direct contact with the phase composite channel layer, and the drain current flowing through the drain-source is maintained at a constant level due to carrier state hybridization even when the gate voltage increases. [Effects of the Invention]

[0015] According to the present invention, the carrier concentration in the composite channel layer is limited to a saturated state, and the introduction of a passivation layer essentially eliminates flicker noise. However, without a passivation layer, the carrier concentration increases with gate voltage application, and the increased carrier concentration also increases Ids. Furthermore, the increased carrier concentration also increases the number of carriers trapped or detrapped at the interface of the gate dielectric film.

[0016] In the present invention described above, even if the gate voltage is increased in the common source configuration, Ids remains constant and the actual output resistance of the transistor is almost invisible, thereby eliminating flicker noise. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a graph showing characteristics of flicker noise according to the prior art; [Figure 2] 1 is a cross-sectional view showing a transistor having improved low-frequency noise characteristics according to an embodiment of the present invention; [Figure 3] 1 is a schematic diagram illustrating a high pressure atomic layer deposition method according to an embodiment of the present invention; [Figure 4] 3 is a cross-sectional view showing the composite channel layer and the surface passivation layer of FIG. 2 according to a preferred embodiment of the present invention. [Figure 5] 1 is an image showing quantum dots in a composite channel layer formed by Preparation Example 1 of the present invention. [Figure 6] 10 is a graph showing the electrical characteristics of two samples measured according to a measurement example of the present invention. [Figure 7] 10 is a graph showing the results of measuring noise according to a measurement example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] Because the present invention can be modified in various ways and can have various forms, specific examples are shown in the drawings and described in detail herein. However, this does not limit the present invention to the specific embodiments, and it should be understood that the present invention includes all modifications, equivalents, and alternatives that fall within the spirit and technical scope of the present invention. In the description of each drawing, similar reference numerals are used for similar components.

[0019] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention pertains. Terms as defined in commonly used dictionaries should be interpreted as meanings consistent with the meanings they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0020] Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings.

[0021] (Example) FIG. 2 is a cross-sectional view showing a transistor having improved low-frequency noise characteristics according to an embodiment of the present invention.

[0022] Referring to FIG. 2, the transistor of this embodiment includes a substrate 100 , a gate electrode 110 , a gate dielectric layer 120 , a composite channel layer 130 , a passivation layer 140 , a source electrode 150 and a drain electrode 160 .

[0023] The composite channel layer 130 has a single-layer structure in which quantum dots 131, which are single-crystal or polycrystalline grains, are distributed and separated from one another in an amorphous matrix 132. In particular, the size of the crystal grains is 5 nm or less, forming quantum dots 131. The quantum dots 131 are formed along the channel, and a mechanism for carriers to move between the quantum dots 131 is provided.

[0024] The amorphous matrix 132 can be interpreted as a non-quantized continuous system, and the quantum dots 131, which are crystalline particles, can be interpreted as a quantized closed system. That is, the amorphous matrix 132 is essentially an open system in which continuous energy states are permitted and the energy intervals between states are very narrow. On the other hand, the quantum dots 131 have discontinuous energy states and constitute a closed system in which only specific energy states are permitted.

[0025] The composite channel layer 130 can be interpreted as a junction between a quantized closed system and a continuous open system, and quantized carriers undergo hybridization due to the electric field applied between the source electrode 150 and the drain electrode 160 and the electric field applied from the gate electrode 110. In the present invention, the term "hybridization" refers to a physical phenomenon in which quantized carriers in the quantum dots 131 tunnel through the amorphous matrix 132, which is a continuous amorphous phase, or move due to an electric field. For hybridization to occur, the quantum dots 131 and the amorphous matrix 132 must be made of the same material. More specifically, the interface between the crystalline grains of the quantum dots 131 and the amorphous matrix 132 may be made of the same material, and an intermediate phase may exist where the crystalline grains are converted to amorphous.

[0026] The phase composite channel layer 130 can be formed as an n-type or p-type. When the phase composite channel layer 130 is an n-type, the phase composite channel layer 130 can include ZnO, MoS2, or IGZO. When the phase composite channel layer 130 is a p-type, the phase composite channel layer 130 can include SnO or Te. That is, the phase composite channel layer 130 is not limited to a specific material as long as it has a structure in which quantum dots of crystal grains are distributed in an amorphous matrix.

[0027] A surface passivation layer 140 is formed on the composite channel layer 130. The surface passivation layer is in contact with the composite channel layer 130 and has a higher band gap than the composite channel layer, contributing to the hybridization of quantized carriers.

[0028] The passivation layer 140 is composed of an organic tunnel layer in which a metal is bonded or doped to an organic material and an insulating layer, and in particular, the passivation layer 140 completely covers the composite channel layer 130 between the source electrode 150 and the drain electrode 160.

[0029] The source electrode 150 and the drain electrode 160 are in direct contact with the composite channel layer 130. The source electrode 150 and the drain electrode 160 are disposed facing each other with the lower gate electrode 110 in the center. Carriers are supplied from the source electrode 150 to the composite channel layer 130. Carriers flowing through the composite channel layer 130 are discharged to the drain electrode 160.

[0030] Here, the surface passivation layer 140 has a higher bandgap than the amorphous matrix 132 or the quantum dots 131 of the phase composite channel layer 130, and the higher bandgap induces the quantum dots 131 of the phase composite channel layer 130 to have a double quantum well structure. That is, a quantum barrier layer is primarily formed by the amorphous matrix 132 surrounding the quantum dots 131, and the surface passivation layer 140 forms a second barrier layer to deepen state hybridization.

[0031] In addition, the source electrode 150 and the drain electrode 160 are in direct contact with the composite channel layer 130. The direct contact with the source electrode 150 can reduce the operating voltage for driving the composite channel layer 130.

[0032] When a gate-source voltage above a certain level is applied, carriers can be supplied from the source electrode 150 to the phase composite channel layer 130. That is, the operation of supplying activation energy to the quantum dots 131 of the phase composite channel layer 130 to turn on the phase composite channel layer 130 is explained by a threshold voltage, and a gate-source voltage that can continuously supply carriers to the phase composite channel layer 130 by applying a voltage above the threshold voltage is additionally required.

[0033] Carriers tunneling from the source electrode 150 through the amorphous matrix 132 are trapped in the quantum dots 131. The composite channel layer 130 has the amorphous matrix 132 and the quantum dots 131, and carriers are trapped in a specific energy state within the quantum dots 131. Carriers trapped within the quantum dots 131 and having a specific energy state move to adjacent quantum dots 131 through the continuous amorphous matrix 132. Here, it is highly unlikely that the carriers trapped in the quantum dots 131 will be trapped at the interface with the gate dielectric film 120 due to the influence of the gate electrode 110.

[0034] This is because the amorphous matrix 132 is distributed with a relatively large thickness between the quantum dots 131 and the gate dielectric film 120. That is, since the separation distance between the quantum dots 131 and the gate dielectric film 120 is much larger than the separation distance between the quantum dots 131, the probability that carriers can tunnel through the amorphous matrix between the quantum dots 131 and the gate dielectric film 120 is nearly 0%.

[0035] In addition, since the surface passivation layer 140 is disposed on the phase composite channel layer 130, the surface passivation layer 140 blocks external elements, and due to its characteristic of having a higher band gap than the phase composite channel layer 130, the probability of carriers being trapped on the upper surface of the phase composite channel layer 130 is almost 0%.

[0036] Therefore, a mechanism appears in which carriers move between the quantum dots 131 by tunneling through the amorphous matrix 132 or by passing through a continuous system.

[0037] 2, the substrate 100 may be made of any insulating material, and may be made of any material whose physical properties are unchanged during the process of forming various functional layers on the substrate 100. In particular, the substrate 100 does not need to be limited to being flexible or non-flexible, and may be made of any non-conductor on which the gate electrode 110 can be formed. For example, the substrate 100 may be made of SiO2.

[0038] A gate electrode 110 is formed on the substrate 100. The gate electrode 110 can be made of any conductive material, such as a metal or doped polysilicon. Examples of usable metal materials include Au, Pt, Ag, Ni, Al, W, and Pd.

[0039] A gate dielectric layer 120 is formed on the gate electrode 110. The gate dielectric layer 120 is preferably made of an insulating material with a high dielectric constant, such as, but not limited to, Al2O3, HfO2, or ZrO2. SiO2 may also be used.

[0040] A composite channel layer 130 is formed on the gate dielectric layer 120. The composite channel layer 130 may be doped n-type or p-type. That is, the composite channel layer 130 may be an n-type semiconductor or a p-type semiconductor. Since the composite channel layer 130 is formed of an n-type semiconductor, the composite channel layer 130 may include ZnO, IGZO, or MoS2. Furthermore, since the composite channel layer 130 is formed of a p-type semiconductor, the composite channel layer 130 may include Te or SnO.

[0041] The composite channel layer 130 has a configuration in which a plurality of quantum dots 131 are formed in parallel within an amorphous matrix 132. The amorphous matrix 132 and the quantum dots 131 are made of the same material, and the composite channel layer 130 is formed in a single process.

[0042] A high-pressure atomic layer deposition method is used to form the phase composite channel layer 130. In a conventional atomic layer deposition method, the precursor dosing time is short, and the partial pressure of the precursor in the chamber after the precursor is supplied is only a few tens of mTorr. In the present invention, a high-pressure atomic layer deposition method is used to form the phase composite channel layer 130.

[0043] FIG. 3 is a schematic diagram illustrating a high pressure atomic layer deposition method according to an embodiment of the present invention.

[0044] Referring to FIG. 3, the exhaust pump of the deposition equipment is operated to create a vacuum in the chamber. Then, the exhaust pump is turned off and the precursor is introduced into the chamber. The pressure in the chamber is set to a high pressure of 1 Torr or more by the introduction of the precursor. When the pressure in the chamber reaches the target value, the introduction of the precursor is stopped and a holding time is given to induce the reaction. After the set holding time has elapsed, the precursor is purged.

[0045] The introduction of precursors is stopped, and a holding time is allowed during which a phase-composite channel layer is formed in a high-pressure environment. At the beginning of the reaction, an amorphous matrix is ​​formed on the amorphous gate dielectric film. Once the growth of the amorphous matrix has continued to a certain extent, quantum dots begin to form on the amorphous matrix in a high-pressure environment. The quantum dots have a single-crystal or polycrystalline phase. However, due to the relatively low process temperature, continuous growth of crystal grains does not occur, and after the formation of nearly spherical quantum dots, the amorphous matrix is ​​again formed.

[0046] The process described above results in the distribution of quantum dots within the amorphous matrix.

[0047] 4 is a cross-sectional view showing the composite channel layer and the passivation layer of FIG. 2 according to a preferred embodiment of the present invention. Referring to FIG. 4, a passivation layer 140 is formed on the composite channel layer 130.

[0048] The passivation layer 140 has a repeating structure of inorganic insulating layers 141 and organic blocking layers 142. The inorganic insulating layers 141 and the organic blocking layers 142 form a kind of superlattice, which acts as a barrier for carriers in the composite channel layer 130. That is, only carriers with energy equal to or greater than the critical energy can be trapped at the interface between the composite channel layer 130 and the passivation layer 140.

[0049] Through this process, quantized carriers are captured by the quantum dots 131 in the composite channel layer 130 and can flow between the quantum dots 131 .

[0050] Al2O3 is used as the inorganic insulating layer 141 that constitutes the surface passivation layer 140, and Al-2,3-dimercapto-1-propanol (Al-DMP) can be used as the organic shielding layer 142. The thiol groups and Al in the organic shielding layer 142 give it higher conductivity than the inorganic insulating layer 141, and it can remove disturbing elements such as external electromagnetic waves.

[0051] The inorganic insulating layer 141 is first formed on the phase composite channel layer 130. If the organic blocking layer 142 is first formed on the phase composite channel layer 130, the organic-inorganic bonding will not bond or chemically bond with the inorganic semiconductor material of the phase composite channel layer 130. Therefore, a material with a large band gap symmetry cannot be provided to the phase composite channel layer 130, and a strong bond will not be formed between the phase composite channel layer 130 and the surface passivation layer 140, resulting in failure to ensure desired physical properties.

[0052] When an inorganic insulating layer 141 made of an inorganic material is formed on a phase composite channel layer 130 made of an inorganic semiconductor or metal material, oxygen atoms and other constituents of the inorganic material chemically bond with elements constituting the phase composite channel layer 130, thereby maintaining strong physical properties.

[0053] Through the superlattice structure of the repeatedly formed inorganic insulating layer 141 and organic shielding layer 142, carriers flowing from the source electrode 150 into the composite channel layer 130 can easily flow through the composite channel layer 130, thereby forming a noise-free signal.

[0054] A source electrode 150 and a drain electrode 160 are formed on the composite channel layer 130. The source electrode 150 and the drain electrode 160 are preferably formed at positions facing each other with the gate electrode 110 in the center. The source electrode 150 and the drain electrode 160 may be made of a metal such as Au, Pt, Ag, Ni, W, or Pd.

[0055] (Production Example 1: Production of a composite channel layer) ZnO was selected as the material for the phase-composite channel layer. The chamber pressure was maintained at 1 Torr, DEZ (Diethylzinc) and H2O were supplied as precursors, and the chamber temperature was maintained at 100°C. The thickness of the phase-composite ZnO channel was adjusted to confirm the size of the ZnO quantum dots. The size of the ZnO quantum dots can be adjusted by changing the hold time in Figure 3.

[0056] FIG. 5 is an image showing quantum dots in a composite channel layer formed by Preparation Example 1 of the present invention.

[0057] 5(a) shows a 3.5 nm thick composite channel layer with ZnO quantum dots formed in an amorphous ZnO matrix. Also, (b) shows quantum dots formed in a 5.3 nm thick composite channel layer, and (c) shows quantum dots formed in a 7.7 nm thick ZnO composite channel layer.

[0058] It is observed that the size of the quantum dots increases as the channel thickness increases, thereby confirming the quantum dot size control within the composite channel layer.

[0059] (Manufacturing Example 2: Fabrication of a transistor device having a composite channel layer and a surface passivation layer) SiO2 is used as the substrate, and a 60nm thick layer of Al is used as the gate electrode. A 10nm thick Ti bonding layer is used to bond the substrate and gate electrode. An 11nm thick layer of Al2O3 is then formed on top of the gate electrode as a gate dielectric. The Al2O3 is formed using the precursor TMA (TriMethyl Aluminum). The composite channel layer formed on the gate dielectric is made of ZnO and is 5.5nm thick. The average diameter of the ZnO quantum dots within the composite channel layer is 3.5nm. The separation distance between the ZnO quantum dots is less than 1nm. The source and drain electrodes are made of the same material as the gate electrode, Al.

[0060] In addition, a passivation layer was formed on the composite channel layer between the source and drain electrodes using an inorganic insulating layer of Al2O3 and an organic shielding layer of Al-DMP. The inorganic insulating layer had an average thickness of 2 nm, and the organic shielding layer had an average thickness of 4 nm, forming a repeating structure of inorganic insulating layer / organic shielding layer, resulting in a total passivation layer thickness of 6 nm.

[0061] (Comparative Manufacturing Example: Fabrication of a Transistor Device with a Phase Composite Channel Layer) As in Preparation Example 2, a bonding layer, a gate electrode, a gate dielectric film, and a phase composite channel layer are formed on a substrate, except that the formation of a surface passivation layer is omitted, and a source electrode and a drain electrode are formed on the phase composite channel layer in the same manner as in Preparation Example 2.

[0062] (Measurement example: Measurement of low-frequency noise characteristics) The noise characteristics of the sample of Manufacturing Example 2 and the sample of Comparative Manufacturing Example were measured. The source electrode was grounded, and the gate-source voltage Vgs was swept from -3 V to 4 V. The drain-source voltage Vds was set to 2 V, and the drain-source current Ids was measured.

[0063] FIG. 6 is a graph showing the electrical characteristics of two samples measured according to a measurement example of the present invention.

[0064] 6, the x-axis represents Vgs and the y-axis represents Ids. Under the condition that a constant drain-source voltage Vds (=2V) is applied, the drain-source current Ids is measured while increasing the gate-source voltage Vgs.

[0065] 6 shows data measured based on a common-source configuration of a transistor. In small-signal modeling, the source electrode is grounded, and a small-signal voltage applied to the gate and source acts as the input, while a small-signal current flowing between the drain and source acts as the output. If an output resistor is connected between the drain and source electrodes in the common-source configuration, a small-signal voltage is output between the drain and source.

[0066] The sample of Comparative Example exhibits a rapid increase in Ids when Vgs exceeds 0 V, continuing to increase rapidly until Vgs reaches 1 V. The sample of Comparative Example has a composite channel layer with the same structure and thickness as the sample of Example 2. When Vgs is applied, carriers move from the source electrode to the quantum dots in the composite channel layer, and Ids increases relatively linearly with the influence of Vds. Furthermore, the rate of increase in Ids slows when Vgs is above 1 V, but an increase in Ids as Vgs increases is observed.

[0067] On the other hand, in the sample of Production Example 2, Ids increases sharply in the Vgs range between -2V and 1V due to the influence of the surface passivation layer formed on the upper part of the composite channel layer. This is a very unusual phenomenon. Furthermore, when Vgs exceeds 0V, Ids saturates and almost no fluctuation in Ids is observed. Regarding this phenomenon, the inventors of the present invention propose the following interpretation model.

[0068] (1) Improvement of doping effect and interface properties of the composite channel layer by the surface passivation layer (2) Carriers do not flow into the phase-composite channel layer when Vgs is negative. The phase-composite channel layer is composed of ZnO and has n-type conductivity, so the carriers are electrons. Electrons cannot move through the phase-composite channel layer when Vgs is negative. However, as shown in Figure 6, Ids increases sharply when Vgs is negative. Oxygen in ZnO is reduced by TMA, a precursor used in forming the inorganic insulating layer, Al2O3. Specifically, Al contained in the precursor combines with oxygen in ZnO to form oxygen vacancies. This is the doping effect of Al, which increases the concentration of oxygen vacancies acting as donors, thereby increasing the carrier concentration. Therefore, carriers are activated by doping and a positive Vds, resulting in an increase in Ids even at negative Vgs. (3) Carrier flow into the composite channel layer and state saturation with respect to input Vgs (4) In a depletion-type n-MOS transistor, Vds must be greater than Vgs to enter the saturation region. To be precise, the requirement Vds > Vgs - Vth (threshold voltage) must be met. In Figure 6, when Vgs is between 0V and 1V, Vds (= 2V) is greater than Vgs, so the transistor operates in the saturation region to meet this condition. However, when Vgs increases above Vds to between 2V and 4V, the transistor operates in the linear region. The linear region is the region where Ids increases linearly with increasing Vds.

[0069] (5) In Figure 6, Vgs is changed. As Vgs increases, Ids increases due to operation in the linear region, but in the transistor of the present invention, Ids is fixed even when Vgs increases. (6) The above phenomenon is highly unusual, and the inventors of the present invention interpret it as follows. First, the concentration of carriers tunneling between quantum dots through the amorphous matrix in the phase composite channel layer is limited. Therefore, to maintain a saturated state even when a high Vgs is applied, a certain amount of carriers are supplied to the phase composite channel layer through tunneling in the amorphous matrix. The carriers trapped in the phase composite channel layer form Ids through the quantum dots according to Vds. (7) When quantum dots are formed in a single layer in an amorphous matrix, the carriers trapped in the quantum dots undergo energy quantization as they tunnel through the amorphous matrix between the quantum dots. That is, the number of carriers trapped in the quantum dots remains constant even when the gate voltage increases. (8) That is, the low noise transistor of the present invention has the characteristic that when the quantum dot and amorphous states are hybridized, the drain current remains constant even when the gate voltage increases. (9) The operation of the device of this example shows that it acts as a current source with a fixed Ids value above a certain Vgs. Checking the graph of an ideal current source reveals that there is almost no fluctuation in Ids, and that there is almost no resistance component due to carrier capture at the interface with the gate dielectric film.

[0070] (10) FIG. 7 is a graph showing the results of measuring noise according to a measurement example of the present invention. (11) Referring to Figure 7, the noise intensity of the sample of Manufacturing Example 2 and the sample of Comparative Manufacturing Example was measured. As described in Figure 6, the device has a common source configuration. That is, the source electrode is grounded, and the gate voltage Vgs is fixed at 3 V and Vds is fixed at 2 V as inputs. Ids was also measured, and the noise component contained in Ids was analyzed. (12) In the graph above, S on the y-axis Ids denotes the current noise spectral density of Ids, and S Ids is A 2 / Hz. Since the current values ​​at which the current noise is measured for the two manufacturing examples are different, the square value of the measured current, Ids 2is normalized to compare the noise spectral density per unit current. Therefore, the size of the y-axis is a normalized representation of the intensity or size of the noise contained in Ids, and indicates the noise spectral density per unit current, with units of (1 / Hz). (13) Graph (a) shows the noise size of the comparative manufacturing example sample, and graph (b) shows the noise size of the manufacturing example 2 sample. In conclusion, the y-axis shows the current noise spectrum density, which represents the fluctuation of the current over time in the frequency band. In the comparative manufacturing example sample, when the frequency increases by 10 times in the low frequency range, S Ids / Ids 2 However, in the sample of Production Example 2 of the present invention, 1 / f noise is not observed even when the frequency increases in the low frequency region, and a constant S Ids / Ids 2 In FIG. 7, frequencies up to 400 Hz are supplied, and the sample of Production Example 2 has an average noise spectral density per unit current of 10 within the frequency range. -10 The following is shown: (14) This is due to the introduction of a passivation layer on top of the phase composite channel layer. The introduction of the passivation layer allows the phase composite channel layer to be located between the gate dielectric layer and the passivation layer, resulting in a quantum well structure. In particular, because an inorganic insulating layer with a high bandgap is first formed on the phase composite channel layer, and an organic shielding layer that blocks external disturbances is then formed, carriers in the phase composite channel layer are not trapped at the interface, resulting in the formation of a very stable drain-source current.

[0071] (15) In the present invention described above, a phase composite channel layer and a surface passivation layer are used. The surface passivation layer is in direct contact with the phase composite channel layer, providing state stabilization and additional doping of the phase composite channel layer. In addition, the source electrode and the drain electrode are in direct contact with the phase composite channel layer, which allows carriers to easily move to the phase composite channel layer. (16) In particular, carriers with a constant concentration due to the phase composite channel layer can operate in the saturation region because the surface passivation layer minimizes the trapping or detrapping phenomenon between the carriers and the gate dielectric interface. That is, the drain current Ids can be maintained constant even with increasing gate voltage. On the other hand, if only the phase composite channel layer is formed, the carrier concentration in the phase composite channel layer increases as the gate voltage increases. Therefore, even when Vds is maintained constant, Ids increases linearly with increasing gate voltage. This means that the transistor is in the linear region rather than the saturation region. As can be seen from the transfer characteristic graph, fluctuations in the gate voltage appear as fluctuations in the drain current, and fluctuations in the voltage at the gate electrode appear as fluctuations in the drain current. That is, low-frequency noise introduced into the gate electrode tends to be amplified and appear at the output terminal.

[0072] (17) In addition, in the present invention, the carrier concentration of the composite channel layer corresponding to the channel layer is limited to a saturated state, limiting the change in the number of carriers. Therefore, the surface passivation layer essentially prevents flicker noise. However, without the surface passivation layer, the carrier concentration increases with the application of gate voltage, and the increased carrier concentration also increases Ids. Furthermore, the increased carrier concentration also increases the number of carriers trapped or detrapped at the interface of the gate dielectric film. (18) In the present invention, even if the gate voltage is increased in the common source configuration, Ids remains constant, and the actual output resistance of the transistor is almost invisible. This eliminates flicker noise. [Explanation of symbols]

[0073] 100 boards 110 gate electrode 120 gate dielectric layer 130-phase composite channel layer 140 Surface stabilization layer 150 Source Electrode 160 Drain electrode

Claims

1. a gate electrode formed on the substrate; a gate dielectric layer formed on the gate electrode; a composite channel layer formed on the gate dielectric layer, the composite channel layer having quantum dots formed in an amorphous matrix; a surface passivation layer formed on the composite channel layer to eliminate flicker noise; and a source electrode and a drain electrode formed on the composite channel layer; The passivation layer is formed in direct contact with the composite channel layer in the space between the source electrode and the drain electrode.

2. The low-noise transistor operates at 10 Hz in the frequency range below 400 Hz. －１０ 2. A low noise transistor according to claim 1, characterized in that it has an average noise spectral density per unit current of:

3. 2. The low noise transistor of claim 1, wherein the separation distance between the quantum dots and the gate dielectric layer is greater than the separation distance between the quantum dots.

4. 2. The low noise transistor of claim 1, wherein the quantum dots are distributed in the amorphous matrix in a monolayer.

5. 2. The low noise transistor according to claim 1, wherein the passivation layer has a structure in which an inorganic insulating layer and an organic shielding layer are alternately stacked, and the organic shielding layer has a higher conductivity than the inorganic insulating layer.

6. 6. The low noise transistor of claim 5, wherein the inorganic insulating layer is formed on the phase composite channel layer before the organic shielding layer and is in contact with the amorphous matrix of the phase composite channel layer.

7. 7. The low noise transistor of claim 6, wherein the inorganic insulating layer comprises Al2O3, and the organic shielding layer comprises Al-2,3-dimercapto-1-propanol (Al-DMP).

8. 7. The low noise transistor of claim 6, wherein the inorganic insulating layer dopes the composite channel layer to increase Ids at negative Vgs.

9. 2. The low noise transistor of claim 1, wherein the gate electrode is used as an input and the drain electrode is used as an output, and the low noise transistor has a common source configuration.

10. a composite channel layer formed on the gate dielectric film, the composite channel layer having quantum dots formed in a single layer within an amorphous matrix; and a surface passivation layer in contact with the composite channel layer and having a superlattice structure of an inorganic insulating layer and an organic shielding layer; The surface passivation layer has a higher bandgap than the composite channel layer, and operates in the saturation region even at a Vgs value greater than Vds.

11. 11. The low-noise transistor according to claim 10, wherein the quantum dots and the amorphous matrix are made of the same material, and carriers quantized in the quantum dots move by tunneling through the amorphous matrix, which is a continuous amorphous phase.

12. 12. The low noise transistor of claim 11, wherein the inorganic insulating layer of the passivation layer contacts the amorphous matrix of the phase composite channel layer.

13. The low noise transistor is 10 －１０ 11. A low noise transistor according to claim 10, characterized in that it has an average noise spectral density per unit current of:

14. 1. A low noise transistor comprising: a source electrode grounded at a small signal level; a drain electrode opposite the source electrode; and a gate electrode to which an input voltage at a small signal level is applied, a gate dielectric layer formed on the gate electrode; a composite channel layer formed on the gate dielectric film; and a surface passivation layer formed on the composite channel layer; the source electrode and the drain electrode are formed facing each other and directly contacting the composite channel layer; A low noise transistor, characterized in that the drain current flowing through the drain-source remains constant even when the gate voltage increases due to carrier state hybridization.

15. 15. The low-noise transistor of claim 14, wherein the phase composite channel layer includes quantum dots formed in an amorphous matrix, and carriers moving through the phase composite channel layer have their energy quantized by the quantum dots, and carriers captured by the quantum dots maintain a constant level even when the gate voltage is increased.

16. 16. The low noise transistor of claim 15, wherein the quantum dots are formed in a single layer, and the separation distance between the quantum dots and the gate dielectric layer is greater than the separation distance between the quantum dots.

17. The low noise transistor of claim 15, wherein the surface passivation layer has a repeated structure of an inorganic insulating layer and an organic shielding layer, and the inorganic insulating layer is formed on the phase composite channel layer and is doped with Al to form Ids at negative Vgs.

18. The passivation layer allows the low noise transistor to －１０ 18. A low noise transistor according to claim 17, characterized in that it has an average noise spectral density per unit current of:

19. 18. The low noise transistor of claim 17, wherein the insulating layer comprises Al2O3 and the organic shielding layer comprises Al-2,3-dimercapto-1-propanol (Al-DMP).

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