Imaging device and electronic apparatus

Abstract

To perform addition reading of a pixel signal with small power consumption while suppressing an increase in circuit scale in an imaging element which performs analog-digital conversion using Δ Σ modulation.SOLUTION: The imaging apparatus includes a plurality of analog-to-digital conversion units configured to perform analog-to-digital conversion using Δ Σ modulation on analog signals output from a plurality of pixels and output digital signals, a selection unit configured to input the plurality of digital signals and select and output at least one digital signal, a plurality of filters configured to convert each of the digital signals into a multi-bit signal, and a control unit configured to control the selection unit and the plurality of filters. When performing addition readout, under the control of the selection unit, the selection unit time-divisionally multiplexes and outputs digital signals to be added out of the plurality of digital signals in each predetermined cycle, and the filter unit converts the multiplexed digital signal into a multi-bit signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an electronic device, and in particular to a technology for analog-to-digital conversion using ΔΣ modulation. [Background technology]

[0002] In recent years, as the frame rates of digital devices have increased, image signals from image sensors have also been read out at high speeds. To achieve high-frame-rate video, a method of adding and reading out adjacent pixel signals from an image sensor is commonly used. In the addition operation described in Patent Document 1, the signal charges of the pixels to be added are stored in the same storage capacitor and output, and the output analog signal is subjected to analog-to-digital conversion (AD conversion) to output a digital signal (see Patent Document 1).

[0003] On the other hand, Non-Patent Document 1 discloses an image sensor that employs a ΔΣ AD conversion method, which enables low-power and high-speed readout. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-14316 [Non-patent literature]

[0005] [Non-Patent Document 1] ISSCC2021-7_6 A High-Speed ​​Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT / C-Cancelling S&H and Delta-Sigma ADC Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology disclosed in Non-Patent Document 1, a ΔΣ modulator and a digital filter are provided for each specific number of column circuits, and even when performing additive driving as described in Patent Document 1, it is necessary to operate the downstream circuit, resulting in high power consumption.

[0007] The present invention has been made in consideration of the above problems, and aims to enable pixel signal addition and reading with low power consumption while suppressing an increase in circuit size in an image sensor that performs analog-to-digital conversion using ΔΣ modulation. [Means for solving the problem]

[0008] In order to achieve the above object, the imaging element of the present invention comprises a pixel region in which a plurality of pixels are arranged in a matrix, a plurality of analog-to-digital conversion means that perform analog-to-digital conversion using ΔΣ modulation on analog signals output from selected pixels of the plurality of pixels and output digital signals, a selection means that inputs the plurality of digital signals from the plurality of analog-to-digital conversion means and selects and outputs at least one digital signal, a plurality of filters that convert the digital signals output from the selection means and any of the plurality of analog-to-digital conversion means into multi-bit signals, and a control means that controls the selection means and the plurality of filters, wherein, when performing an addition readout in which signals from a plurality of pixels are added and readout, the control means controls the selection means so that, in each predetermined period, the selection means time-division multiplexes and outputs the digital signal to be added from the plurality of digital signals, and controls the filter so that the multiplexed digital signal is converted into multi-bit signals. [Effects of the Invention]

[0009] According to the present invention, in an image sensor that performs analog-to-digital conversion using ΔΣ modulation, it is possible to perform additive reading of pixel signals with low power consumption while suppressing an increase in circuit size. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing the configuration of an imaging apparatus according to an embodiment of the present invention. [Figure 2] FIG. 1 is a block diagram showing the configuration of an imaging element according to a first embodiment. [Figure 3] FIG. 2 is a block diagram showing the configuration of a ΔΣ ADC according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing input / output signals to a second selection unit in the first embodiment. [Figure 5] FIG. 4 is a timing chart showing input / output signals to a second selection unit in a non-additive read mode according to the first embodiment. [Figure 6] FIG. 4 is a timing chart showing input / output signals to a second selection unit in an additive readout mode according to the first embodiment. [Figure 7] FIG. 10 is a block diagram showing the configuration of an image sensor according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0012] First Embodiment 1 is a block diagram showing the configuration of an imaging device according to the present invention. Note that the imaging device to which the present invention can be applied may be any electronic device equipped with a camera function, such as a digital camera or digital video camera, a camera-equipped mobile phone, a camera-equipped computer, a game console, a robot, a drone, etc.

[0013] The imaging device shown in FIG. 1 includes an imaging optical system 11, an imaging element 12, a signal processing unit 13, a compression / decompression unit 14, a synchronization control unit 15, an operation unit 16, an image display unit 17, and an image recording unit 18.

[0014] The imaging optical system 11 includes a lens, a lens driving mechanism, a mechanical shutter mechanism, an aperture mechanism, etc. Of these, the movable parts are driven based on control signals from a synchronization control unit 15. The imaging element 12 is an XY address type CMOS sensor, and performs imaging operations based on control signals from the synchronization control unit 15. Then, the image signal is passed through an AD conversion circuit and is digitized, and is output to the signal processing unit 13. Details of the imaging element 12 will be described later.

[0015] The signal processing unit 13, under the control of the synchronization control unit 15, performs signal processing and detection processing of control information such as AF (Auto Focus) and AE (Auto Exposure) on the digitized image signal input from the image sensor 12. Then, the signal processing unit 13 outputs the signal-processed image signal and control information to the synchronization control unit 15. The compression / decompression unit 14 operates under the control of the synchronization control unit 15, and performs compression / encoding processing of image signals of still images and moving images, and decompression / decoding processing of encoded data of still images and moving images.

[0016] The synchronization control unit 15 is a microcontroller composed of, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc., and controls each part of the imaging device in an integrated manner by executing a program stored in the ROM, etc.

[0017] The operation unit 16 is composed of various operation members such as a shutter release button, and outputs a signal to the synchronization control unit 15 in response to an input operation by the user. The image display unit 17 supplies the image signal to a display device such as an LCD (Liquid Crystal Display) to display an image. The image recording unit 18 is connected to, for example, a portable recording medium and records the compressed and encoded image data file on the connected recording medium. Note that the recording medium may be built into the imaging device.

[0018] Next, the basic operation of the imaging device having the above configuration in this embodiment will be described. Before capturing a still image, the image signals output from the image sensor 12 are sequentially supplied to the signal processing unit 13. The signal processing unit 13 performs signal processing on the image signals output from the image sensor 12, and the processed image signals are supplied to the image display unit 17 via the synchronization control unit 15. The image display unit 17 sequentially displays the supplied image signals on a display device, thereby displaying a live view image, and the user can perform framing while viewing the displayed live view image.

[0019] In this state, when a shutter release button (not shown) included in the operation unit 16 is pressed, one frame of image signals output from the image sensor 12 is taken into the signal processing unit 13 under the control of the synchronization control unit 15. The signal processing unit 13 performs signal processing on the captured image signal for one frame, and supplies the processed image signal to the compression / decompression unit 14.

[0020] The compression / decompression unit 14 compresses and encodes the input image signal, and supplies the generated encoded data to the image recording unit 18 via the synchronization control unit 15. As a result, a data file of the captured still image is recorded on a recording medium via the image recording unit 18.

[0021] On the other hand, when playing back a still image recorded on a recording medium, the synchronization control unit 15 reads out a data file of the still image selected in response to an operation input from the operation unit 16 from the recording medium via the image recording unit 18, and supplies the data file to the compression / decompression unit 14. The compression / decompression unit 14 performs a decompression / decoding process on the supplied data file, and the decoded image signal is supplied to the image display unit 17 via the synchronization control unit 15, whereby the still image is played back and displayed on the display device.

[0022] Furthermore, when recording moving images, when a moving image recording button (not shown) included in operation unit 16 is pressed, image signals read out from image sensor 12 at a predetermined cycle are sequentially processed by signal processing unit 13 under the control of synchronization control unit 15. Then, the processed image signals are subjected to compression encoding processing by compression / expansion unit 14, and the generated encoded data of the moving images is sequentially transferred to image recording unit 18 and recorded on a recording medium.

[0023] Furthermore, when playing back moving images recorded on a recording medium, the synchronization control unit 15 sequentially reads out image data of frame images of a moving image data file selected in response to an operation input from the operation unit 16 from the recording medium via the image recording unit 18, and supplies the image data to the compression / decompression unit 14. The compression / decompression unit 14 sequentially performs decompression / decoding on the supplied image data, and the decoded image signals are supplied to the image display unit 17 via the synchronization control unit 15, thereby playing back and displaying the moving images on the display device.

[0024] Next, the image sensor 12 in this embodiment will be described. Fig. 2 is a block diagram showing a schematic configuration of the image sensor 12. The image sensor 12 shown in Fig. 2 includes, for example, a CMOS sensor, and is provided with a pixel region 201 in which a plurality of pixels 200 are arranged in a matrix, a vertical scanning unit 202, CDS (Correlated Double Sampling) units 203_1 to 203_8, first selecting units 204_1 to 204_4, ΔΣ modulators 205_1 to 205_4, a second selecting unit 401, decimation filters 206_1 to 206_4, a horizontal scanning unit 207, an output unit 208, and a timing unit 209.

[0025] The plurality of pixels 200 that make up the pixel region 201 are arranged in a matrix in the horizontal and vertical directions. In Fig. 2, each pixel is represented as Pij, where i is the row and j is the column, and pixel P11 in the first row and first column to pixel P88 in the eighth row and eighth column are shown. Note that in this embodiment, an 8 x 8 array (8 rows and 8 columns) is described as an example, but the pixel array in the pixel region 201 is not limited to this number and is usually composed of a very large number of pixels 200.

[0026] In addition, the multiple pixels 200 are covered with color filters in a 2x2 array, known as a Bayer array, in which odd-numbered rows are a repeat of R (red) filters and G (green) filters, and even-numbered rows are a repeat of G (green) filters and B (blue) filters.

[0027] The vertical scanning unit 202 selects the pixels 200 in the pixel region 201 row by row, and controls operations related to resetting, charge accumulation, and readout of the pixels 200 in the selected row. The pixel control lines 210 are wired for each row of the pixels 200 and transmit drive control signals from the vertical scanning unit 202 for each row.

[0028] The vertical signal lines 211 are connected to each column of the pixels 200, and the image signals of the pixels 200 in the row selected by the pixel control lines 210 are read out to the corresponding vertical signal lines 211, respectively. The CDS units 203_1 to 203_8 are provided for each vertical signal line 211, and perform CDS processing for each pixel signal sent through the vertical signal line 211 in units of a row to find the difference between the signal voltage and the reset voltage.

[0029] The first selection units 204_1 to 204_4 are respectively connected to the CDS units 203_1 and 203_2 to 203_8, the CDS units 203_3 and 203_4, the CDS units 203_5 and 203_6, and the CDS units 203_7 and 203_8, and select one of the outputs of the connected CDS units 203 and output the selected one to the downstream delta-sigma modulators 205_1 to 205_4.

[0030] The delta-sigma modulators 205_1 to 205_4 convert the analog pixel signals after CDS processing, which are input from the first selection units 204_1 to 204_4, into 1-bit digital image signals. Note that the configuration of the delta-sigma modulators 205_1 to 205_4 will be described later with reference to FIG.

[0031] The second selection unit 401 selects and outputs one of the signals input from the ΔΣ modulators 205_1 to 205_4 based on a control signal from the timing unit 209 input via a control line 402.

[0032] The decimation filters 206_1 to 206_4 count the 1-bit (1 or 0) digital signal input from the second selection unit 401 or the ΔΣ modulators 205_2 to 205_4 for a predetermined time to convert it into a multi-bit signal. For example, 8-bit AD conversion is realized by digitally converting the amplitude of the input signal to a corresponding value from 0 LSB to 255 LSB.

[0033] The horizontal scanning unit 207 sequentially selects the decimation filters 206_1 to 206_4 via the column selection lines 213 connected thereto, and controls the decimation filters 206_1 to 206_4 to transfer the digitized pixel signals to the output unit 208 via the horizontal signal lines 212. The output unit 208 outputs the digitized pixel signals in units of rows to the signal processing unit 13 .

[0034] The timing unit 209 outputs various clock signals, control signals, etc. required for the operation of each unit of the image sensor 12 based on a control signal from the synchronization control unit 15 .

[0035] Control lines 214 to 219, 402 transmit clock signals, control signals, etc. from the timing unit 209 to the vertical scanning unit 202, the CDS units 203_1 to 203_8, the first selection units 204_1 to 204_4, the ΔΣ modulators 205_1 to 205_4, the decimation filters 206_1 to 206_4, the horizontal scanning unit 207, and the second selection unit 401, respectively.

[0036] Fig. 3 is a block diagram showing the configuration of the ΔΣ modulators 205_1 to 205_4 shown in Fig. 2. Since the ΔΣ modulators 205_1 to 205_4 have the same configuration, they will be referred to as the ΔΣ modulator 205 in the following description. As shown in FIG. 3, the ΔΣ modulator 205 includes a subtraction circuit 300, an integration circuit 301, a comparator 302, and a digital-to-analog converter (DAC) 303.

[0037] The subtraction circuit 300 outputs to the integration circuit 301 the difference between the pixel signal input from the corresponding first selection unit 204 among the first selection units 204_1 to 204_4 and the output signal of the DAC 303. The integrating circuit 301 includes an integrator that integrates the input signal from the subtracting circuit 300. As the integrating circuit 301, a general integrating circuit such as a gm-C integrating circuit using a transconductor or an RC integrating circuit using an operational amplifier can be used.

[0038] The comparator 302 compares the reference voltage Vref with the voltage signal output from the integrating circuit 301 in synchronization with a clock signal, and outputs the comparison result as a 1-bit digital signal. For example, if the voltage signal output from the integrating circuit 301 is lower than the reference voltage Vref, the comparator 302 outputs 0, and if the voltage signal is equal to or higher than the reference voltage Vref, the comparator 302 outputs 1. This digital signal is supplied to the DAC 303 and is also supplied to the decimation filters 206_1 to 206_4 via the second selecting unit 401 or directly without via the second selecting unit 401, and is counted.

[0039] The DAC 303 converts the digital signal output from the comparator 302 into a predetermined analog signal amount and outputs it to the subtraction circuit 300. For example, when the digital signal output is 1, an analog signal of a predetermined level is output. Note that various circuits can be used as the configuration of the digital-to-analog conversion circuit. Then, as described above, the subtraction circuit 300 subtracts the output signal of the DAC 303 from the pixel signal input from the first selection unit 204, and outputs the obtained difference to the integration circuit 301.

[0040] In the ΔΣ modulator 205 having the above configuration, the larger the pixel signal input from the first selection unit 204, the more frequently the comparator 302 outputs a 1. Therefore, by counting the number of times that the ΔΣ modulator 205 outputs a 1 over a predetermined period of time using the decimation filter 206, a count value corresponding to the magnitude of the pixel signal can be obtained, allowing it to be converted into a digital signal.

[0041] 4 is a block diagram showing input / output signals to the second selection unit 401. The ΔΣ modulators 205_1 to 205_4 convert pixel signals after CDS processing into 1-bit digital signals and output them. At this time, the digital signals after AD conversion for each column are designated as stream data st1, st3, st5, and st7. The stream data st1, st3, st5, and st7 are input to the second selection unit 401, and the stream data st1, st3, st5, and st7 selected in accordance with selection signals mx1, mx3, mx5, and mx7 input from the timing unit 209 via a control line 402 are output.

[0042] Next, the driving of the image sensor 12 having the above configuration will be described. In this embodiment, reading can be performed in an all-pixel reading mode in which image signals are read out from all pixels 200, and in an addition reading mode in which image signals are added (multiplexed) and read out. Control in each mode will be described in detail below.

[0043] (All pixel readout mode) 5 is a timing chart showing control signals to the second selection unit 401 and decimation filters 206_1 to 206_4 in the all-pixel readout mode, and input / output signals to the second selection unit 401. Each signal in FIG. 5 is assumed to be in either a high state (referred to as "H") or a low state (referred to as "L"). Furthermore, sck represents a clock signal, and each unit of the image sensor 12 is controlled in synchronization with the clock signal sck.

[0044] The pixel signals of the pixels P11 to P18 are processed by the CDS units 203_1 to 203_8 of each column via the vertical signal line 211 and then input to the first selection units 204_1 to 204_4. In the first selection units 204_1 to 204_4, the pixel signals of the pixels P11, P13, P15, and P17 are first selected from the input pixel signals of the pixels P11 to P18 and input to the ΔΣ modulators 205_1 to 205_4, respectively.

[0045] The ΔΣ modulators 205_1 to 205_4 convert the pixel signals after CDS processing into 1-bit digital signals and output stream data st1, st3, st5, and st7. At this time, the stream data st1, st3, st5, and st7 output from the ΔΣ modulators 205_1 to 205_4 are input to the second selection unit 401 at the cycle of the clock sck, and the stream data st3, st5, and st7 are also input to the decimation filters 206_2 to 206_4.

[0046] In the all-pixel readout mode, of the selection signals mx1, mx3, mx5, and mx7 for selecting a signal in the second selection unit 401, the selection signal mx1 is H and the selection signals mx3, mx5, and mx7 are L, and these are supplied from timing 209 via a control line 402. As a result, of the stream data st1, st3, st5, and st7 input to the second selection unit 401, the stream data st1 is output to the decimation filter 206_1 as the output signal mdata of the second selection unit 401.

[0047] The decimation filters 206_1 to 206_4 sample the output signal mdata (here, stream data st1) and stream data st3, st5, and st7 at the rising timing of the decimation clock dck generated in accordance with the cycle of the clock sck, and count the number of Hs. This makes it possible to count the number of Hs in the stream data st1, st3, st5, and st7 output from each of the ΔΣ modulators 205_1 to 205_4. This makes it possible to convert analog signals in odd-numbered or even-numbered columns of a selected row, out of the signals output from the CDS units 203_1 to 203_8, into digital values.

[0048] Then, at the next timing, the first selection units 204_1 to 204_4 select the pixel signals of pixels P12, P14, P16, and P18 from the input pixel signals of pixels P11 to P18 and perform the same process, thereby completing the readout of one row. By sequentially performing the above process for all rows, the pixel signals of all pixels 200 can be read out.

[0049] (Additional readout mode) Fig. 6 is a timing chart showing control signals to the second selection unit 401 and decimation filter 206_1 in the binning readout mode, and input / output signals to the second selection unit 401. As in Fig. 5, each signal in Fig. 6 is assumed to be in either a high state (referred to as "H") or a low state (referred to as "L"). Also, sck represents a clock signal, and each unit of the image sensor 12 is controlled in synchronization with the clock signal sck.

[0050] In this embodiment, color filters in a 2×2 Bayer array are arranged in the plurality of pixels 200, so a case will be described in which pixel signals of four pixels of the same color are added in the horizontal direction.

[0051] The pixel signals of the pixels P11 to P18 are processed by the CDS units 203_1 to 203_8 of each column via the vertical signal line 211 and then input to the first selection units 204_1 to 204_4. In the first selection units 204_1 to 204_4, the pixel signals of the pixels P11, P13, P15, and P17 are first selected from the input pixel signals of the pixels P11 to P18 and input to the ΔΣ modulators 205_1 to 205_4, respectively.

[0052] The delta-sigma modulators 205_1 to 205_4 convert the pixel signals after CDS processing into 1-bit digital signals and output stream data st1, st3, st5, and st7. At this time, the stream data st1, st3, st5, and st7 output from the delta-sigma modulators 205_1 to 205_4 are input to the second selection unit 401 at the cycle of the clock sck, and the stream data st3, st5, and st7 are also input to the decimation filters 206_2 to 206_4. Up to this point, the operation is the same as in the all-pixel readout mode.

[0053] In the accumulating readout mode, in each cycle of the clock sck, the second selection unit 401 is sequentially supplied with selection signals mx1, mx3, mx5, and mx7 of different phases, which are supplied from the timing unit 209 via the control line 402. Specifically, in one cycle of the clock sck from time T1 to T6, while the selection signal mx1 is H, stream data st1(H) is output as the output signal mdata from the second selection unit 401. Also, while the selection signal mx2 is H, stream data st3(H) is output, while the selection signal mx3 is H, stream data st5(L) is output, and while the selection signal mx4 is H, stream data st7 is output as the output signal mdata.

[0054] Thereafter, the output signal mdata is output from the second selection section 401 under similar control at each period of the clock sck, that is, from time T6 to time T7, from time T7 to time T8, and from time T8 to time T9.

[0055] In the decimation filter 206_1, the output signal mdata output from the second selection unit 401 is sampled at the rising edge of the decimation clock dck generated in accordance with the cycles of the selection signals mx1, mx3, mx5, and mx7, and the number of Hs is counted. This makes it possible to count the sum of signals for four pixels. At this time, although not shown, the decimation filters 206_2 to 206_4 are controlled not to sample and count the stream data st3, st5, and st7 by not supplying the decimation clock dck to them or by keeping it at L.

[0056] At the next timing, the first selection units 204_1 to 204_4 select the signals of pixels P12, P14, P16, and P18 from the input pixel signals of pixels P11 to P18 and perform the same process, thereby completing the additive readout for one row. By sequentially performing the above process for all rows, it is possible to read out the pixel signals of all pixels 200 while adding them together in the horizontal direction.

[0057] As described above, according to the first embodiment, the outputs of the ΔΣ modulators 205_1 to 205_4 of the columns to be added are input to the second selection unit 401 and multiplexed in a time-division manner, making it possible to perform AD conversion while adding multiple pixel signals.

[0058] Furthermore, since the decimation filters 206_2 to 206_4 (that is, ¾ of all the decimation filters 206) used when no addition is performed are controlled not to operate, it is possible to reduce power consumption.

[0059] Furthermore, when performing horizontal pixel addition in an analog manner, a separate sample-and-hold circuit consisting of a switch and a capacitor is required, but with this embodiment, there is no need to add a dedicated analog circuit or control signal line for the addition operation, making it possible to reduce the circuit size.

[0060] In the first embodiment, for convenience, the first selection unit 204 and the ΔΣ modulator 205 are arranged every two columns, but this may be changed as appropriate depending on the combination of pixels to be added. Furthermore, the number of signals to be added is not limited to four pixels, but may be any other number. In that case, the second selection unit 401 may be configured for each desired column and controlled in the same manner.

[0061] Furthermore, in the above example, the first selection units 204_1 to 204_4 are configured to select and output one of two columns of pixel signals, but the first selection units 204_1 to 204_4 do not have to be provided. In that case, the same number of ΔΣ modulators as the CDS units may be provided, and the second selection unit 401 may select and multiplex digital signals to be added from the plurality of digital signals input from the ΔΣ modulators.

[0062] <Second embodiment> Next, a second embodiment of the present invention will be described. In the first embodiment, a configuration and control for adding pixel signals in the horizontal direction of the image sensor 12 is described, but in the second embodiment, a configuration and control for adding pixel signals in the vertical direction of the image sensor 12 is described. Note that the configuration of the imaging device excluding the image sensor 12 is the same as that described in the first embodiment with reference to Fig. 1, and therefore a description thereof will be omitted here.

[0063] Fig. 7 is a block diagram showing a schematic configuration of the image sensor 12 according to the second embodiment, and shows the configuration of an 8 x 4 array (8 rows and 4 columns) of pixels 200. In the image sensor 12 shown in Fig. 7, the same components as those in the image sensor 12 shown in Fig. 2 are denoted by the same reference numerals.

[0064] 2, the configuration of the image sensor 12 shown in FIG. 7 is configured such that two vertical signal lines are provided for each column, enabling pixels in different rows to be read out to different CDS units 203_1 to 203_8. For example, pixel signals of pixels P11 and P31 can be output to vertical signal lines 602 and 601, respectively. Furthermore, switches 603_1 to 603_4 are configured to connect the CDS units 203_2 and 203_4, the CDS units 203_1 and 203_3, the CDS units 203_6 and 203_8, and the CDS units 203_5 and 203_7, respectively. The CDS units 203_1 to 203_8, first selection units 204_1 to 204_4, and ΔΣ modulators 205_1 to 205_4 are configured for the vertical signal lines of each column.

[0065] Next, the driving of the image sensor 12 having the above configuration will be described. In this embodiment, readout can be performed in an all-pixel readout mode in which image signals are read out from all pixels 200, and in an addition readout mode in which image signals are added (multiplexed) and read out. Control in each mode will be described below.

[0066] (All pixel readout mode) In the all-pixel readout mode, the switches 603_1 to 603_4 are turned off (disconnected). When the first or second row is selected by the vertical scanning unit 202, the first selecting units 204_1 to 204_4 select pixel signals from the CDS units 203_2, 203_4, 203_6, and 203_8. When the third or fourth row is selected, the first selecting units 204_1 to 204_4 select pixel signals from the CDS units 203_1, 203_3, 203_5, and 203_7. In this way, when the (4n+1)th row or the (4n+2)th row is selected, and when the (4n+3)th row or the (4n+4)th row is selected (n is a natural number including 0), the CDS unit 203 corresponding to the pixel 200 to be read out is selected from among the CDS units 203_1 to 203_8 by the first selection units 204_1 to 204_4, and thereafter, pixel signals of all the pixels 200 can be read out by control according to the timing chart shown in FIG. 5.

[0067] (Additional readout mode) Next, the binning readout mode in the second embodiment will be described. In the second embodiment, signals from multiple rows are binned and read out, and when this vertical binning operation is performed, switches 603_1 to 603_4 that connect vertical signal lines 601 and vertical signal lines 602 in different columns are turned on (connected). Also, the image sensor 12 in the second embodiment is capable of selecting pixels to be read out row by row and column by column.

[0068] First, the vertical scanning unit 202 selects pixels in the first and third rows and the first column. As a result, pixel signals of pixels P11 and P31 are output to vertical signal lines 602 and 601. At this time, as described above, the switches 603_1 to 603_4 are on, and therefore the signals output to the vertical signal lines 602 and 601 are output to the CDS units 203_2 and 203_4, and the CDS units 203_1 and 203_3, respectively.

[0069] The first selection unit 204_1 selects the CDS unit 203_2 from the pixel signals of pixels P11 and P31 input from the CDS units 203_2 and 203_1, and outputs the pixel signal of pixel P11 to the ΔΣ modulator 205_1. Also, the first selection unit 204_2 selects the CDS unit 203_3 from the pixel signals of pixels P11 and P31 input from the CDS units 203_4 and 203_3, and outputs the pixel signal of pixel P31 to the ΔΣ modulator 205_1.

[0070] The ΔΣ modulators 205 _ 1 and 205 _ 2 convert the input pixel signals of the pixels P 11 and P 31 into 1-bit digital signals, respectively, to generate stream data st 1 and st 3 , and output them to the second selection unit 401 .

[0071] The second selection unit 401 alternately sets the selection signals mx1 and mx2 to H, thereby alternately selecting and time-division multiplexing the stream data st1 and st3, and outputs the multiplexed output signal mdata to the decimation filter 206_1.

[0072] The decimation filter 206_1 samples the output signal mdata output from the second selection unit 401 at the rising edge of the decimation clock dck generated in accordance with the cycles of the selection signals mx1 and mx2, and counts the number of Hs. This makes it possible to count the sum of signals for two pixels in the vertical direction. At this time, the decimation filters 206_2 to 206_4 are controlled not to sample and count the input stream data by not supplying the decimation clock dck to them or by keeping it at L.

[0073] Then, while maintaining the selection of the first and third rows, the selected columns are shifted in sequence, such as the second column, the third column, etc., to sequentially read out pixels P12 and P32, pixels P13 and P33, pixels P14 and P34, etc. Then, the pixel signals of the read-out pixels are vertically added together, thereby completing the readout of the first and third rows.

[0074] By performing the above-described process while shifting the selected row, the pixel signals of all the pixels 200 can be read out while being added in the vertical direction.

[0075] As described above, according to the second embodiment, the outputs of the ΔΣ modulators 205_1 to 205_4 of the columns to be added are input to the second selection unit 401 and multiplexed in a time-division manner, making it possible to AD convert the pixel signals of multiple vertically arranged pixels 200 while adding them together.

[0076] Furthermore, similarly to the case of horizontal addition, the decimation filters 206_206_4 (that is, ¾ of all the decimation filters 206) used during non-addition are controlled not to operate, thereby making it possible to reduce power consumption.

[0077] Furthermore, when vertical pixel addition is performed in an analog manner, a known method is to simultaneously connect pixels to be added to the same vertical signal line, but this method raises concerns that signal characteristics may be degraded due to improper averaging processing.In contrast, this type of degradation of characteristics does not occur in this embodiment.

[0078] In the second embodiment, the vertical addition operation of pixel signals has been described, but various combinations of addition are possible by switching the selection of the pixel 200 to be read and the control method of the first selection units 204_1 to 204_4 and the second selection unit 401. For example, pixel signals of four pixels, pixels P11, P13, P31, and P33, can be added and read out. In this case, the control is as follows.

[0079] First, with the first and third rows selected, the first and third columns are selected and pixel signals of four pixels, P11, P13, P31, and P33, are output to the CDS units 203_1 to 203_8. Then, the first selection units 204_1 to 204_4 select pixel signals of four pixels, P11, P31, P13, and P33, and output the pixel signals to the delta-sigma modulators 205_1 to 205_4. The delta-sigma modulators 205_1 to 205_4 convert the pixel signals into 1-bit digital signals and output the resulting data streams to the second selection unit 401, which sequentially selects the input data streams to perform time-division multiplexing. The decimation filter 206_1 samples and counts the multiplexed data stream, thereby converting the pixel signals of the pixels P11, P13, P31, and P33 into a digital signal obtained by adding them together.

[0080] <Summary> The disclosure of this embodiment includes the following configuration.

[0081] (Item 1) a pixel region in which a plurality of pixels are arranged in a matrix; a plurality of analog-to-digital conversion means for performing analog-to-digital conversion using ΔΣ modulation on analog signals output from a plurality of selected pixels among the plurality of pixels, and outputting digital signals; a selection means for receiving a plurality of digital signals from the plurality of analog-to-digital conversion means, and selecting and outputting at least one digital signal; a plurality of filters for converting digital signals output from the selection means and any of the plurality of analog-to-digital conversion means into multi-bit signals; a control means for controlling the selection means and the plurality of filters; an image sensor characterized in that, when performing an addition readout in which signals of a plurality of pixels are added and read out, the control means controls the selection means so that, in each predetermined period, digital signals to be added out of the plurality of digital signals are multiplexed in a time-division manner and output, and the control means controls the filter so as to multiply the multiplexed digital signals. (Item 2) The image sensor according to item 1, characterized in that, when the additive readout is performed, the control means controls the plurality of filters so that filters other than the filter that converts the multiplexed digital signal into multi-bit signals do not operate. (Item 3) 3. The image sensor according to item 1 or 2, wherein the control means controls the selection means to output, in each of the cycles, a digital signal output from a predetermined analog-to-digital conversion means among the plurality of digital signals when the additive readout is not performed. (Item 4) 4. The imaging element according to item 3, wherein the plurality of filters are connected to the selection means and to the plurality of analog-to-digital conversion means excluding the predetermined analog-to-digital conversion means among the plurality of analog-to-digital conversion means. (Item 5) vertical signal lines wired to each column of the plurality of pixels arranged in a matrix; a plurality of second selection means provided for each of a predetermined number of the vertical signal lines, 5. The image sensor according to any one of items 1 to 4, wherein each of the plurality of second selection means selects one of the analog signals input via the plurality of vertical signal lines and outputs the selected analog signal to the plurality of analog-to-digital conversion means. (Item 6) The imaging element described in item 5, characterized in that each of the plurality of second selection means sequentially selects and outputs analog signals input via the plurality of vertical signal lines at a predetermined second period. (Item 7) vertical signal lines, each of which is wired for each column of the plurality of pixels, and the pixels connected to the vertical signal lines are different; a plurality of switches capable of switching between connection and disconnection of the vertical signal lines, the vertical signal lines being in different columns and connected to pixels in the same row; a plurality of second selection means provided for each of the plurality of vertical signal lines, the control means further controls the plurality of switches, and when performing the addition readout, turns on the plurality of switches to connect the plurality of vertical signal lines; 5. The image sensor according to any one of items 1 to 4, wherein the plurality of second selection means each selects a signal of a different vertical signal line from among the analog signals input via the plurality of vertical signal lines and outputs the selected signal to the plurality of analog-to-digital conversion means. (Item 8) each of the plurality of analog-to-digital conversion means outputs stream data of a 1-bit digital signal; 8. The image sensor according to any one of items 1 to 7, wherein the plurality of filters each convert the digital signal input from the selection means or the analog-to-digital conversion means into a multi-bit signal by counting the number of times the digital signal becomes 1. (Item 9) The imaging element according to any one of items 1 to 8, a signal processing means for processing a signal output from the imaging element; An electronic device comprising:

[0082] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0083] 200...pixel, 201...pixel region, 202...vertical scanning section, 203_1 to 203_8...CDS section, 204_1 to 204_4...first selection section, 205_1 to 205_4...ΔΣ modulator, 206_1 to 206_4...decimation filter, 207...horizontal scanning section, 208...output section, 209...timing section, 210...pixel control line, 211, 601, 602...vertical signal line, 212...horizontal signal line, 213...column selection line, 214 to 219, 300...subtraction circuit, 301...integration circuit, 302...comparator, 303...digital-analog converter, 402...control line, 401...second selection section, 603_1 to 603_4...switches

Claims

1. a pixel region in which a plurality of pixels are arranged in a matrix; a plurality of analog-to-digital conversion means for performing analog-to-digital conversion using ΔΣ modulation on analog signals output from a plurality of selected pixels among the plurality of pixels, and outputting digital signals; a selection means for receiving a plurality of digital signals from the plurality of analog-to-digital conversion means, and selecting and outputting at least one digital signal; a plurality of filters for converting digital signals output from the selection means and any of the plurality of analog-to-digital conversion means into multi-bit signals; a control means for controlling the selection means and the plurality of filters; an image sensor characterized in that, when performing an addition readout in which signals of a plurality of pixels are added and read out, the control means controls the selection means so that, in each predetermined period, digital signals to be added out of the plurality of digital signals are multiplexed in a time-division manner and output, and the control means controls the filter so as to multiply the multiplexed digital signals.

2. 2. The image sensor according to claim 1, wherein the control means controls the plurality of filters so that, when the additive readout is performed, filters other than the filter that converts the multiplexed digital signal into multi-bit signals do not operate.

3. 2. The image sensor according to claim 1, wherein the control means controls the selection means to output, in each of the cycles, a digital signal output from a predetermined analog-to-digital conversion means from among the plurality of digital signals when the additive readout is not performed.

4. 4. The imaging device according to claim 3, wherein the plurality of filters are connected to the selection means and to the plurality of analog-to-digital conversion means excluding the predetermined analog-to-digital conversion means among the plurality of analog-to-digital conversion means.

5. vertical signal lines wired to each column of the plurality of pixels arranged in a matrix; a plurality of second selection means provided for each of a predetermined number of the vertical signal lines, 2. The image sensor according to claim 1, wherein each of the plurality of second selection means selects one of the analog signals input via the plurality of vertical signal lines and outputs the selected analog signal to the plurality of analog-to-digital conversion means.

6. 6. The image sensor according to claim 5, wherein the plurality of second selection means each select and output analog signals input via the plurality of vertical signal lines in sequence at a predetermined second cycle.

7. vertical signal lines, each of which is wired for each column of the plurality of pixels, and the pixels connected to the vertical signal lines are different; a plurality of switches capable of switching between connection and disconnection of the vertical signal lines, the vertical signal lines being in different columns and connected to pixels in the same row; a plurality of second selection means provided for each of the plurality of vertical signal lines; the control means further controls the plurality of switches, and when performing the addition readout, turns on the plurality of switches to connect the plurality of vertical signal lines; 2. The image sensor according to claim 1, wherein the plurality of second selection means each selects a signal from a different vertical signal line from among the analog signals input via the plurality of vertical signal lines and outputs the selected signal to the plurality of analog-to-digital conversion means.

8. each of the plurality of analog-to-digital conversion means outputs stream data of a 1-bit digital signal; 2. The image sensor according to claim 1, wherein each of the plurality of filters converts the digital signal input from the selection means or the analog-to-digital conversion means into a multi-bit signal by counting the number of times the digital signal becomes 1.

9. The imaging device according to any one of claims 1 to 8, a signal processing means for processing a signal output from the imaging element; An electronic device comprising:

Images