Method of manufacturing semiconductor device
The method employs a scan data controller to manage test patterns and responses in large-scale semiconductor circuits, addressing the challenge of high test costs and complexity by optimizing test pin usage and circuit efficiency.
Patent Information
- Application Number
- JP2024131758
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-08-08
- Publication Date
- 2026-02-20
AI Technical Summary
Existing methods fail to effectively control test pattern input and test response output in semiconductor circuits with a scale of one million to several hundred million gates while meeting test cost constraints.
A method involving a scan data controller that tests a portion of circuits on a wafer by transmitting test patterns to scan chains and receiving responses, utilizing a decoder module and scan data bus to manage test data efficiently, reducing the number of test pins and circuit overhead.
Enables control of test pattern input and output in large-scale semiconductor circuits within budgetary constraints, ensuring high-speed testing and reduced overhead.
Smart Images
Figure 2026029083000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]
[0002] As semiconductor products become larger and smaller, the number of internal elements relative to external terminals is exploding. This has resulted in an explosive increase in test complexity, making it impossible to guarantee test quality within limited time and cost. Non-Patent Documents 1 and 2 disclose a test method in which flip-flop circuits are replaced with scan flip-flops and connected as a scan chain, thereby enabling the scan flip-flops to function as pseudo external terminals. [Prior art documents] [Non-patent literature]
[0003] [Non-Patent Document 1] Encounter Test SmartScanhttp: / / www.candence.com / japan / archive / soconline / vol14 / tec / tec 1.html [Non-patent document 2] B.Refal, et al. “Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation”, ACM TODAES, vol. 20, Feb. 2015 Summary of the Invention [Problem to be solved by the invention]
[0004] However, there has been a problem in that there is no method for manufacturing a semiconductor device that controls test pattern input and test response output in a circuit with a scale of one million to several hundred million gates while satisfying test costs. Therefore, an object of the present disclosure is to provide a method for manufacturing a semiconductor device that controls test pattern input and test response output in a circuit with a scale of one million to several hundred million gates while satisfying test costs.
[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]
[0006] According to one embodiment, a method for manufacturing a semiconductor device includes testing a portion of a plurality of circuits formed on a wafer by selecting a first scan data controller, transmitting a first test pattern to a plurality of first scan chains, and receiving a first test response corresponding to the first test pattern from the plurality of first scan chains. [Effects of the Invention]
[0007] According to the embodiment, it is possible to provide a manufacturing method for a semiconductor device that controls test pattern input and test response output in a circuit with a scale of one million to several hundred million gates while satisfying test costs. [Brief explanation of the drawings]
[0008] [Figure 1] FIG. 1 is a block diagram showing the configuration of a semiconductor device having a test circuit using a related compressed scan design. [Figure 2] 1 is a flowchart of a method for manufacturing a semiconductor device according to the present disclosure. [Figure 3] 1 is a block diagram showing a first configuration of a semiconductor device having a test circuit using a scan data controller according to the present disclosure. [Figure 4]1A and 1B are block diagrams illustrating the configuration of a decoder module of the present disclosure, where (a) highlights the transfer access control module and (b) highlights the transfer data control module. [Figure 5] FIG. 2 is a block diagram showing a configuration of a first scan data controller of the present disclosure. [Figure 6] FIG. 2 is a block diagram illustrating the relationship between a decoder module and a scan data controller of the present disclosure. [Figure 7] FIG. 1 is a block diagram illustrating the correspondence between the number of test circuits and pins using the compressed scan design of the present disclosure. [Figure 8] FIG. 10 is a block diagram showing a second configuration of a semiconductor device having a test circuit using the scan data controller of the present disclosure. [Figure 9] FIG. 10 is a block diagram showing a third configuration of a semiconductor device having a test circuit using the scan data controller of the present disclosure. [Figure 10] 1A and 1B are block diagrams showing the configuration of a first FIFO circuit of the present disclosure, in which FIG. 1A highlights a first transfer data control module, FIG. 1B highlights a first test response output FIFO module, and FIG. 1C highlights a first test pattern input FIFO module. [Figure 11] 1 is a flowchart of the testing method of the present disclosure. [Figure 12] 10 is a flowchart of a test circuit using the FIFO circuit of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0009] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in hardware terms by a CPU (Central Processing Unit), memory, or other circuits, and in software terms by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on hardware, or a combination thereof. In addition, the same elements are designated by the same reference numerals in each drawing, and redundant explanations are omitted as necessary.
[0010] The above-described program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program can also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path.
[0011] (Description of a Semiconductor Device Having Test Circuits Using Related Compressed Scan Design) 1 is a block diagram showing the configuration of a semiconductor device having a test circuit that uses a related compressed scan design. A semiconductor device having a test circuit that uses a related compressed scan design will be described with reference to FIG.
[0012] As shown in FIG. 1, a semiconductor device 101 (Device Under Test (DUT)) includes a decompression circuit 102, a compression circuit 103, and multiple scan chains 104. A compressed scan design refers to the use of the decompression circuit 102 and the compression circuit 103.
[0013] When test data is generated, it is compressed using a compression algorithm, and a decompression circuit 102 for that data is placed between the external terminals and the inputs of the scan chains 104. For example, four input terminals SI1 to SI4 are connected to five scan chains 104 via the decompression circuit 102.
[0014] A compression circuit 103 is installed between the scan chain output and the external terminal to decompress the data obtained from the external terminal. For example, five scan chains 104 are connected to four output terminals SO1 to SO4 via the compression circuit.
[0015] The compression ratio is expressed as the ratio of input terminals to the number of scan chains, and output terminals to the number of scan chains. If the compression ratio is too high, the test quality will deteriorate rapidly. The test cost is expressed as the number of test pins x test time x test circuit size. If the test cost becomes too high compared to the circuit size, the test time will be too long and it will become unusable. Therefore, test circuits using compressed scan design can be applied to 1 million to 100 million gates based on test cost requirements.
[0016] The LOW PIN COUNT TEST described in Non-Patent Document 1 is applied to 100,000 to 500,000 gates due to test cost requirements, while the STREAMING SCAN NETWORK (SSN) PROTOCOL described in Non-Patent Document 2 is applied to 2 billion gates or more because the overhead ratio is high when the circuit scale is small.
[0017] Thus, due to the test cost requirements for circuits using compressed scan design and the overhead of the SSN protocol, there was a problem that there was no test circuit suitable for testing circuits with hundreds of millions of gates.
[0018] (Description of a Manufacturing Method of a Semiconductor Device According to an Embodiment) 2 is a flowchart of the method for manufacturing a semiconductor device according to the present disclosure. With reference to FIG. 2, how the testing method according to the present disclosure is incorporated into the method for manufacturing a semiconductor device according to the embodiment will be described.
[0019] As shown in FIG. 2, first, a wafer is prepared (S201). The wafer is a semiconductor wafer on which a semiconductor device is formed. A semiconductor wafer is a substrate obtained by slicing a single crystal made by growing, for example, silicon or gallium arsenide. Semiconductor wafers come in various sizes, such as diameters of 150 mm, 200 mm, and 300 mm.
[0020] Next, a plurality of semiconductor devices each having a plurality of circuits are formed on the wafer (step S202). A plurality of semiconductor devices each having a plurality of circuits are formed on the wafer through various semiconductor device manufacturing processes such as photolithography, doping, and etching.
[0021] Next, the plurality of circuits are tested (step S203). A part of the plurality of circuits formed in each of the plurality of semiconductor devices is tested. The part of the plurality of circuits is tested by a test circuit using a scan data controller, which will be described later.
[0022] Finally, the wafer is divided to obtain a plurality of semiconductor devices (step S204). The wafer is divided to obtain a plurality of individual semiconductor devices. The process of dividing the wafer is called dicing.
[0023] With the above configuration, testing by a test circuit using a scan data controller is incorporated into the manufacturing method of a semiconductor device.
[0024] (Description of a Test Circuit Using a Scan Data Controller According to an Embodiment) FIG. 3 is a block diagram showing a first configuration of a semiconductor device having a test circuit using a scan data controller according to the present disclosure. FIG. 4 is a block diagram showing a configuration of a decoder module according to the present disclosure, with (a) emphasizing a transfer access control module and (b) emphasizing a transfer data control module. FIG. 5 is a block diagram showing a configuration of a first scan data controller according to the present disclosure. FIG. 6 is a block diagram showing the relationship between the decoder module and the scan data controller according to the present disclosure. FIG. 11 is a flowchart of a test method according to the present disclosure. A test circuit using a scan data controller according to an embodiment will be described with reference to FIGS. 3 to 6 and 11.
[0025] As shown in FIG. 3 , a semiconductor device 301 according to an embodiment includes a scan data bus 302 having a decoder module 303, a first scan data controller 304, and a second scan data controller 305, and a plurality of circuits including a first circuit having a first decompression circuit 306, a first compression circuit 307, and a first set of scan chains to be tested 308, and a second circuit having a second decompression circuit 309, a second compression circuit 310, and a second set of scan chains to be tested 311.
[0026] The first scan chain set 308 includes a plurality of first scan chains 314 configured by electrically connecting a plurality of first flip-flop circuits in series. The second scan chain set 311 includes a plurality of second scan chains 317 configured by electrically connecting a plurality of second flip-flop circuits different from the plurality of first flip-flop circuits in series.
[0027] Here, electrically connected in series means that the output terminal of a first flip-flop circuit is electrically connected directly to the input terminal of another first flip-flop circuit so as to be continuous.
[0028] The decoder module 303 is electrically connected to the first and second scan data controllers. The decoder module 303 selects the first or second scan data controller based on identifier information from the tester. The decoder module 303 transmits the input test pattern input SIDATA to the selected scan data controller. The decoder module 303 also outputs the test response output SODATA received from the selected scan data controller.
[0029] The first scan data controller 304 is electrically connected to a first input terminal 312 and a first output terminal 313 of each of the plurality of first scan chains 314. The second scan data controller 305 is electrically connected to a second input terminal 315 and a second output terminal 316 of each of the plurality of second scan chains 317.
[0030] The first and second scan data controllers have a clock enable function for the scan chain set, transmit test pattern inputs to the connected scan chain set, and transmit received test response outputs to the decoder module 303.
[0031] In this way, one scan data bus 302 includes one decoder module 303 and multiple scan data controllers, the number of which is equal to the number of scan chain sets.
[0032] The first decompression circuit 306 is electrically connected to the first input terminal 312 of each of the plurality of first scan chains 314 in the first scan chain set 308. The first decompression circuit 306 also converts the first test pattern from a data-compressed state to an uncompressed state.
[0033] The first compression circuit 307 is electrically connected to the first output terminal 313 of each of the plurality of first scan chains 314 in the first scan chain set 308. The first compression circuit 307 also converts the first test response from a non-data-compressed state to a data-compressed state.
[0034] The second decompression circuit 309 is electrically connected to the second input terminals 315 of each of the second scan chains 317 of the second scan chain set 311. The second decompression circuit 309 also converts the second test pattern from a data-compressed state to an uncompressed state.
[0035] The second compression circuit 310 is electrically connected to the second output terminal 316 of each of the plurality of second scan chains 317 in the second scan chain set 311. The second compression circuit 310 also converts the second test response from a non-data-compressed state to a data-compressed state.
[0036] The semiconductor device 301 according to the embodiment controls test pattern input and test response output using a decoder module 303 that communicates with a tester and a scan data bus 302 that includes a scan data controller that communicates with a scan chain set. This makes it possible to transmit data to the scan chain set and receive test responses at high speed while reducing the number of test pins and circuit overhead.
[0037] The decoder module 303 will be described in detail with reference to Figure 4. As shown in Figure 4, the decoder module 303 includes a transfer access control module 401 and a transfer data control module 402.
[0038] 4(a), the transfer access control module 401 decodes ID information from the tester and selects a scan data controller. The transfer access control module 401 also controls the data transfer selector of the selected scan data controller. The transfer access control module 401 also controls the clock of the selected scan data controller.
[0039] ASDCT[a:0], which is ID information, is input to the transfer access control module 401. In addition, the transfer access control module 401 outputs sdctrl_sel[a:0] and sdctrl_en[n:0].
[0040] The transfer access control signal ASDCT[a:0] is an input signal from the tester and contains information about the selected scan data controller. a is the number of bits and varies depending on the number of scan data controllers. a = ceil(log2(n)).
[0041] The transfer access control signal sdctrl_sel[a:0] is a control signal for the data transfer selector.
[0042] The transfer access control signal sdctrl_en[n:0] is a clock enable control signal for each scan data controller.
[0043] As shown in FIG. 4(b), the transfer data control module 402 receives the control signal for data transfer and sets the data input selector and data output selector to the selected scan data controller.
[0044] The transfer data control module 402 controls the test response output SODATA[b:0] and the test pattern input SIDATA[b:0].
[0045] The transfer data signal SODATA[b:0] is an output signal from the scan chain set and contains test response information, where b is the number of bits and varies depending on the specification.
[0046] The transfer data signal SIDATA[b:0] is an input signal from the tester and contains test pattern information, where b is the number of bits and varies depending on the specifications.
[0047] The first scan data controller 304 will be described in detail with reference to Fig. 5. As shown in Fig. 5, the first scan data controller 304 includes a first clock control circuit 501. The second scan data controller also includes a similar configuration to the first scan data controller.
[0048] The first clock control circuit 501 controls the first scan clock of the selected scan chain set.
[0049] sdctrl_en[x], SCAN_CLK, and SCAN_EN are input to the first clock control circuit 501. The first clock control circuit 501 outputs gck_scan_clk, which is the first scan clock.
[0050] The clock control signal sdctrl_en[x] indicates 1 while the target scan chain set of the selected scan data controller is transferring data, and indicates 0 otherwise. x varies depending on the scan data controller number.
[0051] The clock control signal gck_scan_clk is SCAN_CLK&SCAN_EN&sdctrl_en[x]. & indicates "and." gck_scan_clk is SCAN_CLK while the target scan chain set of the selected scan data controller is transferring data, and is 0 otherwise.
[0052] 6 shows the transmission and reception of signals between the decoder module 303, the first scan data controller 304, and the second scan data controller 305. For example, the transfer access control module 401 of the decoder module 303 sends sdctrl_en[0] to the first clock control circuit 501 of the first scan data controller 304. The first clock control circuit 501 sends s0_gck_scan_clk to the first scan chain set 308. In other words, the first scan data controller 304 includes the first clock control circuit 501 that controls the first scan clock supplied to the first scan chain set 308.
[0053] Similarly, for example, the transfer access control module 401 of the decoder module 303 sends sdctrl_en[1] to the second clock control circuit 601 of the second scan data controller 305. The second clock control circuit 601 sends s1_gck_scan_clk to the second scan chain set 311. That is, the second scan data controller 305 includes the second clock control circuit 601 that controls the second scan clock supplied to the second scan chain set 311.
[0054] The test pattern input is branched to the first scan data controller 304 and the second scan data controller 305 via the transfer data control module 402. The test response output is integrated from the first scan data controller 304 and the second scan data controller to the transfer data control module 402.
[0055] A test method for a test circuit using a scan data controller according to an embodiment will be described with reference to Fig. 11. As shown in Fig. 11, decoder module 303 selects first scan data controller 304 or second scan data controller 305 based on an identifier from a tester. If the identifier is a first identifier that selects first scan data controller 304, decoder module 303 selects first scan data controller (SDCtrl) 304 (step S1101).
[0056] Next, test data is input / output (step S1102). The decoder module 303 transmits a first test pattern to each of the first input terminals 312 of the first scan chains 314 via the first scan data controller 304. The decoder module 303 then receives a first test response corresponding to the first test pattern from each of the first output terminals 313 of the first scan chains 314 via the first scan data controller 304. In this manner, the first circuit is tested.
[0057] As shown in FIG. 11, next, the decoder module 303 selects the second scan data controller (SDCtrl) 305 if the identifier is the second identifier that selects the second scan data controller 305 (step S1103).
[0058] Next, test data is input / output (step S1104). The decoder module 303 transmits a second test pattern to each of the second input terminals 315 of the plurality of second scan chains 317 via the second scan controller 305. Then, the decoder module 303 receives a second test response corresponding to the second test pattern from each of the second output terminals 316 of the plurality of second scan chains 317 via the second scan data controller 305. In this manner, the second circuit is tested.
[0059] Step S1103 is started after step S1102 is completed. The above method provides a method for manufacturing a semiconductor device that controls test pattern input and test response output in a circuit with a scale of one million to several hundred million gates.
[0060] Although the embodiment has been described as an example having two scan data controllers, there is no limit to the number of scan data controllers as long as there are multiple scan data controllers. In other words, there may be three or more combinations of scan data controllers and circuits to be tested.
[0061] With the above configuration, in a circuit with a scale of one million to several hundred million gates, the scan data bus is placed at the center, communication with the tester is performed, and test patterns are input and test responses are output while switching the selected scan chain set. Therefore, it is possible to provide a manufacturing method for a semiconductor device that controls test pattern input and test response output in a circuit with a scale of one million to several hundred million gates while satisfying test costs.
[0062] (Description of a Test Circuit Using a Scan Data Controller According to the First Embodiment) 7 is a block diagram showing the correspondence between the number of pins and the test circuit using the compressed scan design of the present disclosure. The test circuit using the scan data controller according to the first embodiment will be described with reference to FIG.
[0063] A semiconductor device 701 having a test circuit using the scan data controller according to the first embodiment differs from a semiconductor device 301 having a test circuit using the scan data controller according to the embodiment in that the number of input pins and output pins is not equal.
[0064] As shown in Figure 7, depending on the specifications of the compression scan design, the signal width of SIDATA[a:0] is determined by the number of input pins of the decompression circuit with the most input pins, and the signal width of SODATA[b:0] is determined by the number of output pins of the compression circuit with the most output pins.
[0065] 7, the number of input pins of the first decompression circuit 306 and the number of input pins of the second decompression circuit 309 are 2. Therefore, the input is 2 bits, SIDATA[1:0].
[0066] 7, the number of output pins of the first compression circuit 307 is 2, and the number of output pins of the second compression circuit 310 is 3. Therefore, the output is 3 bits, SODATA[2:0]. Because the number of pins of the first compression circuit 307 is insufficient, a dummy signal is fixed to 0 and output to the decoder module 303.
[0067] (Description of a Test Circuit Using a Scan Data Controller According to a Second Embodiment) 8 is a block diagram showing a second configuration of a semiconductor device having a test circuit using the scan data controller of the present disclosure. The test circuit using the scan data controller according to the second embodiment will be described with reference to FIG.
[0068] The test circuit using the scan data controller according to the second embodiment differs from the test circuit using the scan data controller according to the embodiment in that it does not have a decompression circuit or a compression circuit.
[0069] As shown in FIG. 8, a test circuit using the scan data controller according to the second embodiment requires input pins and output pins equal to the number of first scan chains 314 in the first scan chain set 308 or the number of second scan chains 317 in the second scan chain set 311, whichever is greater.
[0070] In FIG. 8, the number of first scan chains 314 and the number of second scan chains 317 are both five, so five Scan ins and five Scan outs are required.
[0071] In this way, the scan data bus of the present disclosure can be applied even without a compressed scan design.
[0072] (Description of a Test Circuit Using a Scan Data Controller According to a Third Embodiment) FIG. 9 is a block diagram showing a third configuration of a semiconductor device having a test circuit using the scan data controller of the present disclosure. FIG. 10 is a block diagram showing the configuration of a first FIFO circuit of the present disclosure, with (a) emphasizing the first transfer data control module, (b) emphasizing the first test response output FIFO module, and (c) emphasizing the first test pattern input FIFO module. FIG. 12 is a flowchart of a test circuit using the FIFO circuit of the present disclosure. A test circuit using a scan data controller according to a third embodiment will be described with reference to FIGS. 9, 10, and 12.
[0073] The semiconductor device 901 having a test circuit using the scan data controller according to the third embodiment differs from the semiconductor device 301 having a test circuit using the scan data controller according to the embodiment in that the semiconductor device 901 has a FIFO circuit, and therefore the test circuit using the scan data controller according to the third embodiment is compatible with high-speed testers.
[0074] When a high-speed tester is used, timing and test power problems are likely to occur during scan testing, leading to an increased risk of incorrect testing. As a solution, the scan chain set is operated by the first scan clock, scan_clk_div, which is synchronously divided from the second scan clock, SCAN_CLK, which is the input clock of the high-speed tester, and SCAN_CLK and scan_clk_div are connected to the scan data bus 902. This makes it possible to reduce power consumption during testing while using a high-speed tester, and to reduce the risk of incorrect testing.
[0075] A FIFO circuit is added between the decoder module 303 and the scan data controller of the scan data bus 902 that uses a high-speed tester. The decoder module 303 and the FIFO circuit operate on the second scan clock, SCAN_CLK. The scan data controller operates on the first scan clock, scan_clk_div. The number of FIFO circuits is equal to the number of scan chain sets.
[0076] 9, the decoder module 303 is electrically connected to the first scan data controller 304 via a first FIFO circuit 903. The decoder module 303 is also electrically connected to the second scan data controller 305 via a second FIFO circuit 904.
[0077] The first and second FIFO circuits buffer the test patterns and test responses, and also control data transfer between the decoder module 303 and the scan data controller during synchronous frequency division.
[0078] That is, the first FIFO circuit 903 inputs and outputs the first test pattern and the first test response to the first scan data controller based on a second scan clock that is faster than the clock speed of the first scan clock and is supplied from the tester, and the second FIFO circuit 904 inputs and outputs the second test pattern and the second test response to the second scan data controller based on a second scan clock that is faster than the clock speed of the first scan clock and is supplied from the tester.
[0079] The first FIFO circuit 903 will be described in detail with reference to Fig. 10. As shown in Fig. 10, the first FIFO circuit 903 has a first transfer data control module 1001, a first test response output FIFO module 1002, and a first test pattern input FIFO module 1003. The second FIFO circuit 904 has the same configuration as the first FIFO circuit 903.
[0080] 10(a), the first transfer data control module 1001 controls the clock enable of the selected first scan data controller 304. The first transfer data control module 1001 also controls a write_en signal, which is a write enable signal input to a first test response output FIFO module 1002. The first transfer data control module 1001 also controls a read_en signal, which is a read enable signal input to a first test pattern input FIFO module 1003.
[0081] The first transfer data control module 1001 receives sdctrl_en[x], the first scan clock which is scan_clk_div, and so_full as inputs, and also outputs sdctrl_en, write_en, and read_en.
[0082] The transfer data control signal sdctrl_en[x] indicates 1 while the tester is transferring data to the FIFOx circuit, and otherwise indicates 0. x varies depending on the FIFO number.
[0083] The transfer data control signal so_full is a signal that indicates whether the buffer of the first test response output FIFO module 1002 is full or not.
[0084] The transfer data control signal sdctrl_en is the clock enable control signal for each scan data controller. sdctrl_en = (sdctrl_en[x]|~so_full), where ~ indicates an inverted signal and | indicates or.
[0085] The write_en input to the first test response output FIFO module 1002 is sdctrl_en[x]|(scan_clk_div&~so_full). The test response output FIFO signal write_en is a control signal sent from the first scan data controller 304 when writing a test response.
[0086] The read_en input to the first test pattern input FIFO module 1003 is sdctrl_en[x]|(scan_clk_div&~so_full). The test pattern input FIFO signal read_en is a control signal when the test pattern is read into the first scan data controller 304.
[0087] 10(b), the first test response output FIFO module 1002 buffers the first test response transmitted from the selected first scan data controller 304. The first test response output FIFO module 1002 also transmits the buffered first test response to the decoder module 303.
[0088] The first test response output FIFO module 1002 buffers the first test response SODATA[b:0]. The first test response output FIFO module 1002 also receives read_en and write_en as inputs. The first test response output FIFO module 1002 also outputs so_full.
[0089] SODATA[b:0], which is a test response output FIFO signal, is an output signal from the first scan chain set 308 and includes information of the test response, where b is the number of bits and varies depending on the specifications.
[0090] The test response output FIFO signal, read_en, is the control signal when the test response is read into the decoder module 303. read_en is sdctrl_en[x].
[0091] 10(c), the first test pattern input FIFO module 1003 buffers the first test pattern transmitted from the decoder module 303. The first test pattern input FIFO module 1003 transmits the buffered first test pattern to the first scan data controller 304.
[0092] The first test pattern input FIFO module 1003 controls the test pattern SIDATA[b:0]. The first test pattern input FIFO module 1003 receives write_en and read_en as inputs.
[0093] The test pattern input FIFO signal SIDATA[b:0] is an input signal from the tester and includes information about the test pattern.
[0094] The test pattern input FIFO signal write_en is a control signal when writing a test pattern from the decoder module 303. write_en is sdctrl_en[x].
[0095] 12, a test method for a semiconductor device 901 including a first FIFO circuit 903 and a second FIFO circuit 904 will be described. As shown in FIG. 12, first, the first scan data controller 304 is selected (step S1201). Next, test data is input / output to / from the first FIFO circuit 903 (step S1202). Next, test data is input / output to / from the first scan chain set 308 (step S1203).
[0096] Simultaneously with step S1203, the second scan data controller 305 is selected (step S1204). Next, test data is input / output to / from the second FIFO circuit 904 (step S1205). Next, it is determined whether the test has ended (step S1206). If the test has not ended, the process returns to step S1201.
[0097] Simultaneously with step S1206, test data is input to and output from the second scan chain set 311 (step S1207). When the tests on the first scan chain set 308 and the second scan chain set 311 are completed, the process ends.
[0098] In this way, the test of the second scan chain set 311 starts before the test of the first scan chain set 308 is completed. Therefore, the synchronous frequency division control can speed up the transmission and reception of test data. In addition, the circuit overhead is small, which contributes to reducing test costs.
[0099] Although the semiconductor device 901 of the third embodiment does not have a decompression circuit or a compression circuit, it may have a decompression circuit and a compression circuit as in the embodiments. Also, although the third embodiment shows two FIFO circuits, it may have three or more FIFO circuits depending on the number of scan chain sets, which are circuits to be tested.
[0100] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]
[0101] 101 semiconductor device, 102 decompression circuit, 103 compression circuit, 104 scan chain, 301 semiconductor device, 302 scan data bus, 303 decoder module, 304 first scan data controller, 305 second scan data controller, 306 first decompression circuit, 307 first compression circuit, 308 first scan chain set, 309 second decompression circuit, 310 second compression circuit, 311 second scan chain set, 312 first input terminal, 313 first output terminal, 314 first scan chain, 315 second input terminal, 316 second output terminal, 317 second scan chain, 401 transfer access control module, 402 transfer data control module, 501 first clock control circuit, 601 second clock control circuit, 701 semiconductor device, 901 semiconductor device, 902 scan data bus, 903 first FIFO circuit, 904 second FIFO circuit, 1001 First transfer data control module, 1002 first test response output FIFO module, 1003 first test pattern input FIFO module
Claims
1. (a) providing a wafer; (b) forming a plurality of semiconductor devices on the wafer, each semiconductor device having a plurality of circuits; (c) testing a portion of the plurality of circuits formed on each of the plurality of semiconductor devices; (d) dividing the wafer to obtain the plurality of individual semiconductor devices, The plurality of circuits of the semiconductor device include: a first circuit having a first scan chain set including a plurality of first scan chains configured by electrically connecting a plurality of first flip-flop circuits in series; a second circuit having a second scan chain set including a plurality of second scan chains configured by electrically connecting in series a plurality of second flip-flop circuits different from the plurality of first flip-flop circuits; a first scan data controller electrically connected to a first input terminal and a first output terminal of each of the plurality of first scan chains; a second scan data controller electrically connected to the second input terminal and the second output terminal of each of the plurality of second scan chains; a decoder module electrically connected to the first and second scan data controllers; The step (c) (c1) when an identifier input from an externally connected tester is a first identifier indicating that the first scan data controller is to be selected, the decoder module selects the first scan data controller; (c2) the decoder module transmitting a first test pattern to the first input terminals of each of the plurality of first scan chains via the first scan data controller; (c3) receiving, by the decoder module, a first test response corresponding to the first test pattern from the first output terminal of each of the plurality of first scan chains via the first scan data controller; and testing the first circuit by having the first circuit test the first test result.
2. 2. The method for manufacturing a semiconductor device according to claim 1, The step (c) (c4) when the identifier input from the tester is a second identifier indicating that the second scan data controller is to be selected, the decoder module selects the second scan data controller; (c5) the decoder module transmitting a second test pattern to the second input terminals of each of the plurality of second scan chains via the second scan data controller; (c6) receiving, by the decoder module, second test responses corresponding to the second test pattern from the second output terminals of each of the plurality of second scan chains via the second scan data controller; and testing the second circuit by further comprising:
3. 3. The method for manufacturing a semiconductor device according to claim 2, The method for manufacturing a semiconductor device, wherein the step (c4) is started after the step (c3) is completed.
4. 4. The method for manufacturing a semiconductor device according to claim 3, The plurality of circuits include: a first decompression circuit electrically connected to each first input terminal of the plurality of first scan chains of the first scan chain set, the first decompression circuit converting the first test pattern from a data-compressed state to a data-uncompressed state; a first compression circuit electrically connected to each first output terminal of the plurality of first scan chains in the first scan chain set, the first compression circuit converting the first test response from an uncompressed state to a data-compressed state; a second decompression circuit electrically connected to each second input terminal of the plurality of second scan chains in the second scan chain set, the second decompression circuit converting the second test pattern from a data-compressed state to a data-uncompressed state; a second compression circuit electrically connected to each second output terminal of the plurality of second scan chains in the second scan chain set, the second compression circuit converting the second test response from an uncompressed state to a data-compressed state; The method for manufacturing a semiconductor device further comprises:
5. 3. The method for manufacturing a semiconductor device according to claim 2, the first scan data controller includes a first clock control circuit that controls a first scan clock supplied to the first scan chain set; The second scan data controller includes a second clock control circuit that controls the first scan clock supplied to the second scan chain set.
6. 6. The method for manufacturing a semiconductor device according to claim 5, The decoder module is electrically connected to the first scan data controller via a first FIFO circuit and to the second scan data controller via a second FIFO circuit.
7. 7. The method for manufacturing a semiconductor device according to claim 6, a first FIFO circuit configured to input and output the first and second test patterns and the first and second test responses from the first and second scan data controllers based on a second scan clock supplied from the tester, the first and second FIFO circuits each having a speed faster than a clock speed of the first scan clock.
8. 8. The method for manufacturing a semiconductor device according to claim 7, The method for manufacturing a semiconductor device, wherein the step (c4) is started before the step (c3) is completed.
9. 3. The method for manufacturing a semiconductor device according to claim 2, The decoder module: a transfer access control module that decodes identifier information including the first identifier or the second identifier from the tester, selects a first scan data controller or a second scan data controller, controls a data transfer selector of the selected first scan data controller or the selected second scan data controller, and controls a clock of the selected first scan data controller or the selected second scan data controller; a transfer data control module that receives a control signal for data transfer and sets a data input selector and a data output selector to the selected first scan data controller or the selected second scan data controller.
10. 7. The method for manufacturing a semiconductor device according to claim 6, The first FIFO circuit a first transfer data control module that controls a clock enable of the scan data controller, controls a write enable signal of a first test response output FIFO module, and controls a read enable signal of a first test pattern input FIFO module; a first test response output FIFO module that buffers the first test response sent from the scan data controller and sends the buffered first test response to the decoder module; a first test pattern input FIFO module that buffers the first test pattern transmitted from the decoder module and transmits the buffered first test pattern to the scan data controller.