Microprocessor and debugging method for microprocessor

Abstract

To effectively utilize a built-in SRAM of a CPU core.SOLUTION: A microprocessor 1 includes a built-in memory 17 and a DDR (double data rate) - SDRAM2 in which an instruction code is stored, and a processing part 10 for processing the instruction code. The processing unit 10 includes a tracing unit 16 for debugging the instruction code. After the operating system is started, the processing unit 10 uses the tracing unit 16 to store the trace information 161 of the instruction code in the internal memory 17.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a microprocessor and a method for debugging a microprocessor. [Background technology]

[0002] RISC-V is an instruction set architecture developed at the University of California, Berkeley, and is provided as open source. RISC-V is designed based on the principles of reduced instruction set computing. It is possible to design an SoC (System on Chip) that includes a CPU (Central Processing Unit) core based on this RISC-V.

[0003] Patent document 1 describes an invention in which, when the trace control unit 141 receives the value of the program counter, it sequentially writes the value of the program counter to unused registers of the central processing unit that the core control unit 140 is not using to execute instruction code. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-156594 Summary of the Invention [Problem to be solved by the invention]

[0005] The built-in static random access memory (SRAM) of a RISC-V-based CPU core is used exclusively for the operation of the bootstrap loader before the operating system starts, and is therefore not used after the operating system has started to start.In addition, there is a demand to reduce the cost of memory dedicated to the tracing function, rather than providing memory dedicated to the tracing function. Therefore, an object of the present invention is to effectively utilize the built-in SRAM of a CPU core. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the microprocessor of the present invention comprises an internal memory and an external memory in which instruction codes are stored, and a processing unit that processes the instruction codes, and the processing unit comprises a trace unit for debugging the instruction codes, and after the operating system is started, the trace unit is used to store trace information of the instruction codes in the internal memory.

[0007] The microprocessor debugging method of the present invention is characterized by comprising the steps of processing instruction codes stored in an internal memory or an external memory, and starting an operating system using a processing unit equipped with a trace unit for debugging the instruction codes, and after starting the operating system, storing trace information of the instruction codes in the internal memory using the trace unit. Other means will be described in the detailed description of the invention. [Effects of the Invention]

[0008] According to the present invention, since instruction codes are stored as trace information in the internal SRAM after the operating system has started up, the internal SRAM of the CPU core can be effectively utilized, and it is also possible to eliminate the need for a memory dedicated to the trace function. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating the configuration and operation of a microprocessor according to an embodiment of the present invention; [Figure 2] FIG. 2 illustrates the operation of the system before the operating system is started. [Figure 3] FIG. 1 illustrates the operation of the system after the operating system boot has begun. [Figure 4] FIG. 1 is a diagram illustrating the configuration of a computer. [Figure 5]FIG. 2 is a diagram showing the operating modes and levels of each part of a computer. [Figure 6A] 10 is a flowchart showing a tracing operation. [Figure 6B] 10 is a flowchart showing a tracing operation. [Figure 7] FIG. 10 is a diagram showing an example of trace information. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing the configuration and operation of a microprocessor 1 according to this embodiment. The microprocessor 1 includes a processing unit 10, a tracing unit 16, and an internal SRAM 17.

[0011] The processing unit 10 sequentially executes step 11 of fetching an instruction set, step 12 of decoding the instruction set, step 13 of executing the decoded instruction set, step 14 of executing memory access based on the instruction set, and step 15 of writing the contents of the register back to memory.

[0012] The trace unit 16 acquires trace information 161 in step 13, where the processing unit 10 executes the instruction set decoded. The trace information 161 is a combination of the number of clock cycles of the instruction set and the execution address of the instruction set, and will be described in detail later with reference to FIG. 7. The trace unit 16 stores the trace information 161 in the built-in SRAM 17.

[0013] Conventionally, the built-in SRAM 17 has not been used after the operating system has started booting up. In the tracing unit 16 of this embodiment, the built-in SRAM 17 is used as a storage location for the trace information 161 after the operating system has started booting up.

[0014] FIG. 2 is a diagram showing the operation of the system before the operating system 31 is started. The microprocessor 1 includes a CPU core 100, a ROM (Read Only Memory) 18, an internal SRAM 17, a DRAM (Dynamic RAM) controller 191, and a mass storage controller 192. The CPU core 100 includes the processing unit 10 and the tracing unit 16 shown in FIG.

[0015] The DRAM controller 191 controls a DDR-SDRAM (Double Data Rate Synchronous Dynamic RAM) 2 to read and write data from and to the DDR-SDRAM 2. The mass storage controller 192 controls a mass storage device 3 to read and write data from and to the mass storage device 3. The mass storage device 3 stores an operating system 31.

[0016] Before starting up the operating system 31, the CPU core 100 and the bootstrap loader stored in the ROM 18 are read. The CPU core 100 and the built-in SRAM 17 are used to execute the processing of the bootstrap loader.

[0017] FIG. 3 is a diagram showing the operation of a conventional system after the start of booting of the operating system 31. After starting the boot of the operating system 31, the CPU core 100 executes the boot of the operating system using the external DDR-SDRAM 2. At this time, the CPU core 100 does not use the built-in SRAM 17.

[0018] Here, after the operating system 31 has started booting, the CPU core 100 stores trace information for debugging in the built-in SRAM 17. This makes it possible to save trace information for debugging without implementing a memory dedicated to the trace function. By using the built-in SRAM 17, which is no longer used after the operating system has started booting, as a log storage location, valuable logic can be used effectively.

[0019] However, if anyone were to be able to obtain the information in the built-in SRAM 17, there would be a risk in terms of information security. Therefore, in this embodiment, the information is configured to be readable only when the CPU core 100 is in M ​​mode (machine mode).

[0020] FIG. 4 is a diagram showing the configuration of the computer 4. The computer 4 includes a processing unit 10, a tracing unit 16, an internal SRAM 17, an SD card controller 41, and an Ethernet (registered trademark) controller 42.

[0021] By setting hardware access rights for each part of the computer 4, the contents of the built-in SRAM 17 can be made accessible only to specific users, thereby addressing security risks.

[0022] FIG. 5 is a diagram showing the operation modes and levels of each part of the computer 4. Machine mode is the third level. A slave part set in machine mode can only be accessed by a master part set in machine mode. If the level of the master part is equal to or higher than the level of the slave part, the slave part can be accessed.

[0023] Supervisor mode is the first level. A slave part set to supervisor mode can be accessed by a master part set to machine mode and a master part set to supervisor mode. Conversely, a master part set to supervisor mode cannot access a slave part set to machine mode.

[0024] User mode is level 0. A slave part set to user mode can be accessed by a master part set to machine mode, a master part set to supervisor mode, and a master part set to user mode. Conversely, a master part set to user mode cannot access a slave part set to machine mode or supervisor mode.

[0025] In this embodiment, a machine mode access level is set for the built-in SRAM 17 and the trace unit 16. A user mode access level is set for the SD card controller 41 and the Ethernet controller 42. An access level of either the machine mode or the user mode is set for the processing unit 10 depending on the situation. This allows only specific users to access the contents of the built-in SRAM 17, thereby addressing security risks.

[0026] 6A and 6B are flowcharts illustrating the trace operation. First, each unit of the microprocessor 1 acquires setting information for hardware access rights (step S10). Next, the processing unit 10 reads and executes a bootstrap loader to start up the operating system (step S11). The processing unit 10 determines whether or not to enable the tracing unit 16 (step S12).

[0027] If the tracing unit 16 is not enabled (No), the processing in Fig. 6A ends. If the tracing unit 16 is enabled (Yes), the processing proceeds to step S13, where the processing unit 10 determines whether or not the execution of the calculation has started (step S13).

[0028] In step S13, if the processing unit 10 has not started the execution of the calculation (No), the process returns to step S12. If the processing unit 10 has started the execution of the calculation (Yes), the process proceeds to step S14. The processing unit 10 acquires the instruction from the program storage memory and executes the instruction (step S14). The tracing unit 16 acquires address information from the program register (step S15) and acquires the number of cycles of the free-running clock (step S16).

[0029] In step S17, the tracing unit 16 determines whether or not it is possible to access the built-in SRAM 17. If it is not possible to access the built-in SRAM 17 (No), the processing of FIG. 6B ends. If it is possible to access the built-in SRAM 17 (Yes), the processing proceeds to step S18.

[0030] In step S18, the trace unit 16 determines whether wraparound processing is enabled. If wraparound processing is enabled (Yes), the process proceeds to step S19, where the trace information 161 is stored in the built-in SRAM 17 in a wraparound manner, and then the process proceeds to step S22. If wraparound processing is disabled (No), the process proceeds to step S20, where the trace information is stored in the built-in SRAM 17, and then the process proceeds to step S21.

[0031] In step S21, the tracing unit 16 determines whether the storage area of ​​the built-in SRAM 17 is full. If the storage area of ​​the built-in SRAM 17 is full (Yes), the processing of FIG. 6B ends. If the storage area of ​​the built-in SRAM 17 is not full (No), the processing proceeds to step S22.

[0032] In step S22, the processing unit 10 determines whether the program has ended. If the program has ended (Yes), the processing in Fig. 6B ends. If the program has not ended (No), the processing returns to step S12.

[0033] FIG. 7 is a diagram showing an example of the trace information 161. As shown in FIG. The trace information 161 is composed of an array of combinations of 32-bit data indicating the number of clock cycles of an instruction set and 32-bit data indicating the execution address of the instruction set. Each line of the trace information 161 is composed of the number of clock cycles of the instruction set in the upper 8 digits and the execution address of the instruction set in the lower 8 digits. This allows the user to trace whether the intended program code is being executed.

[0034] The configuration and effects of the present invention will be described below.

[0035] [1] An internal memory (17) and an external memory (DDR-SDRAM2) in which instruction codes are stored; a processing unit (10) that processes the instruction code, the processing unit (10) includes a trace unit (16) for debugging the instruction code, and stores trace information of the instruction code in the built-in memory (17) using the trace unit (16) after the operating system is started; A microprocessor characterized by:

[0036] This allows the instruction code to be stored as trace information in the internal SRAM after the operating system has started up, making effective use of the CPU core's internal SRAM.Furthermore, it also eliminates the need for a dedicated memory for the trace function.

[0037] [2] The built-in memory is used as a working area when the operating system is started. 2. The microprocessor of claim 1.

[0038] This clarifies the original purpose of the built-in memory.

[0039] [3] The built-in memory (17) stores the trace information (161), The trace information (161) has a higher access level set than other information. 2. The microprocessor of claim 1.

[0040] This allows the contents of the built-in SRAM to be accessed only by specific users, addressing security risks.

[0041] [4] The trace information (161) is a combination of the number of clock cycles required to execute the instruction code and the address where the instruction code is stored. 2. The microprocessor of claim 1.

[0042] This allows the user to trace a running program to aid in debugging.

[0043] [5] A step in which a processing unit (10) processes instruction codes stored in an internal memory (17) or an external memory (DDR-SDRAM2) and has a trace unit (16) for debugging the instruction codes, and starts up an operating system; storing trace information (161) of the instruction code in the built-in memory (17) using the trace unit (16) after the operating system is started; 1. A method for debugging a microprocessor, comprising:

[0044] This allows the instruction code to be stored as trace information in the internal SRAM after the operating system has started, making effective use of the CPU core's internal SRAM.Furthermore, it also eliminates the need for a dedicated memory for the trace function.

[0045] <<Variation>> The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0046] The above-described configurations, functions, processing units, processing means, etc. may be realized in part or in whole by hardware such as an integrated circuit. The above-described configurations, functions, etc. may be realized by software by a processor interpreting and executing a program that realizes each function. Information such as the programs, tables, and files that realize each function can be stored in a storage device such as a memory, a hard disk, or an SSD (Solid State Drive), or on a storage medium such as a flash memory card or a DVD (Digital Versatile Disk).

[0047] In each embodiment, the control lines and information lines shown are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are interconnected. As modified examples of the present invention, for example, the following (a) to (g) are available.

[0048] (a) To expand the trace storage function, the access level of the built-in SRAM may be divided by address. (b) To expand the trace storage function, the access level of the built-in SRAM may be divided into Read and Write. (c) The access level may be set to master only. (d) Trace information may be passed from a monitor operating in master mode to a user level operating in slave mode. (e) A mechanism may be provided that allows trace information to be output to the outside when an unexpected reset occurs. (f) A mechanism for switching the trace function on and off may be provided. (g) The trace information may be encrypted and stored in the internal SRAM. In this case, it is necessary to manage the key for decrypting the trace information. [Explanation of symbols]

[0049] 1 microprocessor 100 CPU cores 10 Processing section 16 Trace section 161 Trace Information 17 built-in SRAM 18 ROM 191 DRAM Controller 192 Mass Storage Controller 2 DDR-SDRAM 3 Mass storage 31 Operating Systems 4. Computer 41 SD card controller 42 Ethernet Controller

Claims

1. an internal memory and an external memory in which instruction codes are stored; a processing unit that processes the instruction code, the processing unit includes a trace unit for debugging the instruction code, and stores trace information of the instruction code in the built-in memory using the trace unit after the operating system is started; A microprocessor characterized by:

2. The built-in memory is used as a working area when the operating system is started.

2. The microprocessor according to claim 1.

3. The internal memory stores the trace information, The trace information has a higher access level than other information.

2. The microprocessor according to claim 1.

4. the trace information is a combination of the number of clock cycles required to execute the instruction code and an address where the instruction code is stored; 2. The microprocessor according to claim 1.

5. A step of processing instruction codes stored in an internal memory or an external memory, and having a processing unit including a trace unit for debugging the instruction codes, causing an operating system to be started; storing trace information of the instruction code in the internal memory using the trace unit after the operating system is started; 1. A method for debugging a microprocessor, comprising:

Images