Row decoder circuit

Abstract

To provide a row decoder circuit for improving the yield of a product and the convenience of use by providing usability to a partially damaged memory device.SOLUTION: The row decoder circuit 100 includes a pre-decoder, a plurality of decoders, and a mapping control circuit. The predecoder receives row address information and decodes the row address information to provide a set of row select signals. The plurality of decoders sequentially correspond to a plurality of row address ranges. The mapping control circuit is coupled to the pre-decoder and the decoder, and is configured to obtain a selected row address range according to the row selection signal set, and cause the decoder corresponding to the same row address range as the selected row address range to output a word line signal. The mapping control circuit also reorders the row address range corresponding to the decoder based on the verify data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a decoder circuit, and more particularly to a row decoder circuit. [Background technology]

[0002] As memory manufacturing process technology advances, memory density and die area increase, leading to an increased damage rate for each die. It is nearly impossible to ensure that all memory cells or memory blocks within a memory product are 100% undamaged. Therefore, conventional technologies primarily use row / column redundancy techniques and error correction code (ECC) techniques to repair damaged memory cells. However, these techniques have limitations in their repair capabilities, and memory devices (chips) with relatively large amounts of damage cannot be completely repaired. Furthermore, because the location of the damage is random, partially damaged memory devices cannot be shipped as normal products, resulting in reduced product yields. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a row decoder circuit that can provide usability for partially damaged memory devices. [Means for solving the problem]

[0004] The row decoder circuit of the present invention includes a pre-decoder, a plurality of decoders, and a mapping control circuit, and is suitable for a memory device. The pre-decoder is configured to receive row address information and decode the row address information to provide a set of row select signals. The plurality of decoders sequentially correspond to a plurality of row address ranges. The mapping control circuit is coupled to the pre-decoder and the decoders and configured to obtain a selected row address range based on the set of row select signals and cause a decoder having the same selected row address range as the corresponding row address range to output a word line signal. The mapping control circuit reorders the row address ranges corresponding to the decoders based on verification data. [Effects of the Invention]

[0005] Based on the above, by rearranging the row address ranges corresponding to the decoder, the row decoder circuit of the present invention can skip the damaged bad memory blocks during mapping, and the memory device can be used normally, thus making the partially damaged memory device usable, and improving the product yield and convenience of use.

[0006] In order to make the above-mentioned features and advantages of the present invention clearer and easier to understand, the following embodiments will be shown and described in detail in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram of a row decoder circuit according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating the operation of a row decoder circuit according to an embodiment. [Figure 3A] FIG. 2 is a circuit schematic diagram of a mapping control circuit according to one embodiment. [Figure 3B] FIG. 2 is a circuit schematic diagram of a mapping control circuit according to one embodiment. [Figure 3C] FIG. 2 is a circuit schematic diagram of a mapping control circuit according to one embodiment. [Figure 4A]FIG. 10 is an operational schematic diagram of a mapping control circuit according to an embodiment. [Figure 4B] FIG. 10 is an operational schematic diagram of a mapping control circuit according to an embodiment. [Figure 4C] FIG. 10 is an operational schematic diagram of a mapping control circuit according to an embodiment. [Figure 5A] FIG. 10 is a block diagram of a mapping control circuit according to another embodiment. [Figure 5B] FIG. 10 is a block diagram of a mapping control circuit according to another embodiment. [Figure 5C] FIG. 10 is a block diagram of a mapping control circuit according to another embodiment. [Figure 6A] FIG. 10 is a schematic diagram illustrating the operation of a mapping control circuit according to another embodiment. [Figure 6B] FIG. 10 is a schematic diagram illustrating the operation of a mapping control circuit according to another embodiment. [Figure 6C] FIG. 10 is a schematic diagram illustrating the operation of a mapping control circuit according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Referring to FIG. 1 , a row decoder circuit 100 according to this embodiment is suitable for use in standard memory devices such as hybrid memory cubes (HMC), high bandwidth memories (HBM), double data rate (DDR), or low power double data rate (LPDDR). The row decoder circuit 100 includes a pre-decoder 110, decoders 120_0 to 120_11, and a mapping control circuit 130. The pre-decoder 110 receives row address information RA of memory cells to be accessed. The row address information RA may be, for example, 13 bits. The pre-decoder 110 decodes the row address information RA to provide a set of row selection signals SELG. A first portion P1 of the set of row selection signals SELG corresponds to a row address of a most significant bit portion including a first row selection signal RSGSEL0[3:0] and a second row selection signal RSGSEL1[2:0]. The second part P2 of the row selection signal set SELG corresponds to the row address of the lower bits, including the row selection signals RMWSEL0[7:0], RMWSEL1[3:0], RMWSEL2[2:0], and RFXSEL[7:0]. The pre-decoder 110 transmits the first part P1 of the row selection signal set SELG to the mapping control circuit 130 and transmits the second part P2 of the row selection signal set SELG to each of the decoders 120_0 to 120_11.

[0009] Decoders 120_0 to 120_11 correspond sequentially to row address ranges RSG0 to RSG11. The row address range RSG0 to RSG11 represents the initial default row address range of the 12 memory blocks opened by decoders 120_0 to 120_11 in the memory device. For example, assuming that the total range of row addresses provided by the above 12 memory blocks is 0 to 8191, the row address range RSG0 to RSG11 is as shown in Table 1 below.

[0010] [Table 1]

[0011] If none of the 12 memory blocks are damaged (all are usable), decoders 120_0 to 120_11 can output word line signals SWL0 to SWL11 to the 12 memory blocks, respectively, to access memory cells whose row addresses are within the row address range RSG0 to RSG11.

[0012] The mapping control circuit 130 is coupled to the pre-decoder 110 and the decoders 120_0 to 120_11. The mapping control circuit 130 acquires a selected row address range based on the row selection signal set SELG, and causes a decoder among the decoders 120_0 to 120_11 whose selected row address range is the same as the corresponding row address range to output a word line signal at an enable level (e.g., a high logic level).

[0013] Specifically, mapping control circuit 130 analyzes and decodes the signals of the first portion P1 of row select signal set SELG to obtain the selected row address range in which the memory cells to be accessed are located. At this time, a decoder among decoders 120_0 to 120_11 whose selected row address range is the same as the corresponding row address range can output a corresponding word line signal based on the second portion P2 of row select signal set SELG. More specifically, when the selected row address range is equal to row address range RSG0, mapping control circuit 130 causes decoder 120_0 to output word line signal SWL0 at an enable level based on the second portion P2 of row select signal set SELG. When the selected row address range is equal to row address range RSG1, mapping control circuit 130 causes decoder 120_1 to output word line signal SWL1 at an enable level based on the second portion P2 of row select signal set SELG. The rest of the description follows.

[0014] In this embodiment, mapping control circuit 130 can also receive verification data DV. The verification data DV is, for example, data acquired during a chip probing (CP) step. Mapping control circuit 130 can determine the location of damaged memory cells or memory blocks based on the verification data DV.

[0015] Furthermore, the mapping control circuit 130 can generate verification signals SDV0-SDV11 based on multiple bit values ​​constituting the verification data DV. When a verification signal is at a high logic level (logic value 1), it indicates that the corresponding memory block is damaged because the defective memory cells cannot be completely repaired. When a verification signal is at a low logic level (logic value 0), it indicates that the corresponding memory block can be completely repaired and does not have defective memory cells. More specifically, when the verification signal SDV0 is at a high logic level (logic value 1), it indicates that the memory block opened by the decoder 120_0 is damaged, and when the verification signal SDV1 is at a high logic level (logic value 1), it indicates that the memory block opened by the decoder 120_1 is damaged, and the rest can be inferred from this.

[0016] If a damaged or defective memory block exists among the 12 memory blocks opened by the decoders 120_0 to 120_11, the mapping control circuit 130 can rearrange the row address ranges corresponding to the decoders 120_0 to 120_11 based on the verification data DV. For example, as shown in FIG. 2, if the memory block opened by the decoder 120_1 is a damaged or defective memory block, the verification signal SDV1 becomes a high logic level (logic value 1). Therefore, the mapping control circuit 130 can disable the decoder 120_1 from being used as a defective memory block decoder based on the verification signal SDV1 at a high logic level.

[0017] At this time, in order to enable the memory device to be used normally, the mapping control circuit 130, based on the verification signals SDV0 to SDV11, moves the row address range corresponding to the decoders 120_2 to 120_11 arranged after the decoder 120_1, which is determined to be the defective memory block decoder, forward from the row address range RSG2 to RSG11 to the row address range RSG1 to RSG10, so that the decoder 120_2 replaces the decoder 120_1 and corresponds to the row address range RSG1, and the memory block opened by the decoder 120_1 is no longer mapped.

[0018] Similarly, each of the decoders 120_3 to 120_11 is replaced with the previous decoder, and corresponds to the row address range that originally corresponded to the previous decoder.

[0019] In this way, the row decoder circuit 100 of this embodiment can skip damaged defective memory blocks when performing mapping, thereby allowing partially damaged memory devices to continue to be usable.

[0020] In this embodiment, the description is given using 12 decoders 120_0 to 120_11 that can open 12 memory blocks, but the present invention is not limited thereto. Those skilled in the art can infer based on the teachings of the present invention that the number of memory blocks and decoders can be increased or decreased according to actual needs.

[0021] The following describes an embodiment of the mapping control circuit. The mapping control circuit 300 in this embodiment is applied to a situation where a memory block has damaged memory cells and the row address range corresponding to the decoders 400_0 to 400_11 needs to be rearranged. The mapping control circuit 300 includes a latch circuit 310, a first logic circuit 320, a second logic circuit 330, a multiplex circuit 340, and a third logic circuit 350. For clarity, the internal structures of the latch circuit 310, the first logic circuit 320, the second logic circuit 330, the multiplex circuit 340, and the third logic circuit 350 in the mapping control circuit 300 are shown in FIGS. 3A, 3B, and 3C, respectively.

[0022] 3A, 3B, and 3C, a latch circuit 310 can store received verification data DV. When the system is turned on, the latch circuit 310 can obtain the verification data DV from, for example, another one-time programmable (OTP) memory. The latch circuit 310 includes latches L0 to L11. The latches L0 to L11 can sequentially store multiple bit values ​​that make up the verification data DV and output them as verification signals SDV0 to SDV11, respectively.

[0023] The first logic circuit 320 is coupled to the latch circuit 310. The first logic circuit 320 receives the verification signals SDV0 to SDV10 and the low logic level signal VSS, and can perform multi-level operations using the verification signals SDV0 to SDV10 and the low logic level signal VSS to generate the control signals ST0 to ST10.

[0024] 3B, the first logic circuit 320 includes OR gates 322_0 to 322_10. The OR gates 322_0 to 322_10 are connected in series. First input terminals of the OR gates 322_0 to 322_10 receive the verification signals SDV0 to SDV10, respectively. Output terminals of the OR gates 322_0 to 322_10 output the control signals ST0 to ST10, respectively. A second input terminal of the OR gate of the first level (OR gate 322_0) receives the low logic level signal VSS. Second input terminals of the OR gates other than the first level (OR gates 322_1 to 322_10) receive the control signals output from the output terminals of the OR gates of the next higher level.

[0025] The second logic circuit 330 receives the first part P1 of the row selection signal set SELG, and performs an AND operation on the first row selection signal RSGSEL0[3:0] in the first part P1 and the second row selection signal RSGSEL1[2:0] in the first part P1 to generate operation signals RS0 to RS11.

[0026] The second logic circuit 330 includes AND gates 332_0 to 332_11. A first input terminal of each of the AND gates 332_0 to 332_11 receives a corresponding first row selection signal in the first row selection signal RSGSEL0[3:0]. A second input terminal of each of the AND gates 332_0 to 332_11 receives a corresponding second row selection signal in the second row selection signal RSGSEL1[2:0]. Output terminals of the AND gates 332_0 to 332_11 output operation signals RS0 to RS11, respectively.

[0027] 3C, the multiplex circuit 340 is coupled to the first logic circuit 320 and the second logic circuit 330. The multiplex circuit 340 receives the control signals ST0-ST10 and the operation signals RS0-RS11, and selects multiple of the operation signals RS0-RS11 as the decoding signals SCD0-SCD10 based on the control signals ST0-ST10.

[0028] Specifically, the multiplex circuit 340 includes multiplexers 342_0 to 342_10. A first input terminal and a second input terminal of each of the multiplexers 342_0 to 342_10 receive two corresponding operation signals among the operation signals RS0 to RS11. For example, a first input terminal of the multiplexer 342_0 receives the operation signal RS0, and a second input terminal of the multiplexer 342_0 receives the operation signal RS1. A first input terminal of the multiplexer 342_1 receives the operation signal RS1, and a second input terminal of the multiplexer 342_1 receives the operation signal RS2, and so on.

[0029] The control terminals of the multiplexers 342_0 to 342_10 receive control signals ST0 to ST10, respectively, and the output terminals of the multiplexers 342_0 to 342_10 output decoded signals SCD0 to SCD10, respectively. Based on the received control signal, each of the multiplexers 342_0 to 342_10 selects either the signal received at its first input terminal (upper input terminal) or the signal received at its second input terminal (lower input terminal) as a corresponding decoded signal, and outputs the selected signal at its output terminal. Taking the multiplexer 342_1 as an example, when the multiplexer 342_1 receives a control signal ST1 of a high logic level, the multiplexer 342_1 selects and outputs the operation signal RS1 received at its first input terminal (upper input terminal) as the decoded signal SCD1. When the multiplexer 342_1 receives a control signal ST1 of a low logic level, the multiplexer 342_1 selects and outputs the operation signal RS2 received at its second input terminal (lower input terminal) as the decoded signal SCD1.

[0030] The third logic circuit 350 is coupled to the latch circuit 310, the second logic circuit 330, and the multiplex circuit 340. The third logic circuit 350 receives the verification signals SDV0-SDV11, the calculation signal RS0 of the corresponding lowest address among the calculation signals RS0-RS11, and the decoded signals SCD0-SCD10, and after inverting the verification signals SDV0-SDV11, further performs an AND operation with the calculation signal RS0 and the decoded signals SCD0-SCD10, respectively, and outputs the generated enable signals SE0-SE11 to the decoders 400_0-400_11, respectively.

[0031] In detail, the third logic circuit 350 includes inverters 352_0 to 352_11 and AND gates 354_0 to 354_11. Input terminals of the inverters 352_0 to 352_11 receive the verification signals SDV0 to SDV11, respectively.

[0032] A first input terminal of the AND gate 354_0 receives the operation signal RS0. First input terminals of the AND gates 354_1 to 354_11 receive the decoded signals SCD0 to SCD10, respectively. Second input terminals of the AND gates 354_0 to 354_11 are coupled to output terminals of the inverters 352_0 to 352_11, respectively. Output terminals of the AND gates 354_0 to 354_11 output enable signals SE0 to SE11, respectively.

[0033] 4A, 4B, and 4C, if there is a damaged defective memory cell in the memory block opened by the decoder 400_1, the inverter 352_1 in the third logic circuit 350 receives the verify signal SDV1 of a high logic level (logic value 1) from the latch L1 in the latch circuit 310. In this way, the AND gate 354_1 can only output the enable signal SE1 of a low logic level (logic value 0) to the decoder 400_1, thereby disabling the decoder 400_1 from being used as a defective memory block decoder.

[0034] At this time, the OR gate 322_1 of the first logic circuit 320 also receives the verification signal SDV1 at a high logic level. Since the OR gates 322_0 to 322_10 are connected in series, the control signals ST1 to ST10 output by the OR gates 322_1 to 322_10 are all adjusted to a high logic level. In this case, the multiplexers 342_1 to 342_10 in the multiplex circuit 340 are changed so as to select and output the operation signals RS1 to RS10 received at their first input terminals (upper input terminals) as the decoded signals SCD1 to SCD10.

[0035] As a result, the row address ranges corresponding to the decoders 400_2 to 400_11 arranged behind the decoder 400_1 determined to be the defective memory block decoder are moved forward from the row address range RSG2 to RSG11 to the row address range RSG1 to RSG10. In this way, the decoder 400_2 replaces the decoder 400_1 and corresponds to the row address range RSG1, so that the memory block opened by the decoder 400_1 is no longer mapped.

[0036] The following describes an implementation of the mapping control circuit using another embodiment. In this embodiment, the mapping control circuit 500 is applied to a situation where one or two memory blocks are damaged and the row address ranges corresponding to the decoders 600_0 to 600_11 are rearranged. The mapping control circuit 500 includes a latch circuit 510, a first logic circuit 520, a second logic circuit 530, a multiplexing circuit 540, and a third logic circuit 550. For clarity, the internal structures of the latch circuit 510, the first logic circuit 520, the second logic circuit 530, the multiplexing circuit 540, and the third logic circuit 550 in the mapping control circuit 500 are shown in Figures 5A, 5B, and 5C, respectively.

[0037] 5A, 5B, and 5C, a latch circuit 510 can store received verification data DV. Latches L0 to L11 included in the latch circuit 510 can sequentially store multiple bit values ​​constituting the verification data DV and output them as verification signals SDV0 to SDV11, respectively.

[0038] The first logic circuit 520 is coupled to the latch circuit 510. The first logic circuit 520 receives the verification signals SDV0-SDV10 and the low logic level signal VSS, and can perform a multi-level operation using the verification signals SDV0-SDV10 and the low logic level signal VSS to generate the control signals ST0-ST10. Unlike the previous embodiment, in this embodiment, each of the control signals ST0-ST10 is composed of a two-bit signal. For example, the control signal ST0 is composed of a bit signal ST0. <0> and bit signal ST0 <1> The control signal ST1 is composed of bit signal ST1 <0> and bit signal ST1 <1> The rest of the text can be inferred from this.

[0039] 5B, the first logic circuit 520 includes OR gates 522_0 to 522_10, AND gates 524_0 to 524_10, and OR gates 526_0 to 526_10. The OR gates 522_0 to 522_10 are connected in series. First input terminals of the OR gates 522_0 to 522_10 receive the verification signals SDV0 to SDV10, respectively. Output terminals of the OR gates 522_0 to 522_10 output the bit signals ST0 to ST10, respectively. <0> ~ST10 <0> The second input terminal of the OR gate of the first level (OR gate 522_0) receives the low logic level signal VSS. The second input terminals of the OR gates other than the first level (OR gates 522_1 to 522_10) receive the bit signal output from the output terminal of the OR gate of the next higher level.

[0040] The first input terminals of the AND gates 524_0 to 524_10 receive the verification signals SDV1 to SDV11, respectively. The second input terminals of the AND gates 524_0 to 524_10 receive the bit signals ST0 to ST11, respectively. <0> ~ST10 <0> Receive.

[0041] The OR gates 526_0 to 526_10 are connected in series. The first input terminals of the OR gates 526_0 to 526_10 are respectively coupled to the output terminals of the AND gates 524_0 to 524_10. The output terminals of the OR gates 526_0 to 526_9 are respectively coupled to the bit signal ST1 <1> ~ST10 <1> The second input terminal of the OR gate of the first level (OR gate 526_0) receives the low logic level signal VSS. The second input terminals of the OR gates other than the first level (OR gates 526_1 to 526_10) receive the bit signal output from the output terminal of the OR gate of the next higher level.

[0042] The second logic circuit 530 receives the first part P1 of the row selection signal set SELG, and performs an AND operation on the first row selection signal RSGSEL0[3:0] of the first part P1 and the second row selection signal RSGSEL1[2:0] of the first part P1 through AND gates 532_0 to 532_11 to generate operation signals RS0 to RS11.

[0043] 5C, the multiplex circuit 540 is coupled to the first logic circuit 520 and the second logic circuit 530. The multiplex circuit 540 receives the control signals ST0-ST10 and the operation signals RS0-RS11, and selects a plurality of the operation signals RS0-RS11 as the decoding signals SCD0-SCD10 based on the control signals ST0-ST10.

[0044] Specifically, the multiplex circuit 540 includes multiplexers 542_0 to 542_10. Unlike the previous embodiment, a first input terminal of the multiplexer 542_0 receives a low logic level signal VSS, and a second input terminal and a third input terminal of the multiplexer 542_0 receive the operation signals RS0 and RS1. A first input terminal, a second input terminal, and a third input terminal of each of the multiplexers 542_1 to 542_10 receive a corresponding one of the operation signals RS0 to RS11. For example, a first input terminal of the multiplexer 542_1 receives the operation signal RS0, a second input terminal of the multiplexer 542_1 receives the operation signal RS1, and a third input terminal of the multiplexer 542_1 receives the operation signal RS2. A first input terminal of the multiplexer 542_2 receives the operation signal RS1, a second input terminal of the multiplexer 542_2 receives the operation signal RS2, a third input terminal of the multiplexer 542_2 receives the operation signal RS3, and so on.

[0045] The control terminals of the multiplexers 542_0 to 542_10 receive control signals ST0 to ST10, respectively, and the output terminals of the multiplexers 542_0 to 542_10 output decoded signals SCD0 to SCD10, respectively. Each of the multiplexers 542_0 to 542_10 selects one of the signals received at its first input terminal (upper input terminal), the second input terminal (middle input terminal), and the third input terminal (lower input terminal) as the corresponding decoded signal in response to the received control signal, and outputs the selected signal at its output terminal. Taking the multiplexer 542_1 as an example, a bit signal ST1 at a high logic level is <0> and high logic level bit signal ST1 <1> When the multiplexer 542_1 receives the control signal ST1 (logic value 11) configured as <0> and a low logic level bit signal ST1 <1> When the multiplexer 542_1 receives the control signal ST1 (logical value 01) consisting of the bit signal ST1 at a low logic level, the multiplexer 542_1 selects and outputs the operation signal RS1 received at its second input terminal (middle input terminal) as the decoded signal SCD1. <0> and a low logic level bit signal ST1 <1> When the multiplexer 542_1 receives the control signal ST1 (logical value 00) configured as above, it selects and outputs the operation signal RS2 received at its third input terminal (lower input terminal) as the decoded signal SCD1.

[0046] The third logic circuit 550 is coupled to the latch circuit 510, the second logic circuit 530, and the multiplex circuit 540. The third logic circuit 550 receives the verification signals SDV0 to SDV11, the calculation signal RS0 of the corresponding lowest address among the calculation signals RS0 to RS11, and the decoded signals SCD0 to SCD10, inverts the verification signals SDV0 to SDV11 through inverters 552_0 to 552_11, and then performs an AND operation with the calculation signal RS0 and the decoded signals SCD0 to SCD10 through AND gates 554_0 to 554_11, respectively, to generate enable signals SE0 to SE11, which are output to the decoders 600_0 to 600_11, respectively.

[0047] 6A, 6B, and 6C, if two memory blocks opened by decoders 600_1 and 600_5 are damaged, inverters 552_1 and 552_5 in third logic circuit 550 receive verification signals SDV1 and SDV5 of high logic level (logic value 1), respectively, from latches L1 and L5 in latch circuit 510. In this way, AND gates 554_1 and 554_5 can only output enable signals SE1 and SE5 of low logic level (logic value 0) to decoders 600_1 and 600_5, respectively, rendering decoders 600_1 and 600_5 unusable as defective memory block decoders.

[0048] At this time, the OR gate 522_1 in the first logic circuit 520 also receives the verification signal SDV1 at a high logic level. Since the OR gates 522_0 to 522_10 are connected in series, the bit signal ST1 output from the OR gates 522_1 to 522_10 <0> ~ST10 <0> are all adjusted to a high logic level. <0> ~ST10 <0> The output terminals of the AND gates 524_1 to 524_10 that have received these signals are adjusted to the same logic level as the verification signals SDV2 to SDV11, respectively. That is, the output terminal of the AND gate 524_4 is adjusted to the same high logic level as the verification signal SDV5.

[0049] Since the OR gates 526_0 to 526_10 are also connected in series, the bit signals ST5 output by the OR gates 526_4 to 526_9 are <1> ~ST10 <1> are all adjusted to a high logic level. In this case, the logical values ​​of the control signals ST1 to ST3 are "01", the logical values ​​of the control signals ST5 to ST10 are "11", the multiplexers 542_1 to 542_3 in the multiplex circuit 540 are changed so as to select and output the operation signals RS1 to RS3 received at their second input terminals (middle input terminals) as the decoded signals SCD1 to SCD3, and the multiplexers 542_5 to 542_10 are changed so as to select and output the operation signals RS4 to RS9 received at their first input terminals (upper input terminals) as the decoded signals SCD5 to SCD10.

[0050] In this way, the row address range corresponding to decoders 600_2 to 600_4 arranged after decoder 600_1, which is to be the defective memory block decoder, is moved forward from the row address range RSG2 to RSG4 to become the row address range RSG1 to RSG3, and the row address range corresponding to decoders 600_6 to 600_11 arranged after decoder 600_5, which is to be the defective memory block decoder, is moved forward from the row address range RSG6 to RSG11 to become the row address range RSG4 to RSG9. As a result, decoder 600_2 replaces decoder 600_1 and corresponds to the row address range RSG1, and decoder 600_7 replaces decoder 600_5 and corresponds to the row address range RSG5, so that the two memory blocks opened by decoders 600_1 and 600_5 are no longer mapped.

[0051] For ease of understanding, the above embodiment is described using the example of one or two memory blocks having damaged defective memory cells, but the present invention is not limited thereto. Those skilled in the art can adjust the internal structure of the mapping control circuit according to the teachings of the present invention to suit the situation where more memory blocks have damaged defective memory cells.

[0052] In summary, the row decoder circuit of the present invention does not perform conventional repair for memory blocks with defective memory cells, but rearranges the row address range corresponding to the decoder, thus skipping the damaged defective memory blocks during mapping so that the memory device can be used normally, so that the partially damaged memory device can still be used, thereby improving the product yield and convenience of use. [Industrial Applicability]

[0053] The row decoder circuit of the present invention can be applied to a semiconductor memory device. [Explanation of symbols]

[0054] 100: Row decoder circuit 110: Pre-decoder 120_0~120_11, 400_0~400_11, 600_0~600_11: Decoder 130, 300, 500: Mapping control circuit 310, 510: Latch circuit 320, 520: First logic circuit 322_0~322_10, 522_0~522_10, 526_0~526_10: OR gate 330, 530: Second logic circuit 332_0~332_11, 354_0~354_11, 524_0~524_10, 532_0~532_11, 554_0~554_11: AND gate 340, 540: Multiplex circuit 342_0~342_10, 542_0~542_10: Multiplexer 350, 550: Third logic circuit 352_0~352_11, 552_0~552_11: Inverter DV: Validation data L0~L11: Latch P1: 1st part P2: 2nd part RA: Row address information RMWSEL0[7:0], RMWSEL1[3:0], RMWSEL2[2:0], RFXSEL[7:0]: Row selection signals RS0~RS11: Computed signal RSG0~RSG11: Row address range RSGSEL0[3:0]: 1st row selection signal RSGSEL1[2:0]: Second row selection signal SCD0~SCD10: Decoded signals SDV0~SDV11: Verification signals SE0~SE11: Enable signal SELG: Row selection signal set ST0~ST10: Control signals ST0 <0> ~ST10 <0> , ST0 <1> ~ST10 <1> :Bit signal SWL0 to SWL11: Word line signals VSS: Low logic level signal

Claims

1. Suitable for memory devices, a pre-decoder configured to receive row address information and decode the row address information to provide a set of row select signals; a plurality of decoders corresponding sequentially to a plurality of row address ranges; a mapping control circuit coupled to the predecoder and the plurality of decoders, configured to obtain a selected row address range based on the set of row selection signals, and to cause the decoder having the same selected row address range as the corresponding row address range to output a word line signal; The mapping control circuit reorders the plurality of row address ranges corresponding to the plurality of decoders based on verification data.

2. 2. The row decoder circuit of claim 1, wherein the mapping control circuit obtains the selected row address range based on a first portion of the row selection signal set, and the decoder having the same selected row address range as the corresponding row address range outputs the corresponding word line signal based on a second portion of the row selection signal set.

3. 2. The row decoder circuit according to claim 1, wherein said mapping control circuit generates a plurality of verification signals based on said verification data, and disables at least one defective memory block decoder among said plurality of decoders based on said plurality of verification signals.

4. 4. The row decoder circuit of claim 3, wherein the mapping control circuit shifts the row address ranges corresponding to the decoders arranged after the at least one defective memory block decoder forward based on the verification signals, thereby replacing the at least one defective memory block decoder.

5. The mapping control circuit a latch circuit configured to store the verification data; 2. The row decoder circuit according to claim 1, wherein said latch circuit includes a plurality of latches for outputting a plurality of bit values ​​constituting said verification data as a plurality of verification signals, respectively.

6. The mapping control circuit 6. The row decoder circuit of claim 5, further comprising: a first logic circuit coupled to the latch circuit and configured to receive the plurality of verification signals and a low logic level signal, and to perform a multi-level operation using the plurality of verification signals and the low logic level signal to generate a plurality of control signals.

7. The first logic circuit a plurality of OR gates connected in series; 7. The row decoder circuit of claim 6, wherein a first input terminal of each of the plurality of OR gates receives a corresponding verification signal, an output terminal of each of the plurality of OR gates outputs a corresponding control signal, a second input terminal of an OR gate at a first level receives the low logic level signal, and a second input terminal of an OR gate other than the first level receives the control signal output by an output terminal of an OR gate at a level one level higher.

8. each of the plurality of control signals includes a first bit signal and a second bit signal; The first logic circuit a plurality of first OR gates connected in series, a first input terminal of each of the plurality of first OR gates receiving a corresponding verification signal, an output terminal of each of the plurality of first OR gates outputting a corresponding first bit signal, a second input terminal of a first OR gate at a first level receiving the low logic level signal, and a second input terminal of a first OR gate other than the first level receiving the first bit signal output by an output terminal of a first OR gate at a level higher than the first level; a plurality of AND gates, each of which has a first input terminal receiving a corresponding one of the verify signals and a second input terminal receiving a corresponding one of the first bit signals; 7. The row decoder circuit of claim 6, comprising: a plurality of second OR gates connected in series, a first input terminal of each of the plurality of second OR gates coupled to an output terminal of a corresponding one of the AND gates, an output terminal of each of the plurality of second OR gates outputting a corresponding second bit signal, a second input terminal of a second OR gate at a first level receiving the low logic level signal, and a second input terminal of a second OR gate other than the first level receiving the second bit signal output by an output terminal of a second OR gate at a level higher.

9. The mapping control circuit 7. The row decoder circuit of claim 6, further comprising: a second logic circuit configured to receive a first portion of the set of row select signals and AND a plurality of first row select signals in the first portion with a plurality of second row select signals in the first portion to generate a plurality of operational signals.

10. The second logic circuit 10. The row decoder circuit of claim 9, including a plurality of AND gates, wherein a first input terminal of each of the plurality of AND gates receives a corresponding one of the first row selection signals, a second input terminal of each of the plurality of AND gates receives a corresponding one of the second row selection signals, and an output terminal of each of the plurality of AND gates outputs a corresponding one of the operation signals.

11. The mapping control circuit 10. The row decoder circuit of claim 9, further comprising: a multiplex circuit coupled to the first logic circuit and the second logic circuit, receiving the plurality of control signals and the plurality of operational signals, and selecting, based on the plurality of control signals, a plurality of the plurality of operational signals as a plurality of decoded signals.

12. The multiplex circuit 12. The row decoder circuit according to claim 11, comprising a plurality of multiplexers, each of which receives two corresponding operation signals at its first input terminal and its second input terminal, and each of which receives a corresponding control signal at its control terminal, thereby selecting either the signal received at its first input terminal or the signal received at its second input terminal as the corresponding decoded signal and outputting it at its output terminal.

13. The multiplex circuit 12. The row decoder circuit according to claim 11, comprising a plurality of multiplexers, wherein a first input terminal of any of the plurality of multiplexers receives the low logic level signal, a second input terminal and a third input terminal of any of the plurality of multiplexers receive the corresponding two of the operation signals, and each of the other first, second and third input terminals of the plurality of multiplexers receives the corresponding three of the operation signals, and each of the plurality of multiplexers receives a corresponding control signal at a control terminal thereof, thereby selecting any of the signal received at its first input terminal, the signal received at its second input terminal and the signal received at its third input terminal as the corresponding decoded signal and outputting it at its output terminal.

14. The mapping control circuit 12. The row decoder circuit of claim 11, further comprising: a third logic circuit coupled to the latch circuit, the second logic circuit, and the multiplex circuit, receiving the plurality of verification signals, the operation signal of the corresponding lowest address among the plurality of operation signals, and the plurality of decoded signals, and inverting the plurality of verification signals, and then ANDing the inverted verification signals with the operation signal of the corresponding lowest address and the plurality of decoded signals, and outputting a plurality of generated enable signals to the plurality of decoders, respectively.

15. The third logic circuit a plurality of inverters, each inverter having an input terminal receiving a corresponding one of the verification signals; 15. The row decoder circuit of claim 14, comprising: a plurality of AND gates, wherein a first input terminal of any of the plurality of AND gates receives the operation signal of the lowest address corresponding to one of the plurality of operation signals, each other first input terminal of the plurality of AND gates receives the corresponding decoded signal, a second input terminal of each of the plurality of AND gates is coupled to an output terminal of a corresponding one of the inverters, and an output terminal of each of the plurality of AND gates outputs the corresponding one of the enable signals.

16. 2. The row decoder circuit of claim 1, wherein said mapping control circuit determines the location of at least one damaged bad memory block based on said verification data.

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