Semiconductor memory device

Abstract

To provide a semiconductor storage device for storing data by accumulating majority carriers in an electrically floating body of a MOSFET.SOLUTION: In a memory device using a semiconductor device, plate lines PLL0, PLR0 capacitively coupled to floating bodies of memory cells MCL, MCR are wired in parallel with word lines WLL0, WLR0 separately for each word line, and an erase operation of majority carriers is executed simultaneously along the word lines by applying a voltage to the plate lines. In the refresh operation, after the data along the selected word line is read and latched by the sense amplifier S / A, the bit lines BLL and BLR are separated from the sense amplifier to once erase the majority carriers all together from the floating bodies of the cells on the selected word line, and the majority carriers are injected into the cells in which a large number of majority carriers are originally stored depending on the state of the sense amplifier. In addition, the write operation includes an operation of simultaneously extracting majority carriers from the selected cell and simultaneously writing data to the sense amplifier from the outside.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a memory device using a semiconductor element. [Background technology]

[0002] In recent years, with the development of LSI (Large Scale Integration) technology, there has been a demand for memory devices that can incorporate logic circuits using semiconductor elements with higher integration, higher performance, lower power consumption, and higher functionality.

[0003] DRAM (Dynamic Random Access Memory) is widely used as memory for integrated circuits. In order to improve the density of DRAM memory, there are DRAMs (see, for example, Non-Patent Document 1) that use an SGT structure extending in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Non-Patent Document 2), and DRAM memory cells that do not have a capacitor and are composed of a single MOS transistor (see, for example, Non-Patent Documents 3 to 6). This is commonly called "1TDRAM." For example, logical storage data "1" is written by retaining some or all of the holes among the holes and electrons generated in the channel by impact ionization due to a current between the source and drain of an n-channel MOS transistor in the channel. Then, logical storage data "0" is written by removing the holes from the channel.

[0004] For example, in an n-channel MOS transistor formed on SOI (Silicon On Insulator), a source-drain current generates holes and electrons in the channel due to impact ionization. Some or all of the holes are retained in the floating body to write logical data "1" (low threshold voltage). Then, the holes are removed from the body to write logical data "0" (high threshold voltage). Initially, writing "0" was achieved by raising the gate voltage of the cell connected to the word line and then setting the bit line connected to the cell's drain to a negative potential (the cell's source potential is defined as 0V). However, this method required that unselected word lines be set to a negative potential to prevent holes from being extracted from the bodies of other cells connected to the same bit line, thereby lowering the body voltage of unselected cells to a sufficiently low voltage. As a result, when the bit line potential is increased to write a "1," the gate voltage as seen from the drain becomes a large negative value, causing GIDL (Gate Induced Drain Leakage) to cause holes to flow into the body of the "0" data cell, changing the "0" state cell to a "1" state (bit line disturbance).

[0005] To solve this problem, a method has been devised for writing a "0" by increasing the voltage of the plate that is capacitively coupled to the body to extract holes from the body. For example, a cell called Key Shaped Floating Body Memory (KFBM) has a structure in which a tall silicon pillar is separated on all four sides by a thin insulating film and covered with a plate electrode (see Patent Document 1 and Non-Patent Document 7). By raising the voltage of this plate electrode when writing "0" data, holes can be extracted from the body of all cells in the cell array. Because this "0" write does not require selectivity, there is no need to apply a negative potential to the word line when writing a "0"; 0V is sufficient. Therefore, the bit line disturbance issue that was a problem with the original cell when writing a "1" is significantly improved.

[0006] However, in a storage device using this memory element, there remains a problem in that the method for performing write and refresh operations has not been clearly defined. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US 2023 / 0077140 A1 [Patent Document 2] US 11,823,727 B2

[0008] [Non-Patent Document 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991) [Non-patent document 2] H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, YC Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device Research Conference, (2011) [Non-patent document 3] T. Ohsawa、K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asano, and K. Sunouchi, “Memory Design Using a One-Transistor Gain Cell on SOI.” IEEE Journal of Solid State Circuits, Vol. 37, No.11, pp.1510-1522 (2002)

Outdoor Tools 4

Direct Environment 5

Outdoor Configuration6

[0009] An object of the present invention is to provide new write and refresh operations, a circuit for realizing them, and a driving method thereof, in order to realize a random access memory.

[0010] To solve the above problems, a memory device using semiconductor elements according to the present invention has a configuration in which a plate line runs parallel to the word line and is shared among cells belonging to a page selected by the word line, and this plate line is connected to an electrode capacitively coupled to the floating body of the MOSFET forming the memory cell. Then, the word line is activated, data stored in the memory cells belonging to that page is read and latched by a sense amplifier. The bit line and the sense amplifier are then disconnected, and the plate line belonging to that page is activated to drain majority carriers from the floating body of the memory cell belonging to that page. At the same time, the latched state of the sense amplifier is inverted as needed using data input from the data line. Then, writing is achieved by programming (injecting majority carriers) the cells belonging to that page according to the new latched state of the sense amplifier. Refreshing can be achieved using similar operations, except for the operation of "inverting the latched state of the sense amplifier as needed using data input from the data line."

[0011] One aspect of the present invention is a method for producing a medicament for the treatment of a pulmonary arthritis. A page (an example is a group of cells connected to a common WL in FIG. 1) is configured by a plurality of memory cells arranged in a first direction (an example is the direction in which the WL in FIG. 1 extends) on a substrate (an example is 14 in FIG. 17) in a plan view, Each of the memory cells has an electrically floating semiconductor body (e.g., 8 in FIG. 17) and a first impurity region (an example is 9 in FIG. 17) that contacts one side of the side surface of the semiconductor body and is connected to a source line; and a second impurity region (an example is 19 in FIG. 17) that contacts the other side of the side surface of the semiconductor body and is connected to a bit line; a gate insulating film (15 in FIG. 17 is an example) in contact with the semiconductor substrate; a first gate conductor layer (shown as 1 in FIG. 17 as an example) that forms a transistor together with the semiconductor body, the first impurity region, and the second impurity region, the first gate conductor layer being in contact with the gate insulating film and connected to a word line (shown as WL in FIG. 1 as an example); a second gate conductor layer (an example of which is shown in FIG. 17 as 3) that contacts the gate insulating film at a position different from that of the first gate conductor layer and is connected to a plate line (an example of which is shown in FIG. 1 as PL); A first switching circuit (SW3 in FIG. 4) is connected to the bit line. j , SW4 j , SW3 j+1 , SW4 j+1 a sense amplifier circuit (examples include the current load circuit and latch circuit in FIG. 4) that amplifies and latches signals read from the memory cells connected via a sense amplifier circuit (examples include the current load circuit and latch circuit in FIG. 4); The sense amplifier circuit is connected to a second switching circuit (SW1 in FIG. 4). j , SW2 j , SW1 j+1 , SW2 j+1 and data lines (examples are QD and / DQ in FIG. 4) connected via During writing, the semiconductor memory device is characterized in that the word line is activated, the data stored in the memory cell is amplified and latched by the sense amplifier circuit through the first switching circuit, the first switching circuit is turned off, the plate line is selected to erase the memory cell, and at the same time, the second switching circuit is turned on to input data from the data line to the sense amplifier circuit, changing the latch state of the sense amplifier circuit, and then the memory cell is programmed according to the latch state of the sense amplifier circuit (the timing chart in Figure 13 is an example).

[0012] In the semiconductor memory device, preferably, During refresh, the word line is activated to turn on the first switching circuit, and the data stored in the memory cell is amplified and latched by the sense amplifier circuit. turning off the first switching circuit and selecting the plate line to erase the memory cell; Thereafter, the memory cells are programmed in accordance with the latch state of the sense amplifier circuit (the timing chart of FIG. 14 is an example).

[0013] In the semiconductor memory device, preferably, In a plan view, a word line driver circuit (an example of which is the WL drivers in FIG. 16) connected to one end of the word line extending in the first direction is selectively activated by a row address selection circuit (an example of which is the row decoder in FIG. 16), a plate line driver circuit (an example of which is the PL drivers in FIG. 16) connected to one end of the plate line is located in the opposite direction to the word line driver circuit with respect to the first direction; The plate line driving circuit is selectively activated by the word line.

[0014] In the semiconductor memory device, preferably, The sense amplifier circuit (S / A in FIG. 4) j is an example) The first bit line (BLL in Figure 4) j is an example) to the first switching element (SW3 in Figure 4 j The first sense node (SNL in Figure 4) is separated via j is one example) and The first bit line (BLL in FIG. 4) j is an example) of the sense amplifier (S / A in FIG. 4 j 4 is an example), or another second bit line (BLR 1 in FIG. 4) adjacent to the first bit line. j is an example) to the second switching element (SW4 in Figure 4 j The second sense node (SNR in FIG. 4 is an example) is separated via j is one example) and A current load circuit (S / A in FIG. 4) that supplies current to the first and second bit lines via the first and second sense nodes and the first and second switching elements j "Current load circuit" belonging to the A latch circuit (S / A in FIG. 4) amplifies and latches the potential difference between the first and second sense nodes. j "Latch circuit" is an example) and A first program circuit (BLL in FIG. 4) applies a voltage to the first bit line. j (An example is a "program circuit" that connects to A second program circuit (BLR in FIG. 4) applies a voltage to the second bit line. j (An example is a "program circuit" that connects to A third switching element (SW5 in FIG. 4) that drops the first bit line to the ground potential j is one example) and A fourth switching element (SW6 in FIG. 4) that drops the second bit line to the ground potential j is one example) and a fifth switching element that connects the first sense node to one of the common data lines (DQ in FIG. 4 is an example); a sixth switching element that connects the second sense node to the other of the common data lines ( / DQ in FIG. 4 is an example); The present invention is characterized by having the following.

[0015] In the semiconductor memory device, preferably, The current load circuit and the latch circuit are the same circuit (TR20 in FIG. 15). j ~TR28 j An example of the circuit is

[0016] In the semiconductor memory device, preferably, In addition to the sense amplifier circuit, There is a second sense amplifier, and this second sense amplifier The third bit line (BLL in Figure 4) j+1 is an example) to the seventh switching element (SW3 in Figure 4) j+1 The third sense node (SNL in Figure 4) is separated via a j+1 is one example) and The third bit line (BLL in FIG. 4) j+1 4) of the second sense amplifier (S / A j+1 4 ) on the opposite side to the third bit line or adjacent to the third bit line. j+1 is an example) to the eighth switching element (SW4 in Figure 4 j+1 The fourth sense node (SNR in Figure 4) is separated via an j+1 is one example) and A current load circuit (S / A in FIG. 4) that supplies current to the third and fourth bit lines via the third and fourth sense nodes and the seventh and eighth switching elements j+1 "Current load circuit" belonging to the A latch circuit (S / A in FIG. 4) amplifies and latches the potential difference between the third and fourth sense nodes. j+1 An example is the "latch circuit" that belongs to A third program circuit (BLL in FIG. 4) applies a voltage to the third bit line. j;1 (An example is a "program circuit" that connects to A fourth program circuit (BLR in FIG. 4) applies a voltage to the fourth bit line. j+1 (An example is a "program circuit" that connects to The ninth switching element (SW5 in FIG. 4) that drops the third bit line to the ground potential j+1 is one example) and The tenth switching element (SW6 in FIG. 4) that drops the fourth bit line to the ground potential j+1 is one example) and an eleventh switching element that connects the third sense node to one of the common data lines (DQ in FIG. 4 is an example); a twelfth switching element that connects the fourth sense node to the other of the common data lines ( / DQ in FIG. 4 is an example); A thirteenth switching circuit (SW7 in FIG. 4) is connected between the first sense node of the sense amplifier circuit and the third sense node of the second sense amplifier. j, j+1 is an example of an electrical short circuit Alternatively, a fourteenth switch circuit (SW8 in FIG. 4) is connected between the third sense node of the second sense amplifier and the fourth sense node of the second sense amplifier. j, j+1 The device is characterized in that it is electrically short-circuited by a short-circuiting mechanism (for example,

[0017] In the semiconductor memory device, preferably, A first dummy cell (DCL in FIG. 4) having the same structure as the memory cell j is an example) is connected to the first bit line and the first dummy word line, A second dummy cell (DCR in FIG. 4) having the same structure as the memory cell j is an example) is connected to the second bit line and the second dummy word line, A third dummy cell (DCL in FIG. 4) having the same structure as the memory cell j+1 is an example) is connected to the third bit line and the first dummy word line, A fourth dummy cell (DCR in FIG. 4) having the same structure as the memory cell j+1 is an example) is connected to the fourth bit line and the second dummy word line, the states stored in the first dummy cell and the third dummy cell are opposite to each other; The states stored in the second dummy cell and the fourth dummy cell are opposite to each other.

[0018] In the semiconductor memory device, preferably, the semiconductor body is a first semiconductor region of a first conductivity type (e.g., 8 in FIG. 17) extending vertically in a columnar shape from the surface of the substrate in an electrically floating state, the first gate conductor layer is connected to the upper surface of the first semiconductor region via a gate insulating film (15 in FIG. 17 is an example); the second gate conductor layer (an example of which is shown as 3 in FIG. 17) is connected to a pillar portion of the first semiconductor region via the gate insulating film, the first impurity region and the second impurity region are second semiconductor regions of a second conductivity type (examples are 9 and 19 in FIG. 17 ) that are in contact with upper side surfaces of the first semiconductor region and are located on both sides of the first semiconductor region in the horizontal direction, A source line is connected as a first metal wiring layer (an example is shown in FIG. 17 4) to the second semiconductor region (an example is shown in FIG. 17 9) corresponding to the first impurity region, a bit line is connected as a second metal wiring layer (an example is shown in FIG. 17 2) to the second semiconductor region (an example is shown in FIG. 17 19) corresponding to the second impurity region, a word line is connected to the first gate conductor layer, a plate line is connected to the second gate conductor layer, and the word lines are separated and wired in parallel to the word lines. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is an equivalent circuit diagram of a memory device using a semiconductor element according to a first embodiment. [Figure 2] 1 shows the operating principle of writing (programming) "1" in a memory device using a semiconductor element according to the first embodiment. [Figure 3] 1 shows the operating principle of writing (erasing) "0" in a memory device using a semiconductor element according to the first embodiment. [Figure 4] 1 is a block diagram of a sense amplifier circuit of a memory device using a semiconductor element according to a first embodiment. [Figure 5] 2 is an example of a sense amplifier circuit diagram of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 6] 2 is a diagram emphasizing transistors involved in the basic operation of data sensing in a sense amplifier circuit of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 7] 2 is a diagram emphasizing transistors related to the basic operation of a latch in a sense amplifier circuit of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 8] 2 is a diagram emphasizing transistors related to basic programming operations in a sense amplifier circuit of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 9] 1 is a diagram emphasizing transistors involved in the basic erase operation in a sense amplifier circuit of a memory device using a semiconductor element according to a first embodiment. FIG. [Figure 10] 2 is a diagram emphasizing transistors involved in the basic operation of writing to a sense amplifier in a sense amplifier circuit of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 11] 2 is a diagram emphasizing transistors involved in the basic operation of reading from a sense amplifier in a sense amplifier circuit of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 12] 5A to 5C are diagrams illustrating a read operation of the memory device using the semiconductor element according to the first embodiment. [Figure 13] 3A to 3C are diagrams illustrating a write operation of a memory device using a semiconductor element according to the first embodiment. [Figure 14] 5A to 5C are diagrams illustrating a refresh operation of the memory device using the semiconductor element according to the first embodiment. [Figure 15] 4 is another example of a sense amplifier circuit diagram of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 16] 2 is a diagram illustrating a row decoder, a word line driving circuit, and a plate line driving circuit of a memory device using a semiconductor element according to the first embodiment. FIG. [Figure 17A] FIG. 1 is a diagram showing a plan view of a memory device using a semiconductor element according to a first embodiment. [Figure 17B] FIG. 17B is a cross-sectional view taken along the line AA′ in FIG. 17A. [Figure 17C] FIG. 17B is a cross-sectional view taken along line BB' in FIG. 17A. [Figure 17D] FIG. 17B is a cross-sectional view taken along CC' in FIG. 17A. [Figure 17E] FIG. 17B is a cross-sectional view taken along the line DD' in FIG. 17A. [Figure 17F] FIG. 17B is a cross-sectional view taken along the line EE′ of FIG. 17A. [Figure 18A] FIG. 10 is a plan view of a memory device using a semiconductor element according to a second embodiment. [Figure 18B] FIG. 18B is a cross-sectional view taken along the line AA′ in FIG. 18A. [Figure 18C] FIG. 18B is a cross-sectional view taken along line BB' in FIG. 18A. [Figure 18D] FIG. 18B is a cross-sectional view taken along CC' in FIG. 18A. [Figure 18E] FIG. 18B is a cross-sectional view taken along the line DD' in FIG. 18A. [Figure 18F] FIG. 18B is a cross-sectional view taken along the line EE′ of FIG. 18A. [Figure 19] FIG. 10 is an equivalent circuit diagram of a memory device using a semiconductor element according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, a memory device using a semiconductor element according to an embodiment of the present invention will be described with reference to the drawings.

[0021] (First embodiment) An equivalent circuit of a memory cell and a sense amplifier of a memory device using the semiconductor device of this embodiment will be described with reference to FIG. 1. In FIG. 1, a plurality of memory cells (MCL i,j , MCL i+1,j , MCL i+2,j , MCL i,j+1, MCL i+1,j+1 , MCL i+2,j+1 , MCR i,j , MCR i+1,j , MCR i+2,j , MCR i,j+1 , MCR i+1,j+1 , MCR i+2,j+1 ) are arranged in a matrix in the row direction of the cell array (word line group WLL i or WLR i Sense amplifier circuit (S / A j The memory cell of this embodiment is formed of a conventional n-type MOSFET whose body is in an electrically floating state (see Patent Documents 1 and 2). A bit line BLL is connected to the source or drain. j / BLR j Alternatively, a source line SL is connected to the floating body. i or PLR i These memory cells store data by accumulating majority carriers in the floating body. If we define a state in which a large number of majority carriers are accumulated as "1" and a state in which a small number of majority carriers are accumulated as "0," the threshold voltage of a memory cell in the "1" state is lower than that of a "0," and when read under the same voltage conditions, a "1" cell will have a larger current flow than a "0" cell, making it possible to identify the data.

[0022] Here, an example of the structure of a memory cell according to this embodiment will be specifically described. One example of the memory cell has an electrically floating semiconductor body, a first impurity region connected to a source line in contact with both ends of the semiconductor body, a second impurity region connected to a bit line, a gate insulating film in contact with the semiconductor body, a first gate conductor layer in contact with the gate insulating film and connected to a word line, and a second gate conductor layer in contact with the gate insulating film and connected to a plate line.

[0023] In FIG. 1, the sense amplifier circuit (S / A j ) is the group of word lines to the left of WLL i , the word lines on the right side are WLRi Here, i is a natural number representing the word line number (1≦i≦M). Similarly, the sense amplifier circuit (S / A j ) to the left of the BLL j , the word lines on the right side are BLR j Here, j is a natural number representing the bit line number (1≦j≦N). In Figure 1, there are six word lines (WLL), three on each side. i , W.L.L. i+1 , W.L.L. i+2 , W.L.R. i , W.L.R. i+1 , W.L.R. i+2 And two on each side, a total of four bit lines BLL j , BLL j+1 , B.L.R. j , B.L.R. j+1 Only the PLL plate lines are shown. i , PLL i+1 , PLL i+2 , PLR i , PLR i+1 , PLR i+2 Here, the word lines, source lines, and plate lines are all wired in parallel, and the bit lines are wired perpendicular to these. j jth left bit line BLL j and the jth right bit line BLR j Here, the bit line BLL on the left is connected. j and word line WLL i , W.L.L. i+1 and WLL i+2 Each memory cell connected to MCL i,j , MCL i+1,j and MCL i+2,j and the bit line BLL on the left j+1 and word line WLL i , W.L.L. i+1 and WLL i+2 Each memory cell connected to MCL i,j+1 , MCL i+1,j+1 and MCL i+2,j+1 Similarly, the bit line BLR on the right sidej and word line WLR i , W.L.R. i+1 and WLR i+2 Each memory cell connected to MCR i,j , MCR i+1,j and MCR i+2,j and the bit line BLR on the right j+1 and word line WLR i , W.L.R. i+1 and WLR i+2 Each memory cell connected to MCR i,j+1 , MCR i+1,j+1 and MCR i+2,j+1 It is stated as such.

[0024] Using Figure 2, we will explain the write operation in which holes, which are majority carriers, are accumulated in the floating body of a memory cell in a memory device using the semiconductor device of this embodiment. By applying a positive voltage to the word line and a positive voltage to the bit line, the MOSFET of the memory cell is saturated. This causes a pinch-off state near the drain (node ​​connected to the bit line) of the MOSFET, and electrons flowing through the channel are accelerated by a high electric field. These electrons collide with silicon atoms, generating many electron-hole pairs (impact ionization). Of these, electrons flow into the bit line and holes flow into the floating body. This results in holes accumulating in the floating body, creating a state in which many holes are accumulated in the body. This state is defined as "1." Similarly, using Figure 3, we will explain the operation of extracting holes from the floating body of a memory cell in a memory device using the semiconductor device of this embodiment. Starting with a state in which both the gate (word line) and drain (bit line) of the MOSFET of the memory cell are set to 0 V, the plate line (PL) is raised to a positive potential. As a result, many of the holes stored in the floating body flow out of the floating body made of p-type silicon into the n-type silicon layer (such as the source line or bit line), resulting in a decrease in the number of holes stored in the floating body. This state is defined as "0." Note that the above-mentioned methods for realizing the "1" state and the "0" state are only examples, and other methods are also possible.

[0025] First, the configuration of the memory cell array and the sense amplifier circuit will be described with reference to FIG. j The bit line pair BLL will be explained. j , B.L.R. j (This is an example of the bit line of claim 1) to the first switching element pair SW3 j , SW4 j (This is an example of the first switching circuit of claim 1) j , SNR j and the sense node pair SNL j , SNR j and the first switching element pair SW3 j , SW4 j via the bit line pair BLL j , B.L.R. j a current load circuit for passing a current to the sense node pair SNL; j , SNR j a latch circuit for amplifying and latching the potential difference between the bit line pair BLL j , B.L.R. j a program circuit pair that applies a voltage to the bit line pair BLL; j , B.L.R. j The second switching element pair SW5 j , SW6 j and a third switching element pair SW1 connecting the sense node pair to a common data line pair (which is an example of the data line in claim 1). j , SW2 j (This is an example of the second switching circuit of claim 1) j (This is an example of the sense amplifier circuit of claim 1) and the bit line pair BLL j , B.L.R. j The memory cell MCL0 is a metal-insulator-semiconductor field-effect transistor with a floating body and a drain or source connected to the j , MCR0 j (This is an example of the memory cell of claim 1), and the memory cell MCL0 j , MCR0 jplate lines PLL0 and PLR0 (which are examples of the plate lines in claim 1) capacitively coupled to the floating body of the memory cell MCL0; j , MCR0 j The sense amplifier has word lines WLL0 and WLR0 (an example of the word lines in claim 1) connected to the gates of the sense amplifiers, and the plate lines PLL0 and PLR0 are wired in one-to-one correspondence with the word lines WLL0 and WLR0. Although not shown in FIG. 4, there are M word lines on each side of the sense amplifier, and in addition to these, there is one special word line on each side, for example, located closest to the sense amplifier. However, it does not matter where they are located. These are dummy word lines DWLL and DWLR, and are input to the gates of special memory cells. These special cells are dummy cells DCL j , D.C.L. j+1 , D.C.R. j , D.C.R. j+1 It is called DCL, and the states of "1" and "0" are written to every other bit line in advance. j "1" is written to DCL j+1 "0" is written to DCR. Or vice versa. j "1" is written to DCR j+1 is written with "0", or vice versa.

[0026] Here, an example of the structure of a memory cell according to this embodiment will be specifically described. One example of the memory cell has an electrically floating semiconductor body, a first impurity region connected to a source line in contact with both ends of the semiconductor body, a second impurity region connected to a bit line, a gate insulating film in contact with the semiconductor body, a first gate conductor layer in contact with the gate insulating film and connected to a word line, and a second gate conductor layer in contact with the gate insulating film and connected to a plate line.

[0027] Next, the configuration of the sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be described with reference to a circuit block diagram in Fig. 4. In Fig. 4, the parts surrounded by dashed lines are the sense amplifiers S / A j , S / A j+1 Since each configuration is exactly the same, the sense amplifier S / A j Sense amplifier S / A j In the center are the current load circuit and latch circuit, which are controlled by the signals Read and LTC, respectively. j and the right sense node SNR j The left sense node SNL is shared. j is the switch element SW3 j via the left bit line BLL j The right sense node SNR is connected to j is the switch element SW4 j via the right bit line BLR j These switch elements SW3 j and SW4 j Both are controlled by the signal CLMP. j is input to the left program circuit, and the output of the left program circuit is connected to the left bit line BLL j The program circuit on the left side is controlled by a signal PRGL. Similarly, the sense node SNR on the right side j is input to the program circuit on the right side, and the output of the program circuit on the right side is connected to the bit line BLR j The program circuit on the right is controlled by the signal PRGR. The sense node SNL on the left j is the jth column select line CSL j Switch element SW1 controlled by j The right sense node SNR is connected to the DQ side of the common input / output line pair DQ, / DQ via j is the jth column select line CSL j Switch element SW2 controlled by jThe left and right bit lines BLL are connected to the / DQ side of the common input / output line pair DQ, / DQ via j and BLR j are switch elements SW5 controlled by the signal PRCH. j and SW6 j The jth sense amplifier S / A j The left sense node SNL j and the j+1th sense amplifier S / A j+1 The left sense node SNL j+1 is a switch element SW7 controlled by a signal DCAVL. j,j+1 Similarly, the j-th sense amplifier S / A j The right sense node SNR j and the j+1th sense amplifier S / A j+1 The right sense node SNR j+1 is the switch element SW8 controlled by the signal DCAVR j,j+1 Although the current load circuit and the latch circuit are shown as separate circuits in FIG. 4, they may be merged into one circuit block.

[0028] The standby state of the block diagram of the memory cell array and sense amplifier circuit shown in Figure 4 will now be described. This is the state before any basic operation is started or after any basic operation has been completed. First, the source line is always grounded. In the standby state, all word lines and dummy word lines are grounded, and all plate lines are at a negative potential (V PLH ) is set to the CLMP level. j , SW3 j+1 , SW4 j , SW4 j+1 is controlled to be in the on state (positive voltage V CLMP The signal PRCH is set to all switch elements SW5 j , SW5 j+1 , SW6 j , SW6 j+1 Turn on all bit lines BLL j , BLLj+1 , B.L.R. j , B.L.R. j+1 and all sense nodes SNL j , SNL j+1 , SNR j , SNR j+1 The column selection line CSL is controlled to be grounded. j , CSL j+1 is in the non-selected state, and the switch element SW1 j , SW1 j+1 , SW2 j , SW2 j+1 The signals DCAVL and DCAVR are set to the off state. The signal Read puts the current load circuit in a state where it does not pass a load current, and the signal LTC puts the latch circuit in an inactive state. The left and right program circuits are set to a state where they do not output to the left and right bit lines by the signals PRGL and PRGR, respectively. Also, the signals DCAVL and DCAVR are set to the off state by the signals SW7 and SW8. j,j+1 , SW8 j,j+1 This state is the standby state.

[0029] The basic operation of the memory cell and sense amplifier of the storage device using the semiconductor element of this embodiment will be described with reference to FIG.

[0030] First, the basic operation of "data sense" of the memory cell and sense amplifier of the memory device using the semiconductor device of this embodiment will be described. j , MCL0 j+1 The data stored in (MCL0 j "0" data is written to MCL0 j+1 (assuming that "1" data is stored in each of the sense amplifiers S / A j , S / A j+1 Assume that sensing is performed with a 0V positive voltage. Operation starts from the standby state. First, the signal PRCH stops the grounding operation of all bit lines, and the bit lines are set to a floating 0V state. After that, the word line WLL0 selected by the address in the left cell array is set from the ground level to the positive voltage V for reading. WLRAt the same time, the dummy word line D WLR The positive voltage V for readout is set from the ground level. WLR After that, the current load circuit is activated by the signal Read, and the power supply voltage V dd via the bit line to memory cell MCL0 j , MCL0 j+1 and dummy cell DCR j , D.C.R. j+1 This current is drawn into the source line SL at the ground level via the memory cell and the dummy cell. At this time, the sense node SNR j and SNR j+1 Switch element SW8 j,j+1 (by activating the signal DCAVR). j and DCR j+1 Since the opposite data was previously written to the right bit line BLR, this electrical short circuit j and BLR j+1 is the averaged reference current I ref (If the read currents of the "0" cell and the "1" cell are denoted as I0 and I1, respectively, then I ref On the other hand, based on the above assumption, the left bit line BLL j and BLL j+1 In this situation, I0 and I1 flow through the sense amplifier S / A j SNL, which is the sense node pair of j and SNR j SNL j is the SNR j The power supply voltage V dd The signal is developed so that the voltage rises in the direction of the sense amplifier S / A. j+1 SNL, which is the sense node pair of j+1 and SNR j+1 is the SNR j+1 SNL j+1 The power supply voltage V ddThe signal is developed so that the voltage rises in the direction of the arrow A. The above is the basic operation of "data sense" of the memory cell and sense amplifier of the storage device using the semiconductor element of this embodiment.

[0031] Next, the basic operation of the memory cell and the sense amplifier "latch" of the memory device using the semiconductor device of this embodiment will be described. The basic operation of the "latch" starts when the basic operation of the "data sense" is completed. When the voltage difference between the sense node pairs of these sense amplifiers exceeds a certain level, the signal CLMP is set to V CLMP By dropping the sense node pair from the ground level to the ground level, the sense amplifier's sense node pair is disconnected from the bit line. Then, by activating the signal LTC, the sense node pair is disconnected from the ground level and the power supply voltage V dd Under the above assumptions, the SNL j is the power supply voltage V dd SNR level j is latched at ground level. j+1 is the ground level and the SNR j+1 is the power supply voltage V dd The above is the basic operation of the "latch" of the memory cell and sense amplifier of the storage device using the semiconductor element of this embodiment.

[0032] Next, the basic operation of "erase" of the memory cells and sense amplifiers of the memory device using the semiconductor element of this embodiment will be explained. The basic operation of "erase" is to set the memory state of all memory cells selected by the word line to "0". In other words, it is a basic operation that removes majority carrier holes from the floating body of the memory cell to reduce the number of holes present there. The basic operation of "erase" starts when the basic operation of "latch" is completed or from the standby state. When entering the basic operation of "erase" from the standby state, the signal CLMP is set to V CLMPBy dropping the signal PRCH from the power supply voltage V to the ground level, the sense node pair of the sense amplifier is disconnected from the bit line. When the basic operation of "erase" is entered after the basic operation of "latch", the signal CLMP has already been dropped to the ground level. At the same time, if the previous cycle was the basic operation of "data sense", the signal PRCH is dropped to the power supply voltage V dd , and the bit line is grounded. Also, if the previous cycle was the basic operation of "data sense", the selected word line is returned to the ground level. However, without returning it, the positive voltage V WLR or a positive programming voltage V WLW In this state, the plate line PLL0 corresponding to the selected word line WLL0 may be set to V PLH to a positive potential V PLE As a result, as explained in FIG. 3, holes are removed from the floating bodies of the selected memory cells, and the memory state of these cells becomes "0." This completes the basic operation of "erasing" the memory cells and sense amplifiers of the memory device using the semiconductor element of this embodiment.

[0033] Next, the basic operation of "programming" the memory cells and sense amplifiers of the memory device using the semiconductor device of this embodiment will be explained. The basic operation of "programming" is to change the memory state of the memory cells designated by the sense amplifiers among all the memory cells in the "0" memory state selected by the word lines to "1". In other words, it is a basic operation of injecting majority carrier holes into the floating body of the memory cell to increase the number of holes present there. The basic operation of "programming" starts when the basic operation of "latch" and the basic operation of "erase" are completed. First, the grounded bit line is made floating at 0V (signal PRCH is dropped to the ground level). At the same time, the word line is set to a positive programming voltage V WLW Then, activate the program signal PRGL on the cell array side to which the selected word line belongs, in this case the left side, to set the bit line to the program positive voltage V BLWHowever, this program circuit includes the latched voltage SNL j , SNL j+1 , SNR j , SNR j+1 is input, and the basic operation of "programming" is selectively performed depending on the voltage. The above is the basic operation of "programming" of the memory cells and sense amplifiers of the storage device using the semiconductor element of this embodiment.

[0034] Next, the basic operation of "reading from the sense amplifier" of the memory cell and sense amplifier of the memory device using the semiconductor device of this embodiment will be described. The basic operation of "reading from the sense amplifier" starts from the state where the basic operation of "latch" is completed. The column selection line CSL selected by the address j from the ground level to the power supply voltage V dd This causes the switch element SW1 j , SW2 j is turned on, and the selected sense amplifier S / A j Sense node vs. SNL j ,SNR j are connected to the common input / output line pair DQ and / DQ, respectively. j Sense node vs. SNL j and SNR j The latched information is transmitted to the common input / output line pair DQ and / DQ and read out to an external circuit. The above is the basic operation of "reading from the sense amplifier" of the memory cell and sense amplifier of the memory device using the semiconductor element of this embodiment.

[0035] Next, the basic operation of "writing to the sense amplifier" of the memory cell and sense amplifier of the memory device using the semiconductor device of this embodiment will be described. The basic operation of "writing to the sense amplifier" starts from the state where the basic operation of "latch" is completed. The column selection line CSL selected by the address j from the ground level to the power supply voltage V dd This causes the switch element SW1 j and SW2j is turned on, and the selected sense amplifier S / A j Sense node vs. SNL j and SNR j are connected to the common input / output line pair DQ and / DQ, respectively. At the same time, write data is input to the common input / output line pair DQ and / DQ by an external write circuit (not shown in Figure 4). The polarity of this data is j Sense node vs. SNL j and SNR j When the polarity of the sense node is opposite to that of the external circuit, the polarity of the sense node is inverted. j The sense amplifier S / A selected by j The above is the basic operation of "writing to the sense amplifier" of the memory cell and sense amplifier of the storage device using the semiconductor element of this embodiment.

[0036] A more specific circuit configuration of a memory cell and a sense amplifier of a memory device using the semiconductor device of this embodiment will be described with reference to FIG. 5. In FIG. 5, a sense amplifier circuit S / A j is TR1 j ~TR19 j The sense amplifier circuit S / A j+1 is TR1 j+1 ~TR19 j+1 In addition to these MOSFETs, S / A j The left sense node SNL j and S / A j+1 The left sense node SNL j+1 The TR20 is a MOSFET that electrically shorts the S / A j+1 The sense node SNR of the secondary side j+1 and S / A j+1 The right sense node SNR j+1 There is a MOSFET TR21 to electrically short-circuit between j ~TR5 j is the S / A in Figure 4 jThis corresponds to the current load circuit of TR1. j+1 ~TR5 j+1 is the S / A in Figure 4 j+1 In addition, in Figure 5, the n-type MOSFET TR6 j ~TR9 j is the S / A in Figure 4 j This corresponds to the latch circuit of the n-type MOSFET TR6 j+1 ~TR9 j+1 is the S / A in Figure 4 j+1 In addition, in Figure 5, the n-type MOSFET TR10 j ~TR13 j is the S / A in Figure 4 j This corresponds to the program circuit of TR10 of n-type MOSFET. j+1 ~TR13 j+1 is the S / A in Figure 4 j+1 In addition, in Figure 5, the n-type MOSFET TR14 j ~TR19 j is the S / A in Figure 4 j Switching element SW3 j , SW4 j , SW5 j , SW6 j , SW1 j , SW2 j and TR14 of n-type MOSFET. j+1 ~TR19 j+1 is the S / A in Figure 4 j+1 Switching element SW3 j+1 , SW4 j+1 , SW5 j+1 , SW6 j+1 , SW1 j+1 , SW2 j+1 Also, TR20 and TR21 of the n-type MOSFET in Figure 5 correspond to SW7 in Figure 4. j,j+1 , SW8 j,j+1and / LTC, respectively. Furthermore, the signal Read used to pass load current to the memory cell and dummy cell in Figure 4 has been changed to / Read in Figure 5 to indicate that it is activated when the signal is set low because it controls the gate of the p-type MOSFET. A similar change has been made to PRG1 and PRGR. Also, the signal LTC used to control the latch circuit in Figure 4 has been split into two signals in Figure 5: LTC for the p-type cross-coupled MOSFET and / LTC for the n-type cross-coupled MOSFET. Furthermore, the current load circuit is configured as a current mirror connection using p-type MOSFETs, but the current mirror connection must be reversed depending on whether the dummy cell is connected to the left or right sense node. To achieve this, the circuit configuration can be changed using the signals / CML and / CMR.

[0037] The basic operations of the memory cells and sense amplifiers of the memory device using the semiconductor element of this embodiment will be explained below with reference to more specific circuits using FIGS.

[0038] 5 and 6, the basic operation of "data sense" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be described. Of the MOSFETs shown in FIG. 5, the MOSFETs shown in black in FIG. 6 operate in relation to the basic operation of data sense. The state before operation begins is the standby state. In the standby state, / Read, PRCH, / LTC, / PRGL, / PRGR, DQ, and / DQ are all at the power supply voltage V dd Level, SNL j , SNR j , SNL j+1 , SNR j+1 , BLL j , B.L.R. j , BLL j;1 , B.L.R. j+1 , / CML, / CMR, CSL j , CSL j+1 , DCAVL, DCAVR, WLL0, WLR0, DWLL, and DWLR are all at ground level, and PLL0, PLR0, DPLL, and DPLR are all at a negative constant voltage V PLH CLMP is a positive constant voltage VCLMP The state is that SL is always at ground level. The basic operation of data sense will be explained with reference to FIG. 5. First, when the selected word line WLL0 is changed from the ground level to a positive voltage V WLR Here, it is assumed that the word line in the cell array on the left side of the sense amplifier is selected. As a result, in the range of FIG. 4, two memory cells CL j and CL j+1 is selected (although not shown in FIG. 10, all cells connected to the word line are selected). At the same time, the dummy word line DWLR on the right side of the sense amplifier is also raised from the ground level to a positive voltage V WLR As a result, in the range of FIG. 5, the two dummy cells DCR j and DCR j+1 is selected (actually, all dummy cells connected to the word line are selected, although not shown in FIG. 10). The dummy cells have the same structure as memory cells. However, unlike memory cells, they are written with a "1" or "0" state in advance. In this embodiment, the j-th bit line BLR j Dummy cell DCR connected to j The j+1th bit line BLR j+1 Dummy cell DCR connected to j+1 It is assumed that "0" is written to every other dummy cell. In other words, the opposite data is written to every other dummy cell. Here, the polarity of "1" and "0" can be reversed. After the dummy cell is selected, the DCAVR raises the power supply voltage V dd This causes the right sense node SNR corresponding to the two adjacent bit lines to rise to the j and SNR J+1 is electrically shorted by the MOSFET of TR21. This causes the sense node SNR j and SNR J+1 At the same time, as shown in Figure 5, / CML rises from the ground level to the power supply voltage level V ddThis will cause TR5 j and TR5 j+1 The MOSFET of TR4 remains on, but j and TR4 j+1 The MOSFET is turned off, and the current mirror circuit is connected to the right sense node SNR j and SNR J+1 The reference current is input to the / Read side. Then, the / Read is set to the power supply voltage V dd The current mirror circuit is supplied with the power supply voltage V dd Current is supplied from the sense node to the SNR j and SNL j Between and sense node vs. SNR j+1 and SNL j+1 The voltage signal develops between these two points. The above is the basic operation of "data sense" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment.

[0039] 5 and 7, the basic operation of the "latch" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be explained. Among the MOSFETs shown in FIG. 5, the MOSFETs shown in black in FIG. 7 operate in relation to the basic operation of the "latch". The state before the operation starts is the state at the end of the basic operation of the "data sense". That is, the sense node pair SNR j and SNL j Between and sense node vs. SNR j+1 and SNL j+1 The voltage signal between the MOSFETs TR6 and TR7 is shown in black in Figure 7. j , TR7 j , TR8 j , TR9 j and TR6 j+1 , TR7 j+1 , TR8 j+1 , TR9 j+1Generally, the voltage signal between the sense node and the SNR is large enough to properly perform the basic latch function. j and SNL j Between and sense node vs. SNR j+1 and SNL j+1 The LTC is then driven from the ground level to the power supply voltage V dd level, and / LTC rises to the power supply voltage V dd By lowering the sense node level to ground level, the SNR vs. sense node is improved in the basic operation of "Data Sense". j and SNL j Between and sense node vs. SNR j+1 and SNL j+1 The signal between the ground level and the power supply voltage V dd The signal between levels is amplified and latched. The above is the basic operation of the "latch" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment.

[0040] 5 and 8, the basic operation of "erase" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be explained. Among the MOSFETs shown in FIG. 5, the MOSFETs shown in black in FIG. 8 operate in relation to the basic operation of "erase". The state before starting the operation is the state at the end of the basic operation of "latch" or the standby state. In the basic operation of "erase", it is necessary that the bit line is separated from the sense amplifier. Therefore, CLMP is V CLMP The bit line must be set to ground, and PRCH must be set to the power supply voltage V dd As shown in Figure 8, with the word line pulled to ground, the plate line PLL0 must be raised to V PLH from a negative potential to a positive potential V PLE By raising the cell CL0 j , CL0 j+1In the description of this embodiment, two cells MCL0 in the cell array on the left side of the sense amplifier can be extracted. j , MCL0 j+1 Although only mention is made of the word line WLL0, in reality it is possible to simultaneously extract holes from the floating bodies of all memory cells along one word line in the cell array on the left side of the sense amplifier. The above is the basic operation of "erase" in the memory cells and sense amplifier circuit of the memory device using the semiconductor element of this embodiment. Note that it is assumed that the word line WLL0 is activated to a high voltage during the basic operation of "erase."

[0041] 5 and 9, the basic operation of "program" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be described. Among the MOSFETs shown in FIG. 5, the MOSFETs shown in black in FIG. 9 operate in relation to the basic operation of "program." The state before the operation starts is the state at the end of the basic operation of the latch, that is, the sense node pair SNR j and SNL j Between and sense node vs. SNR j+1 and SNL j+1 Between the power supply voltage V dd This is the point when the voltage signal at the ground level is latched and the basic operation of "erase" is completed. j is the ground level and SNL j is the power supply voltage V dd Similarly, the sense node vs. SNR j+1 is the power supply voltage V dd Level and SNL j+1 is assumed to be the ground level. The basic operation of "programming" is to set the word line WLL0 connected to the memory cell to be programmed to V WLWThe program starts by raising the value of the program signal / PRGL to the power supply voltage V. The basic operation of the latch must also continue during this basic program operation. In this situation, the program signal / PRGL on the cell array side where the word line is selected (in this explanation, the cell array side on the left side of the sense amplifier) ​​is raised to the power supply voltage V dd This reduces the TR10 j and TR10 j+1 On the other hand, based on the above assumption, the SNL j is the power supply voltage V dd At the Level, SNL j+1 is at ground level, so TR11 j is in the off state, and TR11 j+1 is in the ON state. Therefore, the bit line BLL j is memory cell MCL0 j The bit line BLL remains at ground level. j+1 is the power supply voltage V dd This causes the memory cell CL0 j No current flows through memory cell MCL0 j+1 is biased to a saturated state, impact ionization occurs, and holes are accumulated in its floating body. j+1 In this way, whether or not programming is performed depends on the latch state of the sense amplifier. The above is the basic operation of "programming" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment. Note that there are other programming methods possible, and the method described here is one example.

[0042] 5 and 10, the basic operation of "reading from the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be explained. Among the MOSFETs shown in FIG. 5, the MOSFETs shown in black in FIG. 10 operate in relation to the basic operation of "reading from the sense amplifier". The state before the operation starts is the state at the end of the basic operation of the latch. That is, the sense node pair SNRj and SNL j Between and sense node vs. SNR j+1 and SNL j+1 Between the power supply voltage V dd In this explanation, the sense node pair SNR j is the ground level and SNL j is the power supply voltage V dd Similarly, the sense node vs. SNR j+1 is the power supply voltage V dd Level and SNL j+1 is assumed to be at ground level. The basic operation of reading from the sense amplifier requires that the sense amplifier be isolated from the bit lines. Therefore, CLMP is V CLMP The voltage of the selected column select line CSL must be reduced to the ground level. j is the voltage V dd level, and beforehand, the power supply voltage V dd The common data input / output line pair DQ, / DQ precharged to a level and the selected sense amplifier S / A j Sense node vs. SNL j , SNR j Between R18 j , TR19 j This electrically shorts DQ to the power supply voltage V dd level, but / DQ remains at the supply voltage V dd Level to Low Voltage TR9 j Therefore, a voltage difference occurs between the common data input / output line pair DQ and / DQ. This voltage difference is amplified by an external circuit such as a secondary sense amplifier circuit (not shown in Figures 4 and 9), and the voltage difference is applied to the memory cell MCL0 j The above is the basic operation of "reading from the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment.

[0043] 5 and 11, the basic operation of "writing to the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment will be explained. Among the MOSFETs shown in FIG. 5, the MOSFETs shown in black in FIG. 11 operate in relation to the basic operation of writing to the sense amplifier. The state before the operation starts is the state at the end of the basic operation of the "latch". That is, the sense node pair SNR j and SNL j Between and sense node vs. SNR j+1 and SNL j+1 Between the power supply voltage V dd In this explanation, the sense node pair SNR j is the ground level and SNL j is the power supply voltage V dd Similarly, the sense node vs. SNR j+1 is the power supply voltage V dd Level and SNL j+1 is assumed to be at ground level. The basic operation of writing to the sense amplifier requires that the sense amplifier be isolated from the bit lines. Therefore, CLMP is V CLMP The voltage of the selected column select line CSL must be reduced to the ground level. j is the voltage V dd level, the common data input / output line pair DQ, / DQ and the selected sense amplifier S / A j Sense node vs. SNL j , SNR j Between R18 j , TR19 j In this state, DQ is connected to the ground level and / DQ is connected to the power supply voltage V dd 4 or 10, the latch circuit (TR6 j , TR7 j , TR8 j , TR9 j ) is the sense node SNR jis ground level and SNL j is the power supply voltage V dd From the latched state to the sense node SNR j is the power supply voltage V dd SNL at the Level j is inverted to the opposite state of being latched at the ground level. This executes the basic operation of writing to the sense amplifier. The above is the basic operation of "writing to the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using the semiconductor element of this embodiment.

[0044] The read operation of a memory device using the semiconductor element of this embodiment will be explained using Figure 12. This can be realized by combining some of the basic operations of the sense amplifier circuit of a memory device using the semiconductor element of this embodiment. The read operation of a memory device using the semiconductor element of this embodiment consists of three basic operations of the sense amplifier circuit of a memory device using the semiconductor element of this embodiment, namely "data sense", "latch" and "read from sense amplifier". First, the system moves from the standby state to the basic operation of "data sense". Then it enters the basic operation of "latch". When data is being latched, the CSL of that data j The sense amplifier S / A selected by j The data is read out to the outside via the common data line pair DQ and / DQ. In other words, the data is read out to the outside by "reading from the sense amplifier."

[0045] The write operation of a memory device using the semiconductor element of this embodiment will be explained using Figure 13. This can be realized by combining some of the basic operations of the sense amplifier circuit of a memory device using the semiconductor element of this embodiment. The write operation of a memory device using the semiconductor element of this embodiment consists of five basic operations of the sense amplifier circuit of a memory device using the semiconductor element of this embodiment, namely, the basic operations of "data sense", "latch", "write to sense amplifier", "erase" and "program". First, the process moves from the standby state to the basic operation of "data sense". Then, the basic operation of "latch" is entered. Up to this point, it is the same as the read operation of . Next, CLMP is set to V CLMP The voltage is dropped to the ground level to separate the sense amplifier and bit line, and the basic operation of "writing to the sense amplifier" is performed on the sense amplifier side, and at the same time, the holes accumulated in the floating bodies of all memory cells connected to the selected word line are erased. In other words, the basic operation of "erase" is performed. After that, while keeping both separated, the basic operation of "program" is performed on the memory cells based on the data written to the sense amplifier. During the basic operation of "erase", the word line activated during the basic operation of "data sense" is supplied with the voltage V WLR The voltage V WLW It doesn't matter if it's either of the above.

[0046] The refresh operation of a memory device using the semiconductor element of this embodiment will be explained using FIG. 14. This can be realized by combining some of the basic operations of the sense amplifier circuit of a memory device using the semiconductor element of this embodiment. The refresh operation of a memory device using the semiconductor element of this embodiment consists of four basic operations of the sense amplifier circuit of a memory device using the semiconductor element of this embodiment, namely, the basic operations of "data sense", "latch", "erase" and "program". First, the device moves from the standby state to the basic operation of "data sense". Then, the device enters the basic operation of "latch". Up to this point, the operation is the same as the read operation. Next, CLMP is set to V CLMPThe voltage is dropped to ground to disconnect the sense amplifier from the bit line, erasing the holes stored in the floating bodies of all memory cells connected to the selected word line (basic "erase" operation). Then, with the two still disconnected, the basic "program" operation is performed on the memory cells based on the data latched in the sense amplifier. The refresh operation of this memory device using the semiconductor element of this embodiment is the same as the write operation of the memory device using the semiconductor element of this embodiment, except that it does not include the basic operation of "writing to the sense amplifier" in the sense amplifier circuit of the memory device using the semiconductor element of this embodiment.

[0047] Another more specific circuit configuration of the memory cell and sense amplifier of the memory device using the semiconductor device of this embodiment will be described using FIG. 15. This corresponds to a specific example of a sense amplifier in which the current load circuit block and latch circuit block in FIG. 4 are merged. When / Read becomes the ground level, current begins to flow through the memory cell and dummy cell. At this time, the signal / Release is still at the power supply voltage V dd level, and the sense node SNL j , SNL j , SNL j+1 , SNR j+1 are both at the same level (0V and V dd Then, when the signal / Release is dropped to the ground level, a positive feedback acts between the cross-coupled inverters, and the sense node vs. SNL j , SNL j and SNL j+1 , SNR j+1 A potential difference develops between them and the data is latched. Other basic operations such as "erase," "program," "read from the sense amplifier," and "write to the sense amplifier" are the same as those in Figure 4.

[0048] FIG. 16 illustrates a plate line PL driver circuit for a 1-Mbit (1024 × 1024-bit) memory device using the semiconductor device of this embodiment. The PL that is activated during data erasure is the plate line PL associated with the selected word line WL. Therefore, it is sufficient for the word line WL driver circuit to be selected and driven by the same row decoder. However, this row decoder is the same circuit as the row decoder for word line WL drive selection, resulting in wasted circuit area. Therefore, as shown in FIG. 16, by using the word line WL itself as the selection signal, circuit duplication can be avoided. That is, as shown in FIG. 16, a more compact memory device can be achieved by driving the plate line PL using the logical product of the word line WL and the signal PDRV, which determines the timing for raising the plate line PL during data erasure. Of course, since the word line voltage and the plate line voltage are generally different, a voltage conversion circuit is required between the word line input and the plate line PL driver circuit, but this is omitted in FIG. 16. Also, in FIG. 16, the dummy word lines and the dummy cells connected thereto, the selection circuits and drive circuits for the dummy word lines, and the plate lines of the dummy cells and their selection circuits and drive circuits are omitted.

[0049] The device structure of a memory element in a storage device using the semiconductor element of this embodiment will be described using Figures 17A to 17F. Figure 17A shows a plan view of the cell structure of a storage device using the semiconductor element of this embodiment. This figure shows six memory cell regions corresponding to three word lines and two bit lines in a cell array in which memory elements are arranged in a matrix. These correspond to the six memory cells whose equivalent circuits are shown in the array on the left or right side of the sense amplifier in Figure 1. Figure 17B shows a cross-sectional view taken along line AA' in the plan view of Figure 17A. Figure 17C shows a cross-sectional view taken along line BB' in the plan view of Figure 17A. Figure 17D shows a cross-sectional view taken along line CC' in the plan view of Figure 17A. Figure 17E shows a cross-sectional view taken along line DD' in the plan view of Figure 17A. Figure 17F shows a cross-sectional view taken along line EE' in the plan view of Figure 17A.

[0050] As can be seen from Figures 17A, 17B, and 17E, first semiconductor regions 8 (an example of a semiconductor body in the claims) corresponding to each memory cell are arranged in a two-dimensional array on a p-type silicon substrate 14 (an example of a substrate in the claims) and a second semiconductor region 10 made of n-type silicon located thereon. Impurity atoms (e.g., boron atoms) are ion-implanted into this first semiconductor region 8 to convert it to p-type silicon. Then, n-type first impurity regions 9 (an example of one of the n-type second impurity regions in the claims) and 19 (an example of the other of the n-type second impurity regions in the claims) are arranged on both sides of the first semiconductor region 8 in the left-right direction of Figure 1, in contact with the upper part of this first semiconductor region 8. To convert it to n-type silicon, for example, phosphorus atoms can be ion-implanted.

[0051] 17A to 17F, a second gate conductor layer (plate line) 3 runs in the vertical direction of Fig. 17A so as to cover the semiconductor region 8, and these are separated by a thin gate insulating film 15 (the gate insulating film in the claims is one example). The region below the top surface of the n-type first semiconductor region 9 and above the n-type third semiconductor region 10 is buried with a first insulating layer 11, except for the first semiconductor region 8, the second gate conductor layer (plate line) 3, and the gate insulating film 15 between them.

[0052] 17A and 17B, a first gate conductor layer (word line) 1 runs vertically in FIG. 17 on top of the first semiconductor layer 8, sandwiching a gate insulating film 15 therebetween, forming an n-type metal oxide semiconductor field effect transistor (MOSFET) with n-type second semiconductor regions 9 and 19 as the source or drain, the first semiconductor region 8 as the body, and the first gate conductor layer as the gate. As described above, the gate insulating film 15 is disposed on the top (upper surface) of the first semiconductor layer 8 and functions to electrically insulate the top of the first semiconductor layer 8 from the first gate conductor layer (word line) 1, and is also disposed so as to cover the side surfaces of the semiconductor region 8 and functions to electrically insulate the second gate conductor layer (plate line) 3 from the semiconductor region 8. These gate insulating films 15 may be disposed as a continuous, integrated film on the side surfaces and top (upper surface) of the first semiconductor layer 8, or may be disposed separately. One of the source or drain is connected to a first metal wiring layer (source line) 4 via a contact hole 6, and the first metal wiring layer (source line) 4 runs vertically in FIG. 17A. Meanwhile, the other of the source or drain is connected to a second metal wiring layer (bit line) via a contact hole 6, a buffer layer 5 made of the same layer as the first metal wiring layer, and a via 7, and the second metal wiring layer (bit line) runs horizontally in FIG. 17A. The area below the top surface of the second metal wiring layer (bit line) and above the top surface of the n-type second semiconductor region is filled with a second insulating layer 12, except for the first gate conductor layer (word line) 1 and the underlying gate insulating film 15, contact hole 6, first metal wiring layer (source line), buffer layer 5, via 7, and second metal wiring layer (bit line). The area above the top surface of the second metal wiring layer (bit line) is covered with a third insulating layer 13.

[0053] The first embodiment of the present invention has the following features.

[0054] (Feature 1) As explained with reference to FIG. 4, in a memory device using a semiconductor element according to the first embodiment of the present invention, plate lines are separated for each word line and run parallel to the word lines, allowing holes to be discharged from the floating bodies of all memory cells along a selected word line. Despite this non-selective erase operation, the memory device according to this embodiment is capable of performing random write and refresh operations. The advantage of this non-selective erase is that it eliminates the need to set the word lines to a negative potential. This means that it is possible to alleviate the problem of "1" disturbance on bit lines, improving the data retention characteristics of cells.

[0055] (Feature 2) As explained using Figure 4, the basic operation of erasing a memory cell and the basic operation of writing to the sense amplifier can be performed simultaneously in parallel while the sense amplifier and bit line are disconnected, thereby shortening the cycle time of the write operation.

[0056] (Feature 3) 16, in a memory device using the semiconductor element according to the first embodiment of the present invention, the plate line driver circuit can be arranged on the opposite side of the cell array from the word line driver circuit, thereby realizing a semiconductor memory device with a small chip area.

[0057] (Second embodiment) The structure of a memory device using the semiconductor element of this embodiment will be described with reference to Figures 18A to 18F and Figure 19. Figure 18A shows a plan view of the cell structure of a memory device using the semiconductor element of this embodiment. Figure 18B shows a cross-sectional view taken along line AA' in the plan view of Figure 18A. Figure 18C shows a cross-sectional view taken along line BB' in the plan view of Figure 18A. Figure 18D shows a cross-sectional view taken along line CC' in the plan view of Figure 18A. Figure 18E shows a cross-sectional view taken along line DD' in the plan view of Figure 18A. Figure 18F shows a cross-sectional view taken along line EE' in the plan view of Figure 18A. Figure 19 shows a cell array equivalent circuit of a memory device using the semiconductor element of this embodiment.

[0058] The cell structure of the memory device using the semiconductor element of this embodiment shown in Figures 18A to 18F is the same as the cell structure of the memory device using the semiconductor element of the first embodiment, except for the structure of the second gate insulating layer (plate line) 3. In the cell structure of the memory device using the semiconductor element of the first embodiment shown in Figures 17A to 17F, the second gate insulating layer (plate line) 3 is arranged separately for each first gate conductor layer (word line) 1, but in the cell structure of the memory device using the semiconductor element of this embodiment shown in Figures 18A to 18F, the second gate insulating layer (plate line) 3 is arranged separately for each two adjacent first gate conductor layers (word lines) 1. Except for this difference, the cell structure of the memory device using the semiconductor element of this embodiment is the same as the cell structure of the memory device using the semiconductor element of the first embodiment.

[0059] 19 shows an equivalent circuit of a cell array of a memory device using the semiconductor device of this embodiment and the relationship between the cell array and a sense amplifier circuit. In FIG. 19, two adjacent bit lines BL j and B.L. j+1 Sense amplifier S / AL j , S / AR j and S / AL j+1 , S / AR j+1 Also, to the left of the left sense amplifier, a dummy bit line DBLL is placed. j , DBLL j+1 are arranged, and in them are dummy cells DCL selected by a dummy word line DWLL and driven by a dummy plate line DPLL. j , D.C.L. j+1 Similarly, a dummy bit line DBLR is connected to the right of the right sense amplifier. j , DBLR j+1 are arranged, and in them are dummy cells DCR selected by a dummy word line DWLR and driven by a dummy plate line DPLR. j , D.C.R. j+1 The sense amplifier circuit itself is the same as that shown in Figure 4 or Figure 5. However, TR4 j, TR5 j , TR4 j+1 , TR5 j+1 is no longer necessary, and TR2 j and TR3 j or TR2 j+1 , TR3 j+1 The common gate node of the SNL j Or SNR j or SNL j+1 Or SNR j+1 Specifically, the left sense amplifier is connected to SNL, and the right sense amplifier is connected to SNR. Also, only one of the transistors TR20 and TR21 shown in Figure 5 is required. Specifically, TR21 is not required for the left sense amplifier, and TR20 is not required for the right sense amplifier.

[0060] The basic operation of each sense amplifier for data sensing and latching is as follows: If an odd-numbered word line is selected, the data stored in the cell connected to it is sent to the left sense amplifier S / AL j and S / AL j+1 In this case, the DWLL is activated and the dummy cell DCL j and DCL j+1 Data is read from the dummy cell DCL j and DCL j+1 The data stored in S / AL are opposite to each other, and are controlled by transistors not shown in FIG. j and S / AL j+1 By electrically shorting the left sense node of the "1" data cell and the "0" data cell, a current flows through these nodes that is the middle of the current flowing through the "1" data cell and the current flowing through the "0" data cell. By referring to these currents, the data of the memory cell selected by the odd-numbered word line mentioned above is sensed. Subsequently, the even-numbered word line that shares the source line with the selected word line is activated, and the data stored in the cell connected to it is sent to the right sense amplifier S / AR j and S / AR j+1In this case, the DWLR is activated and the dummy cell DCR j and DCR j+1 Data is read from the dummy cell DCR. j and DCR j+1 The data stored in the S / AR are opposite to each other, and are controlled by transistors not shown in FIG. j and S / AR j+1 When the left sense node is electrically shorted, a current flows through these nodes that is midway between the current flowing through the "1" data cell and the current flowing through the "0" data cell. The data of the memory cell selected by the even-numbered word line described above is sensed by referring to these currents. When an even-numbered word line is selected, the same process can be performed by reversing the order of the above explanation.

[0061] The basic operation of the program is to activate the odd-numbered word line and j and S / AL j+1 The program is performed based on the state latched in the S / AR register. j and S / AR j+1 The EEPROM is programmed based on the state latched in the EEPROM.

[0062] The basic operation of erasing is to apply a positive voltage V to the plate line that is commonly connected to the odd-numbered and even-numbered word lines. PLE to drain holes from the floating bodies of all memory cells selected by these two word lines.

[0063] When the column select line CSLj or CLSj+1 is activated, the S / AL j and S / AR j Or S / AL j+1 and S / AR j+1 After the address is selected, S / AL is selected depending on whether the WL selected by the address is odd or even. j and S / AR j Or S / ALj+1 and S / AR j+1 Data is read out from the sense amplifiers onto the common data line pair DQ and / DQ.

[0064] Writing to the sense amplifier is performed by activating the column selection line CSLj or CLSj+1. j and S / AR j Or S / AL j+1 and S / AR j+1 After the address is selected, S / AL is selected depending on whether the WL selected by the address is odd or even. j and S / AR j Or S / AL j+1 and S / AR j+1 Data is written to the sense amplifiers from the common data line pair DQ and / DQ.

[0065] The read operation, write operation and refresh operation of the memory device using the semiconductor element of this embodiment are similarly performed using basic operations, and therefore detailed explanations will be omitted here.

[0066] In Figures 18A to 18F and Figure 19, a plate line (PL) is shared between two memory cells that share a source line SL, but the plate line (PL) may also be shared between two memory cells that share a bit line BL.

[0067] The second embodiment of the present invention has the following features.

[0068] (Feature 1) In a memory device using a semiconductor element according to the second embodiment of the present invention, plate lines are separated for every two word lines and run parallel to the word lines, allowing holes to be discharged from the floating bodies of all memory cells along a selected word line and its adjacent word lines. This makes it possible to perform read, write, and refresh operations. By adopting this structure, the memory device using the semiconductor element according to the second embodiment of the present invention can reduce the distance between two cells along a bit line compared to the first embodiment, making it possible to provide a semiconductor memory device with reduced bit cost.

[0069] (Feature 2) In a memory device using the semiconductor element according to the second embodiment of the present invention, the positional relationship between the dummy cells and the sense node pairs is predetermined, eliminating the need for transistors to switch the current mirror connection of the sense amplifier, and in the circuit that averages the cell current to generate a reference current, the dummy cell side is fixed relative to the sense amplifier, eliminating the need for one of the averaging circuits. In this way, the size of the sense amplifier circuit can be made smaller than that of the first embodiment, making it possible to provide a semiconductor memory device that achieves further bit cost reduction. [Industrial Applicability]

[0070] According to the present invention, it is possible to provide a semiconductor memory device that is denser, faster, and has a wider operating margin than conventional devices. [Explanation of symbols]

[0071] (Figure 1) S / A j , S / A j+1 : Sense amplifier circuit BLL j , BLL j+1 , B.L.R. j , B.L.R. j+1 :Bit line SL: Source line WLL i , W.L.L. i+1, W.L.L. i+2 , W.L.R. i , W.L.R. i+1 , W.L.R. i+2 : Word line MCL i, j , MCR i, j : Memory cell (Figure 4) MCL0 j , MCL0 j+1 , MCR0 j , MCR0 j+1 : Memory cell DCL j , D.C.L. j+1 , D.C.R. j , D.C.R. j+1 : Dummy cell SNL j , SNL j+1 , SNR j , SNR j+1 : Sense Node SW1 j ~SW6 j : Switching circuit SW1 j+1 ~SW6 j+1 : Switching circuit SW7 j, j+1 , SW8 j, j+1 : Switching circuit CSL j , CSL j+1 : Column selection line (Figure 5) TR1 j ~TR7 j , TR10 j ~TR13 j : p-type MOSFET TR8 j , TR9 j , TR14 j ~TR19 j : n-type MOSFET TR1 j+1 ~TR7 j+1 , TR10 j+1 ~TR13 j+1 : p-type MOSFET TR8j+1 , TR9 j+1 , TR14 j+1 ~TR19 j+1 : n-type MOSFET TR20, TR21: n-type MOSFET (Figure 15) TR20 j , TR21 j , TR24 j : p-type MOSFET TR22 j , TR23 j , TR25 j ~TR28 j :n-type MOSFET TR20 j+1 , TR21 j+1 , TR24 j+1 : p-type MOSFET TR22 j+1 , TR23 j+1 , TR25 j+1 ~TR28 j+1 :n-type MOSFET (Figure 16) Cell array: Memory cell array MC ij (i=0~1023, j=0~1023): Memory cell BL0~BL 1023 :Bit line WL0~WL 1023 : Word line PL0~PL 1023 : Plate line A 0R ~A 9R , / A 0R ~ / A 9R : Low Address A 0C ~A 9C , / A 0C ~ / A 9C :Column address Row decoder WL drivers: Word line driver circuits Column decoder: Column decoder CSL drivers: Column select line (CSL) driver circuit PL decoder: Plate line decoder PL drivers: Plate line driver circuits Sense amp.: Sense amplifier (Figure 17) 1: First gate conductor layer (word line) 2: Second metal wiring layer (bit line) 3: Second gate conductor layer (plate line) 4: First metal wiring layer (source line) 5: Buffer layer (same layer as the first metal wiring layer) 6: Contact hole (for connecting the silicon layer to the first metal wiring layer) 7: Via (for connection between the first and second metal wiring layers) 8: First semiconductor region 9: Second semiconductor region (source line side) 10: The third semiconductor region 11: First insulating layer 12: Second insulating layer 13: Third insulating layer 14: Circuit board 15: Gate insulating layer 19: Second semiconductor region (bit line side)

Claims

1. a page is configured on a substrate by a plurality of memory cells arranged in a first direction in a plan view; Each of the memory cells comprises an electrically floating semiconductor body; a first impurity region in contact with one side of the semiconductor body and connected to a source line; and a second impurity region in contact with the other side of the semiconductor body and connected to a bit line; a gate insulating film in contact with the semiconductor substrate; a first gate conductor layer that forms a transistor together with the semiconductor body, the first impurity region, and the second impurity region, the first gate conductor layer being in contact with the gate insulating film and connected to a word line; a second gate conductor layer that is in contact with the gate insulating film at a position different from that of the first gate conductor layer and that is connected to a plate line; a sense amplifier circuit that amplifies and latches a signal read from the memory cell connected to the bit line via a first switching circuit; a data line connected to the sense amplifier circuit via a second switching circuit; A semiconductor memory device characterized in that, during writing, the word line is activated to amplify and latch the signal stored in the memory cell by turning on the first switching circuit, and then the first switching circuit is turned off, the plate line is selected to erase the memory cell, and at the same time, the second switching circuit is turned on to input data from the data line to the sense amplifier circuit, changing the latch state of the sense amplifier circuit, and then the memory cell is programmed according to the latch state of the sense amplifier circuit.

2. During refresh, the word line is activated to turn on the first switching circuit, and the data stored in the memory cell is amplified and latched by the sense amplifier circuit. turning off the first switching circuit and selecting the plate line to erase the memory cell; 2. The semiconductor memory device according to claim 1, wherein the memory cells are then programmed in accordance with the latch state of the sense amplifier circuit.

3. a word line driving circuit connected to one end of the word line extending in the first direction is selectively activated by a row address selecting circuit, in a plan view; a plate line driving circuit connected to one end of the plate line is located in an opposite direction to the word line driving circuit with respect to the first direction; 2. The semiconductor memory device according to claim 1, wherein said plate line driving circuit is selectively activated by said word line.

4. The sense amplifier circuit a first sense node separated from the first bit line via a first switching element; the second sense node being separated via a second switching element from another second bit line that is on the opposite side of the first bit line with respect to the sense amplifier or that is adjacent to the first bit line; a current load circuit for causing a current to flow to the first and second bit lines via the first and second sense nodes and the first and second switching elements; a latch circuit that amplifies and latches the potential difference between the first and second sense nodes; a first program circuit that applies a voltage to the first bit line; a second program circuit that applies a voltage to the second bit line; a third switching element for dropping the first bit line to ground potential; a fourth switching element for dropping the second bit line to ground potential; a fifth switching element connecting the first sense node to one of the common data lines; a sixth switching element connecting the second sense node to the other of the common data lines; 2. The semiconductor memory device according to claim 1, further comprising:

5. 5. The semiconductor memory device according to claim 4, wherein the current load circuit and the latch circuit are the same circuit.

6. In addition to the sense amplifier circuit, There is a second sense amplifier, the second sense amplifier a third sense node separated from the third bit line via a seventh switching element; a fourth sense node separated from another fourth bit line on the opposite side of the third bit line with respect to the second sense amplifier or adjacent to the third bit line via an eighth switching element; a current load circuit that causes a current to flow to the third and fourth bit lines via the third and fourth sense nodes and the seventh and eighth switching elements; a latch circuit that amplifies and latches the potential difference between the third and fourth sense nodes; a third program circuit that applies a voltage to the third bit line; a fourth program circuit that applies a voltage to the fourth bit line; a ninth switching element that drops the third bit line to ground potential; a tenth switching element that drops the fourth bit line to ground potential; an eleventh switching element connecting the third sense node to one of the common data lines; a twelfth switching element connecting the fourth sense node to the other of the common data lines; The first sense node of the sense amplifier circuit and the third sense node of the second sense amplifier are electrically short-circuited by a thirteenth switching circuit. Alternatively, the semiconductor memory device according to claim 4, wherein the third sense node of the second sense amplifier and the fourth sense node of the second sense amplifier are electrically short-circuited by a fourteenth switch circuit.

7. a first dummy cell having the same structure as the memory cell is connected to the first bit line and a first dummy word line; a second dummy cell having the same structure as the memory cell is connected to the second bit line and a second dummy word line; a third dummy cell having the same structure as the memory cell is connected to the third bit line and a first dummy word line; a fourth dummy cell having the same structure as the memory cell is connected to the fourth bit line and a second dummy word line; the states stored in the first dummy cell and the third dummy cell are opposite to each other; 7. The semiconductor memory device according to claim 6, wherein the states stored in said second dummy cell and said fourth dummy cell are reversed.

8. the semiconductor body is a first semiconductor region of a first conductivity type that extends vertically in a columnar shape from the surface of the substrate and is in an electrically floating state; the first gate conductor layer is connected to an upper surface of the first semiconductor region via a gate insulating film; the second gate conductor layer is connected to the pillar portion of the first semiconductor region via the gate insulating film; the first impurity region and the second impurity region are second semiconductor regions of a second conductivity type that are in contact with upper side surfaces of the first semiconductor region and are located on both sides of the first semiconductor region in a horizontal direction, 2. The semiconductor memory device according to claim 1, wherein a source line is connected as a first metal wiring layer to the second semiconductor region corresponding to the first impurity region, a bit line is connected as a second metal wiring layer to the second semiconductor region corresponding to the second impurity region, a word line is connected to the first gate conductor layer, and a plate line is connected to the second gate conductor layer, and the plate lines are separated for each word line and wired parallel to the word lines.

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