Semiconductor memory device

Abstract

To reduce manufacturing cost.SOLUTION: According to the embodiment, the semiconductor memory device includes the stacked body in which the plurality of wiring layers 34 and the plurality of insulating layers 35 are alternately stacked one by one, the memory pillar MP passing through the stacked body, and the first member SLT dividing the stacked body. The plurality of insulating layers include a first insulating layer. The plurality of interconnection layers include a first interconnection layer WL2 and a second interconnection layer WL3 provided on the first insulating layer. The memory pillar includes a first sub-pillar passing through the first wiring layer and having an upper end located between the first wiring layer and the second wiring layer, and a second sub-pillar provided on the first sub-pillar and passing through the second wiring layer. The first member includes a first portion LSLT passing through the first wiring layer and the second wiring layer and having an upper end located above the second wiring layer, and a second portion USLT provided on the first portion.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] A three-dimensional stacked NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0071864 [Patent Document 2] US Patent Application Publication No. 2022 / 0415909 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a semiconductor memory device that can reduce manufacturing costs. [Means for solving the problem]

[0005] A semiconductor memory device according to the embodiment includes a stacked body in which multiple wiring layers and multiple insulating layers are alternately stacked in a first direction, a memory pillar extending in the first direction and passing through the stacked body, and a first member extending in the first direction and a second direction intersecting the first direction and dividing the stacked body in a third direction intersecting the first direction and the second direction. The multiple insulating layers include a first insulating layer. The multiple wiring layers include a first wiring layer on which the first insulating layer is provided, and a second wiring layer provided on the first insulating layer. The memory pillar includes a first subpillar extending in the first direction and passing through the first wiring layer, with an upper end located between the first wiring layer and the second wiring layer, and a second subpillar provided on the first subpillar, extending in the first direction, and passing through the second wiring layer. The first member includes a first portion that extends in the first direction and the second direction, passes through the first wiring layer and the second wiring layer, and has an upper end located above the second wiring layer, and a second portion that is provided on the first portion and extends in the first direction and the second direction within the laminate. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 1 is a plan view showing an example of a memory cell array included in a semiconductor memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a connection region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view of the memory cell region taken along line A1-A2 in FIG. 4. [Figure 6] 6 is a cross-sectional view of the memory pillar in the XY plane along the line C1-C2 in FIG. 5. [Figure 7] 5 is a cross-sectional view of the connection region taken along line B1-B2 in FIG. 4. [Figure 8] 3A and 3B are conceptual diagrams showing boundaries between memory pillars, members SLT, and support pillars in the semiconductor memory device according to the first embodiment and the comparative example. [Figure 9] 4 is a flowchart showing an example of a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 10] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 11] 11A and 11B are cross-sectional views taken along lines A1-A2 and B1-B2 in FIG. [Figure 12] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 13] 13 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 12. [Figure 14] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 15] 15 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 14. [Figure 16] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 17] 17A and 17B are cross-sectional views taken along lines A1-A2 and B1-B2 in FIG. 16. [Figure 18] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 19] 19 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 18. [Figure 20] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 21] 21 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 20. [Figure 22] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 23] 23 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 22. [Figure 24] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 25] 25 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 24. [Figure 26] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 27] 27 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 26. [Figure 28] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 29] 29 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 28. [Figure 30] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 31] 31 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 30. [Figure 32] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 33] 33 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 32. [Figure 34] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 35] 35 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 34. [Figure 36] 3A and 3B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 37]37 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 36. [Figure 38] FIG. 10 is a cross-sectional view showing an example of a cross-sectional configuration of a memory cell region in a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 39] FIG. 10 is a cross-sectional view showing an example of a cross-sectional configuration of a connection region in a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 40] 10A and 10B are conceptual diagrams showing boundaries between memory pillars, members SLT, and support pillars in the semiconductor memory device according to the second embodiment and the comparative example. [Figure 41] 10 is a flowchart showing an example of a manufacturing process of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 42] 10 is a flowchart showing an example of a manufacturing process of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 43] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 44] 44 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 43. [Figure 45] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 46] 46 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 45. [Figure 47] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 48] 48 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 47. [Figure 49] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 50] 49A and 49B are cross-sectional views taken along lines A1-A2 and B1-B2 in FIG. [Figure 51]10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 52] 52 is a cross-sectional view taken along the lines A1-A2 and B1-B2 in FIG. 51. [Figure 53] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 54] 54 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 53. [Figure 55] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 56] 56 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 55. [Figure 57] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 58] 58 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 57. [Figure 59] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 60] 59A and 59B are cross-sectional views taken along lines A1-A2 and B1-B2 in FIG. [Figure 61] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 62] 62 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 61. [Figure 63] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 64] 64 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 63. [Figure 65]10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 66] Cross-sectional views along lines A1-A2 and B1-B2 in Figure 65. [Figure 67] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 68] Cross-sectional views along lines A1-A2 and B1-B2 in Figure 67. [Figure 69] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 70] Cross-sectional views along lines A1-A2 and B1-B2 in Figure 69. [Figure 71] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 72] 72 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 71. [Figure 73] 10A and 10B are diagrams showing an example of a planar layout of a memory cell array in a manufacturing process of the memory cell array included in the semiconductor memory device according to the second embodiment. [Figure 74] 74 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 73. [Figure 75] FIG. 11 is a plan view showing an example of a planar layout of a connection region of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 76] 76 is a cross-sectional view of the connection region taken along line B1-B2 of FIG. 75. [Figure 77] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 78] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 79]10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 80] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 81] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 82] FIG. 13 is a diagram showing an example of a cross-sectional configuration of a memory cell region of a memory cell array included in a semiconductor memory device according to a first modification of the third embodiment. [Figure 83] FIG. 13 is a diagram showing an example of a cross-sectional configuration of a connection region of a memory cell array included in a semiconductor memory device according to a first modification of the third embodiment. [Figure 84] FIG. 13 is a diagram showing an example of a cross-sectional configuration of a memory cell region of a memory cell array included in a semiconductor memory device according to a second modification of the third embodiment. [Figure 85] FIG. 13 is a diagram showing an example of a cross-sectional configuration of a connection region of a memory cell array included in a semiconductor memory device according to a second modification of the third embodiment. [Figure 86] FIG. 10 is a plan view showing an example of a planar layout of a connection region of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 87] 87 is a cross-sectional view of the connection region taken along line B1-B2 of FIG. 86. [Figure 88] 10A and 10B are conceptual diagrams showing the boundaries between support pillars and contact plugs in the semiconductor memory device according to the fourth embodiment and the comparative example. [Figure 89] 10 is a flowchart showing an example of a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 90] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 91] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 92]10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 93] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 94] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 95] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 96] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 97] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 98] 10A and 10B are diagrams showing an example of a cross-sectional configuration of a connection region in a manufacturing process of a memory cell array included in a semiconductor memory device according to a fourth embodiment. [Figure 99] FIG. 10 is a cross-sectional view of a memory cell array included in a semiconductor memory device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numeral. Furthermore, when multiple components having the same reference numeral are to be distinguished from one another, a subscript will be added to the common reference numeral. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference numeral, without a subscript. Here, subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase letters added to the end of a reference numeral, and indexes indicating an array.

[0008] 1. First embodiment First, a description will be given of a semiconductor memory device according to the first embodiment. In the following, a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked three-dimensionally on a semiconductor substrate will be taken as an example of the semiconductor memory device.

[0009] 1.1 Configuration 1.1.1 Overall configuration of semiconductor memory device First, an example of the overall configuration of a semiconductor memory device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. Note that in Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to these.

[0010] As shown in FIG. 1, the semiconductor memory device 1 includes a memory core unit 10 and a peripheral circuit unit 20.

[0011] The memory core unit 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.

[0012] The memory cell array 11 is an area in which nonvolatile memory cell transistors (hereinafter also referred to as "memory cells") are arranged three-dimensionally. The memory cell array 11 includes multiple blocks BLK. In the example shown in FIG. 1, the memory cell array 11 includes blocks BLK0 to BLK3. The block BLK is, for example, a collection of multiple memory cell transistors from which data is erased collectively. The block BLK includes multiple memory cell transistors associated with rows and columns. Each block BLK includes one or more string units SU. In the example shown in FIG. 1, the block BLK includes six string units SU0, SU1, SU2, SU3, SU4, and SU5. The string unit SU includes, for example, a collection of multiple NAND strings NS selected collectively in a write operation or a read operation. The NAND string NS includes a collection of multiple memory cell transistors connected in series. The number of blocks BLK in the memory cell array 11 and the number of string units SU in each block BLK are arbitrary. Details of the memory cell array 11 will be described later.

[0013] The row decoder 12 is a circuit that decodes row addresses. The row decoder 12 receives information about row addresses input from an external controller (not shown). The row decoder 12 selects row-direction wiring (word lines and select gate lines) in the memory cell array 11 based on the decoded results of the information about the row addresses. The row decoder 12 supplies a voltage to the selected row-direction wiring.

[0014] The sense amplifier 13 is a circuit that writes and reads data. When reading data, the sense amplifier 13 reads data from any string unit SU in any block BLK. When writing data, the sense amplifier 13 supplies a voltage based on the write data to the memory cell array 11.

[0015] The peripheral circuit section 20 includes a sequencer 21 and a voltage generating circuit 22 .

[0016] The sequencer 21 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generating circuit 22, the row decoder 12, the sense amplifier 13, etc. during write, read, and erase operations.

[0017] The voltage generating circuit 22 generates voltages used in the write operation, read operation, and erase operation, and supplies them to the row decoder 12, the sense amplifier 13, and the like.

[0018] 1.1.2 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 11 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of the memory cell array 11. Note that the example shown in Fig. 2 shows the circuit configuration of one block BLK.

[0019] As shown in FIG. 2, the string unit SU includes a plurality of NAND strings NS.

[0020] The NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example shown in Fig. 2, the NAND string NS includes ten memory cell transistors MC0 to MC9. The number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0021] The memory cell transistor MC is a memory element that stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage film. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type. The MONOS type uses an insulating film for the charge storage film. The FG type uses a conductor for the charge storage film. The following describes the case where the memory cell transistor MC is a MONOS type.

[0022] The select transistors ST1 and ST2 are switching elements. The select transistors ST1 and ST2 are used to select the string units SU during various operations. The number of select transistors ST1 and ST2 included in the NAND string NS is arbitrary. It is sufficient that the NAND string NS includes one or more select transistors ST1 and ST2.

[0023] The current paths of the select transistor ST2, memory cell transistors MC0 to MC9, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0024] The control gates of memory cell transistors MC0 to MC9 in the same block BLK are connected to word lines WL0 to WL9, respectively. More specifically, for example, block BLK includes six string units SU0 to SU5. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for memory cell transistors MC1 to MC9.

[0025] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. The gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3. The gates of the multiple select transistors ST1 in the string unit SU4 are commonly connected to a select gate line SGD4. The gates of the multiple select transistors ST1 in the string unit SU5 are commonly connected to a select gate line SGD5.

[0026] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Note that, similar to the select gate lines SGD, a different select gate line SGS may be provided for each string unit SU.

[0027] The word lines WL0 to WL9, the select gate lines SGD0 to SGD5, and the select gate line SGS are connected to a row decoder 12, respectively.

[0028] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. In the example shown in FIG. 2, m+1 (m is an integer equal to or greater than 0) bit lines BL0 to BLm are provided. The m+1 NAND strings NS in each string unit SU are connected to the bit lines BL0 to BLm, respectively. The same column address is assigned to the multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 13.

[0029] The source line SL is shared among, for example, a plurality of blocks BLK.

[0030] A set of multiple memory cell transistors MC connected to a common word line WL in one string unit SU is referred to as, for example, a “cell unit CU.” For example, write operations and read operations are performed in units of cell units CU.

[0031] 1.1.3 Planar layout of memory cell array Next, an example of a planar layout of the memory cell array 11 will be described with reference to FIG. 3. FIG. 3 is a plan view showing an example of the memory cell array 11. The example shown in FIG. 3 shows areas corresponding to four blocks BLK0 to BLK3. Note that part of the interlayer insulating film is omitted in the example shown in FIG. 3. Hatching is added appropriately in the plan views shown below to make the views easier to see. The hatching added in the plan views does not necessarily relate to the materials or characteristics of the components to which the hatching is added.

[0032] In the following description, the direction parallel to the substrate and in which the word lines WL extend is referred to as the X direction. The direction parallel to the substrate and intersecting the X direction is referred to as the Y direction. The direction intersecting the X and Y directions and perpendicular to the substrate is referred to as the Z direction. In addition, in the Z direction, the direction from the source lines SL stacked and spaced apart in the Z direction toward the word lines WL is referred to as "upward," and the direction from the word lines WL toward the source lines SL is referred to as "downward."

[0033] 3, the planar layout of the memory cell array 11 is divided, for example, in the X direction into a memory cell area MA and connection areas CA1 and CA2. The memory cell array 11 includes multiple wiring layers that function as word lines WL and select gate lines SGD and SGS, and multiple members SLT and SHE. The multiple wiring layers are stacked and spaced apart in the Z direction. Hereinafter, the multiple wiring layers that correspond to the word lines WL and select gate lines SGD and SGS, respectively, stacked and spaced apart in the Z direction will also be referred to as "stacked wiring."

[0034] The memory cell area MA is an area including a plurality of NAND strings NS (a plurality of memory cell transistors MC).

[0035] The connection region CA is an area used for connecting each of the stacked wirings to the row decoder 12. In the connection region CA, each of the stacked wirings is connected to a corresponding contact plug. In the example shown in FIG. 3, 12 wiring layers are provided. For example, the 12 wiring layers function as a select gate line SGS, word lines WL0 to WL9, and a select gate line SGD, from the lower layer (closer to the substrate) to the upper layer, respectively.

[0036] In the example shown in FIG. 3, connection regions CA1 and CA2 are provided at both ends of the memory cell region MA in the X direction. A connection region CA may be provided between two memory cell regions MA. For example, in the connection regions CA1 and CA2, each wiring layer is provided with a connection portion with a contact plug (hereinafter referred to as a "plug connection portion"). In this embodiment, both ends of each stacked wiring extending in the X direction are drawn out in a staircase shape. The staircase portions (staircase regions) of the stacked wiring correspond to the plug connection portions of each wiring layer. In this case, no other wiring layers are provided above the plug connection portions. Hereinafter, when a plug connection portion is arranged in a staircase shape and no other wiring layer is provided above it, the plug connection portion is also referred to as a "terrace." The stacked wiring does not have to be drawn out in a staircase shape. That is, another wiring layer may be provided above the plug connection portion. Even in this case, a contact plug can be formed that is electrically connected to the target wiring layer but not to other wiring layers.

[0037] The multiple members SLT each extend in the X direction and are aligned in the Y direction. Each member SLT crosses (passes through) the memory cell region MA and the connection regions CA1 and CA2 in the X direction in the boundary region between adjacent blocks BLK. In other words, the member SLT is provided across the memory cell region MA and the connection regions CA1 and CA2. Each member SLT may have a structure in which, for example, an insulator or a plate-shaped contact is embedded. Each member SLT separates adjacent stacked wirings via the member SLT.

[0038] The multiple members SHE each extend along the X direction and are aligned in the Y direction. In the example shown in FIG. 3, five members SHE are arranged between adjacent members SLT. Each member SHE crosses the memory cell area MA in the X direction. Both ends of each member SHE are included in connection areas CA1 and CA2, respectively. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent select gate lines SGD via the member SHE. Therefore, the select gate lines SGD are separated into string units SU by the members SLT and SHE.

[0039] Each of the areas separated by the members SLT corresponds to one block BLK. Also, each of the areas separated by the members SLT and SHE corresponds to one string unit SU. In the example shown in Figure 3, one block BLK includes six string units SU0 to SU5.

[0040] The planar layout of the memory cell array 11 is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number. The number of string units SU formed between adjacent components SLT can be changed based on the number of components SHE arranged between adjacent components SLT.

[0041] 1.1.4 Planar layout of connection area Next, an example of a planar layout of the connection region CA1 will be described with reference to FIG. 4. FIG. 4 is a plan view showing an example of a planar layout of the connection region CA1. FIG. 4 shows the connection region CA1 corresponding to one block BLK and a part of the memory cell region MA located in the vicinity thereof. In the example shown in FIG. 4, for the sake of simplicity, one member SHE is provided in the block BLK. That is, the block BLK includes two string units SU. In addition, in the example shown in FIG. 4, part of the interlayer insulating film is omitted.

[0042] As shown in FIG. 4, in the connection area CA1, terraces (plug connection portions) corresponding to the select gate line SGD, the word lines WL9 to WL0, and the select gate line SGS are provided in order from the memory cell area MA toward the end in the X direction (the right side of the paper).

[0043] A member SLT is provided on each of the two side surfaces of one block BLK facing the Y direction. The member SLT extends in the X and Z directions. The member SLT divides the select gate lines SGS, word lines WL0 to WL9, and select gate lines SGD, which are stacked and spaced apart in the Z direction, into individual blocks BLK. For example, each member SLT includes a conductor LI and a spacer SP. The conductor LI is a conductive member extending in the XZ plane and provided within the member SLT. The spacer SP is an insulator provided on the side surface of the conductor LI. The conductor LI is surrounded by the spacer SP in a plan view seen from the Z direction. The conductor LI is electrically connected to a source line SL provided below the stacked wiring. Note that the conductor LI may be omitted. In this case, the member SLT is filled with an insulator.

[0044] The member SHE extends in the X direction. Within the block BLK, the select gate line SGD is divided in the Y direction by the member SHE. Each of the regions divided by the members SLT and SHE corresponds to one string unit SU.

[0045] A plurality of memory pillars MP are provided in the memory cell area MA. The memory pillars MP are pillars corresponding to the NAND strings NS. The structure of the memory pillars MP will be described in detail later. For example, the memory pillars MP have a substantially cylindrical shape extending in the Z direction. The memory pillars MP penetrate (pass through) the select gate lines SGS, word lines WL0 to WL9, and select gate lines SGD that are stacked and spaced apart in the Z direction. In the example shown in FIG. 4, the plurality of memory pillars MP in the memory cell area MA are arranged in a staggered pattern. The arrangement of the memory pillars MP can be designed as desired.

[0046] In the connection regions CA1 and CA2, a plurality of contact plugs CC and a plurality of support pillars HR are provided.

[0047] The contact plugs CC extend in the Z direction. For example, the contact plugs CC have a generally cylindrical shape and are made of a conductor. The contact plugs CC are electrically connected to one of the wiring layers of the stacked wiring, and are not electrically connected to the other wiring layers. In other words, the contact plugs CC are electrically connected to one of the terraces of the select gate line SGS, the word lines WL0 to WL9, and the select gate line SGD. For example, the contact plugs CC connected to the terrace of the select gate line SGD are not electrically connected to the select gate line SGS and the word lines WL0 to WL9. The upper ends of the contact plugs CC are electrically connected to the row decoder 12. 24 contact plugs CC are shown in FIG. 4. The number of contact plugs CC connected to each wiring layer (terrace) may be one or more.

[0048] One method for forming the word lines WL and select gate lines SGD and SGS is to form the wiring layers by, for example, forming a structure corresponding to each wiring layer using a sacrificial film, and then replacing the sacrificial film with a conductive material (hereinafter referred to as "WL replacement"). In WL replacement, the sacrificial film is removed to form a void, which is then filled with a conductive material.

[0049] The support pillars HR function as pillars that support the stacked structure having gaps when replacing WL. The support pillars HR are not electrically connected to the source lines SL, word lines WL, and select gate lines SGD and SGS. The support pillars HR extend in the Z direction. For example, the support pillars HR have a substantially cylindrical structure formed of an insulator. In the connection region CA1, the support pillars HR penetrate (pass through) the select gate lines SGS, word lines WL0 to WL9, and select gate line SGD that are stacked in the Z direction. The number and arrangement of the support pillars HR are arbitrary.

[0050] 1.1.5 Cross-sectional structure of memory cell area An example of the cross-sectional configuration of the memory cell region MA will be described with reference to Figures 5 and 6. Figure 5 is a cross-sectional view of the memory cell region MA taken along line A1-A2 in Figure 4. Figure 6 is a cross-sectional view of the memory pillar MP in the XY plane taken along line C1-C2 in Figure 5. More specifically, Figure 6 shows the cross-sectional structure of the memory pillar MP in a layer that is parallel to the XY plane and includes a wiring layer. Note that in the cross-sectional views shown below, illustration of the configuration may be omitted as appropriate to make the drawings easier to understand.

[0051] As shown in FIG. 5, the memory cell array 11 includes a substrate 30, insulating layers 31, 33, 35, and 36, a semiconductor layer 32, a wiring layer 34, memory pillars MP, and members SLT and SHE.

[0052] The substrate 30 is, for example, a silicon substrate. An insulating layer 31 is provided on the substrate 30. The insulating layer 31 includes, for example, silicon oxide. Circuits such as a row decoder 12 or a sense amplifier 13 may be provided in the region where the insulating layer 31 is provided, i.e., between the substrate 30 and the semiconductor layer 32. Note that, for example, if the semiconductor memory device 1 has a structure in which a chip provided with the memory cell array 11 and a chip provided with circuits other than the memory cell array 11 are bonded together, the substrate 30 provided below the insulating layer 31 may be discarded.

[0053] A semiconductor layer 32 is provided on the insulating layer 31. The semiconductor layer 32 functions as a source line SL. The semiconductor layer 32 extends in the X and Y directions. The semiconductor layer 32 includes, for example, three semiconductor layers 32a, 32b, and 32c. The semiconductor layer 32a is provided on the insulating layer 31. The semiconductor layer 32b is provided on the semiconductor layer 32a. The semiconductor layer 32c is provided on the semiconductor layer 32b. For example, the semiconductor layer 32b is provided in the memory cell region MA, but not in the connection region CA. The semiconductor layer 32b may also be provided in the connection region CA. The semiconductor layer 32b is formed, for example, by replacing an insulating layer provided between the semiconductor layer 32a and the semiconductor layer 32c. In the following description, the replacement of the semiconductor layer 32 is also referred to as "SL replace." The semiconductor layers 32a to 32c include, for example, silicon. The semiconductor layers 32a to 32c contain, for example, phosphorus (P) as an impurity for an n-type semiconductor.

[0054] An insulating layer 33 is provided on the semiconductor layer 32. The insulating layer 33 includes, for example, silicon oxide.

[0055] On the insulating layer 33, for example, 12 wiring layers 34 (stacked wiring) and 12 insulating layers 35 are alternately stacked. Hereinafter, the stacked structure of the 12 wiring layers 34 and the 12 insulating layers 35 will also be referred to as a "stacked body." Of the 12 wiring layers 34, the bottom four wiring layers 34 will be referred to as "wiring layer 34a." The four wiring layers 34a function as the select gate line SGS and the word lines WL0 to WL2, respectively, from the bottom up. The two wiring layers 34 above the wiring layer 34a will be referred to as "wiring layer 34b." The two wiring layers 34b function as the word lines WL3 and WL4, respectively, from the bottom up. The two wiring layers 34 above the wiring layer 34b will be referred to as "wiring layer 34c." The two wiring layers 34c function as the word lines WL5 and WL6, respectively, from the bottom up. The four wiring layers 34 above the wiring layer 34c will be referred to as "wiring layer 34d" when specified. The four wiring layers 34d function as word lines WL7 to WL9 and select gate lines SGD from the bottom up. Note that multiple layers of the wiring layers 34 functioning as select gate lines SGS and SGD may be provided.

[0056] For example, a titanium nitride (TiN) / tungsten (W) stacked structure is used as the conductive material of the wiring layer 34. In this case, the titanium nitride is formed so as to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of tungsten when forming a tungsten film by, for example, chemical vapor deposition (CVD), or as an adhesion layer to improve the adhesion of tungsten. The wiring layer 34 may also include a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed so as to cover the conductive material. For example, in each of the wiring layers 34, a high-dielectric-constant material is provided so as to contact the insulating layers 33 or 35 provided above and below the wiring layer 34 and the side surfaces of the memory pillars MP. Then, titanium nitride is provided so as to contact the high-dielectric-constant material. Furthermore, tungsten is provided so as to contact the titanium nitride and to fill the interior of the wiring layer 34. For example, when aluminum oxide is used as the high-dielectric-constant material, the memory cell transistor MC is also referred to as a MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type.

[0057] Next, the configuration of the memory pillar MP will be described.

[0058] The memory pillar MP extends in the Z direction and passes through the insulating layer 33, the 12 wiring layers 34, and the 12 insulating layers 35. The lower ends of the memory pillar MP reach the semiconductor layer 32a. The upper ends of the memory pillar MP are electrically connected to the bit lines BL via contact plugs (not shown).

[0059] A memory pillar MP may include one or more sub-pillars stacked in the Z direction. In the example shown in FIG. 5, the memory pillar MP includes a lower memory pillar LMP, a middle memory pillar MMP, and an upper memory pillar UMP. The lower memory pillar LMP, the middle memory pillar MMP, and the upper memory pillar UMP are sub-pillars of the memory pillar MP. In other words, the memory pillar MP has a structure formed in three layers. That is, the memory pillar MP is processed in three separate steps. Hereinafter, the layer corresponding to the lower memory pillar LMP will be referred to as the "lower layer T". LMP The layer corresponding to the middle memory pillar MMP is referred to as the "middle layer T MMP The layer corresponding to the upper memory pillar UMP is referred to as the "upper layer T UMP ". The memory pillar MP may have a two-layer structure or a four-layer or more structure. In other words, the memory pillar MP may be divided and processed twice or four or more times.

[0060] The lower memory pillar LMP passes through the insulating layer 33, the four wiring layers 34a, and the four insulating layers 35 provided on the four wiring layers 34a. That is, the lower memory pillar LMP passes through the four wiring layers 34a that function as the select gate lines SGS and the word lines WL0 to WL2. The lower surface of the lower memory pillar LMP reaches the semiconductor layer 32a. Therefore, the lower hierarchy T LMP includes four wiring layers 34a. Hereinafter, the stacked structure of the four wiring layers 34a and four insulating layers 35 through which the lower memory pillar LMP passes will also be referred to as a "lower stacked body."

[0061] The mid-level memory pillar MMP passes through two wiring layers 34b, two wiring layers 34c, and four insulating layers 35 provided on the wiring layers 34b and 34c. That is, the mid-level memory pillar MMP passes through two wiring layers 34b that function as word lines WL3 and WL4, respectively, and two wiring layers 34c that function as word lines WL5 and WL6, respectively. Therefore, the mid-level memory pillar MMP passes through the two wiring layers 34b that function as word lines WL3 and WL4, respectively, and the two wiring layers 34c that function as word lines WL5 and WL6, respectively. MMPincludes two wiring layers 34b and two wiring layers 34c. The lower surface of the mid-level memory pillar MMP contacts the upper surface of the lower memory pillar LMP. A boundary BDm1 where the upper surface of the lower memory pillar LMP and the lower surface of the mid-level memory pillar MMP contact is located between the wiring layer 34a functioning as the word line WL2 and the wiring layer 34b functioning as the word line WL3. In other words, the lower hierarchy T LMP and middle-class T MMP A boundary BDm1 between the two wiring layers 34b and the two insulating layers 35 is located. Hereinafter, the stacked structure of the two wiring layers 34b, the two wiring layers 34c, and the four insulating layers 35 through which the middle memory pillar MMP passes will be referred to as the "middle stack." Furthermore, the layer of the middle stack that includes the two wiring layers 34b and the two insulating layers 35 will be referred to as the "lower layer of the middle stack." The layer of the middle stack that includes the two wiring layers 34c and the two insulating layers 35 will be referred to as the "upper layer of the middle stack."

[0062] The upper memory pillar UMP passes through four wiring layers 34d and four insulating layers 35 provided on the four wiring layers 34d. That is, the upper memory pillar UMP passes through the four wiring layers 34d that function as the word lines WL7 to WL9 and the select gate line SGD. Therefore, the upper hierarchy T UMP The upper memory pillar UMP includes four wiring layers 34d. The lower surfaces of the upper memory pillars UMP contact the upper surfaces of the mid-level memory pillars MMP. That is, a boundary BDm2 where the upper surfaces of the mid-level memory pillars MMP and the lower surfaces of the upper memory pillars UMP contact is located between the wiring layer 34c functioning as the word line WL6 and the wiring layer 34d functioning as the word line WL7. In other words, the mid-level hierarchy T MMP and upper hierarchy T UMP Hereinafter, the stacked structure of the four wiring layers 34d and the four insulating layers 35 through which the upper memory pillar UMP passes will also be referred to as the "upper stacked body."

[0063] Each of the lower memory pillar LMP, the middle memory pillar MMP, and the upper memory pillar UMP has, for example, a tapered shape (also referred to as a "forward tapered shape") in which the diameter at the top end is larger than the diameter at the bottom end. In other words, each of the lower memory pillar LMP, the middle memory pillar MMP, and the upper memory pillar UMP has, for example, a truncated cone shape in which the bottom surface is smaller than the top surface. Therefore, the boundary BDm1 between the lower memory pillar LMP and the middle memory pillar MMP and the boundary BDm2 between the middle memory pillar MMP and the upper memory pillar UMP can be confirmed by observing the shape of the cross section.

[0064] The memory pillar MP includes, for example, a core film 40, a semiconductor film 41, and a stacked film 42. The core film 40, the semiconductor film 41, and the stacked film 42 are each formed as a continuous film, for example, in the lower memory pillar LMP, the middle memory pillar MMP, and the upper memory pillar UMP. The core film 40 has a generally cylindrical shape extending in the Z direction. For example, the upper end of the core film 40 is located in a layer above the wiring layer 34, and the lower end of the core film 40 is located in the same layer as the semiconductor layer 32. The semiconductor film 41 extends in the Z direction and covers the periphery of the core film 40. The side surfaces of the semiconductor film 41 contact the semiconductor layer 32b. The stacked film 42 covers the side surfaces and bottom surface of the semiconductor film 41 except for the contact portions between the semiconductor film 41 and the semiconductor layer 32b. The core film 40 includes an insulator such as silicon oxide. The semiconductor film 41 includes, for example, silicon.

[0065] As shown in FIG. 6, the stacked film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a block insulating film 45.

[0066] In a cross section including the wiring layer 34, the core film 40 is provided, for example, in the center of the memory pillar MP. The semiconductor film 41 surrounds the side surfaces of the core film 40. The tunnel insulating film 43 surrounds the side surfaces of the semiconductor film 41. The charge storage film 44 surrounds the side surfaces of the tunnel insulating film 43. The block insulating film 45 surrounds the side surfaces of the charge storage film 44. The wiring layer 34 surrounds the side surfaces of the block insulating film 45. The tunnel insulating film 43 and the block insulating film 45 each contain, for example, silicon oxide. The charge storage film 44 has the function of storing charges and contains, for example, silicon nitride.

[0067] As shown in FIG. 5, memory cell transistors MC0 to MC9 are formed by combining a memory pillar MP with a wiring layer 34 that functions as word lines WL0 to WL9. Similarly, a select transistor ST1 is formed by combining a memory pillar MP with a wiring layer 34 that functions as a select gate line SGD. A select transistor ST2 is formed by combining a memory pillar MP with a wiring layer 34 that functions as a select gate line SGS. The semiconductor film 41 is used as the channels (current paths) of the memory cell transistors MC0 to MC9 and the select transistors ST1 and ST2. As a result, each memory pillar MP can function as one NAND string NS.

[0068] Next, the configuration of the member SLT will be described.

[0069] In this embodiment, a structure will be described in which the member SLT, and the support pillar HR and contact plug CC described later are formed in two separate layers. That is, a case will be described in which the boundaries of the member SLT, the support pillar HR, and the contact plug CC are provided between layers of the same wiring layer 34. Hereinafter, the layer corresponding to the lower member LSLT, the lower support pillar LHR, and the lower contact plug LCC will be referred to as the "lower layer T". LCA In addition, the layer corresponding to the upper member USLT, the upper support pillar UHR, and the upper contact plug UCC will be referred to as the "upper layer T UCA " should be written as ".

[0070] The member SLT extends in the X and Z directions. The member SLT penetrates (passes through) the insulating layer 33, the 12 wiring layers 34, and the 12 insulating layers 35. The member SLT divides the stacked body in the Y direction. The lower end of the member SLT reaches, for example, the semiconductor layer 32b.

[0071] The member SLT may include one or more sub-portions stacked in the Z direction. In the example shown in FIG. 5, the member SLT includes a lower member LSLT and an upper member USLT provided on the lower member LSLT. The lower member LSLT and the upper member USLT are each a part of the member SLT. In other words, the member SLT is a lower layer T LCA and upper hierarchy T UCA In other words, the member SLT is divided into two parts and processed. The member SLT may have a structure of three or more layers. In other words, the member SLT may be divided into three or more parts and processed. The number of layers (number of divisions) of the member SLT in this embodiment differs from the number of layers (number of divisions) of the memory pillar MP.

[0072] The lower member LSLT passes through the insulating layer 33, the six wiring layers 34 (four wiring layers 34a and two wiring layers 34b), and the six insulating layers 35 provided on the six wiring layers 34. That is, the lower member LSLT passes through the six wiring layers 34 (four wiring layers 34a and two wiring layers 34b) that function as the select gate lines SGS and the word lines WL0 to WL4, respectively. Therefore, the lower hierarchy T LCA The lower member LSLT includes four wiring layers 34a and two wiring layers 34b. The lower end of the lower member LSLT reaches the semiconductor layer 32b.

[0073] The upper member USLT passes through six wiring layers 34 (two wiring layers 34c and four wiring layers 34d) and six insulating layers 35 provided on the six wiring layers 34. That is, the upper member USLT passes through the six wiring layers 34 (two wiring layers 34c and four wiring layers 34d) that function as word lines WL5 to WL9 and select gate lines SGD, respectively. Therefore, the upper hierarchy T UCAThe lower layer T includes two wiring layers 34c and four wiring layers 34d. The lower surface of the upper member USLT contacts the upper surface of the lower member LSLT. That is, a boundary BDc1 where the upper surface of the lower member LSLT and the lower surface of the upper member USLT contact is located between the wiring layer 34b functioning as the word line WL4 and the wiring layer 34c functioning as the word line WL5. In other words, the lower layer T LCA and upper hierarchy T UCA The memory pillar MP and the member SLT have different layer boundaries in the wiring layer 34.

[0074] Each of the lower member LSLT and the upper member USLT has a tapered shape in which the width in the Y direction at the upper end is greater than the width in the Y direction at the lower end, for example. Therefore, the boundary between the lower member LSLT and the upper member USLT can be confirmed by observing the cross-sectional shape.

[0075] The member SLT includes a conductor LI and a spacer SP. The conductor LI and the spacer SP are each formed as a continuous film, for example, in the lower member LSLT and the upper member USLT. In other words, the conductor LI is a conductive member extending in the XZ plane provided in the member SLT. The spacer SP is an insulator provided on the side of the conductor LI. The lower end of the conductor LI is electrically connected to the semiconductor layer 32 (source line SL). The conductor LI includes, for example, tungsten and titanium nitride, or silicon. The spacer SP includes, for example, silicon oxide.

[0076] The member SHE separates the wiring layers 34 that function as select gate lines SGD in the Y direction. In other words, the member SHE separates at least the uppermost wiring layer 34, which is located farthest from the semiconductor layer 32, among the multiple wiring layers 34. The upper end of the member SHE is located in a layer above the uppermost wiring layer 34. The lower end of the member SHE is located in a layer between the wiring layer 34 that functions as select gate lines SGD and the wiring layer 34 that functions as word lines WL. The lower end of the member SHE becomes deeper depending on the number of wiring layers 34 that function as select gate lines SGD. The member SHE includes an insulator such as silicon oxide.

[0077] An insulating layer 36 is provided on the insulating layer 35. The insulating layer 36 includes, for example, silicon oxide.

[0078] 1.1.6 Cross-sectional configuration of the connection area An example of the cross-sectional configuration of the connection region CA will be described with reference to FIG. 7. FIG. 7 is a cross-sectional view of the connection region CA1 taken along line B1-B2 in FIG. 4. In the example shown in FIG. 7, two support pillars HR are shown passing through the terrace of the select gate line SGD so as to coincide with the cross section taken along line B1-B2. In contrast, in each terrace of the word lines WL0 to WL9 and the select gate line SGS, in order to simplify the drawing, some of the support pillars HR are omitted, and only one support pillar HR passing through each terrace is shown. Although some of the support pillars HR are omitted from each terrace of the word lines WL0 to WL9 and the select gate line SGS, support pillars HR and contact plugs CC are provided on each terrace in the same arrangement as on the terrace of the select gate line SGD.

[0079] As shown in FIG. 7, the memory cell array 11 further includes insulating layers 37 and 50, support pillars HR, and contact plugs CC in the connection area CA.

[0080] The insulating layer 37 is formed so as to fill the staircase portion (staircase region) of the stack formed in the connection region CA. The staircase portion is flattened by the insulating layer 37. The insulating layer 37 includes, for example, silicon oxide.

[0081] The insulating layer 50 is provided between the semiconductor layer 32a and the semiconductor layer 32c in the connection region CA. The insulating layer 50 in the connection region CA is a layer that remains without being removed when replacing the semiconductor layer 32 (SL replacement). The insulating layer 50 includes, for example, silicon oxide.

[0082] Next, the support pillar HR will be described.

[0083] The support pillar HR extends in the Z direction and passes through the terrace of one of the wiring layers 34 and the wiring layer 34 located below that terrace. Therefore, the number of wiring layers 34 that the support pillar HR passes through varies depending on the corresponding terrace. For example, the support pillar HR provided on the terrace of the select gate line SGD passes through 12 wiring layers 34. Also, for example, the support pillar HR provided on the terrace of the select gate line SGS passes through one wiring layer 34. The multiple support pillars HR have approximately the same shape regardless of the corresponding terrace. For example, the lower end of the support pillar HR reaches the semiconductor layer 32a. The support pillar HR is embedded with an insulator 38. The insulator 38 includes, for example, silicon oxide.

[0084] The support pillar HR may include one or more sub-pillars stacked in the Z direction. In the example shown in FIG. 7, the support pillar HR includes a lower support pillar LHR and an upper support pillar UHR provided on the lower support pillar LHR. The lower support pillar LHR and the upper support pillar UHR are sub-pillars of the support pillar HR. In other words, the support pillar HR is a part of the lower layer T LCA and upper hierarchy T UCA In other words, the support pillar HR is processed in two separate steps. The support pillar HR may have a structure of three or more layers. In other words, the support pillar HR may be processed in three or more separate steps. The number of layers (number of divisions) of the support pillar HR in this embodiment differs from the number of layers (number of divisions) of the memory pillar MP.

[0085] The lower support pillar LHR passing through each terrace of the select gate line SGS and the word lines WL0 to WL4 passes through the corresponding terrace and the wiring layer 34 located below the terrace. For example, the lower support pillar LHR passing through the terrace of the select gate line SGS passes through the wiring layer 34a that functions as the select gate line SGS and the insulating layer 35 provided on the wiring layer 34a. The lower support pillar LHR passing through the terrace of the word line WL0 passes through two wiring layers 34a that function as the select gate line SGS and the word line WL0, respectively, and two insulating layers 35. The lower support pillar LHR passing through the terrace of the word line WL4 passes through six wiring layers 34 (four wiring layers 34a and two wiring layers 34b) that function as the select gate line SGS and the word lines WL0 to WL4, respectively, and the six insulating layers 35. Furthermore, the lower support pillars LHR that pass through each terrace of the select gate line SGS and word lines WL0 to WL3 pass through the insulating layer 37 used to planarize (bury) the stepped portions. The lower support pillars LHR provided below each terrace of the word lines WL5 to WL9 and select gate line SGD do not pass through the terrace. Below the corresponding terrace, these lower support pillars LHR pass through six wiring layers 34 (four wiring layers 34a and two wiring layers 34b) that function as the select gate line SGS and word lines WL0 to WL4, respectively, and six insulating layers 35. The lower end of each lower support pillar LHR reaches, for example, the semiconductor layer 32a.

[0086] The upper support pillars UHR provided above the terraces of the select gate lines SGS and the word lines WL0 to WL4 pass through the insulating layer 37 without passing through the wiring layer 34. Also, the upper support pillars UHR passing through the terraces of the word lines WL5 to WL9 and the select gate lines SGD pass through the upper hierarchy T UCAThe upper support pillar UHR passes through the wiring layer 34. For example, the upper support pillar UHR provided on the terrace of the word line WL5 passes through the wiring layer 34c that functions as the word line WL5 and the insulating layer 35 provided on the wiring layer 34c. For example, the upper support pillar UHR that passes through the terrace of the select gate line SGD passes through the six wiring layers 34 (two wiring layers 34c and four wiring layers 34d) that function as the word lines WL5 to WL9 and the select gate line SGD, respectively, and the six insulating layers 35. Furthermore, the upper support pillar UHR that passes through each terrace of the word lines WL5 to WL9 passes through the insulating layer 37. The lower surface of each upper support pillar UHR contacts the upper surface of the corresponding lower support pillar LHR. That is, a boundary BDc1 where the upper surface of the lower support pillar LHR and the lower surface of the upper support pillar UHR contact is located between the wiring layer 34b that functions as the word line WL4 and the wiring layer 34c that functions as the word line WL5. The memory pillar MP and the support pillar HR have their respective layer boundaries located in different layers of the wiring layer 34.

[0087] Each of the lower support pillar LHR and the upper support pillar UHR has, for example, a tapered shape in which the diameter at the top end is larger than the diameter at the bottom end. In other words, each of the lower support pillar LHR and the upper support pillar UHR has, for example, a truncated cone shape in which the bottom surface is smaller than the top surface. Therefore, the boundary between the lower support pillar LHR and the upper support pillar UHR can be confirmed by observing the cross-sectional shape.

[0088] Next, the contact plug CC will be described.

[0089] In the connection region CA, contact plugs CC are provided on each terrace. The lower ends of the contact plugs CC contact the terraces of the corresponding wiring layer 34. The contact plugs CC extend in the Z direction. In this embodiment, the contact plugs CC do not pass through the wiring layer 34 located below the terraces. Therefore, the shape (height in the Z direction) of the contact plugs CC differs depending on the terrace to be connected. The upper ends of the contact plugs CC are located above the uppermost wiring layer 34 that functions as the select gate lines SGD. The contact plugs CC contain, for example, tungsten or copper as a conductor.

[0090] The contact plug CC may include one or more sub-plugs stacked in the Z direction. In the example shown in FIG. 7, the contact plug CC includes a lower contact plug LCC and an upper contact plug UCC. The lower contact plug LCC and the upper contact plug UCC are sub-plugs of the contact plug CC. Some of the upper contact plugs UCC are provided on the corresponding lower contact plug LCC. In other words, the contact plug CC is a sub-plug of the lower layer T LCA and upper hierarchy T UCA In other words, the contact plug CC is processed in two separate steps. The contact plug CC may have a one-layer structure or a three- or more-layer structure. In other words, the contact plug CC may be processed all at once without being divided, or may be processed in three or more separate steps. The number of layers (number of divisions) of the contact plug CC in this embodiment is different from the number of layers (number of divisions) of the memory pillar MP.

[0091] A lower contact plug LCC is provided on each terrace of the select gate line SGS and the word lines WL0 to WL4. For example, the upper end of the lower contact plug LCC is located between the wiring layer 34b that functions as the word line WL4 and the wiring layer 34c that functions as the word line WL5. In other words, the upper end of the lower contact plug LCC is located between the wiring layer 34b that functions as the word line WL4 and the wiring layer 34c that functions as the word line WL5. LCA and upper hierarchy T UCA It is located at the boundary BDc1.

[0092] Upper contact plugs UCC are provided on lower contact plugs LCC, which are provided on the terraces of the select gate lines SGS and word lines WL0 to WL4. Upper contact plugs UCC are also provided on the terraces of the word lines WL5 to WL9 and select gate lines SGD. The lower surfaces of the upper contact plugs UCC corresponding to the select gate lines SGS and word lines WL0 to WL4 are in contact with the upper surfaces of the lower contact plugs LCC. That is, a boundary BDc1, where the upper surfaces of the lower contact plugs LCC and upper contact plugs UCC are in contact, is located between the wiring layer 34b functioning as word line WL4 and the wiring layer 34c functioning as word line WL5. The upper end of the upper contact plug UCC is located above the uppermost wiring layer 34d functioning as the select gate line SGD.

[0093] Each of the lower contact plug LCC and the upper contact plug UCC has, for example, a tapered shape with a larger diameter at the top end than at the bottom end. In other words, each of the lower contact plug LCC and the upper contact plug UCC has, for example, a truncated cone shape with a smaller bottom surface than the top surface. Therefore, the boundary between the lower contact plug LCC and the upper contact plug UCC can be confirmed by observing the cross-sectional shape.

[0094] 1.2 Boundary between memory pillar, member SLT and support pillar Next, the boundaries between the memory pillar MP, the component SLT, and the support pillar HR will be described with reference to Fig. 8. Fig. 8 is a conceptual diagram showing the boundaries between the memory pillar MP, the component SLT, and the support pillar HR. Fig. 8 shows, as a comparative example, a case in which the number of boundaries between the memory pillar MP, the component SLT, and the support pillar HR is the same. Note that the shape and number of boundaries of the memory pillar MP are the same between the comparative example and the example.

[0095] First, a comparative example will be described.

[0096] As shown in (a) of FIG. 8, for example, in the comparative example, the number of layers (number of boundaries) of the memory pillar MP, the member SLT, and the support pillar HR is the same. In this case, the hierarchical boundaries of the memory pillar MP, the member SLT, and the support pillar HR are located between the same wiring layers 34.

[0097] For example, the memory pillar MP includes a lower memory pillar LMP, a middle memory pillar MMP, and an upper memory pillar UMP. The member SLT includes a lower member LSLT, a middle member MSLT, and an upper member USLT. The support pillar HR includes a lower support pillar LHR, a middle support pillar MHR, and an upper support pillar UHR. For example, the boundary BDm1 between the lower memory pillar LMP and the middle memory pillar MMP is the same as the boundary between the lower member LSLT and the middle member MSLT, and the boundary between the lower support pillar LHR and the middle support pillar MHR.

[0098] For example, let the distance between the upper end of an adjacent memory pillar MP (upper memory pillar UMP) and the upper end of the member SLT (upper member USLT) be L0. Let the distance between the middle memory pillar MMP and the middle member MSLT in the vicinity of the boundary BDm1 be L1a. Let the distance between the upper memory pillar UMP and the upper member USLT in the vicinity of the boundary BDm2 be L2a. Each of the memory pillar MP, the member SLT, and the support pillar HR has a tapered shape in each of the divided parts. Therefore, the distance L0 and the distance L1a are in the relationship of L0 < L1a. Similarly, the distance L0 and the distance L2a are in the relationship of L0 < L2a.

[0099] Next, the embodiments will be described.

[0100] As shown in (b) of FIG. 8, in the embodiment, the memory pillar MP has three layers. The member SLT and the support pillar HR have two layers. In other words, the memory pillar MP has two boundaries BDm1 and BDm2. The member SLT and the support pillar HR have one boundary BDc1. That is, the memory pillar MP, the member SLT, and the support pillar HR have different numbers of layers (numbers of boundaries).

[0101] In this case, the inter-layer positions of the wiring layer 34 where the boundaries BDm1 and BDm2 between the memory pillar MP and the boundary BDc1 between the member SLT and the support pillar HR are located are different. More specifically, in the description using FIGS. 5 and 7, the boundary BDm1 is located between the wiring layer 34a functioning as word line WL2 and the wiring layer 34b functioning as word line WL3. The boundary BDm2 is located between the wiring layer 34c functioning as word line WL6 and the wiring layer 34d functioning as word line WL7. In contrast, the boundary BDc1 is located between the wiring layer 34b functioning as word line WL4 and the wiring layer 34c functioning as word line WL5.

[0102] Each of the memory pillar MP, the member SLT, and the support pillar HR has a tapered shape in each divided portion (each layer).

[0103] More specifically, the diameter D of the lower end of the lower memory pillar LMP LMP1 and the diameter of the upper end D LMP2 That is, D LMP1 <D LMP2 The diameter D of the lower end of the middle memory pillar MMP is MMP1 and the diameter of the upper end D MMP2 That is, D MMP1 <D MMP2 The diameter D of the lower end of the upper memory pillar UMP is UMP1 and the diameter of the upper end D UMP2 That is, D UMP1 <D UMP2 Furthermore, the upper diameter D of the lower memory pillar LMP LMP2 and the diameter D of the lower end of the middle memory pillar MMP MMP1 That is, D LMP2 >D MMP1 The upper diameter D of the middle memory pillar MMP is MMP2 and the diameter D of the lower end of the upper memory pillar UMP UMP1 That is, D LMP2 >D UMP1 are in a relationship.

[0104] Also, the width W in the Y direction of the lower end of the lower member LSLT LSLT1 and the width W in the Y direction at the top LSLT2That is, W LSLT1 <W LSLT2 is related to the relationship. The width W in the Y direction at the lower end of the upper member USLT USLT1 and the width W in the Y direction at the upper end USLT2 That is, W USLT1 <W USLT2 is related to the relationship. Furthermore, the width W in the Y direction at the upper end of the lower member LSLT LSLT2 and the width W in the Y direction at the lower end of the upper member USLT USLT1 That is, W LSLT2 >W USLT1 is related to the relationship. The support pillar HR also has a similar relationship.

[0105] For example, let the distance between the upper end of adjacent memory pillars MP (upper memory pillar UMP) and the upper end of the member SLT (upper member USLT) be the same L0 as in the comparative example of (a). Let the distance between the memory pillar MP and the member SLT at the boundary BDm1 be L1b. Let the distance between the memory pillar MP and the member SLT at the boundary BDm2 be L2b. The distance L0 and the distance L1b are in the relationship of L0 < L1b. Similarly, the distance L0 and the distance L2b are in the relationship of L0 < L2b.

[0106] In the case of the comparative example of (a), for example, at the boundary BDm1, the width of the middle member MSLT is the narrowest. On the contrary, in the case of the embodiment of (b), the boundary BDm1 is located in the middle of the lower member LSLT. Therefore, when comparing the distance L1a and the distance L1b, the relationship is L1a > L1b. Similarly, in the case of the comparative example of (a), at the boundary BDm2, the width of the upper member USLT is the narrowest. On the contrary, in the case of the embodiment of (b), the boundary BDm2 is located in the middle of the upper member USLT. Therefore, when comparing the distance L2a and the distance L2b, the relationship is L2a > L2b. The relationship between the memory pillar MP and the support pillar HR is the same.

[0107] Therefore, with the structure according to this embodiment, the tapered shape can prevent the distance between the memory pillar MP and the component SLT from increasing. In other words, by locating the boundary positions of the memory pillar MP and the component SLT between different wiring layers 34, the distance between the memory pillar MP and the component SLT can be prevented from increasing. The same applies to the support pillar HR. By locating the boundary positions of the memory pillar MP and the support pillar HR between different wiring layers 34, the distance between the memory pillar MP and the support pillar HR can be prevented from increasing. This can prevent, for example, bending of the stack due to WL replacement.

[0108] 1.3 Memory cell array manufacturing method Next, an example of a manufacturing method of the memory cell array 11 will be described with reference to FIGS. 9 to 37. FIG. 9 is a flowchart showing an example of a manufacturing process of the memory cell array 11. FIGS. 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, and 36 are diagrams showing an example of a planar layout of the memory cell array 11 in the manufacturing process of the memory cell array 11. FIG. 11 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 10. FIG. 13 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 12. FIG. 15 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 14. FIG. 17 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 16. FIG. 19 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 18. 21 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 20. FIG. 23 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 22. FIG. 25 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 24. FIG. 27 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 26. FIG. 29 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 28. FIG. 31 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 30. FIG. 33 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 32. FIG. 35 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 34. FIG. 37 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 36. Note that the sizes of the memory pillars MP, members SLT, support pillars HR, and contact plugs CC in each cross-sectional view are arbitrary. Note that in the cross-sectional views of the manufacturing process shown below, some of the support pillars HR that pass through each terrace are omitted to simplify the drawings.

[0109] As shown in FIG. 9, first, a lower laminate is formed (S101).

[0110] As shown in FIGS. 10 and 11, more specifically, first, an insulating layer 31 is formed on a semiconductor substrate 30. A semiconductor layer 32a is formed on the insulating layer 31. An insulating layer 50 is formed on the semiconductor layer 32a. The insulating layer 50 includes, for example, three insulating layers 50a, 50b, and 50c. For example, the insulating layers 50a and 50c include silicon oxide. The insulating layer 50b includes silicon nitride. Note that the insulating layer 50b is formed in the memory cell region MA where replacement of the insulating layer 50 (SL replacement) is performed in a process described below, but is not formed in the connection region CA where replacement is not performed. A semiconductor layer 32c is formed on the insulating layer 50. An insulating layer 33 is formed on the semiconductor layer 32c. Four sacrificial films 60a and four insulating layers 35 are alternately stacked on the insulating layer 33 as a lower stacked body before WL replacement. The four sacrificial films 60a are formed in the lower hierarchy T LMP In the WL replacement, the sacrificial film 60a is replaced with four wiring layers 34a that function as the select gate lines SGS and the word lines WL0 to WL2, respectively. For example, silicon nitride is used for the sacrificial film 60a.

[0111] As shown in FIG. 9, after step S101 is performed, memory holes LMH corresponding to the lower memory pillars LMP are processed (formed), and the insides of the memory holes LMH are filled with a sacrificial film 61 (S102).

[0112] 12 and 13, a memory hole LMH corresponding to the lower memory pillar LMP is formed in the memory cell region MA. The memory hole LMH has a tapered shape, and the bottom end reaches the semiconductor layer 32a.

[0113] 14 and 15, next, the memory holes LMH are filled with a sacrificial film 61. The sacrificial film 61 may contain carbon, may contain silicon, or may be made of a metal material.

[0114] As shown in FIG. 9, after step S102 is performed, the lower layer of the intermediate stack is deposited (S103).

[0115] 16 and 17, two sacrificial films 60b and two insulating layers 35 are alternately stacked on the lower stack as lower layers of the intermediate stack before WL replacement. In WL replacement, the two sacrificial films 60b are replaced with two wiring layers 34b that function as word lines WL3 and WL4, respectively. For example, silicon nitride is used for the sacrificial films 60b.

[0116] As shown in FIG. 9, after step S103 is executed, the lower layer T LCA A staircase portion corresponding to the above is formed (S104).

[0117] 18 and 19, the lower layers of the lower stacked body and the middle stacked body are processed in a stepped manner to form terraces corresponding to the plurality of sacrificial films 60a and 60b, respectively. In the example shown in Fig. 19, terraces corresponding to the select gate line SGS and the word lines WL0 to WL3 are processed.

[0118] 9, after step S104 is performed, the processing of the lower support pillar LHR and filling with the sacrificial film 62, the processing of the lower member LSLT and filling with the sacrificial film 63, and the processing of the lower contact plug LCC and filling with the sacrificial film 64 are sequentially performed (S105). Note that the order of processing the lower support pillar LHR, the lower member LSLT, and the lower contact plug LCC and filling with the sacrificial films 62 to 64 is arbitrary.

[0119] As shown in FIGS. 20 and 21, the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP (Chemical Mechanical Polishing). Next, in the connection region CA, holes corresponding to the lower support pillars LHR are formed and the insides of the holes are filled with a sacrificial film 62. For example, the bottom ends of the holes corresponding to the lower support pillars LHR reach the semiconductor layer 32a. Next, slits corresponding to the lower members LSLT are formed and the insides of the slits are filled with a sacrificial film 63. The bottom ends of the slits corresponding to the lower members LSLT reach the insulating layer 50. Next, in the connection region CA, holes corresponding to the lower contact plugs LCC are formed and the insides of the holes are filled with a sacrificial film 64. The bottom ends of the lower contact plugs LCC contact the terraces of the corresponding sacrificial film 60 (wiring layer 34). The lower contact plugs LCC are provided on the terraces of the select gate lines SGS and word lines WL0 to WL4, but are not provided on the terraces of the word lines WL5 to WL9 and select gate line SGD. For example, the sacrificial films 62 to 64 may contain carbon, silicon, or a metal material. The sacrificial films 62 to 64 may be made of the same material or different materials.

[0120] As shown in FIG. 9, after step S105 is performed, the upper layer of the intermediate stack is deposited (S106).

[0121] 22 and 23, two sacrificial films 60c and two insulating layers 35 are alternately stacked on the lower layer of the intermediate stack as upper layers of the intermediate stack before WL replacement. In WL replacement, the two sacrificial films 60c are replaced with two wiring layers 34c that function as word lines WL5 and WL6, respectively. For example, silicon nitride is used for the sacrificial films 60c.

[0122] As shown in FIG. 9, after step S106 is performed, memory holes corresponding to the middle memory pillars MMP are processed (formed), and the insides of the memory holes are filled with a sacrificial film 61 (S107).

[0123] 24 and 25, a memory hole corresponding to the mid-level memory pillar MMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the mid-level memory pillar MMP reaches the lower memory pillar LMP. Next, the memory hole corresponding to the mid-level memory pillar MMP is filled with a sacrificial film 61. In other words, a stacked structure of the lower memory pillar LMP and the mid-level memory pillar MMP filled with the sacrificial film 61 is formed.

[0124] As shown in FIG. 9, after step S107 is performed, an upper laminate is formed (S108).

[0125] 26 and 27, four sacrificial films 60d and four insulating layers 35 are alternately stacked on the upper layer of the intermediate stack as an upper stack before WL replacement. In WL replacement, the four sacrificial films 60d are replaced with four wiring layers 34d that function as word lines WL7 to WL9 and select gate lines SGD, respectively. For example, silicon nitride is used for the sacrificial films 60d.

[0126] As shown in FIG. 9, after step S108 is executed, the upper layer T UCA A staircase portion corresponding to the above is formed (S109).

[0127] 28 and 29, the upper layer of the intermediate stack and the upper stack are processed in a stepped manner to form terraces corresponding to the plurality of sacrificial films 60c and 60d, respectively. In the example shown in Fig. 29, terraces corresponding to the word lines WL4 to WL9 are processed.

[0128] 9, after step S109 is performed, the upper support pillar UHR is processed and filled with a sacrificial film 62, the upper member USLT is processed and filled with a sacrificial film 63, and the upper contact plug UCC is processed and filled with a sacrificial film 64 are sequentially performed (S110). Note that the order of processing the upper support pillar UHR, the upper member USLT, and the upper contact plug UCC and filling with the sacrificial films 62 to 64 is arbitrary.

[0129] As shown in FIGS. 30 and 31 , the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP. Next, in the connection region CA, a hole corresponding to the upper support pillar UHR is formed and the hole is filled with a sacrificial film 62. This forms the support pillar HR filled with the sacrificial film 62. Next, a slit corresponding to the upper member USLT is formed and the slit is filled with a sacrificial film 63. This forms the member SLT filled with the sacrificial film 63. Next, in the connection region CA, a hole corresponding to the upper contact plug UCC is formed and the hole is filled with a sacrificial film 64. This forms the contact plug CC filled with the sacrificial film 64.

[0130] As shown in FIG. 9, after step S110 is performed, memory holes corresponding to the upper memory pillars UMP are processed (formed) to form memory pillars MP (S111).

[0131] As shown in Figures 32 and 33, a memory hole corresponding to the upper memory pillar UMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the upper memory pillar UMP reaches the middle memory pillar MMP. Next, the sacrificial film 61 in the memory hole is removed. Next, a stacked film 42, a semiconductor film 41, and a core film 40 are formed to fill the memory hole and form the memory pillar MP.

[0132] As shown in FIG. 9, after step S111 is performed, the sacrificial film 62 in the support pillar HR is removed, and the hole is filled with the insulator 38 (S112).

[0133] After step S112 is performed, the sacrificial film 63 in the member SLT is removed (S113).

[0134] 34 and 35, the sacrificial film 62 inside the support pillar HR is removed, and the inside is filled with an insulator 38. After the insulating layer 36 is formed, an opening is made in the member SLT, and the sacrificial film 63 inside is removed.

[0135] As shown in FIG. 9, after step S113 is executed, SL replacement and WL replacement are executed in sequence (S114).

[0136] After step S114 is performed, the spacers SP and the conductors LI are embedded in the member SLT (S115).

[0137] As shown in Figures 36 and 37, for example, after forming an insulating film on the side surface of the slit corresponding to the member SLT, SL replacement is performed to replace the insulating layer 50 (50a, 50b, 50c) in the memory cell region MA with the semiconductor layer 32b. At this time, in the memory pillar MP, the stacked film 42 in the same layer as the semiconductor layer 32b is removed. More specifically, the insulating layer 50b is removed from the side surface of the slit corresponding to the member SLT by wet etching. Next, the insulating layers 50a and 50c are removed from the side surface of the slit corresponding to the member SLT by wet etching. As a result, in the memory cell region MA where the insulating layer 50b is formed, the insulating layer 50 (50a, 50b, and 50c) is removed. At this time, the stacked film 42 located in the same layer as the insulating layer 50 is also removed at the same time. Next, the semiconductor layer 32b is formed to fill the region from which the insulating layer 50 has been removed. Next, the excess semiconductor layer 32b on the side surface of the slit corresponding to the member SLT and on the insulating layer 36 is removed, thereby forming the semiconductor layer 32b between the semiconductor layers 32a and 32c.

[0138] Next, WL replacement is performed. More specifically, first, the insulating layer provided on the side surface of the slit corresponding to the member SLT is removed. Next, the sacrificial film 60 (60a to 60d) is removed from the side surface of the slit corresponding to the member SLT by wet etching. Next, the wiring layer 34 (34a to 34d) is formed.

[0139] Next, spacers SP and conductors LI are formed in the member SLT.

[0140] 9, after step S115 is performed, the sacrificial film 64 in the contact plug CC is removed, and the hole is filled with a conductor 39 (S116). As a result, the structure of the memory cell array 11 described with reference to FIGS. 5, 7, and 8 is formed.

[0141] 1.4 Effects of this embodiment The configuration according to this embodiment allows for reduced manufacturing costs for the semiconductor memory device 1. This effect will be described in detail below.

[0142] For example, in a three-dimensional stacked NAND flash memory, the difficulty of processing the memory pillars MP, the component SLT, the support pillars HR, and the contact plugs CC increases with the number of stacked word lines WL. For this reason, the memory pillars MP, the component SLT, the support pillars HR, and the contact plugs CC may each be processed in multiple layers. In this case, the number of layers of the memory pillars MP, the component SLT, the support pillars HR, and the contact plugs CC is set to be the same. However, the difficulty of processing the memory pillars MP, the component SLT, the support pillars HR, and the contact plugs CC varies. The desired number of layers varies depending on the processing difficulty. For example, if the number of layers is set to match the memory pillars MP, the number of layers (number of processing operations) of the component SLT, the support pillars HR, and the contact plugs CC may differ from the desired number of layers. For example, if the set number of layers is greater than the desired number of layers, the number of process steps and manufacturing costs for the memory cell array increase.

[0143] In contrast, with the configuration according to this embodiment, the number of memory pillar MP layers can be set to be different from the number of layers of the component SLTs, support pillars HRs, and contact plugs CCs. Furthermore, the boundary positions corresponding to the memory pillar MP layers and the boundary positions corresponding to the component SLTs, support pillars HRs, and contact plugs CC layers can be set between different wiring layers 34. For example, as described with reference to FIG. 5 , a boundary BDm1 where the upper surface of the lower memory pillar LMP and the lower surface of the middle memory pillar MMP meet is located between the wiring layer 34a functioning as word line WL2 and the wiring layer 34b functioning as word line WL3. Furthermore, a boundary BDc1 where the upper surface of the lower support pillar LHR and the lower surface of the upper support pillar UHR meet is located between the wiring layer 34b functioning as word line WL4 and the wiring layer 34c functioning as word line WL5. By optimizing the number of layers of the memory pillars MP and the number of layers of the members SLT, support pillars HR, and contact plugs CC, respectively, the number of process steps and manufacturing costs of the memory cell array can be reduced.

[0144] Furthermore, with the configuration according to this embodiment, the boundary positions corresponding to the layer of the memory pillar MP and the boundary positions corresponding to the layers of the member SLT, support pillar HR, and contact plug CC can be set between different wiring layers 34. This makes it possible to prevent, for example, the distance between the memory pillar MP and the member SLT or support pillar HR from increasing, as described with reference to FIG. 8. This makes it possible to prevent, for example, bending of the stack.

[0145] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a case will be described in which the number of layers of the member SLT, the support pillar HR, and the contact plug CC is greater than the number of layers of the memory pillar MP. Below, the differences from the first embodiment will be mainly described.

[0146] 2.1 Cross-sectional structure of the memory cell area An example of the cross-sectional configuration of the memory cell area MA will be described with reference to Fig. 38. Fig. 38 is a cross-sectional view showing an example of the cross-sectional configuration of the memory cell area MA.

[0147] As shown in Fig. 38, the shape of the memory pillars MP in this embodiment is similar to that of the first embodiment in Fig. 5. The memory pillars MP include lower memory pillars LMP, middle memory pillars MMP, and upper memory pillars UMP.

[0148] Next, the configuration of the member SLT will be described.

[0149] In this embodiment, the member SLT, the support pillar HR, and the contact plugs CC have a structure formed in four separate layers. Hereinafter, the layers corresponding to the middle member MSLT, the middle support pillar MHR, and the middle contact plugs MCC will be referred to as "middle layer T" and "middle layer T". MCA ". In addition, the layer corresponding to the top member TSLT, the top support pillar THR, and the top contact plug TCC will be referred to as the "top layer T TCA " should be written as ".

[0150] The member SLT of this embodiment includes a lower member LSLT, a middle member MSLT, a higher member USLT, and a top member TSLT. The middle member MSLT is provided on the lower member LSLT. The higher member USLT is provided on the middle member MSLT. The top member TSLT is provided on the higher member USLT. In other words, the member SLT of this embodiment includes a lower layer T LCA , medium hierarchy T MCA , upper layer T UCA , and the top hierarchy T TCA That is, the member SLT is divided into four parts and processed.

[0151] The lower member LSLT passes through three wiring layers 34a which function as the select gate line SGS and the word lines WL0 and WL1, respectively. LCA The lower end of the lower member LSLT reaches the semiconductor layer 32b.

[0152] The middle member MSLT passes through three wiring layers 34 (the first wiring layer 34a and the second wiring layer 34b) which function as the word lines WL2 to WL4, respectively. MCA The lower layer T includes three wiring layers 34 (one wiring layer 34a and two wiring layers 34b). The lower surface of the middle member MSLT contacts the upper surface of the lower member LSLT. That is, a boundary BDc1 where the upper surface of the lower member LSLT and the lower surface of the middle member MSLT contact is located between the wiring layer 34a functioning as the word line WL1 and the wiring layer 34a functioning as the word line WL2. In other words, the lower layer T is located between the wiring layer 34a functioning as the word line WL1 and the wiring layer 34a functioning as the word line WL2. LCA and middle-class T MCA The boundary BDc1 is located between the two.

[0153] The upper member USLT passes through three wiring layers 34 (two wiring layers 34c and one wiring layer 34d) that function as word lines WL5 to WL7, respectively. UCA The middle hierarchical level T includes three wiring layers 34 (two wiring layers 34c and one wiring layer 34d). The lower surface of the upper member USLT contacts the upper surface of the middle member MSLT. That is, a boundary BDc2 where the upper surface of the middle member MSLT and the lower surface of the upper member USLT contact is located between the wiring layer 34b functioning as the word line WL4 and the wiring layer 34c functioning as the word line WL5. In other words, the middle hierarchical level T is located between the wiring layer 34b functioning as the word line WL4 and the wiring layer 34c functioning as the word line WL5. MCA and upper hierarchy T UCA The boundary BDc2 is located between the two.

[0154] The top member TSLT passes through three wiring layers 34d which function as word lines WL8 and WL9 and select gate lines SGD, respectively. TCAincludes three wiring layers 34d. The bottom surface of the top member TSLT is in contact with the top surface of the upper member USLT. That is, a boundary BDc3 where the top surface of the upper member USLT and the bottom surface of the top member TSLT are in contact is located between the wiring layer 34d functioning as the word line WL7 and the wiring layer 34d functioning as the word line WL8. In other words, the upper hierarchy T UCA and the top hierarchy T TCA In the present embodiment, the memory pillar MP and the member SLT also have different layer boundaries in the wiring layer 34.

[0155] Each of the lower member LSLT, middle member MSLT, upper member USLT, and top member TSLT has a tapered shape in which the width in the Y direction at the top end is greater than the width in the Y direction at the bottom end, for example. Therefore, the boundaries between each can be confirmed by observing the cross-sectional shape.

[0156] 2.2 Cross-sectional structure of the connection area An example of the cross-sectional configuration of the connection region CA will be described with reference to FIG. 39. FIG. 39 is a cross-sectional view showing an example of the cross-sectional configuration of the connection region CA1. In the example shown in FIG. 39, similar to FIG. 7, two support pillars HR passing through the terrace of the select gate line SGD are shown to coincide with the cross section along line B1-B2. In contrast, in each terrace of the word lines WL0 to WL9 and the select gate line SGS, in order to simplify the drawing, some of the support pillars HR are omitted, and only one support pillar HR passing through each terrace is shown. Although some of the support pillars HR are omitted from each terrace of the word lines WL0 to WL9 and the select gate line SGS, support pillars HR and contact plugs CC are provided on each terrace in the same arrangement as on the terrace of the select gate line SGD.

[0157] As shown in FIG. 39, the support pillars HR in this embodiment include a lower support pillar LHR, a middle support pillar MHR, an upper support pillar UHR, and a top support pillar THR. The middle support pillar MHR is provided on the lower support pillar LHR. The upper support pillar UHR is provided on the middle support pillar MHR. The top support pillar THR is provided on the upper support pillar UHR. The support pillars HR in this embodiment are provided on the lower level T, similar to the member SLT. LCA , medium hierarchy T MCA , upper layer T UCA , and the top hierarchy T TCA That is, the support pillar HR is processed in four separate steps.

[0158] The lower support pillar LHR passing through each terrace of the select gate line SGS and the word lines WL0 and WL1 passes through the corresponding terrace and the wiring layer 34 located below the terrace. For example, the lower support pillar LHR passing through the terrace of the select gate line SGS passes through the wiring layer 34a that functions as the select gate line SGS and the insulating layer 35 provided on the wiring layer 34a. For example, the lower support pillar LHR passing through the terrace of the word line WL1 passes through the three-layer wiring layer 34a that functions as the select gate line SGS and the word lines WL0 and WL1, respectively, and the three-layer insulating layer 35. Furthermore, the lower support pillar LHR passing through each terrace of the select gate line SGS and the word line WL0 passes through the insulating layer 37 provided above the corresponding terrace. The lower support pillar LHR provided below each terrace of the word lines WL2 to WL9 and the select gate line SGD does not pass through the terrace. Below the corresponding terraces, these lower support pillars LHR pass through three wiring layers 34a that function as select gate lines SGS and word lines WL0 and WL1, respectively, and three insulating layers 35. The bottom ends of the lower support pillars LHR reach, for example, the semiconductor layer 32a.

[0159] The middle support pillars MHR provided above the terraces of the select gate line SGS and the word lines WL0 and WL1 pass through the insulating layer 37. The middle support pillars MHR passing through the terraces of the word lines WL2 to WL4 pass through the corresponding terraces and the middle hierarchy T MCA WL2 to WL3. For example, the mid-level support pillar MHR passing through the terrace of the word line WL2 passes through the wiring layer 34a that functions as the word line WL2 and the insulating layer 35 provided on the wiring layer 34a. For example, the mid-level support pillar MHR passing through the terrace of the word line WL4 passes through the three wiring layers 34 (the uppermost wiring layer 34a and the second wiring layer 34b) that function as the word lines WL2 to WL4, respectively, and the three insulating layers 35. Furthermore, the mid-level support pillar MHR passing through each terrace of the word lines WL2 and WL3 passes through the insulating layer 37 provided above the terrace. Moreover, the mid-level support pillar MHR provided below each terrace of the word lines WL5 to WL9 and the select gate line SGD does not pass through the terrace. These mid-level support pillars MHR pass through three wiring layers 34 (the topmost wiring layer 34a and the second wiring layer 34b) that function as word lines WL2 to WL4, and three insulating layers 35, below the corresponding terraces. The bottom surface of each mid-level support pillar MHR contacts the top surface of the corresponding lower support pillar LHR. That is, a boundary BDc1 where the top surface of the lower support pillar LHR and the bottom surface of the mid-level support pillar MHR contact is located between the wiring layer 34a that functions as word line WL1 and the topmost wiring layer 34a that functions as word line WL2.

[0160] The upper support pillars UHR provided above the terraces of the select gate lines SGS and the word lines WL0 to WL4 pass through the insulating layer 37. The upper support pillars UHR passing through the terraces of the word lines WL5 to WL7 pass through the corresponding terraces and the upper hierarchy T UCAFor example, the upper support pillar UHR passing through the terrace of the word line WL5 passes through the wiring layer 34c that functions as the word line WL5 and the insulating layer 35 provided on the wiring layer 34c. For example, the upper support pillar UHR passing through the terrace of the word line WL7 passes through the three wiring layers 34 (the two wiring layers 34c and the bottom wiring layer 34d) that function as the word lines WL5 to WL7, respectively, and the three insulating layers 35. Furthermore, the upper support pillar UHR passing through each terrace of the word lines WL5 and WL6 passes through the insulating layer 37 provided above the terraces. Furthermore, the upper support pillar UHR provided below each terrace of the word lines WL8 and WL9 and the select gate line SGD does not pass through the terraces. These upper support pillars UHR pass through three wiring layers 34 (two wiring layers 34c and the lowest wiring layer 34d) that function as word lines WL5 to WL7 below the corresponding terraces, and three insulating layers 35. The lower surface of each upper support pillar UHR contacts the upper surface of the corresponding middle support pillar MHR. That is, a boundary BDc2 where the upper surface of the middle support pillar MHR and the lower surface of the upper support pillar UHR contact is located between the uppermost wiring layer 34b that functions as word line WL4 and the lowest wiring layer 34c that functions as word line WL5.

[0161] The top support pillars THR provided above the terraces of the select gate line SGS and the word lines WL0 to WL7 pass through the insulating layer 37. The top support pillars THR passing through the terraces of the word lines WL8 and WL9 and the select gate line SGD pass through the top layer T TCAWL8 and WL9. For example, the top support pillar THR passing through the terrace of the word line WL8 passes through the wiring layer 34d that functions as the word line WL8 and the insulating layer 35 provided on the wiring layer 34d. For example, the top support pillar THR passing through the terrace of the select gate line SGD passes through the three-layer wiring layer 34 (the three-layer wiring layer 34d) that function as the word lines WL8 and WL9 and the select gate line SGD, respectively, and the three-layer insulating layer 35. Furthermore, the top support pillar THR passing through each terrace of the word lines WL8 and WL9 passes through the insulating layer 37 provided above the terrace. The bottom surface of each top support pillar THR contacts the top surface of the corresponding upper support pillar UHR. That is, a boundary BDc3 where the top surface of the upper support pillar UHR and the bottom surface of the top support pillar THR contact is located between the wiring layer 34d that functions as the word line WL7 and the wiring layer 34d that functions as the word line WL8.

[0162] In this embodiment as well, the memory pillar MP and the support pillar HR have their respective layer boundaries located in different wiring layers 34.

[0163] Each of the lower support pillar LHR, middle support pillar MHR, upper support pillar UHR, and top support pillar THR has, for example, a tapered shape in which the diameter at the top end is larger than the diameter at the bottom end. In other words, each of the lower support pillar LHR, middle support pillar MHR, upper support pillar UHR, and top support pillar THR has, for example, a truncated cone shape in which the bottom surface is smaller than the top surface. Therefore, the boundaries of each of the lower support pillar LHR, middle support pillar MHR, upper support pillar UHR, and top support pillar THR can be confirmed by observing the cross-sectional shapes.

[0164] Next, the contact plug CC will be described.

[0165] The contact plugs CC include lower contact plugs LCC, middle contact plugs MCC, upper contact plugs UCC, and top contact plugs TCC. Some of the middle contact plugs MCC are provided on the corresponding lower contact plugs LCC. Some of the upper contact plugs UCC are provided on the corresponding middle contact plugs MCC. Some of the top contact plugs TCC are provided on the corresponding upper contact plugs UCC. Therefore, the contact plugs CC in this embodiment, like the member SLT and the support pillar HR, are provided on the lower layer T. LCA , medium hierarchy T MCA , upper layer T UCA , and the top hierarchy T TCA That is, the contact plug CC is processed in four separate steps.

[0166] A lower contact plug LCC is provided on each terrace of the select gate line SGS and the word lines WL0 and WL1. For example, the upper end of the lower contact plug LCC is located between the wiring layer 34a that functions as the word line WL1 and the wiring layer 34a that functions as the word line WL2. In other words, the upper end of the lower contact plug LCC is located between the wiring layer 34a that functions as the word line WL1 and the wiring layer 34a that functions as the word line WL2. LCA and middle-class T MCA It is located at the boundary BDc1.

[0167] Mid-level contact plugs MCC are provided on the lower contact plugs LCC corresponding to the select gate line SGS and the word lines WL0 and WL1, respectively. Mid-level contact plugs MCC are also provided on the terraces of the word lines WL2 to WL4. The lower surfaces of the mid-level contact plugs MCC corresponding to the select gate line SGS and the word lines WL0 and WL1, respectively, contact the upper surfaces of the lower contact plugs LCC. That is, a boundary BDc1, where the upper surfaces of the lower contact plugs LCC and the lower surfaces of the mid-level contact plugs MCC contact, is located between the wiring layer 34a functioning as the word line WL1 and the wiring layer 34a functioning as the word line WL2.

[0168] Upper contact plugs UCC are provided on the mid-level contact plugs MCC corresponding to the select gate line SGS and the word lines WL0 to WL4, respectively. Upper contact plugs UCC are also provided on the terraces of the word lines WL5 to WL7. The lower surfaces of the upper contact plugs UCC corresponding to the select gate line SGS and the word lines WL0 to WL4, respectively, contact the upper surfaces of the mid-level contact plugs MCC. That is, a boundary BDc2 where the upper surfaces of the mid-level contact plugs MCC and the lower surfaces of the upper contact plugs UCC contact is located between the wiring layer 34b functioning as the word line WL4 and the wiring layer 34c functioning as the word line WL5.

[0169] The topmost contact plugs TCC are provided on the upper contact plugs UCC corresponding to the select gate line SGS and the word lines WL0 to WL7, respectively. The topmost contact plugs TCC are also provided on the terraces of the word lines WL8 and WL9 and the select gate line SGD. The bottom surfaces of the topmost contact plugs TCC corresponding to the select gate line SGS and the word lines WL0 to WL7, respectively, are in contact with the top surfaces of the upper contact plugs UCC. That is, a boundary BDc3 where the top surfaces of the upper contact plugs UCC and the bottom surface of the topmost contact plug TCC are in contact is located between the wiring layer 34d functioning as the word line WL7 and the wiring layer 34d functioning as the word line WL8. The top end of the topmost contact plug TCC is located above the uppermost wiring layer 34d functioning as the select gate line SGD.

[0170] Each of the lower contact plug LCC, the middle contact plug MCC, the upper contact plug UCC, and the top contact plug TCC has, for example, a tapered shape in which the diameter of the upper end is larger than the diameter of the lower end. In other words, each of the lower contact plug LCC, the middle contact plug MCC, the upper contact plug UCC, and the top contact plug TCC has, for example, a truncated cone shape in which the bottom surface is smaller than the top surface. Therefore, the boundaries of each of the lower contact plug LCC, the middle contact plug MCC, the upper contact plug UCC, and the top contact plug TCC can be confirmed by observing the cross-sectional shapes.

[0171] 2.3 Boundary between memory pillar, member SLT, and support pillar Next, the boundaries between the memory pillar MP, the member SLT, and the support pillar HR will be described with reference to Fig. 40. Fig. 40 is a conceptual diagram showing the boundaries between the memory pillar MP, the member SLT, and the support pillar HR.

[0172] The comparative example shown in Fig. 40(a) is the same as the comparative example described with reference to Fig. 8 of the first embodiment. The following description focuses on the example.

[0173] As shown in (b) of Figure 40, in this embodiment, the memory pillar MP has three levels. The member SLT and the support pillar HR have four levels. In other words, the memory pillar MP has two boundaries BDm1 and BDm2. The member SLT and the support pillar HR have three boundaries BDc1, BDc2, and BDc3. In other words, the number of levels of the member SLT and the support pillar HR is greater than the number of levels of the memory pillar MP.

[0174] In this case, the interlayer positions of the wiring layer 34 where the boundaries BDm1 and BDm2 of the memory pillar MP and the boundaries BDc1, BDc2, and BDc3 of the member SLT and the support pillar HR are located are different from each other. More specifically, in the description using FIGS. 38 and 39, the boundary BDm1 is located between the wiring layer 34a functioning as the word line WL2 and the wiring layer 34b functioning as the word line WL3. The boundary BDm2 is located between the wiring layer 34c functioning as the word line WL6 and the wiring layer 34d functioning as the word line WL7. On the other hand, the boundary BDc1 is located between the wiring layer 34a functioning as the word line WL1 and the wiring layer 34a functioning as the word line WL2. The boundary BDc2 is located between the wiring layer 34b functioning as the word line WL4 and the wiring layer 34c functioning as the word line WL5. The boundary BDc3 is located between the wiring layer 34d functioning as the word line WL7 and the wiring layer 34d functioning as the word line WL8.

[0175] For example, let the distance between the upper end of an adjacent memory pillar MP (upper memory pillar UMP) and the upper end of the member SLT (uppermost member TSLT) be the same L0 as in the comparative example of (a). Let the distance between the memory pillar MP and the member SLT at the boundary BDm1 be L1b. Let the distance between the memory pillar MP and the member SLT at the boundary BDm2 be L2b. The distance L0 and the distance L1b are in the relationship of L0 < L1b. Similarly, the distance L0 and the distance L2b are in the relationship of L0 < L2b.

[0176] When comparing the distance L1a and the distance L1b, similar to the description using FIG. 8 of the first embodiment, the relationship of L1a > L1b is obtained. Also, when comparing the distance L2a and the distance L2b, the relationship of L2a > L2b is obtained.

[0177] 2.4 Method for manufacturing a memory cell array Next, an example of a manufacturing method of the memory cell array 11 will be described with reference to FIGS. 41 to 74. FIGS. 41 and 42 are flowcharts showing an example of a manufacturing process of the memory cell array 11. FIGS. 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, and 73 are diagrams showing an example of a planar layout of the memory cell array 11 in the manufacturing process of the memory cell array 11. FIG. 44 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 43. FIG. 46 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 45. FIG. 48 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 47. FIG. 50 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 49. FIG. 52 is a cross-sectional view taken along lines A1-A2 and B1-B2 in FIG. 51. FIG. 54 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 53. FIG. 56 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 55. FIG. 58 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 57. FIG. 60 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 59. FIG. 62 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 61. FIG. 64 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 63. FIG. 66 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 65. FIG. 68 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 67. FIG. 70 is a cross-sectional view taken along lines A1-A2 and B1-B2 of FIG. 69. Fig. 72 is a cross-sectional view taken along lines A1-A2 and B1-B2 in Fig. 71. Fig. 74 is a cross-sectional view taken along lines A1-A2 and B1-B2 in Fig. 73. Note that in the cross-sectional views of the manufacturing process shown below, some of the support pillars HR that pass through each terrace are omitted to simplify the drawings.

[0178] In the following description, of the stack consisting of 12 wiring layers 34 and 12 insulating layers 35, the structure consisting of the three lower wiring layers 34a and the three insulating layers 35 provided thereon will be referred to as the "first stack." The structure consisting of the top wiring layer 34a and the insulating layer 35 provided thereon will be referred to as the "second stack." The structure consisting of the two wiring layers 34b and the two insulating layers 35 provided thereon will be referred to as the "third stack." The structure consisting of the two wiring layers 34c and the two insulating layers 35 provided thereon will be referred to as the "fourth stack." The structure consisting of the bottom wiring layer 34d and the insulating layer 35 provided thereon will be referred to as the "fifth stack." The structure consisting of the top three wiring layers 34d and the three insulating layers 35 provided thereon will be referred to as the "sixth stack."

[0179] As shown in FIG. 41, first, a first laminate is formed (S201).

[0180] 43 and 44, three sacrificial films 60a and three insulating layers 35 are alternately stacked one by one on the insulating layer 33 as a first stack before WL replacement. LCA In the WL replacement, the wiring layers 34a are replaced with three wiring layers 34a that function as the select gate lines SGS and the word lines WL0 and WL1, respectively.

[0181] As shown in FIG. 41, after step S201 is executed, the lower layer T LCA A staircase portion corresponding to the above is formed (S202).

[0182] 45 and 46, the first stacked body is processed into steps to form terraces corresponding to the three-layer sacrificial film 60a. That is, terraces corresponding to the select gate line SGS and word line WL0 are processed.

[0183] 41, after step S202 is performed, the processing of the lower support pillar LHR and filling with the sacrificial film 62, the processing of the lower member LSLT and filling with the sacrificial film 63, and the processing of the lower contact plug LCC and filling with the sacrificial film 64 are sequentially performed (S203). Note that the order of processing the lower support pillar LHR, the lower member LSLT, and the lower contact plug LCC and filling with the sacrificial films 62 to 64 is arbitrary.

[0184] As shown in FIGS. 47 and 48, the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP. Next, in the connection region CA, holes corresponding to the lower support pillars LHR are formed and the holes are filled with a sacrificial film 62. For example, the bottom ends of the holes corresponding to the lower support pillars LHR reach the semiconductor layer 32a. Next, slits corresponding to the lower members LSLT are formed and the slits are filled with a sacrificial film 63. The bottom ends of the slits corresponding to the lower members LSLT reach the insulating layer 50. Next, in the connection region CA, holes corresponding to the lower contact plugs LCC are formed and the holes are filled with a sacrificial film 64. The bottom ends of the lower contact plugs LCC reach the terraces of the corresponding sacrificial film 60a (wiring layer 34a). The lower contact plugs LCC are provided on the terraces of the select gate line SGS and word lines WL0 and WL1, but not on the terraces of the word lines WL2 to WL9 and select gate line SGD.

[0185] 41, after step S203 is performed, a second stack is formed (S204). As the second stack before WL replacement, one sacrificial film 60a and one insulating layer 35 are stacked. In WL replacement, the sacrificial film 60a is replaced with a wiring layer 34a that functions as the word line WL2.

[0186] After step S204 is performed, similar to step S102 described with reference to FIG. 9 of the first embodiment, memory holes LMH corresponding to the lower memory pillars LMP are processed (formed), and the memory holes LMH are filled with the sacrificial film 61 (S205).

[0187] 49 and 50, a memory hole corresponding to the lower memory pillar LMP is formed in the memory cell region MA. Then, a sacrificial film 61 is buried inside the memory hole.

[0188] As shown in FIG. 41, after step S205 is performed, a third stack is formed (S206).

[0189] 51 and 52, as a third stack before WL replacement, two sacrificial films 60b and two insulating layers 35 are alternately stacked one by one. In WL replacement, the two sacrificial films 60b are replaced with two wiring layers 34b that function as word lines WL3 and WL4, respectively.

[0190] As shown in FIG. 41, after step S206 is executed, the middle layer T MCA A staircase portion corresponding to the above is formed (S207).

[0191] 53 and 54, the second and third stacked bodies are processed into steps to form terraces corresponding to the sacrificial film 60a and the two sacrificial films 60b. That is, terraces corresponding to the word lines WL1 to WL3 are processed.

[0192] 41, after step S207 is performed, the processing of the middle support pillar MHR and filling with the sacrificial film 62, the processing of the middle member MSLT and filling with the sacrificial film 63, and the processing of the middle contact plug MCC and filling with the sacrificial film 64 are sequentially performed (S208). Note that the order of processing the middle support pillar MHR, the middle member MSLT, and the middle contact plug MCC and filling with the sacrificial films 62 to 64 is arbitrary.

[0193] 55 and 56, the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP. Next, in the connection region CA, holes corresponding to the middle support pillars MHR are formed and the holes are filled with a sacrificial film 62. Next, slits corresponding to the middle members MSLT are formed and the slits are filled with a sacrificial film 63. Next, in the connection region CA, holes corresponding to the middle contact plugs MCC are formed and the holes are filled with a sacrificial film 64.

[0194] As shown in FIG. 41, after step S208 is performed, a fourth stack is formed (S209).

[0195] 57 and 58, as a fourth stack before WL replacement, two sacrificial films 60c and two insulating layers 35 are alternately stacked one by one. In WL replacement, the two sacrificial films 60c are replaced with two wiring layers 34c that function as word lines WL5 and WL6, respectively.

[0196] As shown in FIG. 41, after step S209 is performed, similar to step S107 described using FIG. 9 of the first embodiment, memory holes corresponding to the middle memory pillars MMP are processed (formed), and the memory holes are filled with a sacrificial film 61 (S210).

[0197] As shown in Figures 59 and 60, a memory hole corresponding to the mid-level memory pillar MMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the mid-level memory pillar MMP reaches the lower memory pillar LMP. Next, the memory hole corresponding to the mid-level memory pillar MMP is filled with a sacrificial film 61. In other words, a stacked structure of the lower memory pillar LMP and the mid-level memory pillar MMP filled with the sacrificial film 61 is formed.

[0198] As shown in FIG. 41, after step S210 is performed, a fifth stack is formed (S211).

[0199] 61 and 62, as a fifth stack before WL replacement, one sacrificial film 60d and one insulating layer 35 are stacked. In WL replacement, the sacrificial film 60d is replaced with a wiring layer 34d that functions as a word line WL7.

[0200] As shown in FIG. 42, after step S211 is executed, the upper layer T UCA A staircase portion corresponding to the above is formed (S212).

[0201] 63 and 64, the fourth and fifth stacked bodies are processed into steps to form terraces corresponding to the two sacrificial film layers 60c and the one sacrificial film layer 60d. That is, terraces corresponding to the word lines WL4 to WL6 are processed.

[0202] 42, after step S212 is performed, the upper support pillar UHR is processed and filled with a sacrificial film 62, the upper member USLT is processed and filled with a sacrificial film 63, and the upper contact plug UCC is processed and filled with a sacrificial film 64 are sequentially performed (S213). Note that the order of processing the upper support pillar UHR, the upper member USLT, and the upper contact plug UCC and filling with the sacrificial films 62 to 64 is arbitrary.

[0203] As shown in Figures 65 and 66, the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP. Next, in the connection region CA, holes corresponding to the upper support pillars UHR are formed and the holes are filled with a sacrificial film 62. Next, slits corresponding to the upper members USLT are formed and the slits are filled with a sacrificial film 63. Next, in the connection region CA, holes corresponding to the upper contact plugs UCC are formed and the holes are filled with a sacrificial film 64.

[0204] As shown in FIG. 42, after step S213 is performed, a sixth stack is formed (S214).

[0205] 67 and 68, as a sixth stack before WL replacement, three sacrificial films 60d and three insulating layers 35 are alternately stacked one by one. In WL replacement, the three sacrificial films 60d are replaced with three wiring layers 34d that function as word lines WL8 and WL9 and select gate line SGD, respectively.

[0206] As shown in FIG. 42, after step S214 is executed, the top layer T TCA A staircase portion corresponding to the above is formed (S215).

[0207] 69 and 70, the sixth stack is processed into steps to form terraces corresponding to the three sacrificial films 60d. That is, terraces corresponding to the word lines WL7 to WL9 are processed.

[0208] 42, after step S215 is performed, the top support pillar THR is processed and filled with a sacrificial film 62, the top member TSLT is processed and filled with a sacrificial film 63, and the top contact plug TCC is processed and filled with a sacrificial film 64 are sequentially performed (S216). Note that the order of processing the top support pillar THR, the top member TSLT, and the top contact plug TCC and filling with the sacrificial films 62 to 64 is arbitrary.

[0209] As shown in Figures 71 and 72, the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP. Next, in the connection region CA, a hole corresponding to the top support pillar THR is formed and the hole is filled with a sacrificial film 62. This forms a support pillar HR filled with the sacrificial film 62. Next, a slit corresponding to the top member TSLT is formed and the slit is filled with a sacrificial film 63. This forms a member SLT filled with the sacrificial film 63. Next, in the connection region CA, a hole corresponding to the top contact plug TCC is formed and the hole is filled with a sacrificial film 64. This forms a contact plug CC filled with the sacrificial film 64.

[0210] As shown in FIG. 42, after step S216 is performed, similar to step S111 described using FIG. 9 of the first embodiment, memory holes corresponding to the upper memory pillars UMP are processed (formed) to form memory pillars MP (S217).

[0211] As shown in Figures 73 and 74, a memory hole corresponding to the upper memory pillar UMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the upper memory pillar UMP reaches the middle memory pillar MMP. Next, the sacrificial film 61 in the memory hole is removed. Next, a stacked film 42, a semiconductor film 41, and a core film 40 are formed to fill the memory hole and form the memory pillar MP.

[0212] As shown in FIG. 9, after step S217 is performed, the sacrificial film 62 inside the support pillar HR is removed, and the inside of the hole is filled with an insulator 38 (S218), similar to step S112 described with reference to FIG. 9 in the first embodiment.

[0213] Next, similarly to step S113 described with reference to FIG. 9 in the first embodiment, the sacrificial film 63 in the member SLT is removed (S219).

[0214] Next, similarly to step S114 described with reference to FIG. 9 in the first embodiment, SL replacement and WL replacement are executed in sequence (S220).

[0215] Next, similarly to step S115 described with reference to FIG. 9 in the first embodiment, the spacers SP and the conductors LI are embedded in the member SLT (S221).

[0216] 9 of the first embodiment, the sacrificial film 64 in the contact plug CC is removed, and the hole is filled with a conductor 39 (S222). This completes the structure of the memory cell array 11 described with reference to FIGS. 38 and 39.

[0217] 2.5 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0218] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a structure of the contact plug CC different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0219] 3.1 Planar layout of the connection area First, an example of a planar layout of the connection region CA1 will be described with reference to FIG. 75. FIG. 75 is a plan view showing an example of a planar layout of the connection region CA1. FIG. 75 shows the connection region CA1 corresponding to one block BLK and a part of the memory cell region MA located in the vicinity thereof. Note that, in the example shown in FIG. 75, for the sake of simplicity, one member SHE is provided in the block BLK. That is, the block BLK includes two string units SU. Also, in the example shown in FIG. 75, part of the interlayer insulating film is omitted.

[0220] As shown in Figure 75, in the connection area CA1, terraces corresponding to the select gate line SGD, the word lines WL9 to WL0, and the select gate line SGS are arranged in order from the memory cell area MA toward the end in the X direction (the right side of the paper), as in the first embodiment.

[0221] The configurations and arrangements of the memory pillars MP, members SLT and SHE in the memory cell area MA, and the support pillars HR in the connection area CA1 are the same as those in the first embodiment.

[0222] The contact plugs CC in this embodiment are contacts that extend in the Z direction and penetrate the terrace of the corresponding wiring layer 34 and the wiring layer 34 located below it. For example, the contact plugs CC have protruding portions that protrude concentrically on the XY plane at the connection portions with the corresponding terraces. The contact plugs CC are electrically connected to the corresponding terraces via the protruding portions, but are not electrically connected to the underlying wiring layer 34. Furthermore, the bottom ends of the contact plugs CC reach the semiconductor layer 32, but are not electrically connected to the semiconductor layer 32. That is, the contact plugs CC are electrically connected to the terrace of the wiring layer 34 that corresponds to any one of the select gate line SGS, the word lines WL0 to WL9, and the select gate line SGD.

[0223] 3.2 Cross-sectional structure of the connection area Next, an example of the cross-sectional configuration of the connection area CA will be described with reference to Fig. 76. Fig. 76 is a cross-sectional view of the connection area CA1 taken along line B1-B2 in Fig. 75. Note that in the example shown in Fig. 76, the support pillars HR are omitted for the sake of simplicity.

[0224] As shown in FIG. 76, a stepped portion is formed in the connection region CA by terraces (plug connection portions) of the multiple wiring layers 34. In the wiring layer 34 of this embodiment, the terraces are thickened. That is, the wiring layer 34 includes a first portion P1 in the center extending in the X direction and a second portion P2 provided at an end (terrace) of the first portion P1 in the X direction, and the film thickness of the second portion P2 is thicker than the film thickness of the first portion P1. No second portion P2 (thick film portion) of another wiring layer 34 is provided above or below the second portion P2. The second portions P2 of the multiple wiring layers 34 are arranged side by side in the X direction. Two second portions P2 adjacent to each other in the X direction are separated from each other by a distance LS in the X direction so as not to be electrically connected. Note that the distance LS is arbitrary.

[0225] The contact plugs CC pass through the corresponding second portions P2 (terraces) and the first portions P1 of another wiring layer 34 located below the second portions P2. Hereinafter, such contact plugs CC will also be referred to as "through contacts." The heights of the contact plugs CC corresponding to the respective terraces are approximately the same. The contact plugs CC have protruding portions PR provided in the same layer as the second portions P2. The protruding portions PR have an approximately cylindrical shape. The side surfaces of the protruding portions PR contact the second portions P2. The lower surfaces of the protruding portions PR may be electrically connected to the terraces. The film thickness (height) of the protruding portions PR is approximately the same as that of the second portions P2.

[0226] An insulator 71 is provided between the contact plug CC and the first portion P1 of the wiring layer 34 through which the contact plug CC penetrates. The insulator 71 has an annular shape that surrounds the side surface of the contact plug CC. The insulator 71 prevents the contact plug CC from being electrically connected to the first portion P1 of the wiring layer 34.

[0227] The lower end of the contact plug CC reaches, for example, the semiconductor layer 32a. An insulator 70 is provided between the contact plug CC and the semiconductor layers 32a and 32c. The insulator 70, which is provided in the same layer as the semiconductor layer 32c, surrounds the side surfaces of the contact plug CC. The insulator 70, which is provided in the same layer as the semiconductor layer 32a, surrounds the side surfaces and bottom surface of the contact plug CC. The insulator 70 prevents the contact plug CC from being electrically connected to the semiconductor layer 32. For example, the insulators 70 and 71 contain silicon oxide.

[0228] The contact plug CC includes a lower contact plug LCC and an upper contact plug UCC, similarly to the first embodiment.

[0229] 3.3 Manufacturing method of contact plug Next, a method for manufacturing the contact plugs CC will be described with reference to Figures 77 to 81. Figures 77 to 81 are diagrams showing an example of a cross-sectional configuration of the connection region CA in the manufacturing process of the memory cell array 11. In the following explanation, the process from processing the lower contact plugs LCC to burying them with the sacrificial film 64 will be described. Note that in the cross-sectional views of the manufacturing process shown below, the support pillars HR are omitted to simplify the drawings.

[0230] The overall flow of the manufacturing method of the memory cell array 11 of the third embodiment is the same as the flowchart of the first embodiment described with reference to Fig. 9. The steps in step S104, the method of processing the lower contact plugs LCC in step S105, the step in step S109, and the method of processing the upper contact plugs UCC in step S110 are different from those in the first embodiment.

[0231] 77, for example, the same steps as steps S101 to S103 described with reference to FIG. 9 of the first embodiment are performed up to the deposition of the lower layer of the intermediate stacked body. Next, in step S104, first, the lower layer T LCA More specifically, the lower layers of the lower stack and the middle stack are processed into steps to form terraces corresponding to the plurality of sacrificial films 60a and 60b. Next, the second portion P2 is formed by the sacrificial films 60a and 60b. More specifically, after the terraces of the sacrificial films 60a and 60b are exposed, the sacrificial film 60 is formed and the entire surface is covered with the sacrificial film 60. Next, the sacrificial film 60 is processed to form the second portion P2.

[0232] As shown in FIG. 78, first, the stepped portion is filled with an insulating layer 37 and planarized by, for example, CMP. Next, holes corresponding to the lower contact plugs LCC are formed in step S105, the process of processing the lower contact plugs LCC and filling with a sacrificial film 64 described with reference to FIG. 9 of the first embodiment. In this embodiment, holes corresponding to the lower contact plugs LCC are formed at positions corresponding to the terraces of the select gate lines SGS, word lines WL0 to WL9, and select gate lines SGD. The bottom ends of the holes reach the semiconductor layer 32a. Next, the semiconductor layers 32a and 32c exposed below the holes corresponding to the lower contact plugs LCC are oxidized to form an insulator 70.

[0233] As shown in FIG. 79, recess etching is performed on the sacrificial films 60a and 60b from the side surface of the hole corresponding to the lower contact plug LCC.

[0234] As shown in FIG. 80, an insulator 71 is formed to fill recess regions corresponding to the first portions P1 of the sacrificial films 60a and 60b. More specifically, for example, the insulator 71 is conformally formed to a thickness equal to or greater than half the thickness of the first portions P1 and less than half the thickness of the second portions P2. As a result, the recess portions of the first portions P1 are filled with the insulator 71, and the recess portions of the second portions P2 are not filled with the insulator 71. In this state, wet etching is performed on the insulator 71 to remove the insulator 71 from the side surfaces of the holes corresponding to the lower contact plugs LCC and from the recess portions of the second portions P2.

[0235] As shown in FIG. 81, the hole corresponding to the lower contact plug LCC is filled with a sacrificial film 64.

[0236] Steps S106 to S108 are the same as those explained with reference to FIG. 9 in the first embodiment.

[0237] In steps S109 and S110, the same processes as in steps S104 and S105 are performed to form through contact plugs CC filled with the sacrificial film 64.

[0238] The steps from step S111 onwards are the same as those explained with reference to FIG. 9 in the first embodiment.

[0239] 3.4 Effects of this embodiment The effects according to this embodiment are similar to those of the first embodiment.

[0240] 3.5 Modification of the third embodiment Next, two modified examples of the third embodiment will be described. In the two modified examples, the film thicknesses of the insulating layers 35 formed on the multiple wiring layers 34 are different. The following description will focus on the differences from the third embodiment.

[0241] 3.5.1 First variant First, the first modification will be described. In the first modification, each layer (lower layer T LMP , medium hierarchy T MMP , upper layer T UMP , lower hierarchy T LCA , and the upper hierarchy T UCA A case where the uppermost insulating layer 35 of the insulating layer 35 is thicker than the other insulating layers 35 will be described.

[0242] An example of the cross-sectional configuration of the memory cell array 11 will be described with reference to Figures 82 and 83. Figure 82 is a diagram showing an example of the cross-sectional configuration of a memory cell region MA. Figure 83 is a diagram showing an example of the cross-sectional configuration of a connection region CA1. Note that in the example shown in Figure 83, the support pillars HR are omitted to simplify the explanation.

[0243] As shown in FIGS. 82 and 83 , in this modification, when depositing the stack (corresponding to steps S101, S103, S106, and S108 in FIG. 9 ), the uppermost insulating layer 35 is made thicker than the lower insulating layer 35. The other manufacturing methods are the same as those of the third embodiment. More specifically, for example, in step S101, when depositing the lower stack, the insulating layer 35 provided on the sacrificial film 60a to be replaced by the wiring layer 34a functioning as the word line WL2 is made thicker than the lower insulating layer 35. In step S103, when depositing the lower layer of the middle stack, the insulating layer 35 provided on the sacrificial film 60b to be replaced by the wiring layer 34b functioning as the word line WL4 is made thicker than the lower insulating layer 35. In step S106, when depositing the upper layers of the intermediate stack, the insulating layer 35 provided on the sacrificial film 60c to be replaced by the wiring layer 34c functioning as the word line WL6 is made thicker than the lower insulating layer 35. In step S108, when depositing the upper stack, the insulating layer 35 provided on the sacrificial film 60d to be replaced by the wiring layer 34d functioning as the select gate line SGD is made thicker than the lower insulating layer 35.

[0244] For example, the thickness of each of the insulating layers 35 provided on the sacrificial films 60 to be replaced by the wiring layers 34 that function as the word lines WL2, WL4, and WL6 and the select gate line SGD is defined as T1. The thickness of each of the other insulating layers 35 is defined as T2. In this case, the thicknesses T1 and T2 have a relationship of T1 > T2. Note that the insulating layers 35 to be thickened are not limited to these. For example, the topmost insulating layer 35 during each staircase processing may be thicker than the underlying insulating layers 35 in accordance with the number of staircase processing steps performed in the connection region CA.

[0245] 3.5.2 Second variant Next, a second modification will be described. In the second modification, the lower layer T corresponding to the connection area CA LCA and upper hierarchy T UCA A case where the uppermost insulating layer 35 is thicker than the other insulating layers 35 will be described.

[0246] An example of the cross-sectional configuration of the memory cell array 11 will be described with reference to Figures 84 and 85. Figure 84 is a diagram showing an example of the cross-sectional configuration of a memory cell region MA. Figure 85 is a diagram showing an example of the cross-sectional configuration of a connection region CA1. Note that in the example shown in Figure 85, the support pillars HR are omitted to simplify the explanation.

[0247] As shown in FIGS. 84 and 85 , in this modification, when forming the lower layer and upper stack of the intermediate stack (corresponding to steps S103 and S108 in FIG. 9 ), the uppermost insulating layer 35 is made thicker than the lower insulating layer 35. The other manufacturing methods are the same as those of the third embodiment. More specifically, for example, in step S103, when forming the lower layer of the intermediate stack, the insulating layer 35 provided on the sacrificial film 60b to be replaced by the wiring layer 34b functioning as the word line WL4 is made thicker than the lower insulating layer 35. Furthermore, in step S108, when forming the upper stack, the insulating layer 35 provided on the sacrificial film 60d to be replaced by the wiring layer 34d functioning as the select gate line SGD is made thicker than the lower insulating layer 35.

[0248] For example, the thickness of each insulating layer 35 provided on each sacrificial film 60 to be replaced by the wiring layer 34 functioning as the word line WL4 and the select gate line SGD is defined as T1. The thickness of the other insulating layer 35 is defined as T2. In this case, the relationship between the thickness T1 and the thickness T2 is T1>T2.

[0249] 3.5.3 Effects of the First and Second Modifications The configurations according to the first and second modifications can provide the same effects as the first embodiment.

[0250] In the configuration according to the first modification, by forming the insulating layers 35 with a thicker film thickness in part, it is possible to suppress thinning of the insulating layers 35, for example, when processing the memory pillars MP, the members SLT, the support pillars HR, and the contact plugs CC, or when planarizing the insulating layers 37 by CMP or the like. Furthermore, in the configuration according to the first modification, by thickening the insulating layers 35 corresponding to the boundaries between two hierarchical levels, it is possible to ensure, for example, an area between the lower memory pillar LMP and the mid-level memory pillar MMP for forming a connection portion that connects the lower memory pillar LMP and the mid-level memory pillar MMP.

[0251] The configuration according to the second modification can suppress thinning of the insulating layer 35 due to, for example, processing of the member SLT, the support pillar HR, and the contact plug CC, or planarization of the insulating layer 37 by CMP or the like.

[0252] The first and second modified examples can be applied to the first or second embodiment.

[0253] 4. Fourth embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a structure of the memory cell array 11 different from those of the first and third embodiments will be described. The following description will focus on the differences from the first and third embodiments.

[0254] 4.1 Planar layout of the connection area First, an example of a planar layout of the connection area CA1 will be described with reference to FIG. 86. FIG. 86 is a plan view showing an example of a planar layout of the connection area CA1. FIG. 86 shows the connection area CA1 corresponding to one block BLK and a part of the memory cell area MA located in the vicinity thereof. Note that, in the example shown in FIG. 86, for the sake of simplicity, one member SHE is provided in the block BLK. That is, the block BLK includes two string units SU.

[0255] As shown in FIG. 86, in the connection region CA1, from the memory cell region MA toward the end in the X direction (the right side of the drawing), plug connection portions corresponding to the select gate line SGD, the word lines WL9 to WL0, and the select gate line SGS are provided in this order. However, in this embodiment, no staircase is formed by the stacked body in the connection region CA. In other words, no terrace is provided. In this embodiment, another wiring layer 34 is provided above the plug connection portions corresponding to the select gate line SGS and the word lines WL0 to WL9.

[0256] The planar layout of the memory pillars MP, members SLT and SHE, support pillars HR, and contact plugs CC is the same as that of the first embodiment.

[0257] The contact plugs CC of this embodiment extend in the Z direction, pass through the wiring layer 34 located above the plug connection portion of the corresponding wiring layer 34, and have their lower ends in contact with the plug connection portion. Therefore, similar to the first embodiment, the height of the contact plugs CC varies depending on the corresponding plug connection portion (wiring layer 34). Sidewalls made of an insulator are provided on the sides of the contact plugs CC. The sidewalls prevent the contact plugs CC from being electrically connected to the wiring layer 34 located above the plug connection portion. In other words, the contact plugs CC are electrically connected to the plug connection portions of the wiring layer 34 corresponding to any one of the select gate line SGS, word lines WL0 to WL9, and select gate line SGD.

[0258] 4.2 Cross-sectional structure of the connection area Next, an example of the cross-sectional configuration of the connection region CA will be described with reference to FIG. 87. FIG. 87 is a cross-sectional view of the connection region CA1 taken along line B1-B2 in FIG. 86. In the example shown in FIG. 87, similar to FIG. 7, two support pillars HR passing through the terrace of the select gate line SGD are shown so as to coincide with the cross section taken along line B1-B2. In contrast, in each terrace of the word lines WL0 to WL9 and the select gate line SGS, in order to simplify the drawing, some of the support pillars HR are omitted, and only one support pillar HR passing through each terrace is shown. Although some of the support pillars HR are omitted from each terrace of the word lines WL0 to WL9 and the select gate line SGS, support pillars HR and contact plugs CC are provided on each terrace in the same arrangement as on the terrace of the select gate line SGD.

[0259] As shown in FIG. 87, in the connection area CA of this embodiment, no staircase is formed by the multiple wiring layers 34. In other words, the X-direction ends of the multiple wiring layers 34 are not drawn out in a staircase shape. The length of each wiring layer 34 in the X-direction is approximately the same. For this reason, in this embodiment, the insulating layer 37 is omitted.

[0260] The support pillars HR in this embodiment include lower support pillars LHR, middle support pillars MHR, and upper support pillars UHR. The middle support pillars MHR are provided on the lower support pillars LHR. The upper support pillars UHR are provided on the middle support pillars MHR. In this embodiment, the memory pillars MP and the support pillars HR have the same layer boundary position. That is, the support pillars HR, like the memory pillars MP, are located on the lower layer T. LMP , medium hierarchy T MMP , and the upper hierarchy T UMP87, the support pillar HR is embedded in the insulator 38, but it may have the same structure as the memory pillar MP. That is, the support pillar HR may be embedded in the core film 40, the semiconductor film 41, and the stacked film 42. In the connection region CA, SL replacement is not performed, that is, the insulating layer 50 is not replaced with the semiconductor layer 32b. Therefore, even if the support pillar HR has the same structure as the memory pillar MP, the support pillar HR is not electrically connected to the semiconductor layer 32.

[0261] The lower support pillar LHR, like the lower memory pillar LMP, LMP That is, the lower support pillar LHR passes through four wiring layers 34a that function as the select gate lines SGS and the word lines WL0 to WL2. The lower surfaces of the lower support pillars LHR reach, for example, the semiconductor layer 32a.

[0262] The middle support pillar MHR, like the middle memory pillar MMP, MMP That is, the middle support pillar MHR passes through two wiring layers 34b that function as word lines WL3 and WL4, respectively, and two wiring layers 34c that function as word lines WL5 and WL6, respectively. The bottom surface of the middle support pillar MHR contacts the top surface of the lower support pillar LHR at the boundary BDm1.

[0263] The upper support pillar UHR, like the upper memory pillar UMP, is the upper layer T UMP That is, the upper support pillar UHR passes through four wiring layers 34d which function as word lines WL7 to WL9 and select gate lines SGD. The bottom surface of the upper support pillar UHR contacts the top surface of the middle support pillar MHR at boundary BDm2.

[0264] Each of the lower support pillar LHR, middle support pillar MHR, and upper support pillar UHR has, for example, a tapered shape in which the diameter at the top end is larger than the diameter at the bottom end. In other words, each of the lower support pillar LHR, middle support pillar MHR, and upper support pillar UHR has, for example, a truncated cone shape in which the bottom surface is smaller than the top surface. Therefore, the boundaries of each of the lower support pillar LHR, middle support pillar MHR, and upper support pillar UHR can be confirmed by observing the cross-sectional shapes.

[0265] Next, the contact plugs CC will be described. In the connection region CA, a corresponding contact plug CC is provided on the plug connection portion of each wiring layer 34. In other words, the lower end of the contact plug CC is in contact with the plug connection portion of the corresponding wiring layer 34. The contact plugs CC are provided extending in the Z direction. The contact plugs CC pass through the wiring layer 34 located above the corresponding plug connection portion. The shape (height) of the contact plugs CC varies depending on the plug connection portion to be connected. The contact plugs CC include a conductor 39 and an insulator 72 covering the side surfaces of the conductor 39. The bottom surface of the conductor 39 is in contact with the corresponding plug connection portion. The insulator 72 prevents the side surfaces of the contact plugs CC from being electrically connected to the wiring layer 34 that they penetrate (pass through). For example, the insulator 72 includes silicon oxide.

[0266] The contact plug CC includes a lower contact plug LCC and an upper contact plug UCC, as in the first embodiment. Hereinafter, a case will be described in which the boundary position of the contact plug CC and the layer is the same as that of the member SLT, as in the first embodiment. Note that the boundary position of the layer of the member SLT may be the same as that of the memory pillar MP and the support pillar HR, or may be different from that of the memory pillar MP, the support pillar HR, and the contact plug CC.

[0267] 4.3 Boundary of support pillar and contact plug Next, referring to FIG. 88, the boundary between the support pillar HR and the contact plug CC will be described. FIG. 88 is a conceptual diagram showing the boundary between the support pillar HR and the contact plug CC. In FIG. 88, as a comparative example, a case where the number of boundaries of each of the support pillar HR and the contact plug CC is the same is shown. Note that the shape and the number of boundaries of the support pillar HR are the same between the comparative example and the embodiment.

[0268] First, the comparative example will be described.

[0269] As shown in (a) of FIG. 88, for example, in the comparative example, the number of layers (number of boundaries) of the support pillar HR and the contact plug CC is the same. In this case, the hierarchical boundary between the support pillar HR and the contact plug CC is located between the same wiring layers 34.

[0270] For example, the support pillar HR includes a lower support pillar LHR, a middle support pillar MHR, and an upper support pillar UHR. The contact plug CC includes a lower contact plug LCC, a middle contact plug MCC, and an upper contact plug UCC. For example, the boundary BDm1 between the lower support pillar LHR and the middle support pillar MHR is the same as the boundary between the lower contact plug LCC and the middle contact plug MCC. Also, the boundary BDm2 between the middle support pillar MHR and the upper support pillar UHR is the same as the boundary between the middle contact plug MCC and the upper contact plug UCC.

[0271] For example, let the distance between the upper end of the adjacent support pillar HR (upper support pillar UHR) and the upper end of the contact plug CC (upper contact plug UCC) be L5. Let the distance between the middle support pillar MHR and the middle contact plug MCC in the vicinity of the boundary BDm1 be L6a. Let the distance between the upper support pillar UHR and the upper contact plug UCC in the vicinity of the boundary BDm2 be L7a. Each of the support pillar HR and the contact plug CC has a tapered shape in each of the divided parts. Therefore, the relationship between the distance L5 and the distance L6a is L5 < L6a. Similarly, the relationship between the distance L5 and the distance L7a is L5 < L7a.

[0272] Next, examples will be described.

[0273] As shown in (b) of FIG. 88, in the example, the support pillar HR has three layers. The contact plug CC has two layers. In other words, the support pillar HR has two boundaries BDm1 and BDm2. The contact plug CC has one boundary BDc1. That is, the support pillar HR and the contact plug CC have different numbers of layers (numbers of boundaries).

[0274] In this case, as described using FIG. 87, the interlayer positions of the wiring layer 34 where the boundaries BDm1 and BDm2 of the support pillar HR and the boundary BDc1 of the contact plug CC are located are different from each other.

[0275] Each of the support pillar HR and the contact plug CC has a tapered shape in each of the divided parts (each layer).

[0276] For example, let the distance between the upper end of an adjacent support pillar HR (upper support pillar UHR) and the upper end of the contact plug CC (upper contact plug UCC) be the same L5 as in the comparative example of (a). Let the distance between the support pillar HR and the contact plug CC at the boundary BDm1 be L6b. Let the distance between the support pillar HR and the contact plug CC at the boundary BDm2 be L7b. The distance L5 and the distance L6b are in the relationship of L5 < L6b. Similarly, the distance L5 and the distance L7b are in the relationship of L5 < L7b.

[0277] In the comparative example (a), for example, the diameter of the middle contact plug MCC is smallest at the boundary BDm1. In contrast, in the example (b), the boundary BDm1 is located in the middle of the lower contact plug LCC. Therefore, when comparing the distance L6a and the distance L6b, the relationship L6a > L6b is established. Similarly, in the comparative example (a), the diameter of the upper contact plug UCC is smallest at the boundary BDm2. In contrast, in the example (b), the boundary BDm2 is located in the middle of the upper contact plug UCC. Therefore, when comparing the distance L7a and the distance L7b, the relationship L7a > L7b is established.

[0278] Therefore, with the structure according to this embodiment, the tapered shape can prevent the distance between the support pillar HR and the contact plug CC from increasing. In other words, by locating the boundary position of the support pillar HR and the boundary position of the contact plug CC between different wiring layers 34, the distance between the support pillar HR and the contact plug CC can be prevented from increasing. In the configuration according to this embodiment, the contact plug CC passes through the wiring layer 34 located above the plug connection portion. Therefore, the contact plug CC, like the support pillar HR, functions as a pillar supporting the stacked structure having a gap during WL replacement. By preventing the distance between the support pillar HR and the contact plug CC from increasing, the deflection of the stacked body due to WL replacement above the plug connection portion can be prevented.

[0279] 4.4 Memory cell array manufacturing method Next, a method for manufacturing the memory cell array 11 will be described with reference to FIGS. 89 to 98. FIG. 89 is a flowchart showing an example of a manufacturing process for the memory cell array 11. FIGS. 90 to 98 are diagrams showing an example of a cross-sectional configuration of the connection region CA in the manufacturing process for the memory cell array 11. Note that in the example shown in FIGS. 90 to 98, the support pillars HR are omitted for the sake of simplicity. The following description will focus on the process for processing the contact plugs CC.

[0280] As shown in FIG. 89, for example, the steps up to the lower laminated body are formed in the same manner as in step S101 described with reference to FIG. 9 of the first embodiment.

[0281] After step S101 is performed, the processing of the lower support pillar LHR and filling with the sacrificial film 62, and the processing of the lower memory pillar LMP and filling with the sacrificial film 61 are sequentially performed (S301). Note that the order of processing the lower support pillar LHR and the lower memory pillar LMP and filling with the sacrificial films 61 and 62 is arbitrary. Also, the lower support pillar LHR and the lower memory pillar LMP may be processed collectively. In this case, the holes corresponding to the lower support pillar LHR and the lower memory pillar LMP may be filled with the same sacrificial material.

[0282] After step S301 is performed, the lower layer of the intermediate laminate is formed in the same manner as described with reference to FIG. 9 in the first embodiment (S103).

[0283] After step S103 is performed, the processing of the lower member LSLT and filling with the sacrificial film 63, and the processing of the lower contact plug LCC and filling with the sacrificial film 64 are sequentially performed (S302). The processing of the lower member LSLT and the lower contact plug LCC and the filling with the sacrificial films 63 and 64 may be performed in any order. In this embodiment, when forming holes corresponding to the lower contact plug LCC and the upper contact plug UCC, the processing of the holes is performed in multiple steps. More specifically, multiple holes with different heights (depths) are formed by repeatedly etching selected holes while increasing the number of wiring layers 34 processed in one step by a power of two.

[0284] A method for processing the lower contact plug LCC will be described in detail with reference to FIGS.

[0285] 90, first, holes corresponding to the uppermost insulating layer 35 are processed in the plug connection portions of the select gate line SGS and the word lines WL0 to WL4 (0L processing shown in FIG. 90). At this stage, the sacrificial film 60 is not processed. This completes the formation of the hole for the lower contact plug LCC corresponding to the plug connection portion of the word line WL4.

[0286] As shown in FIG. 91, at the plug connection portions of the select gate line SGS and the word lines WL1 and WL3, one layer of the sacrificial film 60 and one layer of the insulating layer 35 in the holes are processed (1L processing shown in FIG. 91). 0 This completes the formation of the hole for the lower contact plug LCC corresponding to the plug connection portion of the word line WL3.

[0287] As shown in FIG. 92, at each plug connection portion of the word lines WL1 and WL2, two layers of the sacrificial film 60 and two layers of the insulating layer 35 in the hole are processed (2L processing shown in FIG. 92). 1 Two layers of the sacrificial film 60 are processed. This completes the formation of holes for the lower contact plugs LCC corresponding to the plug connection portions of the word lines WL1 and WL2.

[0288] As shown in FIG. 93, at each plug connection portion of the select gate line SGS and the word line WL0, four layers of the sacrificial film 60 and four layers of the insulating layer 35 in the hole are processed (4L processing shown in FIG. 93). 2 4L=4 layers of the sacrificial film 60 are processed. This completes the formation of holes for the lower contact plugs LCC corresponding to the plug connection portions of the select gate line SGS and the word line WL0. After the 4L processing, the holes corresponding to the lower contact plugs LCC are filled with the sacrificial film 64.

[0289] After step S302 is performed, the upper layer of the intermediate stack is deposited (S106) in the same manner as described with reference to FIG. 9 in the first embodiment.

[0290] After step S106 is performed, processing of the middle support pillar MHR and filling with the sacrificial film 62, and processing of the middle memory pillar MMP and filling with the sacrificial film 61 are sequentially performed (S303). Note that the order of processing the middle support pillar MHR and middle memory pillar MMP and filling with the sacrificial films 61 and 62 is arbitrary. Also, the middle support pillar MHR and middle memory pillar MMP may be processed collectively. In this case, the holes corresponding to the middle support pillar MHR and middle memory pillar MMP may be filled with the same sacrificial material.

[0291] After step S303 is performed, an upper stacked body is formed in the same manner as described with reference to FIG. 9 in the first embodiment (S108).

[0292] After step S108 is performed, processing of the upper member USLT and filling with the sacrificial film 63, and processing of the upper contact plug UCC and filling with the sacrificial film 64 are sequentially performed (S304). Note that the order of processing the upper member USLT and upper contact plug UCC and filling with the sacrificial films 63 and 64 is arbitrary.

[0293] A method for processing the upper contact plug UCC will be described in detail with reference to FIGS.

[0294] 94, first, holes corresponding to the insulating layer 36 and the uppermost insulating layer 35 are processed in the plug connection portions of the select gate lines SGS and SGD and the word lines WL0 to WL9 (0L processing shown in FIG. 94). At this stage, the sacrificial film 60 is not processed. This completes the formation of holes for the upper contact plugs UCC (contact plugs CC) corresponding to the plug connection portions of the select gate lines SGD.

[0295] As shown in FIG. 95, at the plug connection portions of the word lines WL5, WL7, and WL9, one layer of the sacrificial film 60 and one layer of the insulating layer 35 in the holes are processed (1L processing shown in FIG. 95). 0This completes the formation of a hole for the upper contact plug UCC (contact plug CC) corresponding to the plug connection portion of the word line WL9.

[0296] As shown in FIG. 96, at the plug connection portions of the select gate line SGS and the word lines WL0 to WL4, WL7 and WL8, two layers of the sacrificial film 60 and two layers of the insulating layer 35 in the holes are processed (2L processing shown in FIG. 96). 1 Two layers of the sacrificial film 60 are processed. This completes the formation of holes for the upper contact plugs UCC (contact plugs CC) corresponding to the plug connection portions of the word lines WL7 and WL8.

[0297] As shown in FIG. 97, at the plug connection portions of the select gate line SGS and the word lines WL0 to WL6, four layers of sacrificial film 60 and four layers of insulating layer 35 in the holes are processed (4L processing shown in FIG. 97). 2 Four layers of the sacrificial film 60 are processed. This completes the formation of holes for the upper contact plugs UCC (contact plugs CC) corresponding to the plug connection portions of the word lines WL5 and WL6. Furthermore, in the plug connection portions of the select gate line SGS and the word lines WL0 to WL4, the formation of holes for the upper contact plugs UCC, whose lower ends reach the lower contact plugs LCC, is completed.

[0298] 98, the hole corresponding to the upper contact plug UCC is filled with the sacrificial film 64. As a result, the contact plug CC filled with the sacrificial film 64 is formed.

[0299] After step S304 is performed, the upper support pillar UHR is processed and buried with the sacrificial film 62 (S305).

[0300] After step S305 is executed, similarly to the description using FIG. 9 of the first embodiment, memory holes corresponding to the upper memory pillars UMP are processed (formed) to form memory pillars MP (S111).

[0301] After step S111 is performed, the sacrificial film 62 in the support pillar HR is removed, and the holes are filled with an insulator 38 (S112), as in the description using FIG. 9 of the first embodiment. If the support pillar HR and the memory pillar MP are formed simultaneously, steps S305 and S112 are omitted. Then, in step S111, the memory pillar MP and the support pillar HR are formed simultaneously. More specifically, holes corresponding to the upper support pillar UHR and the upper memory pillar UMP are formed simultaneously. Next, the sacrificial films 61 and 62 in each hole are removed. Next, the stacked film 42, the semiconductor film 41, and the core film 40 are formed, and the holes are filled with the sacrificial films 61 and 62, and the support pillar HR and the memory pillar MP are formed simultaneously.

[0302] Steps S113 to S116 are the same as those explained with reference to FIG. 9 in the first embodiment.

[0303] 4.5 Effects of this embodiment With the configuration of this embodiment, as with the first embodiment, the number of process steps and manufacturing costs of the memory cell array can be reduced by optimizing the number of layers of the memory pillars MP, members SLT, support pillars HR, and contact plugs CC. Furthermore, with the configuration according to this embodiment, it is possible to provide a contact plug CC that passes through the wiring layer 34 provided above the plug connection portion and whose lower end contacts the plug connection portion. Furthermore, with the configuration according to this embodiment, the boundary position corresponding to the level of the support pillar HR and the boundary position corresponding to the level of the contact plug CC can be set between different wiring layers 34. This makes it possible to suppress, for example, the increase in the distance between the support pillar HR and the contact plug CC, as described with reference to FIG. 88 . Therefore, for example, it is possible to suppress bending of the stack above the plug connection portion.

[0304] 5. Modifications, etc. The semiconductor memory device according to the above embodiment includes a stacked body in which multiple wiring layers (34) and multiple insulating layers (35) are alternately stacked one by one in a first direction (Z direction), a memory pillar (MP) extending in the first direction and passing through the stacked body, and a first member (SLT) extending in the first direction and in a second direction (X direction) intersecting the first direction and dividing the stacked body in a third direction (Y direction) intersecting the first direction and the second direction. The multiple insulating layers include a first insulating layer. The multiple wiring layers include a first wiring layer (WL2) on which the first insulating layer is provided, and a second wiring layer (WL3) provided on the first insulating layer. The memory pillar includes a first sub-pillar (LMP) extending in a first direction, passing through a first wiring layer, and having an upper end located between the first wiring layer and a second wiring layer, and a second sub-pillar (MMP) provided on the first sub-pillar, extending in the first direction, and passing through the second wiring layer. The first member includes a first portion (LSLT) extending in the first and second directions, passing through the first and second wiring layers, and having an upper end located above the second wiring layer, and a second portion (USLT) provided on the first member and extending in the first and second directions within the stack.

[0305] The configuration according to the above embodiment can reduce manufacturing costs.

[0306] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0307] For example, in the above embodiment, the lower memory pillar LMP, the middle memory pillar MMP, and the upper memory pillar UMP each have a forward tapered shape in which the diameter at the top end is larger than the diameter at the bottom end, but the shape of each pillar is not limited to this. For example, the pillar may have a straight shape with a connection portion at the layer boundary, or a bowing shape in which the diameter at the middle portion in the Z direction is the largest. The same applies to the member SLT, the support pillar HR, and the contact plug CC.

[0308] Furthermore, in the above embodiment, for example, the diameter D of the upper end of the lower memory pillar LMP LMP2and the diameter D of the lower end of the middle memory pillar MMP MMP1 That is, D LMP2 >D MMP1 99 is a cross-sectional view showing the vicinity of the upper end of the lower memory pillar LMP and the vicinity of the lower end of the middle memory pillar MMP. In the example shown in FIG. 99, the diameter D LMP2 and the diameter D of the lower end of the middle memory pillar MMP MMP1 That is, D LMP2 =D MMP1 And the lower hierarchy T LMP The upper end of the lower memory pillar LMP included in the MMP At the bottom end of the mid-level memory pillar MMP included in the lower memory pillar LMP, the shape of the side surface of the lower memory pillar LMP and the shape of the side surface of the mid-level memory pillar MMP are discontinuous (i.e., in the cross section in the Z direction, the extension line of the side surface of the lower memory pillar LMP and the side surface of the mid-level memory pillar MMP are misaligned). Furthermore, the upper end of the lower memory pillar LMP has an inverse tapered shape (a shape in which the diameter of the upper side is smaller than the diameter of the lower side). Even in such a case, the boundary BDm1 between the lower memory pillar LMP and the mid-level memory pillar MMP can be confirmed by observing the shape of the cross section. The same applies to the relationship between the mid-level memory pillar MMP and the upper memory pillar UMP. The same also applies to the member SLT, the support pillar HR, and the contact plug CC.

[0309] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0310] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0311] 1...semiconductor memory device, 10...memory core section, 11...memory cell array, 12...row decoder, 13...sense amplifier, 20...peripheral circuit section, 21...sequencer, 22...voltage generation circuit, 30...substrate, 31, 33, 35, 36, 37, 50, 50a, 50b, 50c...insulating layer, 32, 32a to 32c...semiconductor layer, 34, 34a, 34b, 34c, 34d...wiring layer, 38, 70, 7 1, 72...insulator, 39, LI...conductor, 40...core film, 41...semiconductor film, 42...laminated film, 43...tunnel insulating film, 44...charge storage film, 45...block insulating film, 60, 60a, 60b, 60c, 60d, 61 to 64...sacrificial film, BL, BL0 to BLm...bit line, BLK, BLK0 to BLK3...block, CA1, CA2...connection region, CC...contact plug, HR...support pin LCC...lower contact plug, LHR...lower support pillar, LMP...lower memory pillar, LSLT...lower member, MA...memory cell area, MC, MC0 to MC9...memory cell transistor, MCC...middle contact plug, MHR...middle support pillar, MMP...middle memory pillar, MP...memory pillar, MSLT...middle member, SGD, SGD0 to SGD5, SGS...select gate line, SHE, SLT...member, SP...spacer, ST1, ST2...select transistor, SU, SU0 to SU5...string unit, TCC...top contact plug, THR...top support pillar, TSLT...top member, UCC...upper contact plug, UHR...upper support pillar, UMP...upper memory pillar, USLT...upper member, WL, WL0 to WL9...word line

Claims

1. a laminate in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked one by one in a first direction; a memory pillar extending in the first direction and passing through the stack; a first member that stretches in the first direction and a second direction intersecting the first direction and that divides the laminate in a third direction intersecting the first direction and the second direction; Equipped with the plurality of insulating layers includes a first insulating layer; The plurality of wiring layers include: a first wiring layer on which the first insulating layer is provided; a second wiring layer provided on the first insulating layer; Including, The memory pillar is a first sub-pillar extending in the first direction, passing through the first wiring layer, and having an upper end located between the first wiring layer and the second wiring layer; a second sub-pillar provided on the first sub-pillar, extending in the first direction, and passing through the second wiring layer; Including, The first member is a first portion extending in the first direction and the second direction, passing through the first wiring layer and the second wiring layer, and having an upper end located above the second wiring layer; a second portion provided on the first portion and extending in the first direction and the second direction within the laminate; Including, Semiconductor memory device.

2. a first contact plug extending in the first direction and electrically connected to the first wiring layer; The first contact plug is a first sub-plug electrically connected to the first wiring layer, extending in the first direction, and having an upper end located above the second wiring layer; a second sub-plug provided on the first sub-plug and extending in the first direction; Including, 2. The semiconductor memory device according to claim 1.

3. the plurality of insulating layers further includes a second insulating layer; The plurality of wiring layers include: a third wiring layer provided above the second wiring layer and having the second insulating layer provided thereon; a fourth wiring layer provided on the second insulating layer; Further comprising: the second sub-pillar passes through the third wiring layer, and an upper end of the second sub-pillar is located between the third wiring layer and the fourth wiring layer; the memory pillar further includes a fifth sub-pillar provided on the second sub-pillar, extending in the first direction, and passing through the fourth wiring layer; the second portion of the first member passes through the third wiring layer and the fourth wiring layer, and an upper end of the second portion is located above the plurality of wiring layers; 2. The semiconductor memory device according to claim 1.

4. a laminate in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked one by one in a first direction; a memory pillar extending in the first direction and passing through the stack; a support pillar extending in the first direction, passing through the stacked body, and not electrically connected to the plurality of wiring layers; Equipped with The laminate is a memory region including the memory pillar; a staircase region arranged next to the memory region in a second direction intersecting the first direction, the staircase region including the support pillar, and in which a portion of each of the plurality of wiring layers is provided in a staircase shape; Including, the plurality of insulating layers includes a first insulating layer; The plurality of wiring layers include: a first wiring layer on which the first insulating layer is provided; a second wiring layer provided on the first insulating layer; Including, The memory pillar is a first sub-pillar extending in the first direction, passing through the first wiring layer, and having an upper end located between the first wiring layer and the second wiring layer; a second sub-pillar provided on the first sub-pillar, extending in the first direction, and passing through the second wiring layer; Including, The support pillar is a third sub-pillar extending in the first direction, passing through the first wiring layer and the second wiring layer, and having an upper end located above the second wiring layer; a fourth sub-pillar provided on the third sub-pillar and extending in the first direction; and Including, Semiconductor memory device.

5. a laminate in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked one by one in a first direction; a memory pillar extending in the first direction and passing through the stack; a support pillar extending in the first direction, passing through the stacked body, and not electrically connected to the plurality of wiring layers; a first contact plug extending in the first direction and electrically connected to any one of the plurality of wiring layers; Equipped with the plurality of insulating layers includes a first insulating layer; The plurality of wiring layers include: a first wiring layer on which the first insulating layer is provided; a second wiring layer provided on the first insulating layer; Including, The support pillar is a first sub-pillar extending in the first direction, passing through the first wiring layer, and having an upper end located between the first wiring layer and the second wiring layer; a second sub-pillar provided on the first sub-pillar, extending in the first direction, and passing through the second wiring layer; Including, The first contact plug is a first sub-plug extending in the first direction, passing through the second wiring layer, not electrically connected to the second wiring layer, having a lower end electrically connected to the first wiring layer and an upper end located above the second wiring layer; a second sub-plug provided on the first sub-plug and extending in the first direction; Including, Semiconductor memory device.

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