Semiconductor device and semiconductor apparatus including the same

Abstract

To provide a semiconductor element with improved reliability, and a semiconductor device including the same.SOLUTION: The semiconductor device includes a memory cell array region including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, and a peripheral circuit region including a first semiconductor device of a first device region and a second semiconductor device of a second device region, wherein each of the semiconductor devices 200 includes a substrate 203, a fin structure 205 extending in a first direction on the substrate, a gate structure 210 including a gate dielectric layer and a gate metal layer extending in a second direction orthogonal to the first direction on the fin structure, and a source region 220 and a drain region 230 formed in the substrate at both ends of the fin structure and spaced apart from each other. A thickness of the gate dielectric layer included in the first semiconductor device may be greater than a thickness of the gate dielectric layer included in the second semiconductor device, and the source region and the drain region included in the first semiconductor device may be doped with impurities of the first conductivity type to have different structures.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor element and a semiconductor device including the same. [Background technology]

[0002] Semiconductor devices are an important part of the electronics industry, and memory devices that store data and processors that process data are all implemented as semiconductor devices. FINFET devices are used as semiconductor devices to improve integration, and research into FINFET devices that can operate under high voltage conditions is particularly active. FINFET devices that operate under high voltages need to address characteristics such as HCI (Hot Carrier Injection) and GIDL (Gate Induced Drain Leakage), which affect device reliability. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a semiconductor element with improved reliability and a semiconductor device including the same. [Means for solving the problem]

[0004] In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes: a memory cell array region including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; and a peripheral circuit region including a first semiconductor element in a first element region and a second semiconductor element in a second element region, wherein each of the first semiconductor element and the second semiconductor element includes a substrate, a fin structure extending in a first direction parallel to an upper surface of the substrate, a gate structure including a gate dielectric layer and a gate metal layer extending on the fin structure in a second direction parallel to an upper surface of the substrate and perpendicular to the first direction, the gate structure including a gate dielectric layer and a gate metal layer, and a source region and a drain region spaced apart from each other in the first direction at both ends of the fin structure in the substrate, wherein in a third direction perpendicular to the upper surface of the substrate, a thickness of the gate dielectric layer included in the first semiconductor element is greater than a thickness of the gate dielectric layer included in the second semiconductor element, and the source region and the drain region included in the first semiconductor element have different structures by being doped with impurities of a first conductivity type.

[0005] In order to achieve the above-mentioned object, one aspect of the present invention provides a semiconductor device comprising: a substrate; a fin structure extending on the substrate in a first direction parallel to an upper surface of the substrate; a gate structure extending on the fin structure in a second direction parallel to an upper surface of the substrate and perpendicular to the first direction; and a source region and a drain region spaced apart from each other in the first direction at both ends of the fin structure in the substrate, wherein at least one dimension of the source region and the drain region is the same, and in a third direction perpendicular to the upper surface of the substrate and perpendicular to the first direction and the second direction, the source region and the drain region are positioned at different positions relative to the gate structure.

[0006] In order to achieve the above object, another aspect of the present invention provides a semiconductor device comprising: a substrate; a fin structure extending on the substrate in a first direction parallel to an upper surface of the substrate; a gate structure extending on the fin structure in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction; and a source region and a drain region spaced apart from each other in the first direction at both ends of the fin structure in the substrate, wherein at least one dimension of the drain region is larger than a size of the source region, and the shortest distance between a lower surface of the gate structure and a lower surface of the drain region is smaller than the shortest distance between the lower surface of the gate structure and a lower surface of the source region. [Effects of the Invention]

[0007] According to the present invention, the source and drain regions of a semiconductor device have different structures, thereby reducing the electric field around the overlapping region of the gate structure and the drain region. Furthermore, the source and drain regions of the semiconductor device have different structures, thereby providing a semiconductor device with improved HCI and GIDL characteristics, thereby improving the reliability of the semiconductor device.

[0008] The various yet significant advantages and effects of the present invention are not limited to the above, but will be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a simplified diagram illustrating a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a simplified diagram illustrating a semiconductor device according to an embodiment of the present invention; [Figure 3] FIG. 2 is a simplified diagram illustrating a sub-word line driver according to one embodiment of the present invention. [Figure 4] FIG. 2 is a plan view simply showing an example of an element region according to an embodiment of the present invention. [Figure 5a] 5 is a cross-sectional view showing a cross section taken along line II' in FIG. 4. FIG. [Figure 5b] 5 is a cross-sectional view showing a cross section taken along line II-II' in FIG. 4. FIG. [Figure 6] 1 is a simplified cross-sectional view of a first example semiconductor device according to an embodiment of the present invention; [Figure 7] FIG. 2 is a simplified cross-sectional view of a second example semiconductor device according to an embodiment of the present invention. [Figure 8] FIG. 10 is a simplified cross-sectional view of a third example of a semiconductor device according to an embodiment of the present invention. [Figure 9] FIG. 10 is a simplified cross-sectional view of a fourth example of a semiconductor device according to an embodiment of the present invention. [Figure 10] FIG. 10 is a simplified cross-sectional view of a fifth example of a semiconductor device according to an embodiment of the present invention. [Figure 11] FIG. 10 is a simplified cross-sectional view of a sixth example of a semiconductor device according to an embodiment of the present invention. [Figure 12] FIG. 10 is a plan view simply showing another example of an element region according to an embodiment of the present invention. [Figure 13] 13 is a cross-sectional view showing a first example of a cross section taken along line III-III' in FIG. 12. FIG. [Figure 14] 13 is a cross-sectional view showing a second example of a cross section taken along the line III-III' in FIG. 12. FIG. [Figure 15] 13 is a cross-sectional view showing a third example of a cross section taken along the line III-III' in FIG. 12. FIG. [Figure 16] 13 is a cross-sectional view showing a fourth example of a cross section taken along the line III-III' in FIG. 12. FIG. [Figure 17a] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 17b] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 18a] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 18b]1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 19a] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 19b] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 20a] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 20b] 1A to 1C are views provided to explain a method for manufacturing a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0011] 1 and 2 are simplified diagrams showing a semiconductor device according to one embodiment of the present invention.

[0012] 1 is a block diagram showing a simplified structure of a semiconductor device according to an embodiment of the present invention. The semiconductor device according to an embodiment of the present invention is a dynamic random access memory (DRAM). In the embodiment shown in FIG. 1, the semiconductor device 1 includes a row decoder 20, a PXI generator (PXI GRN.) 22, a connection circuit 42, a word line driver circuit 32, a cell array 10, a sense amplifier circuit 12, etc.

[0013] The row decoder 20 decodes an externally input upper row address (RA2 to RA8) MRADD and selects a word line corresponding to the upper row address MRADD from among the word lines WL. In other words, the row decoder 20 determines a selected word line from among the word lines WL in response to the upper row address MRADD. For example, the row decoder 20 outputs a word line enable signal NWEI to the word line driver 32 to enable the selected word line. The row decoder 20 includes logic gates, which are configured with semiconductor elements. For example, the logic gates are configured with PMOS transistors and NMOS transistors.

[0014] The PXI generator 22 outputs a pre-decoding signal PXI in response to a lower row address (RA0-RA1) LRADD. As an example, the PXI generator 22 decodes the lower row address LRADD among the row addresses input from the outside and generates a pre-decoding signal PXI corresponding to the selected word line. The pre-decoding signal PXI is input to drive signal generators (40, 50) included in the connection circuit 42.

[0015] The drive signal generators (40, 50) generate drive signals (PXID, PXIB) for driving the word lines WL in response to the pre-decoding signals PXI. As an example, the drive signal generators (40, 50) include pull-up circuits that increase the drive signals (PXID, PXIB) by a predetermined voltage level. The drive signals (PXID, PXIB) are output to sub-word line drivers SWD included in the word line drive circuit 32.

[0016] The semiconductor device includes a memory cell region where memory cells for storing data are arranged, and a peripheral circuit region where word line drivers, sense amplifiers, row decoders, column decoders, and control circuits are arranged.

[0017] The sub-word line driver SWD activates and precharges a selected word line in response to the word line enable signal NWEI and the drive signals PXID and PXIB. For example, the drive signal generators 40 and 50 increase the level of a first drive signal PXID input to the sub-word line driver SWD connected to the selected word line from a first voltage to a second voltage and set the level of the second drive signal PXIB to the first voltage. The sub-word line driver SWD, to which the first drive signal PXID having the second voltage and the second drive signal PXIB having the first voltage are input, inputs the first drive signal PXID to the selected word line.

[0018] Meanwhile, the unselected word line drivers SWD connected to the unselected word lines not selected by the word line enable signal NWEI apply a predetermined power supply voltage to the unselected word lines. In one embodiment, the power supply voltage applied to the unselected word lines is lower than the second voltage. For example, the power supply voltage is a negative constant voltage lower than 0V.

[0019] In the cell array 10, memory cells MC are connected to word lines WL and bit lines BL. Each memory cell MC includes a storage capacitor and a switch element, which will be described in more detail below with reference to FIG.

[0020] 2, each memory cell MC includes a storage capacitor CC and a switch element SW. The control terminal of the switch element SW is connected to word lines WL0 to WLn, and the input terminal of the switch element SW is connected to bit lines BL0 to BLm, BL0B to BLmB. The word lines WL0 to WLn are connected to a sub-word line driver SWD, and the bit lines BL0 to BLm, BL0B to BLmB are connected to a sense amplifier BLSA.

[0021] Semiconductor devices are an important part of the electronics industry, and memory devices that store data and processors that process data are all implemented as semiconductor devices. FINFET devices are being used as semiconductor devices to improve integration, and active research is being conducted on FINFET devices that can operate under high voltage conditions. However, there is a risk that the reliability of FINFET devices will decrease if they operate under high voltages.

[0022] A semiconductor device according to an embodiment of the present invention includes a plurality of semiconductor elements. In one embodiment, the plurality of semiconductor elements are FINFET elements. Some of the plurality of semiconductor elements operate at a relatively high voltage. The relatively high voltage refers to a power supply voltage of 3V or more applied between a source region and a drain region. For example, a sub-word line driver includes a semiconductor element that operates at a relatively high voltage.

[0023] A semiconductor device according to an embodiment of the present invention includes at least one semiconductor element having a source region and a drain region with different structures. By different structures, it is meant that the source region and the drain region do not have substantially the same structure. In one embodiment, a semiconductor element that operates at a relatively high voltage has a source region and a drain region with different structures.

[0024] By forming the source and drain regions of a semiconductor device with different structures, the electric field around the overlapping region of the gate structure and the drain region can be reduced. In particular, the electric field in the lateral direction can be reduced. By forming the source and drain regions with different structures, the peak of the electric field formed in the path of charge transfer from the source region to the drain region can be minimized. Therefore, a semiconductor device with improved HCI and GIDL characteristics can be provided, resulting in improved reliability of the semiconductor device.

[0025] FIG. 3 is a simplified diagram of a sub-word line driver according to one embodiment of the present invention.

[0026] 3, the sub-word line driver SWD includes a PMOS transistor 60, a first NMOS transistor 70, and a second NMOS transistor 80. The PMOS transistor 60 has a first drive signal PXID connected to its source, a word line enable signal NWEI connected to its gate, and a word line WL connected to its drain. The first NMOS transistor 70 has a back bias voltage VBB connected to its source, a word line enable signal NWEI connected to its gate, and a word line WL connected to its drain. The second NMOS transistor 80 has a second drive signal PXIB connected to its gate, a back bias voltage VBB connected to its source, and a word line WL connected to its drain.

[0027] The word line enable signal NWEI is generated at the ground voltage level in response to the word line enable signal NWEI activated at the boosted voltage level. In response to the sub-word line enable signal NWEI at the ground voltage level and the first drive signal PXID at the boosted voltage level, the sub-word line WL has the boosted voltage level. During the precharge operation, in response to the sub-word line enable signal NWEI at the boosted voltage level and the second drive signal PXIB, the sub-word line WL has the back bias voltage VBB level.

[0028] In one embodiment of the present invention, at least one of the PMOS transistor 60, first NMOS transistor 70, and second NMOS transistor 80, which are semiconductor elements included in the sub-word line driver SWD, is a FINFET transistor. In this specification, the semiconductor element is exemplified as including a FINFET, but is not limited to this. The structure and layout of the source and drain regions described below also apply to planar elements, GAA (Gate All Around) elements, etc.

[0029] In one embodiment of the present invention, the source and drain regions of a FINFET device are formed with different structures. By forming the source and drain regions of the FINFET device with different structures, it is possible to reduce an electric field peak around the overlap region between the gate structure and the drain region. By providing the source and drain regions of the semiconductor device with different structures, it is possible to provide a semiconductor device with improved HCI and GIDL characteristics, thereby improving the reliability of the semiconductor device.

[0030] FIG. 4 is a simplified plan view showing an example of an element region according to an embodiment of the present invention.

[0031] 4, a semiconductor device according to an embodiment of the present invention includes a first device region 100a and a second device region 100b in a peripheral circuit region. The first device region 100a and the second device region 100b each include an NMOS region and / or a PMOS region. In one embodiment, the first device region 100a includes semiconductor devices that are driven by a relatively high voltage, and the second device region 100b includes semiconductor devices that are driven by a relatively low voltage.

[0032] The first element region 100a includes a first semiconductor element 170a and a second semiconductor element 180a. In one embodiment, the first semiconductor element 170a and the second semiconductor element 180a are included in a sub-word line driver. Referring to FIG. 3 as an example, the first semiconductor element 170a is a first NMOS transistor 70 of the sub-word line driver SWD, and the second semiconductor element 180a is a second NMOS transistor 80 of the sub-word line driver SWD. The first semiconductor element 170a and the second semiconductor element 180a each include a source region 120a and share a drain region 130a.

[0033] The second element region 100b includes a third semiconductor element 170b and a fourth semiconductor element 180b. In one embodiment, the third semiconductor element 170b and the fourth semiconductor element 180b are included in a sense amplifier. Referring to FIG. 2 as an example, a sense amplifier BLSA that operates by applying a relatively low voltage is disposed in the second element region 100b.

[0034] The first element region 100a and the second element region 100b include substrates (103a, 103b) having a plurality of fin structures (105a, 105b), active regions provided on the substrates (103a, 103b) to provide source regions (120a, 120b) and drain regions (130a, 130b), and gate structures (110a, 110b) disposed between the active regions and extending to intersect the plurality of fin structures (105a, 105b). The active regions are formed of silicon (Si) and doped with N-type impurities such as phosphorus (P), nitrogen (N), arsenic (As), or antimony (Sb).

[0035] The substrates 103a and 103b are the base on which semiconductor devices are fabricated and include well regions. The substrates 103a and 103b have recess regions formed by removing portions of their upper surfaces. The substrates 103a and 103b may be bulk wafers, epitaxial layers, silicon-on-insulator (SOI) layers, or semiconductor-on-insulator (SeOI) layers. The substrates 103a and 103b include semiconductor materials such as group IV semiconductors, III-V compound semiconductors, or II-VI compound semiconductors. For example, group IV semiconductors include silicon, germanium, or silicon germanium. The substrates 103a and 103b include first conductivity type impurities, such as, but not limited to, p-type impurities.

[0036] The first element region 100a and the second element region 100b include a plurality of fin structures (105a, 105b) extending in a first direction (X-axis direction) on the substrates (103a, 103b) and gate structures (110a, 110b) extending in a second direction (Y-axis direction) so as to intersect with the plurality of fin structures (105a, 105b). The plurality of fin structures (105a, 105b) are formed to protrude from the upper surfaces of the substrates (103a, 103b) and have a fin structure.

[0037] The active region includes a base active region and a plurality of fin structures (105a, 105b). The plurality of fin structures (105a, 105b) contain impurities. The plurality of fin structures (105a, 105b) are separated by element isolation layers (107a, 107b) within the substrate and extend in a first direction (X-direction). The plurality of fin structures (105a, 105b) are spaced apart from the element isolation layers (107a, 107b) in a second direction (Y-axis direction). The element isolation layers (107a, 107b) include an insulating material such as silicon oxide, silicon nitride, or silicon dioxide.

[0038] To form source regions 120a, 120b and drain regions 130a, 130b, portions of the fin structures 105a, 105b on both sides of the gate structures 110a, 110b are removed, and a selective epitaxial growth (SEG) process is applied to the remaining portions of the fin structures 105a, 105b to form the source regions 120a, 120b and drain regions 130a, 130b.

[0039] The gate structures (110a, 110b) extend along a second direction (Y-axis direction) and intersect with a plurality of fin structures (105a, 105b) extending in a first direction (X-axis direction) intersecting the second direction. Gate spacers (113a, 113b) are formed on the side surfaces of the gate structures (110a, 110b), respectively. The gate structures (110a, 110b) include a gate insulating layer, a gate metal layer (112a, 112b), etc.

[0040] FIG. 5a is a cross-sectional view showing a cross section along line II' in FIG.

[0041] 5a, the first device region 100a includes a substrate 103a, a plurality of fin structures 105a extending in a first direction (X-axis direction) on the substrate 103a, and a gate structure 110a extending in a second direction (Y-axis direction) on the plurality of fin structures 105a. In one embodiment, the first device region 100a is included in a word line driver. The gate structures 110a on the plurality of fin structures 105a extend in the second direction (Y-axis direction). The gate structures 110a are spaced apart with an active region sandwiched therebetween. For example, a transistor is formed in a region where the gate structure 110a and the plurality of fin structures 105a intersect.

[0042] The gate structure 110a includes a gate insulating layer 111a and a gate metal layer 112a. The gate insulating layer 111a is disposed between the gate metal layer 112a and the plurality of fin structures 105a. Gate spacers 113a made of an insulating material are disposed on the side surfaces of the gate structure 110a, and active regions are provided outside the gate spacers 113a.

[0043] The active region provides the source region 120a and drain region 130a of the semiconductor device and has an elevated source / drain configuration in which the upper surface thereof is located higher than the lower surface of the gate structure 110. In the embodiments shown in FIGS. 5a to 11, the active region is shown as a square, but the active region may have various shapes, for example, either a polygonal or circular shape. The active region has a structure in which three fin structures 105a are connected or merged with each other. The number of fin structures 105a connected with each other in one active region may vary.

[0044] When the semiconductor device is an NMOS transistor, the fin structure 105a and the active region include silicon (Si). The active region includes a source region 120a and a drain region 130a. The source region 120a and the drain region 130a are epitaxially grown from the fin structure 105a. The source region 120a and the drain region 130a are doped with impurities of a first conductivity type and have different doping concentrations depending on the embodiment. For example, the impurities of the first conductivity type are N-type impurities, and the doping concentration of the drain region 130a is lower than the doping concentration of the source region 120a.

[0045] As described above, the first device region 100a according to an embodiment of the present invention includes a FINFET device to improve integration density. However, since a FINFET device operates at a relatively high voltage, the HCI and GIDL characteristics that affect the reliability of the device may be degraded. Therefore, the source region 120a and the drain region 130a of the FINFET device have different structures.

[0046] The different structures mean that the source region 120a and the drain region 130a have substantially different characteristics (e.g., dimensions, shapes, doping concentrations, etc.). In one embodiment, the dimensions refer to the length in a first direction, the length in a second direction, the thickness in a third direction, and the volume of each of the source region 120a and the drain region 130a. For example, referring to FIG. 5a, the lower surface of the drain region 130a is located higher than the lower surface of the source region 120a in the third direction (Z-axis direction). In other words, the shortest distance between the lower surface of the gate structure 110a and the lower surface of the drain region 130a is smaller than the shortest distance between the lower surface of the gate structure 110a and the lower surface of the source region 120a.

[0047] By forming the source region 120a and the drain region 130a of the semiconductor device with different structures, the peak of the electric field around the overlapping region of the gate structure 110a and the drain region 130a can be reduced, thereby providing a semiconductor device with improved HCI and GIDL characteristics, and ultimately improving the reliability of the semiconductor device.

[0048] FIG. 5b is a cross-sectional view taken along line II-II' in FIG.

[0049] 5b, second element region 100b includes substrate 103b, a plurality of fin structures 105b extending in a first direction (X-axis direction) on substrate 103b, and gate structures 110b extending in a second direction (Y-axis direction). In one embodiment, second element region 100b is included in a sense amplifier.

[0050] 4 to 5b, the first element region 100a includes semiconductor elements that are driven by a relatively high voltage, and the second element region 100b includes semiconductor elements that are driven by a relatively low voltage. For example, the first element region 100a is included in a sub-word line driver, and the second element region 100b is included in a sense amplifier.

[0051] The thickness of the gate insulating layer 111a included in the first element region 100a is thicker than the thickness of the gate insulating layer 111b included in the second element region 100b. A semiconductor element that operates upon application of a relatively high voltage requires a relatively high breakdown voltage and therefore includes a relatively thick gate insulating layer 111a. A semiconductor element that operates upon application of a relatively low voltage requires a relatively low breakdown voltage and therefore includes a relatively thin gate insulating layer 111b. Therefore, the thickness of the gate insulating layer 111a included in the first element region 100a, to which a relatively high voltage is applied, is greater than the thickness of the gate insulating layer 111b included in the second element region 100b, to which a relatively low voltage is applied.

[0052] 5a and 5b together, the source region 120a and the drain region 130a in the first device region 100a have different characteristics (e.g., size, shape, doping concentration, etc.), while the source region 120b and the drain region 130b in the second device region 100b have substantially the same characteristics. In one embodiment, the other characteristics of the source region 120a and the drain region 130a in the first device region 100a mean that the bottom surface of the drain region 130a in the third direction (Z-axis direction) is higher than the bottom surface of the source region 120a.

[0053] In the first element region 100a, which operates at a relatively high voltage, the HCI and GIDL characteristics, which affect the reliability of the element, may be degraded, so the first element region 100a is intentionally formed so that the source region 120a and the drain region 130a have different structures.On the other hand, in the second element region 100b, which operates at a relatively low voltage, the source region 120b and the drain region 130b do not have different structures.

[0054] 6 to 11 are simplified cross-sectional views of various exemplary semiconductor devices according to embodiments of the present invention.

[0055] In one embodiment of the present invention, a semiconductor device includes a memory cell array region and a peripheral circuit region. The peripheral circuit region includes a first semiconductor element 200 and a second semiconductor element. The first semiconductor element 200 and the second semiconductor element each include a substrate 203, a fin structure 205 extending in a first direction (X-axis direction) on the substrate 203, a gate structure 210 extending in a second direction (Y-axis direction) on the fin structure 205, a source region 220, and a drain region 230.

[0056] The first semiconductor element 200 is an element that operates when a relatively high voltage is applied, and the second semiconductor element is an element that operates when a relatively low voltage is applied. The source region and drain region included in the first semiconductor element 200 have different structures. For example, referring to FIGS. 6 to 8, the bottom surface of the drain region is positioned higher than the bottom surface of the source region in the third direction (Z-axis direction). Meanwhile, the source region and drain region included in the second semiconductor element have substantially the same structure based on the gate structure.

[0057] 6, in the first semiconductor device 200, active regions including a source region 220 and a drain region 230 are formed on both ends of the fin structure 205 centered around the gate structure 210. The active regions including the source region 220 and the drain region 230 are formed by removing the fin structure 205 and performing an epitaxial growth process. In one embodiment, the etching process of the fin structure 205 to form the source region 220 and the drain region 230 and the epitaxial growth process are performed separately.

[0058] The first semiconductor element 200 includes a source region 220. The source region 220 in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 210. The source region 220 includes a region that protrudes in the first direction (X-axis direction) in the region that extends below the lower surface of the gate structure 210. The source region 220 in the third direction (Z-axis direction) includes a region that extends above the lower surface of the gate structure 210, and overlaps with the gate structure 210 in this region.

[0059] The first semiconductor element 200 includes a drain region 230. The drain region 230 in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 210. The drain region 230 in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 210, and overlaps with the gate structure 210 in this region. The source region 220 and the drain region 230 include portions that face each other at the bottom of the gate structure 210 with the fin structure 205 in between.

[0060] 6, the source region 220 and the drain region 230 included in the first semiconductor device 200 according to an embodiment of the present invention have different shortest distances to the gate structure 210 in a first direction (X-axis direction). In the first direction (X-axis direction), the shortest distance p2 between the gate structure 210 and the drain region 230 is larger than the shortest distance p1 between the gate structure 210 and the source region 220. By removing the fin structures 205 to form the source region 220 and the drain region 230, the source region 220 forms a region that protrudes in the first direction (X-axis direction), unlike the drain region 230, and the shortest distance p1 between the gate structure 210 and the source region 220 in the first direction (X-axis direction) is smaller than the shortest distance p2 between the gate structure 210 and the drain region 230.

[0061] 6, the lower surface of the drain region 230 in the third direction (Z-axis direction) is located higher than the lower surface of the source region 220. The shortest distance d2 between the lower surface of the gate structure 210 and the lower surface of the drain region 230 in the third direction (Z-axis direction) is smaller than the shortest distance d1 between the lower surface of the gate structure 210 and the lower surface of the source region 220. To form the source region 220 and the drain region 230, the fin structures 205 are removed, respectively, so that the lower surface of the drain region 230 in the third direction (Z-axis direction) is located higher than the lower surface of the source region 220, and the shortest distances (d1, d2) between the lower surface of the gate structure 210 and the lower surfaces of the source region 220 and the drain region 230 in the third direction are different.

[0062] In one embodiment of the present invention, epitaxial growth processes for forming the source region 220 and the drain region 230 are performed separately. By performing the epitaxial growth processes separately, the thickness h1 of the source region 220 and the thickness h2 of the drain region 230 are not the same in the third direction (Z-axis direction). For example, the thickness h2 of the drain region 230 is smaller than the thickness h1 of the source region 220. Because the fin structure 205 removal and epitaxial growth processes are performed separately, the lower surface of the source region 220 in the third direction (Z-axis direction) is located below the lower surface of the drain region 230, and the positions of the upper surfaces of the source region 220 and the drain region 230 are substantially the same.

[0063] In one embodiment of the present invention, the source region 220 and the drain region 230 included in the first semiconductor device 200 have different structures in the first direction (X-axis direction) and the third direction (Z-direction). The first semiconductor device 200 having the source region 220 and the drain region 230 with different structures can reduce the electric field around the region where the gate structure 210 and the drain region 230 overlap, compared to a second semiconductor device having the source region and the drain region with substantially the same structure. By forming the source region 220 and the drain region 230 of the first semiconductor device 200 with different structures, it is possible to provide the first semiconductor device 200 with improved characteristics such as HCI and GIDL, and as a result, the reliability of the first semiconductor device 200 when a relatively high voltage is applied can be improved.

[0064] In one embodiment of the present invention, a semiconductor device includes a memory cell array region and a peripheral circuit region. The peripheral circuit region includes a first semiconductor element 200a and a second semiconductor element 200a. The first semiconductor element 200a operates when a relatively high voltage is applied, and a source region 220a and a drain region 230a included in the first semiconductor element 200a have different structures.

[0065] Referring to FIG. 7, the first semiconductor element 200a includes a substrate 203a, a fin structure 205a extending in a first direction (X-axis direction) on the substrate 203a, a gate structure 210a extending in a second direction (Y-axis direction) on the fin structure 205a, and a source region 220a and a drain region 230a formed in the substrate 203a on both ends of the fin structure 205a.

[0066] The source region 220a included in the first semiconductor element 200a is formed by removing the fin structure 205a and performing an epitaxial growth process. The source region 220a in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 210a. The source region 220a includes a region that protrudes in the first direction (X-axis direction) from the region that extends below the lower surface of the gate structure 210a. The source region 220a in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 210a, and overlaps with the gate structure 210a in this region.

[0067] The drain region 230a included in the first semiconductor element 200a is formed by removing the fin structure 205a and performing an epitaxial growth process. The drain region 230a in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 210a. The drain region 230a in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 210a, and overlaps with the gate structure 210a in this region. The source region 220a and the drain region 230a include portions that face each other at the bottom of the gate structure 210a with the fin structure 205a in between.

[0068] 7, the source region 220a and the drain region 230a included in the first semiconductor device 200a according to an embodiment of the present invention have different shortest distances from the gate structure 210a in the first direction (X-axis direction). In the first direction (X-axis direction), the shortest distance p4 between the gate structure 210a and the drain region 230a is larger than the shortest distance p3 between the gate structure 210a and the source region 220a. By separately removing the fin structure 205a for forming the source region 220a and the drain region 230a, the source region 220a has a protruding region in the first direction (X-axis direction), and the shortest distance p4 between the drain region 230a and the gate structure 210a in the first direction (X-axis direction) is larger than the shortest distance p3 between the source region 220a and the gate structure 210a.

[0069] 7, the lower surface of the drain region 230a in the third direction (Z-axis direction) is located higher than the lower surface of the source region 220a. In other words, the shortest distance d4 between the lower surface of the drain region 230a and the lower surface of the gate structure 210a in the third direction (Z-axis direction) is smaller than the shortest distance d3 between the lower surface of the source region 220a and the lower surface of the gate structure 210a.

[0070] Meanwhile, the epitaxial growth processes for forming the source region 220a and the drain region 230a of the first semiconductor device 200a are performed simultaneously. Because the epitaxial growth processes are performed simultaneously, the thickness h3 of the source region 220a and the thickness h4 of the drain region 230a in the third direction are substantially the same. In one embodiment, when the widths of the source region 220a and the drain region 230a in the first direction are substantially the same, the sizes of the source region 220a and the drain region 230a are substantially the same.

[0071] In one embodiment of the present invention, the positions of the top and bottom surfaces of the source region 220a and the drain region 230a of the first semiconductor element 200a in the third direction (Z-axis direction) are different from each other. For example, the positions of the top and bottom surfaces of the drain region 230a are higher in the third direction than the positions of the top and bottom surfaces of the source region 220a. The source region 220a and the drain region 230a of the first semiconductor element 200a have a structure in which they are arranged differently from each other in the third direction (Z-axis direction) with respect to the gate structure 210a.

[0072] In one embodiment of the present invention, the source region 220a and the drain region 230a included in the first semiconductor device 200a have different structures. The different structures of the source region 220a and the drain region 230a can reduce the electric field around the overlapping region of the gate structure 210a and the drain region 230a. The different structures of the source region 220a and the drain region 230a of the first semiconductor device 200a can provide the first semiconductor device 200a with improved characteristics such as HCI and GIDL, thereby improving the reliability of the first semiconductor device 200a when operated under relatively high voltages.

[0073] In one embodiment of the present invention, a semiconductor device includes a memory cell array region and a peripheral circuit region. The peripheral circuit region includes a first semiconductor element 200b and a second semiconductor element 200b. The first semiconductor element 200b operates when a relatively high voltage is applied, and a source region 220b and a drain region 230b included in the first semiconductor element 200b have different structures.

[0074] Referring to FIG. 8, the first semiconductor element 200b includes a substrate 203b, a fin structure 205b extending in a first direction (X-axis direction) on the substrate 203b, a gate structure 210b extending in a second direction (Y-axis direction) on the fin structure 205b, and a source region 220b and a drain region 230b formed in the substrate 203b on both ends of the fin structure 205b.

[0075] 8, the first semiconductor element 200b includes a source region 220b. The source region 220b in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 210b. The source region 220b includes a region that protrudes in the first direction (X-axis direction) from the region that extends below the lower surface of the gate structure 210b. The source region 220b in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 210b, and overlaps with the gate structure 210b in this region.

[0076] The first semiconductor element 200b includes a drain region 230b. The drain region 230b in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 210b. The drain region 230b in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 210b, and overlaps with the gate structure 210b in this region. The source region 220b and the drain region 230b include portions that face each other at the bottom of the gate structure 210b, with the fin structure 205b in between.

[0077] Referring to FIG. 8 , the drain region includes a first drain region 230b and a second drain region 235b disposed between the first drain region 230b and the gate structure 210b. The second drain region 235b is doped at a lower concentration than the first drain region 230b. For example, the second drain region 235b is a lightly doped drain (LDD) region. To form the second drain region 235b, a pad oxide pattern and a mask pattern are formed on the source region 220b. The pad oxide pattern is a layer provided to protect the source region 220b and may be omitted in some embodiments. The mask pattern is a mask layer used to pattern the semiconductor device and may include silicon nitride, a carbon-containing material, or the like. The mask pattern may also have multiple layers.

[0078] Referring to FIG. 8, the drain regions (230b, 235b) included in the first semiconductor device 200b have a different structure from the source region 220b. The drain regions (230b, 235b) include a first drain region 230b and a second drain region 235b, and the source region 220b includes a region protruding in the first direction (X-axis direction) from the bottom of the gate structure 210b. In particular, the drain region includes the second drain region 235b, which can reduce the electric field around the region where the gate structure 210b and the drain regions (230b, 235b) overlap. The different structures between the source region 220b and the drain region (230b, 235b) of the first semiconductor device 200b can provide a semiconductor device with improved characteristics such as HCI and GIDL, thereby improving the reliability of the first semiconductor device 200b.

[0079] In one embodiment of the present invention, a semiconductor device includes a memory cell array region and a peripheral circuit region. The peripheral circuit region includes a first semiconductor element 300 and a second semiconductor element. The first semiconductor element 300 operates when a relatively high voltage is applied, and a source region 320 and a drain region 330 included in the first semiconductor element 300 have different structures.

[0080] 9, the first semiconductor device 300 includes a substrate 303, a fin structure 305 extending in a first direction (X-axis direction) on the substrate 303, a gate structure 310 extending in a second direction (Y-axis direction) on the fin structure 305, and a source region 320 and a drain region 330 formed in the substrate 303 on both ends of the fin structure 305. The source region 320 and the drain region 330 are doped with impurities of a first conductivity type.

[0081] The source region 320 included in the first semiconductor device 300 is formed by removing the fin structure 305 and performing an epitaxial growth process thereon. The source region 320 in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 310. However, the source region 320 is not limited thereto, and in some embodiments (not explicitly shown), the source region 320 includes a region that protrudes in the first direction (X-axis direction) from the lower surface of the gate structure 310. The source region 320 in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 310 and overlaps with the gate structure 310 in this region.

[0082] The drain region 330 included in the first semiconductor element 300 is formed by implanting ions into the fin structure 305. For example, the drain region 330 is formed by implanting impurities of a first conductivity type into the fin structure 305. The drain region 330 includes a region that extends below the lower surface of the gate structure 310 in the third direction (Z-axis direction). The source region 320 and the drain region 330 include portions that face each other at the bottom of the gate structure 310 with the fin structure 305 in between.

[0083] In one embodiment, the position of the top surface of the drain region 330 and the position of the top surface of the source region 320 in the third direction are not the same. Because the source region 320 is epitaxially grown after the fin structure 305 is removed, the top surface of the source region 320 is located higher in the third direction than the bottom surface of the gate structure 310. Because the fin structure 305 is not removed from the drain region 330, the top surface of the drain region 330 is substantially the same as the bottom surface of the gate structure 310. Therefore, the top surface of the drain region 330 in the third direction is located lower than the top surface of the source region 320.

[0084] In one embodiment, the drain region 330 is doped with impurities of the first conductivity type at least once. The drain region 330 is doped at least once by varying at least one of the energy, concentration, and angle at which the impurities of the first conductivity type are implanted. By doping the drain region 330 multiple times by varying the energy, concentration, angle, etc. at which the impurities of the first conductivity type are implanted, the electric field around the overlapping region of the gate structure 310 and the drain region 330 can be reduced.

[0085] 9, the source region 320 and the drain region 330 included in the first semiconductor element 300 have structures that differ from each other in terms of whether or not the fin structure 305 is removed, the position of the top surface in the third direction (Z-axis direction), etc. The source region 320 and the drain region 330 have different structures from each other, which can reduce the electric field around the region where the gate structure 310 and the drain region 330 overlap. The source region 320 and the drain region 330 of the first semiconductor element 300 have different structures from each other, which can provide a semiconductor element with improved characteristics such as HCI and GIDL, and as a result, the reliability of the first semiconductor element 300 can be improved.

[0086] In one embodiment of the present invention, a semiconductor device includes a memory cell array region and a peripheral circuit region. The peripheral circuit region includes a first semiconductor element 300a and a second semiconductor element 300a. The first semiconductor element 300a operates when a relatively high voltage is applied, and a source region 320a and a drain region 330a included in the first semiconductor element 300a have different structures.

[0087] Referring to FIG. 10, the first semiconductor element 300a includes a substrate 303a, a fin structure 305a extending in a first direction (X-axis direction) on the substrate 303a, a gate structure 310a extending in a second direction (Y-axis direction) on the fin structure 305a, and a source region 320a and a drain region 330a formed in the substrate 303a on both ends of the fin structure 305a.

[0088] In one embodiment of the present invention, the source region 320a and the drain region 330a included in the first semiconductor device 300a are formed. The source region 320a is formed by performing an epitaxial growth process after removing the fin structure 305a. The drain region 330a is formed by directly implanting impurities of the first conductivity type into the fin structure 305a without removing the fin structure 305a.

[0089] The source region 320a included in the first semiconductor device 300a is formed by removing the fin structure 305a and performing an epitaxial growth process thereon. The source region 320a in the third direction (Z-axis direction) includes a region that extends below the lower surface of the gate structure 310a. However, the source region 320a is not limited thereto, and in some embodiments (not explicitly shown), the source region 320a may include a region that protrudes in the first direction (X-axis direction) from the lower surface of the gate structure 310a. The source region 320a in the third direction (Z-axis direction) has a region that extends above the lower surface of the gate structure 310a and overlaps the gate structure 310a in this region.

[0090] The drain region 330a included in the first semiconductor element 300a is formed by implanting ions into the fin structure 305a. For example, the drain region 330a is formed by implanting impurities of a first conductivity type into the fin structure 305a. The drain region 330a includes a region that extends below the lower surface of the gate structure 310a in the third direction (Z-axis direction). The source region 320a and the drain region 330a include portions that face each other at the bottom of the gate structure 310a with the fin structure 305a in between.

[0091] 10, a first semiconductor device 300a includes a counter-doping region 331a between a gate structure 310a and a drain region 330a, which is doped with impurities of a second conductivity type different from the impurities of the first conductivity type. Counter-doping refers to intentionally doping impurities to adjust electrical characteristics during fabrication of a semiconductor device, and the impurities vary depending on the type of semiconductor. To prevent the counter-doping from degrading the overall characteristics of the semiconductor device, the counter-doping region 331a is formed only partially between the gate structure 310a and the drain region 330a.

[0092] In one embodiment of the present invention, a first semiconductor device 300a includes a counter-doped region 331a between a gate structure 310a and a drain region 330a, and the drain region 330a and the source region 320a have different structures. By forming the counter-doped region 331a, the breakdown voltage of the first semiconductor device 300a is improved and the electric field around the overlapping region of the gate structure 310a and the drain region 330a is reduced. The different structures of the source region 320a and the drain region 330a of the first semiconductor device 300a can provide a semiconductor device with improved characteristics such as HCI and GIDL, thereby improving the reliability of the first semiconductor device 300a.

[0093] In one embodiment of the present invention, a semiconductor device includes a memory cell array region and a peripheral circuit region. The peripheral circuit region includes a first semiconductor element 300b and a second semiconductor element 300b. The first semiconductor element 300b operates when a relatively high voltage is applied, and a source region 320b and a drain region 330b included in the first semiconductor element 300b have different structures.

[0094] 11, the first semiconductor device 300b includes a substrate 303b, a fin structure 305b extending in a first direction (X-axis direction) on the substrate 303b, a gate structure 310b extending in a second direction (Y-axis direction) on the fin structure 305b, and a source region 320b and a drain region 330b formed in the substrate 303b on both ends of the fin structure 305b. The source region 320b and the drain region 330b are doped with impurities of a first conductivity type.

[0095] In one embodiment of the present invention, the semiconductor device 300b includes a source region 320b and a drain region 330b. The source region 320a is formed by performing an epitaxial growth process after removing the fin structure 305b. The drain region 330b is formed by directly implanting impurities of the first conductivity type into the fin structure 305a without removing the fin structure 305b.

[0096] The drain region includes a first drain region 330b and a second drain region 335b disposed between the first drain region 330b and the gate structure 310b. The second drain region 335b is doped with impurities of the first conductivity type at a lower concentration than the first drain region 330b. For example, the second drain region 335b is a lightly doped drain (LDD) region. The first drain region 330b is doped with impurities of the first conductivity type at a higher concentration than the second drain region 335b. The first drain region 330b is a highly doped drain (HDD) region.

[0097] By doping the first drain region 330b with a relatively high concentration of impurities of the first conductivity type and the second drain region 335b with a relatively low concentration of impurities of the first conductivity type, the electric field around the overlapping region of the gate structure 310b and the first drain region 330b can be reduced. By having the source region 320b and the drain region (330b, 335b) of the first semiconductor device 300b have different structures, a semiconductor device with improved characteristics such as HCI and GIDL can be provided, resulting in improved reliability of the first semiconductor device 300b.

[0098] FIG. 12 is a plan view simply showing another example of an element region according to an embodiment of the present invention.

[0099] A semiconductor device according to an embodiment of the present invention includes a device region 400 in a peripheral circuit region. The device region 400 includes an NMOS region and / or a PMOS region. In one embodiment, the device region 400 includes a semiconductor device that is driven by a relatively high voltage.

[0100] The device region 400 includes a first semiconductor device 470 and a second semiconductor device 480. In one embodiment, the sub-word line driver includes the first semiconductor device 470 and the second semiconductor device 480. Referring to FIG. 3 as an example, the first semiconductor device 470 is the first NMOS transistor 70 of the sub-word line driver SWD, and the second semiconductor device 480 is the second NMOS transistor 80 of the sub-word line driver SWD.

[0101] The device region 400 includes a substrate 403 having a plurality of fin structures 405, active regions provided on the substrate 403 to provide source regions 420 and drain regions 430, and gate structures 410 disposed between the active regions and extending to cross the plurality of fin structures 405. The active regions are formed of silicon (Si) and doped with N-type impurities such as phosphorus (P), nitrogen (N), arsenic (As), or antimony (Sb).

[0102] The substrate 403 serves as a base on which a semiconductor device is fabricated and includes a well region. The substrate 403 has a recess region formed by removing a portion of its top surface. The substrate 403 may be a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. The substrate 403 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, group IV semiconductors include silicon, germanium, or silicon germanium. The substrate 403 includes a first conductivity type impurity, such as, but not limited to, a p-type impurity.

[0103] The element region 400 includes a plurality of fin structures 405 extending in a first direction (X-axis direction) on the substrate 403, and a gate structure 410 extending in a second direction (Y-axis direction) so as to intersect with the plurality of fin structures 405. The plurality of fin structures 405 are formed so as to protrude from the upper surface of the substrate 403, and have a fin structure.

[0104] The active region includes a base active region and a plurality of fin structures 405. The plurality of fin structures 405 contain impurities. The plurality of fin structures 405 are separated by element isolation films 407 within the substrate and extend in a first direction (X-direction). The plurality of fin structures 405 are spaced apart from the element isolation films 407 in a second direction (Y-axis direction). The element isolation films 407 include an insulating material such as silicon oxide, silicon nitride, or silicon oxide.

[0105] The fin structures 405 on both sides of the gate structure 410 are removed to form the source region 420 and the drain region 430. The removed fin structures 405 are subjected to a selective epitaxial growth process to form the source region 420 and the drain region 430.

[0106] The gate structure 410 extends along a second direction (Y-axis direction) and intersects with the multiple fin structures 405 extending in a first direction (X-axis direction) intersecting the second direction. Gate spacers 413 are formed on the side surfaces of the gate structure 410. The gate structure 410 includes a gate insulating layer, a gate metal layer 412, etc.

[0107] 13 to 16 are cross-sectional views showing various examples of cross sections taken along the line III-III' in FIG.

[0108] 13, the device region 400 includes a substrate 403, a plurality of fin structures 405 extending in a first direction (X-axis direction) on the substrate 403, and a gate structure 410 extending in a second direction (Y-axis direction) on the plurality of fin structures 405. In one embodiment, the device region 400 includes a semiconductor device driven by a relatively high voltage and is included in a word line driver. In one embodiment, etching processes of the fin structures 405 to form source regions 420 and drain regions 430 are performed simultaneously, and epitaxial growth processes are performed separately.

[0109] In one embodiment of the present invention, the source region 420 includes a region that extends in the third direction (the Z-axis direction) below the bottom surface of the gate structure 410. Additionally, the source region 420 includes a region that extends above the bottom surface of the gate structure 410 in the third direction and overlaps the gate structure 410 in this region.

[0110] In one embodiment of the present invention, the drain region 430 includes a region that extends below the lower surface of the gate structure 410 in the third direction. Furthermore, the drain region 430 includes a region that extends above the lower surface of the gate structure 410 and overlaps the gate structure 410 in this region. Meanwhile, the width W2 of the drain region 430 in the first direction (X-axis direction) is greater than the width W1 of the source region 420.

[0111] In one embodiment of the present invention, the multiple fin structures 405 for forming the source region 420 and the drain region 430 are removed simultaneously. Because the multiple fin structures 405 are removed simultaneously, the shortest distance P1 between the gate structure 410 and the source region 420 and the shortest distance P2 between the gate structure 410 and the drain region 430 in the first direction (X-axis direction) are substantially the same. In addition, the shortest distance D1 between the lower surface of the gate structure 410 and the lower surface of the source region 420 and the shortest distance D2 between the lower surface of the gate structure 410 and the lower surface of the drain region 430 in the third direction (Z-axis direction) are also substantially the same. In addition, the position of the lower surface of the source region 420 and the position of the lower surface of the drain region 430 in the third direction are substantially the same.

[0112] Meanwhile, epitaxial growth processes are performed to form the source region 420 and the drain region 430 included in the element region 400. By performing the epitaxial growth processes, the thickness H1 of the source region 420 and the thickness H2 of the drain region 430 in the third direction (Z-axis direction) can be made the same. Furthermore, the position of the top surface of the source region 420 and the position of the top surface of the drain region 430 in the third direction (Z-axis direction) are substantially the same. However, since the width W2 of the drain region 430 in the first direction (X-axis direction) is larger than the width W1 of the source region 420, the size of the source region 420 and the size of the drain region 430 are different. For example, the size of the drain region 430 is larger than the size of the source region 420.

[0113] 13, the source region 420 and the drain region 430 included in the device region 400 have structures in which the width length in the first direction and the area size are different from each other. The source region 420 and the drain region 430 included in the device region 400 have different structures from each other, thereby reducing the electric field around the area where the gate structure 410 and the drain region 430 overlap. The source region 420 and the drain region 430 of the semiconductor device have different structures from each other, thereby providing a semiconductor device with improved characteristics such as HCI and GIDL, and as a result, improving the reliability of the semiconductor device.

[0114] 14, the device region 400a includes a substrate 403a, a plurality of fin structures 405a extending in a first direction (X-axis direction) on the substrate 403a, and a gate structure 410a extending in a second direction (Y-axis direction) on the plurality of fin structures 405a. In one embodiment, the device region 400a includes a semiconductor device driven by a relatively high voltage and included in a word line driver. To form a source region 420a and a drain region 430a, the fin structures 405a are respectively removed, and epitaxial growth processes are simultaneously performed.

[0115] In one embodiment of the present invention, the source region 420a includes a region that extends below the bottom surface of the gate structure 410a in the third direction (Z-axis direction). At the bottom surface of the gate structure 410a, the source region 420a includes a region that protrudes in the first direction (X-axis direction). The source region 420a also includes a region that extends above the bottom surface of the gate structure 410a in the third direction (Z-axis direction), and overlaps the gate structure 410a in this region.

[0116] In one embodiment of the present invention, the drain region 430a includes a region that extends below the lower surface of the gate structure 410a in the third direction. Furthermore, the drain region 430a also includes a region that extends above the lower surface of the gate structure 410a and overlaps the gate structure 410a in this region. Meanwhile, the width W4 of the drain region 430a in the first direction (X-axis direction) is greater than the width W3 of the source region 420a.

[0117] The fin structures 405a for forming the source region 420a and the drain region 430a are removed. Because the fin structures 405a are removed, the shortest distance P4 between the gate structure 410a and the drain region 430a in the first direction is greater than the shortest distance P3 between the gate structure 410a and the source region 420a. Furthermore, the shortest distance D4 between the lower surface of the gate structure 410a and the lower surface of the drain region 430a in the third direction is smaller than the shortest distance D3 between the lower surface of the gate structure 410a and the source region 420a.

[0118] Meanwhile, the epitaxial growth processes for forming the source region 420a and the drain region 430a are performed simultaneously. Because the width W4 of the drain region 430a in the first direction is wider than the width W3 of the source region 420a, when the epitaxial growth processes for the source region 420a and the drain region 430a are performed simultaneously, the thickness H4 of the drain region 430a in the third direction is different from the thickness H3 of the source region 420a. For example, the thickness H4 of the drain region 430a in the third direction is smaller than the thickness H3 of the source region 420a. Even though the thickness H4 of the drain region 430a is smaller than the thickness H3 of the source region 420a, the width W4 of the drain region 430a is wider than the width W3 of the source region 420a, so the size of the drain region 430a is larger than the size of the source region 420a. In one embodiment, the position of the top surface of the source region 420a and the position of the top surface of the drain region 430a in the third direction are substantially the same.

[0119] 14, the source region 420a and the drain region 430a included in the device region 400a have different widths and sizes. The different structures of the source region 420a and the drain region 430a can reduce the electric field around the overlapping region of the gate structure 410a and the drain region 430a. The different structures of the source region 420a and the drain region 430a of the semiconductor device can provide a semiconductor device with improved characteristics such as HCI and GIDL, thereby improving the reliability of the semiconductor device.

[0120] 15, the device region 400b includes a substrate 403b, a plurality of fin structures 405b extending in a first direction (X-axis direction) on the substrate 403b, and a gate structure 410b extending in a second direction (Y-axis direction) on the plurality of fin structures 405b. In one embodiment of the present invention, a width W6 of the drain region 430b in the first direction is greater than a width W5 of the source region 420b. An etching process and an epitaxial growth process are respectively performed to form the source region 420b and the drain region 430b.

[0121] In one embodiment of the present invention, the source region 420b includes a region that extends below the bottom surface of the gate structure 410b in the third direction (Z-axis direction). At the bottom surface of the gate structure 410b, the source region 420b includes a region that protrudes in the first direction (X-axis direction). The source region 420b also includes a region that extends above the bottom surface of the gate structure 410b in the third direction (Z-axis direction), and overlaps the gate structure 410b in this region.

[0122] In one embodiment of the present invention, the drain region 430b includes a region that extends below the bottom surface of the gate structure 410b in the third direction. Furthermore, the drain region 430b also includes a region that extends above the bottom surface of the gate structure 410b and overlaps the gate structure 410b in this region. Meanwhile, the width W6 of the drain region 430b in the first direction (X-axis direction) is greater than the width W5 of the source region 420b.

[0123] Because etching processes are performed to form the source region 420b and the drain region 430b, the shortest distance P6 between the gate structure 410b and the drain region 430b in the first direction is greater than the shortest distance P5 between the gate structure 410b and the source region 420b. Also, the shortest distance D6 between the bottom surface of the gate structure 410b and the bottom surface of the drain region 430b in the third direction is smaller than the shortest distance D5 between the bottom surface of the gate structure 410b and the source region 420b.

[0124] Because epitaxial growth processes are also performed to form the source region 420b and the drain region 430b, the thickness H6 of the drain region 430b in the third direction is different from the thickness H5 of the source region 420b. For example, the thickness H6 of the drain region 430b is smaller than the thickness H5 of the source region 420b. Furthermore, the positions of the upper and lower surfaces of the source region 420b and the drain region 430b in the third direction are different. For example, the upper surface of the drain region 430b in the third direction is located lower than the upper surface of the source region 420b, and the lower surface of the drain region 430b is located higher than the lower surface of the source region 420b.

[0125] 15, the source region 420b and the drain region 430b included in the device region 400b have different widths and thicknesses. The different structures of the source region 420b and the drain region 430b can reduce the electric field around the overlapping region of the gate structure 410b and the drain region 430b. The different structures of the source region 420b and the drain region 430b of the semiconductor device can provide a semiconductor device with improved characteristics such as HCI and GIDL, thereby improving the reliability of the semiconductor device.

[0126] 16, the element region 400c includes a substrate 403c, a plurality of fin structures 405c extending in a first direction (X-axis direction) on the substrate 403c, and a gate structure 410c extending in a second direction (Y-axis direction). In one embodiment, a width W8 of the drain region 430c in the first direction is greater than a width W7 of the source region 420c.

[0127] In one embodiment of the present invention, the source region 420c includes a region that extends below the bottom surface of the gate structure 410c in the third direction (Z-axis direction). At the bottom surface of the gate structure 410c, the source region 420c includes a region that protrudes in the first direction (X-axis direction). The source region 420c also includes a region that extends above the bottom surface of the gate structure 410c in the third direction (Z-axis direction) and overlaps the gate structure 410c in this region.

[0128] In one embodiment of the present invention, the drain region 430c includes a region that extends below the lower surface of the gate structure 410c in the third direction. Furthermore, the drain region 430c also includes a region that extends above the lower surface of the gate structure 410c and overlaps the gate structure 410c in this region. Meanwhile, the width W8 of the drain region 430c in the first direction (X-axis direction) is greater than the width W7 of the source region 420c.

[0129] 16, the drain region includes a first drain region 430c and a second drain region 435c disposed between the first drain region 430c and the gate structure 410c. The second drain region 435c is doped at a relatively lower concentration than the first drain region 430c. The second drain region 435c is an LDD region.

[0130] According to an embodiment of the present invention, the source region 420c and the drain region (430c, 435c) included in the device region 400c have structures that differ in the presence or absence of an LDD region. The different structures of the source region 420c and the drain region (430c, 435c) can reduce the electric field around the overlapping region of the gate structure 410c and the drain region (430c, 435c). The different structures of the source region 420c and the drain region (430c, 435c) of the semiconductor device can provide a semiconductor device with improved characteristics such as HCI and GIDL, resulting in improved reliability of the semiconductor device.

[0131] 17a to 20b are views provided to explain a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0132] 17a and 17b, the semiconductor device includes a substrate 503, a plurality of fin structures 505 extending in a first direction (X-axis direction) on the substrate 503, and a dummy gate structure 510 extending in a second direction (Y-axis direction). In the first direction (X-axis direction), the dummy gate structure 510 and the active region are spaced apart from each other. In the second direction (Y-axis direction), the plurality of fin structures 505 and the element isolation film 540 are spaced apart from each other. The plurality of fin structures 505 are provided to provide an active region of a semiconductor device.

[0133] The semiconductor device includes a substrate 503, a plurality of fin structures 505 on the substrate 503, and a dummy gate structure 510 on the plurality of fin structures 505. The top surfaces of the plurality of fin structures 505 are parallel to the bottom surface of the dummy gate structure 510.

[0134] The dummy gate structure 510 includes a dummy gate insulating layer 511, a dummy gate metal layer 512, a mask pattern layer 514, etc. The dummy gate insulating layer 511 and the dummy gate metal layer 512 are formed by an etching process using the mask pattern layer 514. The dummy gate insulating layer 511 is made of silicon oxide, and the dummy gate metal layer 512 is made of polysilicon.

[0135] The gate spacers 513 are formed by forming an insulating film on the dummy gate structure 510, the fin structures 505, and the isolation film 540, and then anisotropically etching the insulating film. The gate spacers 513 may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0136] 18a and 18b, a plurality of fin structures 505 are selectively removed on one side 520 of the dummy gate structure 510. This portion will become a source region of the semiconductor device. To remove only one side 520 of the dummy gate structure 510, a separate mask pattern is formed on the other side 530 of the dummy gate structure 510. The mask pattern is a layer provided to protect the other side 530 of the dummy gate structure 510 and includes silicon nitride, a carbon-containing material, etc.

[0137] The recess is formed by removing the fin structure 505 from one side 520 of the dummy gate structure 510. The recess may be formed by forming a separate mask layer or by etching the fin structure 505 using the mask pattern layer 514 and the gate spacer 513 as a mask. In one embodiment, the recess is formed by sequentially applying a dry etching process and a wet etching process.

[0138] Optionally, after forming the recess, a process of curing the surface of the recessed fin structure 505 through a separate process is performed. The upper surface of the recessed fin structure 505 is lower than the lower surface of the dummy gate structure 510, but is not necessarily limited to this. In other embodiments, the upper surface of the recessed fin structure 505 may be coplanar with the lower surface of the dummy gate structure 510.

[0139] 19a and 19b, the fin structures 505 are selectively removed from the other side 530 of the dummy gate structure 510. This portion will become the drain region of the semiconductor device. To remove only the other side 530 of the dummy gate structure 510, a mask pattern is formed separately from the one side 520 of the dummy gate structure 510.

[0140] The recess is formed by removing the fin structure 505 from the other side 530 of the dummy gate structure 510. The process of removing the fin structure 505 from the other side 530 of the dummy gate structure 510 is the same as the process of removing the one side 520 of the dummy gate structure 510.

[0141] As described above, the steps of removing the fin structure 505 in the portions that will become the source region 520 and the drain region 530 of the semiconductor device are performed. The fin structure 505 is removed so that the shortest distance between the dummy gate structure 510 and the portion that will become the drain region 530 in the first direction is larger than the shortest distance between the dummy gate structure 510 and the portion that will become the source region 520. Furthermore, the fin structure 505 is removed so that the shortest distance between the dummy gate structure 510 and the portion that will become the drain region 530 in the third direction is smaller than the shortest distance between the dummy gate structure 510 and the portion that will become the source region 520. Therefore, the portions that will become the source region 520 and the drain region 530 of the semiconductor device have different structures.

[0142] 20a, active regions (525, 535) are formed using a fin structure 505. The active regions (525, 535) are formed by applying a selective epitaxial growth process to the fin structure 505 included in the NMOS region. In one embodiment, the epitaxial growth processes for forming the source region 520 and the drain region 530 are performed simultaneously.

[0143] A capping layer is formed to cover the active regions when the epitaxial growth process is performed on the source region 520 and the drain region 530. The capping layer may include an insulating material such as silicon oxide or silicon nitride.

[0144] The active regions 525 and 535 formed in the NMOS region include silicon (Si). When forming the active regions 525 and 535 in the NMOS region, N-type impurities are doped in-situ or by a separate ion implantation process. The N-type impurities doped into the active regions 525 and 535 include phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), etc.

[0145] 20b, the source region 520 and the drain region 530 included in the semiconductor device have different structures. The shortest distance between the dummy gate structure 510 and the source region 520 and the drain region 530 in the first direction and the shortest distance between the dummy gate structure 510 and the source region 520 and the drain region 530 in the third direction are different. The source region 520 and the drain region 530 of the semiconductor device have different structures, which can reduce the electric field around the overlapping region between the gate structure and the drain region 530. The source region 520 and the drain region 530 of the semiconductor device have different structures, which can provide a semiconductor device with improved characteristics such as HCI and GIDL, thereby improving the reliability of the semiconductor device.

[0146] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0147] 1. Semiconductor device 10 Cell Array 12 Sense amplifier circuit 20 Row Decoder 22 PXI Generator (PXI GEN.) 32 Word line driver circuit 40, 50 Drive signal generator 42 Connection circuit 60 PMOS transistors 70, 80 First and second NMOS transistors 100a, 100b First and second element regions 103a, 103b, 203, 203a, 203b, 303, 303a, 303b, 403, 403a, 403b, 403c, 503 board 105a, 105b, 205, 205a, 205b, 305, 305a, 305b, 405, 405a, 405b, 405c, 505 Fin structure 107a, 107b, 407, 540 Element isolation film 110a, 110b, 210, 210a, 210b, 310, 310a, 310b, 410, 410a, 410b, 410c gate structure 111a, 111b gate insulating layer 112a, 112b, 412 gate metal layer 113a, 113b, 413 Gate spacer 120a, 120b, 220, 220a, 220b, 320, 320a, 320b, 420, 420a, 420b, 420c, 520 Source region 130a, 130b, 230, 230a, 230b, 330, 330a, 330b, 430, 430a, 430b, 530 drain region 170a, 200, 200a, 200b, 300, 300a, 300b, 470 First semiconductor element 170b third semiconductor element 180a, 480 second semiconductor element 180b fourth semiconductor element 235b, 335b, 435c second drain region 330b First drain region 331a Counter-doped region 400, 400a, 400b, 400c Element area 430c first drain region 510 Dummy Gate Structure 511 Dummy gate insulating layer 512 dummy gate metal layer 513 Gate Spacer 514 Mask Pattern Layer 520 One side 525, 535 active area 530 The other side BL0~BLm, BL0B~BLmB bit lines BLSA Sense Amplifier CC Storage Capacitor LRADD Lower row address (RA0~RA1) MC memory cell MRADD Upper row address (RA2 to RA8) NWEI Word Line Enable Signal PXI Pre-Decoding Signals PXIB, PXID 2nd and 1st drive signals SW switch element SWD sub-word line driver VBB back bias voltage WL, WL0~WLn word lines

Claims

1. a memory cell array region including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a peripheral circuit region including a first semiconductor element in the first element region and a second semiconductor element in the second element region; Each of the first semiconductor element and the second semiconductor element is A substrate; a fin structure extending on the substrate in a first direction parallel to a top surface of the substrate; a gate structure including a gate dielectric layer and a gate metal layer extending over the fin structure in a second direction parallel to the top surface of the substrate and orthogonal to the first direction; a source region and a drain region spaced apart from each other in the first direction at opposite ends of the fin structure in the substrate; In a third direction perpendicular to the top surface of the substrate, a thickness of the gate dielectric layer included in the first semiconductor element is greater than a thickness of the gate dielectric layer included in the second semiconductor element; The semiconductor device according to claim 1, wherein the source region and the drain region included in the first semiconductor element are doped with impurities of a first conductivity type and have mutually different structures.

2. the peripheral circuit region includes a sub-word line driver and a sense amplifier; the sub-word line driver includes a first semiconductor device in the first device region; 2. The semiconductor device according to claim 1, wherein the sense amplifier includes a second semiconductor element in the second element region.

3. 2. The semiconductor device according to claim 1, wherein in the first direction, the shortest distance between the gate structure and the drain region included in the first semiconductor element is greater than the shortest distance between the gate structure and the source region.

4. 4. The semiconductor device according to claim 3, wherein in a third direction perpendicular to the first direction and the second direction, a shortest distance between the gate structure and a lower surface of the drain region is smaller than a shortest distance between the gate structure and a lower surface of the source region.

5. 4. The semiconductor device according to claim 3, wherein the thickness of the drain region and the thickness of the source region are the same in a third direction perpendicular to the first direction and the second direction.

6. 4. The semiconductor device according to claim 3, wherein the thickness of the drain region and the thickness of the source region are different from each other in a third direction perpendicular to the first direction and the second direction.

7. In the first direction, the width of the drain region included in the first semiconductor element is larger than the width of the source region, 2. The semiconductor device according to claim 1, wherein the thickness of the drain region and the thickness of the source region are different from each other in a third direction perpendicular to the first direction and the second direction.

8. 2. The semiconductor device of claim 1, wherein the drain region included in the first semiconductor element includes a counter-doping region doped with impurities of a second conductivity type different from the impurities of the first conductivity type.

9. A substrate; a fin structure extending on the substrate in a first direction parallel to a top surface of the substrate; a gate structure extending over the fin structure in a second direction parallel to the top surface of the substrate and perpendicular to the first direction; a source region and a drain region spaced apart from each other in the first direction at opposite ends of the fin structure in the substrate; at least one dimension of the source region and the drain region is the same; 10. A semiconductor device comprising: a first insulating layer formed on a first insulating film and a second insulating layer formed on a second insulating film; a first insulating layer formed on a second insulating film; a second insulating layer formed on a second insulating film; a second insulating layer formed on a second insulating film;

10. A substrate; a fin structure extending on the substrate in a first direction parallel to a top surface of the substrate; a gate structure extending over the fin structure in a second direction parallel to the top surface of the substrate and perpendicular to the first direction; a source region and a drain region spaced apart from each other in the first direction at opposite ends of the fin structure in the substrate; at least one dimension of the drain region is larger than at least one dimension of the source region; 10. A semiconductor device comprising: a first gate structure and a second drain region; a first gate structure and a second drain region; a second source region and a second source region; a second gate structure and a second source region;

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