Method for forming a MOS transistor structure

Abstract

To provide a method for forming a metal-oxide-semiconductor (MOS) transistor structure.SOLUTION: A method for forming a metal-oxide-semiconductor (MOS) transistor structure includes the following steps: A plurality of fin structures are defined in a semiconductor substrate. A sacrificial spacer is formed surrounding sidewalls of each fin structure of the plurality of fin structures. A dielectric layer is formed to surround the sacrificial spacer. Then, after the sacrificial spacer is removed, a plurality of gate structures are formed, wherein each of the plurality of gate structures covers a sidewall of each of the plurality of fin structures.SELECTED DRAWING: Figure 2G

Description

[Technical Field]

[0001] The present invention relates to methods for forming integrated circuits, and more particularly to methods for forming metal-oxide-semiconductor (MOS) transistor structures. [Background technology]

[0002] The monolithic integration of silicon devices for integrated circuits (ICs) achieved over 50 billion transistors on a die in 2021. This year marked the transition from the Very Large Scale Integration (VLSI) era (over millions of transistors on a die) to Gigabyte-Scale Integration (GSI) (over billions of transistors on a die). This dramatic increase in the transistor integration capacity on a die has dramatically enabled more powerful microsystems with significantly improved PPAC (higher performance, better power management capability, effective usage of area, and lower cost per bit), resulting in a multitude of powerful chips, including CPUs, GPUs, FPGAs, SOCs, SRAMs, and DRAMs. This increased system capability continues to support Moore's Law, which is the foundation for exponential economic growth.

[0003] The high productivity generated by GSI is fueling new applications that stimulate rapid economic growth, urging the integration of more transistors on a die. Therefore, the semiconductor industry is expected to make every effort to advance toward Tera-Scale Integration (TSI) (i.e., trillions of transistors integrated on a single chip die). Therefore, to rapidly improve transistors to meet the TSI challenge, inventions and technological improvements are required for fundamentally different transistor structures with better power-phase-coupled capacitors (PPAC). For example, if a chip has one trillion transistors integrated on a die, and each transistor is designed to achieve a standby current (or Ioff) of approximately 0.5 pA (A stands for ampere), the Ioff of the entire die of one trillion transistors will approach 0.5 amperes.

[0004] However, conventional transistor technologies with a thickness of less than 20 nm rarely achieve this Ioff of 0.5 pA. Even with various transistor structures such as FinFET or Tri-Gate designs, some Ioff can be as high as 5-10 pA. How to reduce Ioff (e.g., to less than 1 pA) while continuing to shrink device dimensions is a key challenge.

[0005] An example of a conventional field-effect transistor (FinFET) includes an active region typically formed as a fin structure (as shown in FIG. 1). A transistor gate structure 5, using some conductive material (such as metal, polysilicon, or polycide) on an insulator or dielectric layer (such as oxide, oxide / nitride, or some high-k dielectric), is formed on the fin structure or 3D silicon surface. The sidewalls of the fin structure or 3D silicon surface are insulated from the sidewalls of other transistors by using insulating materials (such as oxide, oxide / nitride, or other dielectrics). For example, an NMOS transistor includes source and drain regions 11 and 12, which are formed by ion implantation and thermal annealing techniques to implant a high concentration of n-type dopants into a p-type substrate (or p-type well), resulting in two separate n+ / p junction regions. Furthermore, to mitigate impact ionization and hot carrier injection in front of the heavily doped n+ / p junction, it is common to form a lightly doped-drain (LDD) region 13 in front of the heavily doped n+ source / drain regions 11 / 12 by ion implantation+thermal annealing techniques. Such ion implantation+thermal annealing techniques frequently cause the LDD region 13 to penetrate into the portion of the 3D active region under the gate structure 5. Therefore, the effective channel between the LDD regions 13 is inevitably shortened.

[0006] Meanwhile, advances in manufacturing processing technology continue to advance rapidly by scaling down device geometries in both the horizontal (lateral) and vertical (length) directions (e.g., reducing the minimum feature size, called lambda (λ), from 28 nm to 5 nm or 3 nm). However, this scaling of FinFET or Trigate geometries has introduced or exacerbated a number of problems.

[0007] For example, as the gate length of devices is scaled down, the distance (spacing) between two adjacent fin structures can no longer be well controlled by conventional lithography and etching patterning techniques.Furthermore, the pitch or distance between the gate electrodes of two adjacent MOS transistors can also hardly be controlled by conventional lithography and etching patterning techniques.

[0008] Furthermore, when device dimensions are scaled down to 7 nm, 5 nm, or even 3 nm, the height of the fin structure (e.g., 50-100 nm) becomes much larger than the width of the fin structure (e.g., 3-10 nm), which makes the fin structure weak or even collapse during subsequent processes (e.g., source / drain formation, gate formation, etc.). Summary of the Invention

[0009] One aspect of the present disclosure provides a method for forming a metal-oxide-semiconductor (MOS) transistor structure. The method includes the following steps: first, a first fin structure and a second fin structure adjacent to the first fin structure are defined in a semiconductor substrate, where a shallow trench isolation (STI) region exists between the first fin structure and the second fin structure; next, a first sacrificial spacer is formed along a sidewall of the first fin structure, and a second sacrificial spacer is formed along a sidewall of the second fin structure, where a gap exists between the first sacrificial spacer and the second sacrificial spacer; next, an insertion dielectric layer is formed to fill the gap between the first sacrificial spacer and the second sacrificial spacer; after removing the first sacrificial spacer and the second sacrificial spacer, two gate structures are formed on the first fin structure and the second fin structure, respectively, where the two gate structures are separated by the insertion dielectric layer.

[0010] According to one embodiment of the present disclosure, the first sacrificial spacer and the second sacrificial spacer comprise epitaxial semiconductor material selectively grown on the sidewalls of the first fin structure and the second fin structure.

[0011] According to an embodiment of the present disclosure, before the step of forming the first sacrificial spacer and the second sacrificial spacer, the method further includes the steps of: first, forming a capping dielectric layer covering the first fin structure and the second fin structure, and then defining the gate opening in the capping dielectric layer so as to partially expose the sidewalls of the first fin structure and the second fin structure through the gate opening.

[0012] According to one embodiment of the present disclosure, the method further includes, before forming the capping dielectric layer, forming fin spacers to surround the sidewalls of the first fin structure and the second fin structure; and, before forming the first sacrificial spacers and the second sacrificial spacers, performing at least one etching process to remove the fin spacers in the gate openings to partially expose the sidewalls of the first fin structure and the second fin structure.

[0013] According to one embodiment of the present disclosure, the material constituting the inserting dielectric layer is different from the material constituting the capping dielectric layer.

[0014] According to one embodiment of the present disclosure, the method further includes deepening the gate opening to expose the semiconductor substrate after the epitaxial semiconductor material is formed and before the gate opening is filled with the insertion dielectric layer.

[0015] According to one embodiment of the present disclosure, during the step of deepening the gate opening, a portion of the semiconductor substrate is removed.

[0016] According to one embodiment of the present disclosure, during the deepening of the gate opening, a portion of the STI region is removed, thereby leaving another portion of the STI region underlying the epitaxial semiconductor material.

[0017] According to one embodiment of the present disclosure, the bottom of the insertion dielectric layer is lower than the bottom of the other portion of the STI region.

[0018] According to one embodiment of the present disclosure, the dielectric constant of the insertion dielectric layer is lower than that of SiO2.

[0019] According to one embodiment of the present disclosure, the first sacrificial spacer and the second sacrificial spacer comprise amorphous silicon covering the sidewalls of the first fin structure and the second fin structure.

[0020] According to one embodiment of the present disclosure, the method further includes, before the step of forming the first sacrificial spacer and the second sacrificial spacer, forming a fin spacer to surround the sidewalls of the first fin structure and the second fin structure.

[0021] According to one embodiment of the present disclosure, the method further includes forming a capping dielectric layer covering the first fin structure, the second fin structure, the first sacrificial spacer, the second sacrificial spacer, and the inserting dielectric layer; and defining gate openings in the capping dielectric layer such that the sidewalls of the first fin structure and the second fin structure are partially exposed from the gate openings.

[0022] According to one embodiment of the present disclosure, the method further includes, before the step of removing the sacrificial spacers, removing a portion of the STI region that is not covered by the first sacrificial spacers and the second sacrificial spacers so as to expose a portion of the semiconductor substrate.

[0023] According to one embodiment of the present disclosure, the bottom of the insertion dielectric layer is lower than the bottom of another portion of the STI region underlying the first sacrificial spacer and the second sacrificial spacer.

[0024] Another aspect of the present disclosure provides a MOS transistor structure. The MOS transistor structure includes a first active region, a second active region adjacent to the first active region, an insertion dielectric layer, a first trench, a second trench, a first gate structure, and a second gate structure. The first and second active regions are formed in a semiconductor substrate. An STI region exists between the first and second active regions. The insertion dielectric layer is disposed between the first and second active regions. The first trench surrounds or is over the first active region, and is adjacent to one side of the insertion dielectric layer. The second trench surrounds or is over the second active region, and is adjacent to another side of the insertion dielectric layer. The first gate structure is over the first active region and within the first trench, and covers a first portion of the STI region. The second gate structure is over the second active region and within the first trench, the second gate structure covering a second portion of the STI region, and the distance between the first gate structure and the second gate structure is determined by the padding dielectric layer.

[0025] According to an embodiment of the present disclosure, the MOS transistor structure further includes a first source region and a first drain region electrically contacting a first channel in the first active region, and a second source region and a second drain region electrically contacting a second channel in the second active region, and a width of the insertion dielectric layer between the first active region and the second active region is not defined by a photolithography process.

[0026] Yet another aspect of the present disclosure provides a MOS transistor structure. The MOS transistor structure includes a first fin structure, a second fin structure adjacent to the first fin structure, an insertion dielectric layer, a first trench, a second trench, a first gate structure, and a second gate structure. The first fin structure and the second fin structure are formed in a semiconductor substrate. An STI region exists between the first fin structure and the second fin structure. The insertion dielectric layer is disposed between the first fin structure and the second fin structure. The first trench surrounds or is on the first fin structure, and the first trench is adjacent to one side of the insertion dielectric layer. The second trench surrounds or is on the second fin structure, and the second trench is adjacent to another side of the insertion dielectric layer. The first gate structure is on the first fin structure and within the first trench, and the first gate structure covers a first portion of the STI region. The second gate structure is located on the second fin structure and within the first trench, the second gate structure covering a second portion of the STI region, and a bottom of the insertion dielectric layer is lower than a bottom of the first portion of the STI region or a bottom of the second portion of the STI region.

[0027] According to one embodiment of the present disclosure, the MOS transistor structure further includes a first source region and a first drain region electrically contacting a first channel in the first fin structure; and a second source region and a second drain region electrically contacting a second channel in the second fin structure. [Brief explanation of the drawings]

[0028] These and other aspects of the present disclosure will be better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s), the following description being made with reference to the accompanying drawings. [Figure 1] FIG. 1 illustrates a FinFET according to the prior art. [Figure 2A(1)]FIG. 1 is a top view of the structure after fin structures have been defined in the semiconductor substrate. [Figure 2A(2)] FIG. 2A is a cross-sectional view taken along the cutting line C2A1 shown in FIG. 2A(1). [Figure 2A(3)] FIG. 2A is a cross-sectional view taken along the cutting line C2A2 shown in FIG. 2A(1). [Figure 2B(1)] FIG. 10 is a top view of the structure after a capping dielectric layer has been formed over the fin structure. [Figure 2B(2)] FIG. 2B(1) is a cross-sectional view taken along the cutting line C2B1 shown in FIG. 2B(1). [Figure 2B(3)] FIG. 2B(1) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 2B(1). [Figure 2C(1)] FIG. 10 is a top view of the structure after the fin structure is partially exposed through the gate opening. [Figure 2C(2)] FIG. 2C(1) is a cross-sectional view taken along the cutting line C2C1 shown in FIG. 2C(1). [Figure 2C(3)] FIG. 2B is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 2C(1). [Figure 2D(1)] FIG. 2 is a top view of the structure after epitaxial semiconductor material has been formed. [Figure 2D(2)] FIG. 2D(1) is a cross-sectional view taken along the cutting line C2D1 shown in FIG. 2D(1). [Figure 2E(1)] FIG. 10 is a top view of the structure after the gate opening has been filled with a dielectric layer. [Figure 2E(2)] FIG. 2E(1) is a cross-sectional view taken along the cutting line C2E1 shown in FIG. 2E(1). [Figure 2F(1)] FIG. 10 is a top view of the structure after the gate structure has been formed. [Figure 2F(2)] FIG. 2F(1) is a cross-sectional view taken along the cutting line C2F1 shown in FIG. 2F(1). [Figure 2F(3)] FIG. 2F(1) is a cross-sectional view taken along the cutting line C2F2 shown in FIG. 2F(1). [Figure 2G]FIG. 2 is a perspective view showing a semiconductor device having two adjacent MOS transistors formed by the method shown in FIGS. 2A(1) to 2F(3). [Figure 3A(1)] FIG. 1 is a top view of the structure after fin structures have been defined in the semiconductor substrate. [Figure 3A(2)] FIG. 3A is a cross-sectional view taken along the cutting line C3A1 shown in FIG. 3A(1). [Figure 3A(3)] FIG. 3A is a cross-sectional view taken along the cutting line C3A2 shown in FIG. 3A(1). [Figure 3B(1)] FIG. 10 is a top view of the structure after the dielectric layer and capping dielectric layer have been formed. [Figure 3B(2)] FIG. 3B(1) is a cross-sectional view taken along the cutting line C3B1 shown in FIG. 3B(1). [Figure 3B(3)] FIG. 3B(1) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 3B(1). [Figure 3C(1)] FIG. 10 is a top view of the structure after the fin structure is partially exposed through the gate opening. [Figure 3C(2)] FIG. 3C(1) is a cross-sectional view taken along the cutting line C3C1 shown in FIG. 3C(1). [Figure 3C(3)] FIG. 3C(1) is a cross-sectional view taken along the cutting line C3C2 shown in FIG. 3C(1). [Figure 3D(1)] FIG. 10 is a top view of the structure after the gate structure has been formed. [Figure 3D(2)] FIG. 3D(1) is a cross-sectional view taken along the cutting line C3E1 shown in FIG. 3D(1). [Figure 3D(3)] FIG. 3D(1) is a cross-sectional view taken along the cutting line C3D2 shown in FIG. 3D(1). [Figure 4A(1)] FIG. 1 is a top view of the structure after fin structures have been defined in the semiconductor substrate. [Figure 4A(2)] FIG. 4A is a cross-sectional view taken along the cutting line C4A1 shown in FIG. 4A(1). [Figure 4A(3)] FIG. 4A is a cross-sectional view taken along the cutting line C4A2 shown in FIG. 4A(1). [Figure 4B(1)]FIG. 10 is a top view of the structure after a capping dielectric layer has been formed over the fin structure. [Figure 4B(2)] FIG. 4B is a cross-sectional view taken along the cutting line C4B1 shown in FIG. 4B(1). [Figure 4B(3)] FIG. 4B(1) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 4B(1). [Figure 4C(1)] FIG. 10 is a top view of the structure after the fin structure is partially exposed through the gate opening. [Figure 4C(2)] FIG. 4C(1) is a cross-sectional view taken along the cutting line C4C1 shown in FIG. 4C(1). [Figure 4C(3)] FIG. 4B is a cross-sectional view taken along the cutting line C4B2 shown in FIG. 4C(1). [Figure 4D(1)] FIG. 2 is a top view of the structure after epitaxial semiconductor material has been formed. [Figure 4D(2)] FIG. 4D(1) is a cross-sectional view taken along the cutting line C4D1 shown in FIG. 4D(1). [Figure 4E(1)] FIG. 10 is a top view of the structure after the gate opening has been deepened to expose the semiconductor substrate. [Figure 4E(2)] FIG. 4E(1) is a cross-sectional view taken along the cutting line C4E1 shown in FIG. 4E(1). [Figure 4F(1)] FIG. 10 is a top view of the structure after the gate opening has been filled with a dielectric layer. [Figure 4F(2)] FIG. 4F(1) is a cross-sectional view taken along the cutting line C4F1 shown in FIG. 4F(1). [Figure 4G(1)] FIG. 10 is a top view of the structure after the gate structure has been formed. [Figure 4G(2)] FIG. 4G(1) is a cross-sectional view taken along the cutting line C4G1 shown in FIG. 4G(1). [Figure 4G(3)] FIG. 4G(1) is a cross-sectional view taken along the cutting line C4G2 shown in FIG. 4G(1). [Figure 5A(1)] FIG. 1 is a top view of the structure after fin structures have been defined in the semiconductor substrate. [Figure 5A(2)] FIG. 5A is a cross-sectional view taken along the cutting line C5A1 shown in FIG. 5A(1). [Figure 5A(3)]FIG. 5A is a cross-sectional view taken along the cutting line C5A2 shown in FIG. 5A(1). [Figure 5B(1)] FIG. 10 is a top view of the structure after the portions of the STI not covered by the fin spacers have been removed. [Figure 5B(2)] FIG. 5B is a cross-sectional view taken along the cutting line C5B1 shown in FIG. 5B(1). [Figure 5B(3)] FIG. 5B is a cross-sectional view taken along the cutting line C5B2 shown in FIG. 5B(1). [Figure 5C(1)] FIG. 10 is a top view of the structure after the dielectric layer and capping dielectric layer have been formed. [Figure 5C(2)] FIG. 5C is a cross-sectional view taken along the cutting line C5C1 shown in FIG. 5C(1). [Figure 5C(3)] FIG. 5C is a cross-sectional view taken along the cutting line C5C2 shown in FIG. 5C(1). [Figure 5D(1)] FIG. 10 is a top view of the structure after the fin structure is partially exposed through the gate opening. [Figure 5D(2)] FIG. 5D(1) is a cross-sectional view taken along the cutting line C5D1 shown in FIG. 5D(1). [Figure 5D(3)] FIG. 5D(1) is a cross-sectional view taken along the cutting line C5D2 shown in FIG. 5D(1). [Figure 5E(1)] FIG. 10 is a top view of the structure after the gate structure has been formed. [Figure 5E(2)] FIG. 5E(1) is a cross-sectional view taken along the cutting line C5E1 shown in FIG. 5E(1). [Figure 5E(3)] FIG. 5E(1) is a cross-sectional view taken along the cutting line C5E2 shown in FIG. 5E(1). DETAILED DESCRIPTION OF THE INVENTION

[0029] The present disclosure provides a method for forming a semiconductor device having multiple MOS transistors such that the pitch between adjacent gate structures of adjacent MOS transistors is minimized and well-controlled. These and other aspects of the present disclosure will be better understood from the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

[0030] Several embodiments of the present disclosure are disclosed below with reference to the accompanying drawings. However, the structures and contents disclosed in these embodiments are for the purpose of illustration and description, and the scope of protection of the present disclosure is not limited to these embodiments. It should be noted that the present disclosure does not show all possible embodiments, and that a person skilled in the art of the present disclosure may make appropriate modifications or changes based on the specification disclosed below to meet actual needs without departing from the spirit of the present disclosure. The present disclosure may be applicable to other implementation forms not disclosed herein.

[0031] Embodiment 1 This embodiment discloses a semiconductor device 20 having two MOS transistors T21 and T22, which are formed based on two adjacent fin structures 201F1 and 201F2, respectively. The detailed steps of the method for manufacturing the semiconductor device 20 are as follows: Step S21: A plurality of fin structures 201F1 and 201F2 are defined on the semiconductor substrate 201, and each of the fin structures 201F1 and 201F2 is surrounded by a fin spacer 207; Step S21 includes substeps S211 to S215: Sub-step S211: A portion of the semiconductor substrate 201 is removed using the patterned pad dielectric layer 210 (including the patterned pad oxide layer 210A and the patterned pad nitride layer 210B), thereby defining fin structures 201F1 and 201F2. Substep S212: A shallow trench isolation (STI) region 208 is formed surrounding the fin structures 201F1 and 201F2; Substep S213: performing an etch-back process to remove portions of the shallow trench isolation (STI) region 208, so that the sidewalls of the fin structures 201F1 and 201F2 are exposed; Substep S214: A thermal oxidation process is performed so that oxide spacers 207A are formed on the sidewalls of the fin structures 201F1 and 201F2; Substep S215: A nitride deposition process is performed so that nitride spacers 207B are formed on the oxide spacers 207A; Step S22: A gate opening 202 is defined in the capping dielectric layer 209 covering the fin structures 201F1 and 201F2 and the STI 208. A sidewall of each fin structure of the fin structures 201F1 and 201F2 is partially exposed from a corresponding gate opening 202 of the plurality of gate openings 202; Step S22 includes substeps S221 to S222: Sub-step S221: An oxide deposition process is performed so as to form a capping dielectric layer 209 on the fin structures 201F1 and 201F2; Substep S222: A patterning process is performed to remove a portion of the capping dielectric layer 209 to define the gate opening 202, thereby exposing the nitride spacer 207B; Substep S223: The nitride spacers 207B and the oxide spacers 207A in the gate opening 202 are removed so that each of the fin structures 201F1 and 201F2 can be partially exposed from the gate opening 202; Step S23: forming an epitaxial semiconductor material 203 (which serves as a sacrificial spacer) on the exposed portions of the fin structures 201F1 and 201F2; Step S24: The gate opening 202 is filled with an interposed dielectric layer 211 so as to surround the epitaxial semiconductor material 203; Step S25: The epitaxial semiconductor material 203 is removed so that the exposed portions 201E1 and 201E2 of the fin structures 201F1 and 201F2 are exposed again; Step S26: Gate structures 204 and 205 are formed on the fin structures 201F1 and 201F2, respectively; step S26 includes substeps S261 to S262: Substep S261: The nitride spacers 207B and the oxide spacers 207A are removed so as to expose the fin structures 201F1 and 201F2; Sub-step S262: forming gate dielectric layers 204O and 205O covering the tops and sidewalls of the fin structures 201F1 and 201F2, respectively; Substep S263: Gate electrodes 204S and 205S are formed, covering the gate oxide layers 204O and 205O, respectively.

[0032] Referring to step S21, a plurality of fin structures 201F1 and 201F2 are defined on the semiconductor substrate 201, and each of the fin structures 201F1 and 201F2 is surrounded by a fin spacer 207. Referring to FIGS. 2A(1) to 2A(3), FIG. 2A(1) is a top view showing the structure after the fin structures 201F1 and 201F2 are defined on the semiconductor substrate 201, FIG. 2A(2) is a cross-sectional view taken along cutting line C2A1 shown in FIG. 2A(1), and FIG. 2A(3) is a cross-sectional view taken along cutting line C2A2 shown in FIG. 2A(1). The fin structures 201F1 and 201F2 are defined by the following sub-steps S211 to S215.

[0033] Referring to sub-step S211, an etching process is performed using the patterned pad dielectric layer 210 (including the patterned pad oxide layer 210A and the patterned pad nitride layer 210B) as an etching mask to remove portions of the silicon material of the semiconductor substrate 201, thereby forming trenches 201T and defining multiple fin structures 201F1 and 201F2 in the semiconductor substrate 201. In some embodiments, the distance (spacing) between two adjacent fin structures 201F1 and 201F2 may be approximately 30 to 50 nm. Each of the fin structures 201F1 and 201F2 has a thickness of approximately 3 to 10 nm (e.g., 5 nm).

[0034] Referring to sub-step S212: shallow trench isolation (STI) regions 208 are formed surrounding fin structures 201F1 and 201F2. In some embodiments of the present disclosure, an oxide material is deposited to completely fill trench 201T and then etched back, such that the oxide material remaining in trench 201T can function as STI regions 208 surrounding fin structures 201F1 and 201F2. Referring to sub-step S213: an etch-back process is performed to remove portions of shallow trench isolation (STI) regions 408, such that sidewalls of fin structures 201F1 and 201F2 are exposed.

[0035] Next, reference is made to sub-step S214: a thermal oxidation process is performed to form oxide spacers 207A on the sidewalls of fin structures 201F1 and 201F2. Reference is made to sub-step S215: a nitride deposition process is performed to form nitride spacers 207B on oxide spacers 207A (as shown in FIGS. 2A(2) and 2A(3)).

[0036] Referring to step S22, a gate opening 202 is defined in the capping dielectric layer 209 covering the fin structures 201F1 and 201F2 and the STI region 208. A sidewall of each fin structure of the fin structures 201F1 and 201F2 is partially exposed from a corresponding gate opening 202 of the plurality of gate openings 202; step S22 includes substeps S221 to S222.

[0037] Referring to substep S221, an oxide deposition process is performed to form a capping dielectric layer 209 on the fin structures 201F1 and 201F2. Referring to FIGS. 2B(1) to 2B(3), FIG. 2B(1) is a top view illustrating the structure after the capping dielectric layer 209 is formed over the fin structures 201F1 and 201F2, FIG. 2B(2) is a cross-sectional view taken along the cutting line C2B1 shown in FIG. 2B(1), and FIG. 2B(3) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 2B(1). In this embodiment, the oxide deposition process to form the capping dielectric layer 209 is followed by a planarization process. The capping dielectric layer 209 includes silicon dioxide (SiO2).

[0038] Referring to sub-step S222, a patterning process is performed to remove a portion of the capping dielectric layer 209 to define the gate opening 202, thereby exposing the nitride spacers 207B. Referring to sub-step S223, the nitride spacers 207B and the oxide spacers 207A are then removed by another etching process, respectively, so that each of the fin structures 201F1 and 201F2 can be partially exposed from the gate opening 202. Referring to FIGS. 2C(1) to 2C(3), FIG. 2C(1) is a top view showing the structure after the fin structures 201F1 and 201F2 are partially exposed from the gate opening 202, FIG. 2C(2) is a cross-sectional view taken along the cutting line C2C1 shown in FIG. 2C(1), and FIG. 2C(3) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 2C(1).

[0039] Referring to step S23, an epitaxial semiconductor material 203 (which functions as a sacrificial spacer) is formed on the exposed portions of the fin structures 401F1 and 201F2. Referring to Figures 2D(1) and 2D(2), Figure 2D(1) is a top view illustrating the structure after the epitaxial semiconductor material 203 is formed, and Figure 2D(2) is a cross-sectional view taken along the cutting line C2D1 shown in Figure 2D(1). In some embodiments of the present disclosure, the epitaxial semiconductor material 203 (e.g., Si, SiGe, Ge, etc.) is formed on the exposed portions of the fin structures 201F1 and 201F2 by a selective epitaxy growth (SEG) method. In some other embodiments of the present disclosure, depending on the material of the fin structures, other semiconductor epitaxial materials (e.g., SiC, gallium arsenide (GaAs), gallium nitride (GaN), etc.) may be grown on the exposed portions of fin structures 201F1 and 201F2. The epitaxial semiconductor material 203 has a thickness of approximately 5-12 nm (e.g., 7-8 nm).

[0040] Next, referring to step S24: the gate opening 202 is filled with an insertion dielectric layer 211. See FIGS. 2E(1) and 2E(2). FIG. 2E(1) is a top view illustrating the structure after the gate opening 202 is filled with the insertion dielectric layer 211, and FIG. 2E(2) is a cross-sectional view taken along the section line C2E1 shown in FIG. 2E(1). In some embodiments of the present disclosure, the material constituting the insertion dielectric layer 211 may be different from the material constituting the capping dielectric layer 209. In this embodiment, the insertion dielectric layer 211 is formed by a low-k dielectric material (e.g., SiCOH) deposition process. The insertion dielectric layer 211 may then be etched back. As a result, the patterned pad nitride layer 210B (or even the pad oxide layer 210A) can be exposed from the partially filled gate opening 202. Furthermore, as shown in FIG. 2E(2), the distance D2 between the two epitaxial semiconductor materials 203 or sacrificial spacers may be approximately 15 to 30 nm (e.g., 20 nm), and the distance D2 may be equal to or substantially equal to the “gate cut” distance or “poly cut” distance between the two gate structures of adjacent transistors.

[0041] Referring to step S25: the epitaxial semiconductor material 203 is removed, resulting in the formation of voids and re-exposing the sidewalls of the fin structures 201F1 and 201F2. Next, referring to step S26: gate structures 204 and 205 are formed on the fin structures 201F1 and 201F2, respectively. See FIGS. 2F(1) and 2F(2). FIG. 2F(1) is a top view showing the structure after the gate structures 204 and 205 are formed. FIG. 2F(2) is a cross-sectional view taken along the cutting line C2F1 shown in FIG. 2F(1). FIG. 2F(3) is a cross-sectional view taken along the cutting line C2F2 shown in FIG. 2F(1).

[0042] Step S26 for forming gate structures 204 and 205 includes substeps S261 to S262: Refer to substep S461: removing nitride spacers 207B and oxide spacers 207A so as to expose fin structures 201F1 and 201F2. In this embodiment, nitride spacers 207B and oxide spacers 207A are removed by different etching processes, respectively.

[0043] Next, reference is made to sub-step S262: forming gate dielectric layers 204O and 205O, which cover the tops and sidewalls of fin structures 201F1 and 201F2, respectively. In some embodiments of the present disclosure, gate dielectric layers 204O and 205O are formed by an oxide deposition process. Next, reference is made to sub-step S263: forming gate electrodes 204S and 205S, which cover gate dielectric layers 204O and 205O, respectively. In some embodiments of the present disclosure, gate electrodes 204S and 205S are formed by polysilicon or metal. Thus, the voids formed after epitaxial semiconductor material 203 is removed are just filled with gate dielectric layers 204O and 205O and gate electrodes 204S and 205S.

[0044] After the formation of gate structures 204 and 205, source / drain regions for the transistors may be formed. For example, portions of the fin structure outside the gate regions are removed, and localized insulation portions 215 and 225 are (optionally) formed in semiconductor substrate 201. Source region 212, including LDD region (e.g., N-semiconductor region) 212A, N+ semiconductor region 212B, and landing pad 212C, and drain region 213, including LDD region (e.g., N-semiconductor region) 213A, N+ semiconductor region 213B, and landing pad 213C, are formed on localized insulation portions 215 and electrically contact fin structure 201F1. Landing pad 212C (or 213C) may contact the lateral-most sidewall of N+ semiconductor region 212B (or 213B). Similarly, source region 222, including LDD region (e.g., N-semiconductor region) 222A, N+ semiconductor region 222B, and landing pad 222C, and drain region 223, including LDD region (e.g., N-semiconductor region) 223A, N+ semiconductor region 223B, and landing pad 223C, are formed on localized insulation 225 and electrically contact fin structure 201F2. As a result, semiconductor device 20 (see FIG. 2G) is formed having two adjacent MOS transistors T21 and T22, spaced apart by a gate electrode pitch P2 (also referred to as a "gate cut" distance or a "poly cut" distance). Gate electrode pitch P2 may be equal to a distance D2 defined by a portion of dielectric material 211 disposed between two adjacent fin structures 201F1 and 201F2.

[0045] After a series of downstream process steps are performed, the semiconductor device 20 (e.g., an SRAM cell) employing the MOS transistors T21 and T22 can be formed. A certain distance D2 can be well controlled by the dielectric material 211 deposited in the gate opening 202, which is much smaller than the conventional lithography rule used to define the gate electrode pitch of two adjacent MOS transistors. Therefore, the gate electrode pitch P2 between the two adjacent MOS transistors T21 and T22 can be significantly minimized.

[0046] Furthermore, the fin structures 201F1 and 201F2 can be protected by the fin spacer 207 before the formation of the gate and source / drain, and can also be well supported by the first dielectric material 209, thereby preventing the fin structures 201F1 and 201F2 from collapsing during the processes for forming the gate structures 204 and 205, the source regions 212 / 222, and the drain regions 213 / 223.

[0047] Embodiment 2 This embodiment discloses another semiconductor device 30 having two MOS transistors T31 and T32, which are formed based on two adjacent fin structures 301F1 and 301F2, respectively. The detailed steps of the manufacturing method for the semiconductor device 30 are as follows: Step S31: A plurality of fin structures 301F1 and 301F2 are defined on the semiconductor substrate 301, and each of the fin structures 301F1 and 301F2 is surrounded by a fin spacer 307; Step S31 includes substeps S311 to S313: Sub-step S311: A portion of the semiconductor substrate 301 is removed using the patterned pad dielectric layer 310 (including the patterned pad oxide layer 310A and the patterned pad nitride layer 310B), thereby defining fin structures 301F1 and 301F2. Substep S312: A shallow trench isolation (STI) 308 is formed surrounding the fin structures 301F1 and 301F2; Substep S313: performing an etch-back process to remove portions of the shallow trench isolation (STI) 308, so that the sidewalls of the fin structures 301F1 and 301F2 are exposed; Substep S314: A thermal oxidation process is performed so that oxide spacers 307A are formed on the sidewalls of the fin structures 301F1 and 301F2; Substep S315: A nitride deposition process is performed so that nitride spacers 307B are formed on the oxide spacers 307A; Substep S316: Amorphous silicon spacers 307C (which function as sacrificial spacers) are formed on the nitride spacers 307B; Step S32: A gate opening 302 is defined in the capping dielectric layer 309 covering the fin structures 301F1 and 301F2 and the STI 308. A sidewall of each fin structure of the fin structures 301F1 and 301F2 is partially exposed from a corresponding gate opening 302 of the plurality of gate openings 302. Step S32 includes sub-steps S321 to S324: Substep S321: An interposing dielectric layer 311 is formed so as to surround the sidewalls of the fin structures 301F1 and 301F2; Substep S322: An oxide deposition process is performed so that a capping dielectric layer 309 is formed on the fin structures 301F1 and 301F2 and on the inserting dielectric layer 311; Substep S323: performing a patterning process to remove a portion of the capping dielectric layer 309, thereby defining a gate opening 302; Substep S324: The amorphous silicon spacers 307C, the nitride spacers 307B, and the oxide spacers 307A are removed so that each of the fin structures 301F1 and 301F2 can be partially exposed from the gate opening 302; Step S33: Gate structures 304 and 305 are formed on the fin structures 301F1 and 301F2, respectively; step S33 includes substeps S331 to S332: Sub-step S331: forming gate dielectric layers 304O and 305O covering the tops and sidewalls of the fin structures 301F1 and 301F2, respectively; Substep S332: Gate electrodes 304S and 305S are formed, covering the gate oxide layers 304O and 305O, respectively.

[0048] Referring to step S31, a plurality of fin structures 301F1 and 301F2 are defined on the semiconductor substrate 301, and each of the fin structures 301F1 and 301F2 is surrounded by a fin spacer 307. Referring to FIGS. 3A(1) to 3A(3), FIG. 3A(1) is a top view showing the structure after the fin structures 301F1 and 301F2 are defined on the semiconductor substrate 301, FIG. 3A(2) is a cross-sectional view taken along cutting line C3A1 shown in FIG. 3A(1), and FIG. 3A(3) is a cross-sectional view taken along cutting line C3A2 shown in FIG. 3A(1). The fin structures 301F1 and 301F2 are defined by the following sub-steps S311 to S315.

[0049] Referring to substep S311, an etching process is performed using the patterned pad dielectric layer 310 (including the patterned pad oxide layer 310A and the patterned pad nitride layer 310B) as an etching mask to remove portions of the silicon material of the semiconductor substrate 301, thereby forming trenches 301T and defining multiple fin structures 301F1 and 301F2 in the semiconductor substrate 301. In some embodiments, the distance between two adjacent fin structures 301F1 and 301F2 may be approximately 30 to 50 nm. Each of the fin structures 301F1 and 301F2 has a thickness of approximately 3 to 10 nm (e.g., 5 nm).

[0050] Referring to sub-step S312: forming shallow trench isolation (STI) regions 308 surrounding fin structures 301F1 and 301F2. In some embodiments of the present disclosure, an oxide material is deposited to completely fill trench 301T and then etched back, so that the oxide material remaining in trench 301T can function as STI 308 surrounding multiple fin structures 301F1 and 301F2. Referring to sub-step S313: performing an etch-back process to remove portions of shallow trench isolation (STI) regions 308, so that sidewalls of fin structures 301F1 and 301F2 are exposed.

[0051] Next, reference is made to sub-step S314: a thermal oxidation process is performed to form oxide spacers 307A on sidewalls of fin structures 301F1 and 301F2. Next, reference is made to sub-step S315: a nitride deposition process is performed to form nitride spacers 307B on oxide spacers 307A. Next, reference is made to sub-step S316: amorphous silicon spacers 307C (which function as sacrificial spacers) are formed on nitride spacers 307B. In some embodiments of the present disclosure, forming amorphous silicon spacers 307C includes depositing amorphous silicon to cover fin spacers 307, shallow trench isolation (STI) 308, and fin structures 301F1 and 301F2, and performing an anisotropic etching process to remove portions of the amorphous silicon so as to leave portions of the amorphous silicon disposed on sidewalls of nitride spacers 307B. Each of the amorphous silicon spacers 307C has a thickness of approximately 5 to 10 nm.

[0052] Referring to step S32, gate openings 302 are defined in the capping dielectric layer 309 covering the fin structures 301F1 and 301F2 and the STIs 308. A sidewall of each fin structure of the fin structures 301F1 and 301F2 is partially exposed from a corresponding one of the gate openings 302. Step S32 includes substeps S321 to S324.

[0053] Referring to sub-step S321: an insertion dielectric layer 311 is formed so as to surround the sidewalls of the fin structures 301F1 and 301F2. Referring to sub-step S322: an oxide deposition process is performed so as to form a capping dielectric layer 309 on the fin structures 301F1 and 301F2 and on the insertion dielectric layer 311. Referring to FIGS. 3B(1) to 3B(3), FIG. 3B(1) is a top view showing the structure after the insertion dielectric layer 311 and the capping dielectric layer 309 have been formed, FIG. 3B(2) is a cross-sectional view taken along the cutting line C3B1 shown in FIG. 3B(1), and FIG. 3B(3) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 3B(1).

[0054] In some embodiments of the present disclosure, the material constituting the insertion dielectric layer 311 may be different from the material constituting the capping dielectric layer 309. In this embodiment, the insertion dielectric layer 311 is formed by a process of depositing a low-k dielectric material (e.g., SiCOH) to fill the trench 301T. The deposited low-k dielectric material may be planarized by chemical-mechanical polishing (CMP) and then etched back using the pad nitride layer 310B, nitride spacers 307B, and amorphous silicon spacers 307C as etch stop layers. As a result, the pad nitride layer 310B, nitride spacers 307B, and amorphous silicon spacers 307C may be exposed from the partially filled trench 301T. Sub-step S322: An oxide deposition process for forming the capping dielectric layer 309 includes depositing SiO2 to cover the pad nitride layer 310B, the nitride spacers 307B, and the amorphous silicon spacers 307C, and the oxide deposition process is followed by a planarization process (e.g., CMP).

[0055] Referring to sub-step S323: a patterning process is performed to remove portions of the capping dielectric layer 309, thereby defining the gate opening 302. In some embodiments, a patterned photoresist layer (not shown) is formed on the capping dielectric layer 309 to expose the portions of the capping dielectric layer 309 covering the fin structures 301F1 and 301F2. An etching process is then performed to remove the exposed portions of the capping dielectric layer 309, thereby defining the gate opening 302 in the capping dielectric layer 309.

[0056] Referring to substep S324: the amorphous silicon spacers 307C, the nitride spacers 307B, and the oxide spacers 307A are removed so that each of the fin structures 301F1 and 301F2 can be partially exposed from the gate opening 302. Referring to Figures 3C(1) to 3C(3), Figure 3C(1) is a top view showing the structure after the fin structures 301F1 and 301F2 are partially exposed from the gate opening 302, Figure 3C(2) is a cross-sectional view taken along the cutting line C3C1 shown in Figure 3C(1), and Figure 3C(3) is a cross-sectional view taken along the cutting line C3C2 shown in Figure 3C(1).

[0057] In this embodiment, after the gate opening 302 is defined in the capping dielectric layer 309, another etching process is performed to remove the amorphous silicon spacers 307C. After the patterned photoresist layer is stripped, another process is performed to remove the nitride spacers 307B and portions of the patterned pad nitride 310B from the gate opening 302. Next, the oxide spacers 307A and portions of the patterned pad oxide layer 310A exposed from the gate opening 302 are removed by another etching process, resulting in the top and sidewalls of each fin structure 301F1 and 301F2 being exposed.

[0058] Referring to step S33: gate structures 304 and 305 are formed on fin structures 301F1 and 301F2, respectively. See Figures 3D(1) to 3D(3). Figure 3D(1) is a top view showing the structure after gate structures 304 and 305 are formed, Figure 3D(2) is a cross-sectional view taken along section line C3E1 shown in Figure 3D(1), and Figure 3D(3) is a cross-sectional view taken along section line C3D2 shown in Figure 3D(1).

[0059] Step S33 for forming the gate structures 304 and 305 includes substeps S331-S332: Refer to substep S331: forming gate dielectric layers 304O and 305O, which cover the tops and sidewalls of the fin structures 301F1 and 301F2, respectively. In some embodiments of the present disclosure, the gate dielectric layers 304O and 305O are formed by an oxide deposition process. Next, refer to substep S332: forming gate electrodes 304S and 305S, which cover the gate dielectric layers 304O and 305O, respectively. In some embodiments of the present disclosure, the gate electrodes 304S and 305S are formed by polysilicon or metal.

[0060] After the formation of the gate structures 304 and 305, the capping dielectric layer 309 may be removed and the source / drain regions may be formed as described above. Again, the second dielectric material of the insertion dielectric layer 311 deposited in the gate opening 302 allows for good control of this distance, which is much smaller than the conventional lithography rules used to define the gate electrode pitch of two adjacent MOS transistors. Therefore, the gate electrode pitch between the two adjacent MOS transistors T31 and T32 can be significantly minimized.

[0061] Furthermore, the sidewalls of the fin structures 301F1 and 301F2 can be protected by the fin spacer 307 before the formation of the gate and source / drain, and can also be well supported by the first dielectric material of the capping dielectric layer 309 and the second dielectric material of the inserting dielectric layer 311, thereby preventing the fragile fin structures 301F1 and 301F2 from collapsing during the processes for forming the gate structures 304 and 305, the source regions 312 / 322, and the drain regions 313 / 323.

[0062] Embodiment 3 This embodiment discloses a semiconductor device 40 having two MOS transistors T41 and T42, which are formed based on two adjacent fin structures 401F1 and 401F2, respectively. The detailed steps of the method for manufacturing the semiconductor device 40 are as follows: Step S41: A plurality of fin structures 401F1 and 401F2 are defined on the semiconductor substrate 401, and each of the fin structures 401F1 and 401F2 is surrounded by a fin spacer 407; Step S41 includes substeps S411 to S415: Sub-step S411: A portion of the semiconductor substrate 401 is removed using a patterned pad dielectric layer 410 (including a patterned pad oxide layer 410A and a patterned pad nitride layer 410B), thereby defining fin structures 401F1 and 401F2; Substep S412: A shallow trench isolation (STI) region 408 is formed surrounding the fin structures 401F1 and 401F2; Substep S413: performing an etch-back process to remove portions of the shallow trench isolation (STI) region 408, thereby exposing the sidewalls of the fin structures 401F1 and 401F2; Substep S414: A thermal oxidation process is performed so that oxide spacers 407A are formed on the sidewalls of the fin structures 401F1 and 401F2; Substep S415: A nitride deposition process is performed so that nitride spacers 407B are formed on the oxide spacers 407B; Step S42: A gate opening 402 is defined in the capping dielectric layer 409 covering the fin structures 401F1 and 401F2 and the STI 408. A sidewall of each fin structure of the fin structures 401F1 and 401F2 is partially exposed from a corresponding gate opening 402 of the plurality of gate openings 402; Step S42 includes substeps S421 to S422: Sub-step S421: An oxide deposition process is performed so as to form a capping dielectric layer 409 on the fin structures 401F1 and 401F2; Substep S422: A patterning process is performed to remove a portion of the capping dielectric layer 409 to define the gate opening 402, thereby exposing the nitride spacer 407B; Substep S423: The nitride spacer 407B and the oxide spacer 407B in the gate opening 402 are removed so that each of the fin structures 401F1 and 401F2 can be partially exposed from the gate opening 402; Step S43: forming an epitaxial semiconductor material 403 (which serves as a sacrificial spacer) on the exposed portions of the fin structures 401F1 and 401F2; Step S44: The gate opening 402 is deepened by etching the STI region 408 in the gate opening 402 so as to expose the semiconductor substrate 401; Step S45: The gate opening 402 is filled with an intercalating dielectric layer 411 so as to surround the epitaxial semiconductor material 403; Step S46: The epitaxial semiconductor material 403 is removed so that the exposed portions 401E1 and 401E2 of the fin structures 401F1 and 401F2 are exposed again; Step S47: Gate structures 404 and 405 are formed on the fin structures 401F1 and 401F2, respectively.

[0063] Referring to step S41, a plurality of fin structures 401F1 and 401F2 are defined on the semiconductor substrate 401, and each of the fin structures 401F1 and 401F2 is surrounded by a fin spacer 407. Referring to FIGS. 4A(1) to 4A(3), FIG. 4A(1) is a top view showing the structure after the fin structures 401F1 and 401F2 are defined on the semiconductor substrate 401, FIG. 4A(2) is a cross-sectional view taken along cutting line C4A1 shown in FIG. 4A(1), and FIG. 4A(3) is a cross-sectional view taken along cutting line C4A2 shown in FIG. 4A(1). The fin structures 401F1 and 401F2 are defined by the following sub-steps S411 to S415.

[0064] Referring to substep S411, an etching process is performed using the patterned pad dielectric layer 410 (including the patterned pad oxide layer 410A and the patterned pad nitride layer 410B) as an etching mask to remove portions of the silicon material of the semiconductor substrate 401, thereby forming trenches 401T and defining multiple fin structures 401F1 and 401F2 in the semiconductor substrate 401. In some embodiments, the distance between two adjacent fin structures 401F1 and 401F2 may be approximately 30 to 50 nm. Each of the fin structures 401F1 and 401F2 has a thickness of approximately 3 to 10 nm (e.g., 5 nm).

[0065] Reference is made to sub-step S412: shallow trench isolation (STI) regions 408 are formed surrounding the fin structures 401F1 and 401F2. In some embodiments of the present disclosure, an oxide material is deposited to completely fill the trench 401T and then etched back, such that the oxide material remaining in the trench 401T can function as the STI regions 408 surrounding the plurality of fin structures 401F1 and 401F2. Reference is made to sub-step S413: an etch-back process is performed to remove portions of the shallow trench isolation (STI) regions 408, such that the sidewalls of the fin structures 401F1 and 401F2 are exposed.

[0066] Next, reference is made to sub-step S414: a thermal oxidation process is performed to form oxide spacers 407A on the sidewalls of fin structures 401F1 and 401F2. Reference is made to sub-step S415: a nitride deposition process is performed to form nitride spacers 407B on oxide spacers 407A (as shown in FIGS. 4A(2) and 4A(3)).

[0067] Referring to step S42, a gate opening 402 is defined in the capping dielectric layer 409 covering the fin structures 401F1 and 401F2 and the STI 408. A sidewall of each fin structure of the fin structures 401F1 and 401F2 is partially exposed from a corresponding gate opening 402 of the plurality of gate openings 402; step S42 includes substeps S421 to S422.

[0068] Referring to substep S421, an oxide deposition process is performed to form a capping dielectric layer 209 on the fin structures 201F1 and 401F2. Referring to FIGS. 4B(1)-4B(3), FIG. 4B(1) is a top view illustrating the structure after the capping dielectric layer 409 is formed over the fin structures 401F1 and 401F2, FIG. 4B(2) is a cross-sectional view taken along the cutting line C4B1 shown in FIG. 4B(1), and FIG. 4B(3) is a cross-sectional view taken along the cutting line C2B2 shown in FIG. 4B(1). In this embodiment, the oxide deposition process to form the capping dielectric layer 409 is followed by a planarization process. The capping dielectric layer 409 includes SiO2.

[0069] Referring to sub-step S422: a patterning process is performed to remove a portion of the capping dielectric layer 209 to define the gate opening 402, thereby exposing the nitride spacers 407B. Referring to sub-step S423: the nitride spacers 407B and the oxide spacers 407A are then removed by another etching process, respectively, so that each of the fin structures 401F1 and 401F2 can be partially exposed from the gate opening 402. Referring to FIGS. 4C(1) to 4C(3), FIG. 4C(1) is a top view showing the structure after the fin structures 401F1 and 401F2 are partially exposed from the gate opening 402, FIG. 4C(2) is a cross-sectional view taken along the cutting line C4C1 shown in FIG. 4C(1), and FIG. 4C(3) is a cross-sectional view taken along the cutting line C4B2 shown in FIG. 4C(1).

[0070] Referring to step S43, an epitaxial semiconductor material 403 (which functions as a sacrificial spacer) is formed on the exposed portions of the fin structures 401F1 and 401F2. Referring to FIGS. 4D(1) and 4D(2), FIG. 4D(1) is a top view illustrating the structure after the epitaxial semiconductor material 403 is formed, and FIG. 4D(2) is a cross-sectional view taken along the cutting line C4D1 shown in FIG. 4D(1). In some embodiments of the present disclosure, the epitaxial semiconductor material 403 (e.g., Si, SiGe, Ge, etc.) is formed on the exposed portions of the fin structures 401F1 and 401F2 by a SEG method. In some other embodiments of the present disclosure, other semiconductor epitaxial materials (e.g., GaAs, GaN, SiC, etc.) may be grown on the exposed portions of the fin structures 401F1 and 401F2. The epitaxial semiconductor material 403 has a thickness of approximately 5 to 12 nm (eg, 7 to 8 nm).

[0071] Next, reference is made to step S44: the gate opening 402 is deepened to expose the semiconductor substrate 401. See FIGS. 4E(1) and 4E(2). FIG. 4E(1) is a top view illustrating the structure after the gate opening 402 has been deepened to expose the semiconductor substrate 401, and FIG. 4E(2) is a cross-sectional view taken along cut line C4E1 shown in FIG. 4E(1). In some embodiments of the present disclosure, an etching process is performed to remove portions of the STI regions 408 exposed from the gate opening 402 and portions of the semiconductor substrate 401 underlying the removed portions of the STI regions 408.

[0072] Hereinafter, reference will be made to step S45: the gate opening 402 is filled with an insertion dielectric layer 411 so as to surround the epitaxial semiconductor material 403 and the remaining STI 408. See FIGS. 4F(1) and 4F(2). FIG. 4F(1) is a top view showing the structure after the gate opening 402 is filled with the insertion dielectric layer 411, and FIG. 4F(2) is a cross-sectional view taken along the cutting line C4F1 shown in FIG. 4F(1). In some embodiments of the present disclosure, the material constituting the insertion dielectric layer 411 may be different from the material constituting the capping dielectric layer 409. In this embodiment, the insertion dielectric layer 411 is formed by a low-k dielectric material (e.g., SiCOH) deposition process. The bottom of the insertion dielectric layer 411 (SiCOH) is lower than the bottom of the STI 408. The dielectric constant of the insertion dielectric layer 411 (SiCOH) is lower than that of the STI 408, which may improve the coupling effect between the two gate structures 404 and 406 (which will be formed later; see Figures 4G(1) to 4G(3)). The insertion dielectric layer 411 may then be etched back, exposing the patterned pad nitride layer 410B from the partially filled gate opening 402. Furthermore, as shown in Figure 4F(2), the distance D4 between the two epitaxial semiconductor materials 403 or sacrificial spacers may be approximately 15 to 30 nm (e.g., 20 nm), and the distance D4 may be equal to or substantially equal to the "gate cut" distance or "poly cut" distance between the two gate structures of adjacent transistors. The distance D4 may be equal to the width of the insertion dielectric layer 411 between the fin structures 401F1 and 401F2.

[0073] Referring to step S46, the epitaxial semiconductor material 403 is removed, thereby forming voids and re-exposing the sidewalls of the fin structures 401F1 and 401F2. Then, referring to step S47, gate structures 404 and 405 are formed on the fin structures 401F1 and 401F2, respectively. See FIGS. 4G(1) to 4G(3). FIG. 4G(1) is a top view showing the structure after the gate structures 404 and 405 are formed, FIG. 4G(2) is a cross-sectional view taken along the cutting line C4G1 shown in FIG. 4G(1), and FIG. 4G(3) is a cross-sectional view taken along the cutting line C4G2 shown in FIG. 4G(1).

[0074] Step S47 for forming gate structures 404 and 405 includes substeps S471 to S473: Referring to substep S471, nitride spacers 407B and oxide spacers 407A are removed so as to expose fin structures 401F1 and 401F2. In this embodiment, nitride spacers 407B and oxide spacers 407A are removed by different etching processes, respectively.

[0075] Next, reference is made to sub-step S472: forming gate dielectric layers 404O and 405O, which cover the tops and sidewalls of fin structures 401F1 and 401F2, respectively. In some embodiments of the present disclosure, the gate dielectric layers 404O and 405O are formed by an oxide deposition process. Next, reference is made to sub-step S473: forming gate electrodes 404S and 405S, which cover the gate dielectric layers 404O and 405O, respectively. In some embodiments of the present disclosure, the gate electrodes 404S and 405S are formed by polysilicon or metal. Thus, the voids formed after the epitaxial semiconductor material 403 is removed are just filled with the gate dielectric layers 404O and 405O and the gate electrodes 204S and 205S.

[0076] After forming the gate structures 404 and 405, the source / drain regions for the transistors may be formed as previously described.

[0077] Compared with embodiment I, in this embodiment, the bottom of the insertion dielectric layer 411 (SiCOH) between the two gate structures 404 and 405 is lower than the bottom of the STI 408. Because the dielectric constant of the insertion dielectric layer 411 (SiCOH) is lower than that of the STI region 408, the coupling effect between the two gate structures 404 and 405 may be improved.

[0078] Embodiment 4 This embodiment discloses another semiconductor device 50 having two MOS transistors T51 and T52, which are formed based on two adjacent fin structures 501F1 and 501F2, respectively. The detailed steps of the method for manufacturing the semiconductor device 50 are as follows: Step S51: A plurality of fin structures 501F1 and 501F2 are defined on a semiconductor substrate 501, and each of the fin structures 501F1 and 501F2 is surrounded by a fin spacer 507; Step S51 includes substeps S511 to S513: Sub-step S511: A portion of the semiconductor substrate 501 is removed using a patterned pad dielectric layer 510 (including a patterned pad oxide layer 510A and a patterned pad nitride layer 510B), thereby defining fin structures 501F1 and 501F2; Substep S512: shallow trench isolation (STI) regions 508 are formed surrounding the fin structures 501F1 and 501F2; Substep S513: performing an etch-back process to remove portions of the shallow trench isolation (STI) region 508, thereby exposing the sidewalls of the fin structures 501F1 and 501F2; Substep S514: A thermal oxidation process is performed so that oxide spacers 507A are formed on the sidewalls of the fin structures 501F1 and 501F2; Substep S515: A nitride deposition process is performed so that nitride spacers 507B are formed on the oxide spacers 507A; Substep S516: Amorphous silicon spacers 507C (which function as sacrificial spacers) are formed on the nitride spacers 507B; Step S52: The portions of the STI 508 that are not covered by the fin spacers 507 (including the oxide spacers 507A, the nitride spacers 507B, and the amorphous silicon spacers 507C) are removed, thereby exposing the portions of the semiconductor substrate 501 underlying the removed portions of the STI 508; Step S53: A gate opening 502 is defined in the capping dielectric layer 509 covering the fin structures 501F1 and 501F2 and the STI 508. A sidewall of each fin structure of the fin structures 501F1 and 501F2 is partially exposed from a corresponding gate opening 502 of the plurality of gate openings 502; Step S53 includes substeps S531 to S534: Substep S531: An interposing dielectric layer 511 is formed so as to surround the sidewalls of the fin structures 501F1 and 501F2; Substep S532: An oxide deposition process is performed so that a capping dielectric layer 509 is formed on the fin structures 501F1 and 501F2 and on the inserting dielectric layer 511; Substep S533: performing a patterning process to remove a portion of the capping dielectric layer 509, thereby defining the gate opening 502; Substep S534: The amorphous silicon spacers 507C, the nitride spacers 507B, and the oxide spacers 507A are removed so that each of the fin structures 501F1 and 501F2 can be partially exposed from the gate opening 502; Step S54: Gate structures 504 and 505 are formed on the fin structures 501F1 and 501F2, respectively; step S54 includes substeps S541 to S542: Substep S541: forming gate dielectric layers 504O and 505O covering the tops and sidewalls of the fin structures 501F1 and 501F2, respectively; Substep S542: Gate electrodes 504S and 505S are formed, covering the gate oxide layers 504O and 505O, respectively.

[0079] Referring to step S51, a plurality of fin structures 501F1 and 501F2 are defined in the semiconductor substrate 501, and each of the fin structures 501F1 and 501F2 is surrounded by a fin spacer 507. Referring to FIGS. 5A(1) to 5A(3), FIG. 5A(1) is a top view illustrating the structure after the fin structures 501F1 and 501F2 are defined in the semiconductor substrate 501, FIG. 5A(2) is a cross-sectional view taken along cutting line C5A1 shown in FIG. 5A(1), and FIG. 5A(3) is a cross-sectional view taken along cutting line C5A2 shown in FIG. 5A(1). The fin structures 501F1 and 501F2 are defined by the following sub-steps S511 to S515.

[0080] Referring to substep S511, an etching process is performed using the patterned pad dielectric layer 510 (including the patterned pad oxide layer 510A and the patterned pad nitride layer 510B) as an etching mask to remove portions of the silicon material of the semiconductor substrate 501, thereby forming trenches 501T and defining multiple fin structures 501F1 and 501F2 in the semiconductor substrate 501. In some embodiments, the distance between two adjacent fin structures 501F1 and 501F2 may be approximately 30 to 50 nm. Each of the fin structures 501F1 and 501F2 has a thickness of approximately 3 to 10 nm (e.g., 5 nm).

[0081] Reference is made to sub-step S512: shallow trench isolation (STI) 508 is formed surrounding fin structures 501F1 and 501F2. In some embodiments of the present disclosure, oxide material is deposited to completely fill trench 501T and then etched back, such that the oxide material remaining in trench 501T can function as STI 508 surrounding multiple fin structures 501F1 and 501F2. Reference is made to sub-step S513: an etch-back process is performed to remove portions of shallow trench isolation (STI) region 508, such that sidewalls of fin structures 501F1 and 501F2 are exposed.

[0082] Next, reference is made to sub-step S514: a thermal oxidation process is performed to form oxide spacers 307A on sidewalls of fin structures 501F1 and 501F2. Next, reference is made to sub-step S515: a nitride deposition process is performed to form nitride spacers 507B on oxide spacers 507A. Next, reference is made to sub-step S516: amorphous silicon spacers 507C (which function as sacrificial spacers) are formed on nitride spacers 507B. In some embodiments of the present disclosure, forming amorphous silicon spacers 507C includes depositing amorphous silicon to cover fin spacers 507, shallow trench isolation (STI) 508, and fin structures 501F1 and 501F2, and performing an anisotropic etching process to remove portions of the amorphous silicon so as to leave portions of the amorphous silicon disposed on sidewalls of nitride spacers 507B. Each of the amorphous silicon spacers 507C has a thickness of approximately 5 to 10 nm.

[0083] Referring to step S52, portions of the STI regions 508 not covered by the fin spacers 507 (including the oxide spacers 507A, the nitride spacers 507B, and the amorphous silicon spacers 507C) are removed, thereby exposing portions of the semiconductor substrate 501 underlying the removed portions of the STI regions 508. Referring to FIGS. 5B(1) to 5B(3), FIG. 5B(1) is a top view showing the structure after the portions of the STI regions 508 not covered by the fin spacers 507 have been removed, FIG. 5B(2) is a cross-sectional view taken along the cutting line C5B1 shown in FIG. 5B(1), and FIG. 5B(3) is a cross-sectional view taken along the cutting line C5B2 shown in FIG. 5B(1).

[0084] In this embodiment, the portions of semiconductor substrate 501 that underlie the removed portions of STI regions 508 may also be removed so that the top surface of the remaining portions of semiconductor substrate 501 is lower than the bottom of the remaining STI regions 508.

[0085] Referring to step S53: gate openings 502 are defined in a capping dielectric layer 509 covering the fin structures 501F1 and 501F2 and the STIs 508. A sidewall of each fin structure of the fin structures 501F1 and 501F2 is partially exposed from a corresponding gate opening 502 of the plurality of gate openings 502. Step S53 includes substeps S531 to S534.

[0086] Referring to sub-step S531: an insert dielectric layer 511 is formed so as to surround the sidewalls of the fin structures 501F1 and 501F2. Referring to sub-step S532: an oxide deposition process is performed so as to form a capping dielectric layer 509 on the fin structures 501F1 and 501F2 and on the insert dielectric layer 511. Referring to FIGS. 5C(1) to 5C(3), FIG. 5C(1) is a top view showing the structure after the insert dielectric layer 511 and the capping dielectric layer 509 are formed, FIG. 5C(2) is a cross-sectional view taken along the cutting line C5C1 shown in FIG. 5C(1), and FIG. 5C(3) is a cross-sectional view taken along the cutting line C5C2 shown in FIG. 5C(1).

[0087] In some embodiments of the present disclosure, the material constituting the dielectric layer 511 may be different from the material constituting the capping dielectric layer 509. In this embodiment, the dielectric layer 511 is formed by a process of depositing a low-k dielectric material (e.g., SiCOH) to cover the top surface of the remaining portion of the semiconductor substrate 501. The deposited low-k dielectric material may be planarized by chemical mechanical polishing (CMP) and then etched back using the patterned pad nitride layer 510B, nitride spacers 507B, and amorphous silicon spacers 507C as an etch stop layer. As a result, the patterned pad nitride layer 510B, nitride spacers 507B, and amorphous silicon spacers 507C may be exposed from the partially filled trench 501T.

[0088] Substep S532: An oxide deposition process for forming the capping dielectric layer 509 includes depositing SiO to fill the trench 501T, followed by a planarization process (e.g., CMP). The bottom of the insertion dielectric layer 511 (SiCOH) is lower than the bottom of the remaining STI region 508. The dielectric constant of the insertion dielectric layer 511 (SiCOH) is lower than that of the STI region 508, which may improve the coupling effect between the two gate structures 504 and 506 (described below).

[0089] Referring to sub-step S533: a patterning process is performed to remove portions of the capping dielectric layer 509, thereby defining the gate opening 502. In some embodiments, a patterned photoresist layer (not shown) is formed on the capping dielectric layer 509 to expose the portions of the capping dielectric layer 509 covering the fin structures 501F1 and 501F2. An etching process is then performed to remove the exposed portions of the capping dielectric layer 509, thereby defining the gate opening 502 in the capping dielectric layer 509.

[0090] Referring to sub-step S534: the amorphous silicon spacers 507C, the nitride spacers 507B, and the oxide spacers 507A are removed so that each of the fin structures 501F1 and 501F2 can be partially exposed from the gate opening 502. In the present embodiment, after the gate opening 502 is defined in the capping dielectric layer 509, another etching process is performed to remove the amorphous silicon spacers 507C that are not covered by the patterned photoresist layer (not shown) from the gate opening 502.

[0091] Next, another process is performed to remove the nitride spacers 507B and portions of the patterned pad nitride 510B from the gate opening 502. After the patterned photoresist layer PR is stripped, the oxide spacers 507A and portions of the patterned pad oxide layer 510A exposed from the gate opening 502 are removed by another etching process, resulting in the top and sidewalls of each fin structure 501F1 and 501F2 being exposed. Referring to FIGS. 5D(1) to 5D(3), FIG. 5D(1) is a top view showing the structure after the fin structures 501F1 and 501F2 are partially exposed from the gate opening 502, FIG. 5D(2) is a cross-sectional view taken along the cut line C5D1 shown in FIG. 5D(1), and FIG. 5D(3) is a cross-sectional view taken along the cut line C5D2 shown in FIG. 5D(1).

[0092] Referring to step S54: gate structures 504 and 505 are formed on fin structures 501F1 and 501F2, respectively. See FIGS. 5E(1) to 5E(3). FIG. 5E(1) is a top view showing the structure after gate structures 504 and 505 are formed, FIG. 5E(2) is a cross-sectional view taken along section line C5E1 shown in FIG. 5E(1), and FIG. 5E(3) is a cross-sectional view taken along section line C5E2 shown in FIG. 5E(1).

[0093] Step S54 for forming gate structures 504 and 505 includes substeps S541-S542: Referring to substep S541, gate dielectric layers 504O and 505O are formed, covering the tops and sidewalls of fin structures 501F1 and 501F2, respectively. In some embodiments of the present disclosure, the gate dielectric layers 504O and 505O are formed by an oxide deposition process. Next, referring to substep S542, gate electrodes 504S and 505S are formed, covering the gate dielectric layers 504O and 505O, respectively. In some embodiments of the present disclosure, the gate electrodes 504S and 505S are formed by polysilicon or metal. After the formation of gate structures 504 and 505, capping dielectric layer 309 is removed, and source / drain regions may be formed as described above.

[0094] Compared with embodiment II, in this embodiment, the bottom of the insertion dielectric layer 511 (SiCOH) between the two gate structures 504 and 505 is lower than the bottom of the STI region 508. Because the dielectric constant of the insertion dielectric layer 511 (SiCOH) is lower than that of the STI region 508, the coupling effect between the two gate structures 504 and 505 may be improved.

[0095] Those skilled in the art will readily appreciate that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. 1. A method for forming a metal-oxide-semiconductor (MOS) transistor structure, comprising: defining a first fin structure and a second fin structure adjacent to the first fin structure in a semiconductor substrate, wherein a shallow trench isolation (STI) region exists between the first fin structure and the second fin structure; forming a first sacrificial spacer disposed along a sidewall of the first fin structure and forming a second sacrificial spacer disposed along a sidewall of the second fin structure, wherein a gap exists between the first sacrificial spacer and the second sacrificial spacer; forming an intercalating dielectric layer to fill a gap between the first sacrificial spacer and the second sacrificial spacer; removing the first sacrificial spacer and the second sacrificial spacer; and forming two gate structures on the first fin structure and the second fin structure, respectively, wherein the two gate structures are separated by the intervening dielectric layer; A method comprising:

2. 2. The method of claim 1, wherein the first sacrificial spacers and the second sacrificial spacers comprise epitaxial semiconductor material selectively grown on the sidewalls of the first fin structure and the second fin structure.

3. before forming the first sacrificial spacers and the second sacrificial spacers; forming a capping dielectric layer overlying the first fin structure and the second fin structure; and defining the gate opening in the capping dielectric layer such that the sidewalls of the first fin structure and the second fin structure are partially exposed from the gate opening; The method of claim 2 further comprising:

4. forming a fin spacer surrounding the sidewalls of the first fin structure and the second fin structure before forming the capping dielectric layer; and performing at least one etching process to remove the fin spacers in the gate openings to partially expose the sidewalls of the first fin structure and the second fin structure prior to forming the first sacrificial spacers and the second sacrificial spacers. The method of claim 3 further comprising:

5. The method of claim 3 , wherein the material of the inserting dielectric layer is different from the material of the capping dielectric layer.

6. 4. The method of claim 3, further comprising deepening the gate opening to expose the semiconductor substrate after the epitaxial semiconductor material is formed and before the gate opening is filled with the intervening dielectric layer.

7. 7. The method of claim 6, wherein a portion of the semiconductor substrate is removed during the step of deepening the gate opening.

8. 7. The method of claim 6, wherein during the deepening of the gate opening, a portion of the STI region is removed, thereby leaving another portion of the STI region underlying the epitaxial semiconductor material.

9. The method of claim 8 , wherein a bottom of the insertion dielectric layer is lower than a bottom of the other portion of the STI region.

10. The dielectric constant of the insertion dielectric layer is SiO ２ The method of claim 1 , wherein the dielectric constant is less than 0.

05.

11. 2. The method of claim 1, wherein the first sacrificial spacers and the second sacrificial spacers comprise amorphous silicon covering the sidewalls of the first fin structure and the second fin structure.

12. forming a fin spacer surrounding the sidewalls of the first fin structure and the second fin structure prior to forming the first sacrificial spacer and the second sacrificial spacer. The method of claim 11 further comprising:

13. forming a capping dielectric layer covering the first fin structure, the second fin structure, the first sacrificial spacer, the second sacrificial spacer, and the interposing dielectric layer; and defining the gate opening in the capping dielectric layer such that the sidewalls of the first fin structure and the second fin structure are partially exposed from the gate opening; The method of claim 11 further comprising:

14. removing a portion of the STI region that is not covered by the first sacrificial spacer and the second sacrificial spacer so as to expose a portion of the semiconductor substrate before removing the sacrificial spacer. The method of claim 11 further comprising:

15. 15. The method of claim 14, wherein a bottom of the interpolating dielectric layer is lower than a bottom of another portion of the STI region underlying the first sacrificial spacer and the second sacrificial spacer.

16. A metal-oxide-semiconductor (MOS) transistor structure comprising: a first active area in a semiconductor substrate and a second active area adjacent to the first active area, where a shallow trench isolation (STI) region exists between the first active area and the second active area; an interposing dielectric layer disposed between the first active area and the second active area; a first trench surrounding or overlying the first active area, wherein the first trench is adjacent to one side of the intercalating dielectric layer; a second trench surrounding or overlying the second active area, wherein the second trench is adjacent to another side of the intercalating dielectric layer; a first gate structure overlying the first active area and within the first trench, wherein the first gate structure covers a first portion of the STI region; a second gate structure overlying the second active area and within the first trench, wherein the second gate structure covers a second portion of the STI region; a first source region and a first drain region in electrical contact with a first channel in the first active region; and a second source region and a second drain region electrically contacting a second channel in the second active region; Including, A MOS transistor structure, wherein the distance between the first gate structure and the second gate structure is determined by the intervening dielectric layer.

17. 17. The MOS transistor structure of claim 16, wherein a width of the intervening dielectric layer between the active area and the second active area is not defined by a photolithography process.

18. A metal-oxide-semiconductor (MOS) transistor structure comprising: a first fin structure and a second fin structure adjacent to the first fin structure in a semiconductor substrate, wherein a shallow trench isolation (STI) region exists between the first fin structure and the second fin structure; an intervening dielectric layer disposed between the first fin structure and the second fin structure; a first trench surrounding or overlying the first fin structure, wherein the first trench is adjacent to one side of the intercalating dielectric layer; a second trench surrounding or overlying the second fin structure, wherein the second trench is adjacent to another side of the interposed dielectric layer; a first gate structure overlying the first fin structure and within the first trench, wherein the first gate structure covers a first portion of the STI region; and a second gate structure overlying the second fin structure and within the first trench, wherein the second gate structure covers a second portion of the STI region; Including, A MOS transistor structure, wherein a bottom of the insertion dielectric layer is lower than a bottom of the first portion of the STI region or a bottom of the second portion of the STI region.

19. a first source region and a first drain region in electrical contact with a first channel in the first fin structure; and a second source region and a second drain region electrically contacting a second channel in the second fin structure; 17. The MOS transistor structure of claim 16, further comprising:

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